Semiconductor Device

Abstract

To provide a semiconductor device in which a switch can be provided suitably.SOLUTION: A semiconductor device includes a first chip 10 and a second chip 20, first to fourth driving buffers 41 to 44 in a first power domain 31A, a standard cell 56 including various logic circuits such as a NAND circuit and inverter, and an SRAM in a second power domain 31B, a VDD wire to which a power source potential of VDD is supplied, a VVDD wire to which a power source potential of VVDD is supplied, a VSS wire to which a power source potential of VSS is supplied, and a VVSS wire to which a power source potential of VVSS is supplied. To the first to fourth driving buffers, VDD and VSS are supplied. To the standard cell in the second power domain, VVDD and VVSS are supplied. The semiconductor device also includes first to fourth switching transistors 51 to 54, which are controlled by a control circuit through the first to fourth driving buffers.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] A semiconductor device includes various circuit regions, one example of which is a standard cell region. The standard cell region includes various logic circuits. When a power supply potential of VDD is supplied to the semiconductor device, the power supply potential of VVDD is supplied to the logic circuits in the standard cell region, and a switch such as a transistor may be connected between the power supply line of VDD and the power supply line of VVDD.

[0003] The switch turns on and off the supply of the VVDD power supply potential to the transistors in the logic circuit. By using the switch, the power supply can be turned off when the logic circuit does not need to operate, suppressing leakage current generated in the transistors that make up the logic circuit and reducing power consumption.

[0004] In addition, a technology has been proposed in which a secondary semiconductor chip including wiring is attached to the back side of a primary semiconductor chip, and power potential is supplied to the transistors of the primary semiconductor chip via the wiring of the secondary semiconductor chip. This technology is sometimes called BS-PDN (backside-power delivery network). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2015 / 0162448 [Patent Document 2] U.S. Patent No. 9,754,923 [Patent Document 3] US Patent Application Publication No. 2018 / 0145030 [Patent Document 4] U.S. Patent No. 8,530,273 [Patent Document 5] Patent No. 6469269 Summary of the Invention [Problem to be solved by the invention]

[0006] So far, no detailed consideration has been given to a specific configuration in the case where a switch is provided in a subsidiary semiconductor chip including wiring.

[0007] An object of the present disclosure is to provide a semiconductor device in which a switch can be appropriately provided. [Means for solving the problem]

[0008] The semiconductor device according to the disclosed technique includes a substrate, a first wiring layer formed on a first surface of the substrate, and a second surface of the substrate opposite to the first surface. Placed opposite a second wiring layer formed on the first surface side of the semiconductor device, a first power supply line formed in the second wiring layer and supplied with a first power supply potential, a second power supply line formed in the second wiring layer and supplied with a second power supply potential, a third power supply line formed in the second wiring layer and supplied with a third power supply potential, a fourth power supply line formed on the first surface side of the semiconductor device and supplied with the first power supply potential, a fifth power supply line formed on the first surface side of the semiconductor device and supplied with the second power supply potential, and a sixth power supply line formed on the first surface side of the semiconductor device and supplied with the third power supply potential. a seventh power supply line formed in the second wiring layer; a first via formed on the substrate and connecting the first power supply line and the fourth power supply line; a second via formed on the substrate and connecting the second power supply line and the fifth power supply line; a third via formed on the substrate and connecting the third power supply line and the sixth power supply line; and a first switch connected between the first power supply line and the second power supply line. ,before a first circuit connected between the fifth power supply line and the sixth power supply line; and, Have the seventh power supply line is supplied with the first power supply potential, and a second switch is connected between the first power supply line and the seventh power supply line; or the seventh power supply line is supplied with the third power supply potential, and a second switch is connected between the third power supply line and the seventh power supply line. do. Effect of the Invention

[0009] According to the disclosed technology, the switch can be appropriately provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing an overview of a semiconductor device to which the present disclosure is applied. [Diagram 2] FIG. 2 is a diagram showing the layout of the first chip. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration of an example of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing a configuration of the driving buffer. [Diagram 5] FIG. 5 is a schematic diagram showing a planar configuration of an example of a driving buffer. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of an inverter. [Figure 7] FIG. 7 is a schematic diagram showing a plan configuration of the inverter. [Figure 8] FIG. 8 is a schematic diagram (part 1) showing a planar configuration of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a schematic diagram (part 2) showing the planar configuration of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 1) showing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 2) illustrating the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a schematic diagram showing a planar configuration of a semiconductor device according to a first modified example of the first embodiment. [Figure 13] FIG. 13 is a schematic diagram showing a planar configuration of a semiconductor device according to a second modification of the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. [Figure 15] FIG. 15 is a circuit diagram showing a configuration of an example of a circuit included in a semiconductor device according to a fourth modification of the first embodiment. [Figure 16] FIG. 16 is a schematic diagram (part 1) showing a planar configuration of a semiconductor device according to a fifth modified example of the first embodiment. [Figure 17] FIG. 17 is a schematic diagram (part 2) showing a planar configuration of a semiconductor device according to a fifth modified example of the first embodiment. [Figure 18] FIG. 18 is a schematic diagram showing a planar configuration of a semiconductor device according to a sixth modified example of the first embodiment. [Figure 19] FIG. 19 is a schematic diagram (part 1) showing a planar configuration of a semiconductor device according to a second embodiment. [Figure 20] FIG. 20 is a schematic diagram (part 2) showing the planar configuration of the semiconductor device according to the second embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 1) illustrating the semiconductor device according to the second embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 2) illustrating the semiconductor device according to the second embodiment. [Diagram 23] FIG. 23 is a cross-sectional view (part 1) showing an example of a cross-sectional configuration of a switch transistor. [Figure 24] FIG. 24 is a cross-sectional view (part 2) illustrating an example of a cross-sectional configuration of a switch transistor. [Diagram 25] FIG. 25 is a cross-sectional view (part 3) illustrating an example of a cross-sectional configuration of a switch transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid repetitive description. In the following description, two directions parallel to the surface of the substrate and perpendicular to each other are defined as the X direction and the Y direction, and a direction perpendicular to the surface of the substrate is defined as the Z direction. In addition, the term "matching of arrangements" in this disclosure does not strictly exclude mismatching caused by manufacturing variations, and even if there is a deviation in the arrangement due to manufacturing variations, the arrangements can be considered to be matched.

[0012] (Overview of Semiconductor Device to Which the Present Disclosure is Applied) First, an overview of a semiconductor device to which the present disclosure is applied will be described. Fig. 1 is a cross-sectional view showing an overview of a semiconductor device to which the present disclosure is applied. The semiconductor device shown in Fig. 1 includes a first chip 10 and a second chip 20.

[0013] The first chip 10 is, for example, a semiconductor chip, and includes a substrate 11 and a first wiring layer 12. The substrate 11 is, for example, a silicon substrate, and a semiconductor element such as a transistor is formed on the front side of the substrate 11. The transistor is, for example, a FinFET including fins 13 in the source, drain, and channel. The first wiring layer 12 is formed on the front side of the substrate 11, and includes wiring 14 and an insulating layer 15. A part of the wiring 14 is connected to the fin 13. Furthermore, for example, a power line 16 connected to the wiring 14 is formed on the front side of the substrate 11, and a via 17 is provided in the substrate 11, which extends from the power line 16 to the rear side of the substrate 11. The via 17 is, for example, a through-silicon via (TSV). As shown in FIG. 1, a part of the wiring 14 may have a shape like a via and be connected to the power line 16. The material of the wiring 14 and the power line 16 is, for example, copper, tungsten, cobalt, ruthenium, molybdenum, or the like.

[0014] The second chip 20 is, for example, a semiconductor chip, and is disposed opposite the rear surface of the substrate 11 of the first chip 10. The second chip 20 includes, for example, a second wiring layer 22 and a pad 23. The second wiring layer 22 includes a wiring 24 and an insulating layer 25. The upper surface of the second wiring layer 22 faces, for example, the rear surface of the substrate 11 of the first chip 10. That is, the substrate 11 is located between the first wiring layer 12 and the second wiring layer 22. The second wiring layer 22 may have a plurality of wirings 24 as shown in FIG. 1. The plurality of wirings 24 may be connected through vias 28 provided in the second wiring layer 22. The pads 23 are, for example, external connection terminals connected to a wiring substrate, a board, or the like. A portion of the wiring 24 is connected to the vias 17. The pads 23 are provided on the rear surface of the second wiring layer 22, and are connected to the wiring 24 through the vias 28. A power supply potential and signals are supplied to the second wiring layer 22 through the pads 23. The wiring 24 and the vias 28 are made of a material such as copper, tungsten, cobalt, ruthenium, or molybdenum.

[0015] The second chip 20 may have a size approximately equal to that of the first chip 10, or may have a size larger than that of the first chip 10. Furthermore, the pads 23 may be provided on the surface of the second chip 20 facing the first chip 10, outside the first chip 10 in a plan view. Hereinafter, in this specification, a plan view refers to a plan view of the main surface of the first chip 10.

[0016] The second wiring layer 22 may be provided by forming wiring 24, an insulating layer 25, etc. on the back surface of the substrate 11. The second wiring layer 22 may be formed on a second substrate on which a TSV is formed, and a pad 23 may be provided on the back surface of the second substrate.

[0017] The cross-sectional view shown in FIG. 1 shows an outline of the semiconductor device, and the details are shown in FIG. 10, FIG. 11, etc.

[0018] Next, a description will be given of the layout of the first chip 10. FIG 2 is a diagram showing the layout of the first chip 10.

[0019] 2, the first chip 10 includes a first power domain 31A, a second power domain 31B, and an input / output (I / O) cell area 32. The I / O cell area 32 is, for example, arranged around the first power domain 31A and the second power domain 31B. The number of the first power domains 31A and the number of the second power domains 31B may be two or more.

[0020] [Circuits included in semiconductor device] Next, a circuit included in the semiconductor device will be described with reference to Fig. 3, which is a circuit diagram showing an example of a configuration of a circuit included in the semiconductor device.

[0021] 3, the semiconductor device has a first drive buffer 41, a second drive buffer 42, a third drive buffer 43, and a fourth drive buffer 44 in a first power domain 31A. The semiconductor device has a standard cell 56 in a second power domain 31B. The semiconductor device has a VDD wiring to which a power supply potential of VDD is supplied, a VVDD wiring to which a power supply potential of VVDD is supplied, a VSS wiring to which a power supply potential of VSS is supplied, and a VVSS wiring to which a power supply potential of VVSS is supplied. For example, the power supply potential of VSS is a ground potential, and the VSS wiring is a ground wiring.

[0022] The first to fourth drive buffers 41 to 44 in the first power domain 31A are supplied with the power supply potentials VDD and VSS.

[0023] A power supply potential of VVDD and a power supply potential of VVSS are supplied to the standard cells 56 in the second power domain 31B. The standard cells 56 include various logic circuits such as a NAND circuit and an inverter. The standard cells 56 may include a static random access memory (SRAM) or a macro. Note that in FIG. 3, a VVDD wiring may not be provided and a VDD wiring may be connected to the standard cells 56 instead, or a VVSS wiring may not be provided and a VSS wiring may be connected to the standard cells 56 instead. In this case, the power supply potential of VVDD and a power supply potential of VSS are supplied to the standard cells 56, or the power supply potential of VDD and a power supply potential of VVSS are supplied to the standard cells 56.

[0024] The semiconductor device has a first switch transistor 51, a second switch transistor 52, a third switch transistor 53, and a fourth switch transistor .

[0025] The first switch transistor 51 is, for example, a P-channel MOS transistor. For example, a control signal from the first drive buffer 41 is input to the gate of the first switch transistor 51. The source (VDD connection part) of the first switch transistor 51 is connected to the VDD wiring, and the drain (VVDD connection part) is connected to the VVDD wiring.

[0026] The second switch transistor 52 is, for example, a P-channel MOS transistor. For example, a control signal from the second drive buffer 42 is input to the gate of the second switch transistor 52. The second switch transistor 52 is provided on the VDD wiring. A first terminal (drain) 521 of the second switch transistor 52 is connected to the source of the first switch transistor 51. A first power supply pad 81 is connected to the first terminal 521 and the source of the first switch transistor 51. A power supply potential of VDD is supplied to the first power supply pad 81 from the outside. A second power supply pad 82 is connected to a second terminal (source) 522 of the second switch transistor 52. A power supply potential of VDD is supplied to the second power supply pad 82 from the outside.

[0027] The third switch transistor 53 is, for example, an N-channel MOS transistor. For example, a control signal from the third drive buffer 43 is input to the gate of the third switch transistor 53. The source (VSS connection part) of the third switch transistor 53 is connected to the VSS wiring, and the drain (VVSS connection part) is connected to the VVSS wiring.

[0028] The fourth switch transistor 54 is, for example, an N-channel MOS transistor. For example, a control signal from the fourth drive buffer 44 is input to the gate of the fourth switch transistor 54. The fourth switch transistor 54 is provided on the VSS wiring. A first terminal (drain) 541 of the fourth switch transistor 54 is connected to the source of the third switch transistor 53. A third power supply pad 83 is connected to the first terminal 541 and the source of the third switch transistor 53. A power supply potential of VSS is supplied to the third power supply pad 83 from the outside. A fourth power supply pad 84 is connected to a second terminal (source) 542 of the fourth switch transistor 54. A power supply potential of VSS is supplied to the fourth power supply pad 84 from the outside.

[0029] The first to fourth drive buffers 41 to 44 are connected to a control circuit (not shown), and the operations of the first to fourth switch transistors 51 to 54 are controlled by the control circuit via the first to fourth drive buffers 41 to 44. For example, the control circuit is provided in the first power domain 31A, and a power supply potential of VDD and a power supply potential of VSS are supplied to the control circuit. The control circuit switches the first switch transistor 51 on / off to control the conduction between the VDD wiring and the VVDD wiring. The control circuit switches the third switch transistor 53 on / off to control the conduction between the VSS wiring and the VVSS wiring. The control circuit switches the second and fourth switch transistors 52 and 54 on / off to control the conduction between the first power domain 31A and the second power domain 31B.

[0030] Although details will be described later, the second wiring layer 22 has a first sub-wiring layer 201 and a second sub-wiring layer 202. The first sub-wiring layer 201 is located closer to the first chip 10 than the second sub-wiring layer 202. In the first embodiment, the first to fourth switch transistors 51 to 54 are provided in the second sub-wiring layer 202.

[0031] The first to fourth switch transistors 51 to 54 may be configured by thin film transistors (TFTs), or may be micro electro mechanical systems (MEMS) switches.

[0032] [First to fourth driving buffers 41 to 44] Next, there will be described the configurations of the first to fourth drive buffers 41 to 44. Fig. 4 is a circuit diagram showing the configuration of the first drive buffer 41. Fig. 5 is a schematic diagram showing the planar configuration of an example of the first drive buffer 41.

[0033] 4, the first drive buffer 41 has an inverter 61 and an inverter 62. An input signal IN is input to the inverter 61, and an output of the inverter 61 is input to the inverter 62, and an output signal OUT is output from the inverter 62. The inverter 61 includes a P-channel MOS transistor 610P and an N-channel MOS transistor 610N. The inverter 62 includes a P-channel MOS transistor 620P and an N-channel MOS transistor 620N.

[0034] In the example shown in FIG. 5, for example, a power line 1110 corresponding to a VDD wiring and a power line 1130 corresponding to a VSS wiring are provided. The power lines 1110 and 1130 extend in the X direction. A semiconductor fin 651 extending in the X direction is provided on the power line 1130 side of the power line 1110. For example, two fins 651 are provided. A semiconductor fin 652 extending in the X direction is provided on the power line 1130 side of the fin 651. For example, two fins 652 are provided. A local wiring 631 is provided that is connected to the power line 1110 via a via 681, extends in the Y direction, and is connected to the fin 651. A local wiring 632 is provided that is connected to the power line 1130 via a via 682, extends in the Y direction, and is connected to the fin 652. A local wiring 634 is provided on the positive side of the X direction from the local wirings 631 and 632, and is connected to the fins 651 and 652. A local wire 636 connected to the fins 651 and 652 is provided on the negative side in the X direction from the local wires 631 and 632 .

[0035] Between the local wiring 631 and the local wiring 634 and between the local wiring 632 and the local wiring 634, a gate electrode 612 is provided intersecting with the fins 651 and 652 via a gate insulating film (not shown). Between the local wiring 631 and the local wiring 636 and between the local wiring 632 and the local wiring 636, a gate electrode 622 is provided intersecting with the fins 651 and 652 via a gate insulating film (not shown). The gate electrode 612 is connected to the wiring 611 via the local wiring 633 and a via 641. The gate electrode 622 is connected to the wiring 692 via the local wiring 635 and a via 643. The wiring 692 is also connected to the local wiring 634. The local wiring 636 is connected to the wiring 621 via a via 644. An input signal IN is input to the wiring 611, and an output signal OUT is output from the wiring 621 (see FIG. 4).

[0036] The wiring 692 may be connected to the gate of the first switch transistor 51. Instead of the wiring 692, either the wiring 611 or the wiring 621 may be connected to the gate of the first switch transistor 51. That is, the output of the inverter 61 may be input to the gate of the first switch transistor 51. Instead of the output of the inverter 61, either the input of the inverter 61 or the output of the inverter 62 may be connected to the gate of the first switch transistor 51.

[0037] The second to fourth drive buffers 42 to 44 may have the same configuration as the first drive buffer 41.

[0038] The configuration of the inverters 61 and 62 is merely an example, and the inverters 61 and 62 may include two or more pairs of P-channel MOS transistors and N-channel MOS transistors, for example.

[0039] [Standard Cell 56] Next, a configuration of an inverter will be described as an example of a circuit included in the standard cell 56. Fig. 6 is a circuit diagram showing the configuration of the inverter. Fig. 7 is a schematic diagram showing the planar configuration of the inverter.

[0040] As shown in FIG. 6, inverter 70 includes a P-channel MOS transistor 710P and an N-channel MOS transistor 710N.

[0041] For example, as shown in FIG. 7, a power supply line 2120 corresponding to a VVDD wiring and a power supply line 2130 corresponding to a VVSS wiring are provided. The power supply lines 2120 and 2130 extend in the X direction. A semiconductor fin 751 extending in the X direction is provided on the power supply line 2130 side of the power supply line 2120. For example, two fins 751 are provided. A semiconductor fin 752 extending in the X direction is provided on the power supply line 2130 side of the fin 751. For example, two fins 752 are provided. A local wiring 731 is provided that is connected to the power supply line 2120 via a via 781, extends in the Y direction, and is connected to the fin 751. A local wiring 732 is provided that is connected to the power supply line 2130 via a via 782, extends in the Y direction, and is connected to the fin 752. A local wiring 734 connected to the fins 751 and 752 is provided on the positive side of the X direction from the local wirings 731 and 732. A circuit may be provided across three or more regions of the power supply lines 2120 and 2130. In other words, a so-called multi-height circuit may be provided.

[0042] A gate electrode 712 is provided between the local wiring 731 and the local wiring 734 and between the local wiring 732 and the local wiring 734, intersecting the fins 751 and 752 with a gate insulating film (not shown) interposed therebetween. The gate electrode 712 is connected to a wiring 711 through a local wiring 733 and a via 741. The local wiring 734 is connected to a wiring 760 through a via 742. An input signal IN is input to the wiring 711, and an output signal OUT is output from the wiring 760 (see FIG. 6).

[0043] Although Figures 5 and 7 show examples of transistors using fins (FinFETs), planar transistors, complementary field effect transistors (CFETs), transistors using nanowires, etc. may also be provided in logic circuits such as buffers.

[0044] It is sufficient that at least one of the VVDD wiring or the VVSS wiring is provided. For example, if the VVDD wiring is provided, the VSS wiring may be provided instead of the VVSS wiring. In this case, the combination of the third driving buffer 43 and the third switch transistor 53 may not be provided. Also, for example, if the VVSS wiring is provided, the VDD wiring may be provided instead of the VVDD wiring. In this case, the combination of the first driving buffer 41 and the first switch transistor 51 may not be provided.

[0045] Furthermore, as long as either the combination of the second driving buffer 42 and the second switch transistor 52 or the combination of the fourth driving buffer 44 and the fourth switch transistor 54 is provided, the other may not be provided. For example, as long as the combination of the second driving buffer 42 and the second switch transistor 52 is provided, the combination of the fourth driving buffer 44 and the fourth switch transistor 54 may not be provided.

[0046] (First embodiment) Here, the first embodiment will be described. In the first embodiment, the VVSS wiring, the third driving buffer 43, the third switch transistor 53, and the fourth switch transistor 54 are not provided in the circuit shown in FIG. 3. FIGS. 8 and 9 are schematic diagrams showing a planar configuration of the semiconductor device according to the first embodiment. FIGS. 10 and 11 are cross-sectional views showing the semiconductor device according to the first embodiment. FIG. 8 shows the internal configurations of the first chip 10 and the second chip 20, and FIG. 9 shows the internal configuration of the second chip 20. FIG. 10 corresponds to a cross-sectional view taken along the line Y11-Y21 in FIGS. 8 and 9, and FIG. 11 corresponds to a cross-sectional view taken along the line Y12-Y22 in FIGS. 8 and 9.

[0047] [First tip 10] The first chip 10 includes a control signal line 3110 extending in the X direction. In the example of FIG. 8, the first chip 10 includes a power supply line 2160 extending in the X direction and a power supply line 2170 extending in the X direction, which are arranged on the positive side of the Y direction from the control signal line 3110. In the example of FIG. 8, the power supply line 2160 is located closer to the control signal line 3110 than the power supply line 2170. For example, the power supply line 2160 corresponds to a VVDD wiring, and the power supply line 2170 corresponds to a VSS wiring. The control signal line 3110 is connected between the first drive buffer 41 and the gate of the first switch transistor 51. A plurality of pairs of the power supply line 2160 and the power supply line 2170 may be alternately arranged. The power supply line 2160 and the power supply line 2170 are arranged in the second power domain 31B. The control signal line 3110 may also be arranged in the second power domain 31B.

[0048] In the example of FIG. 8, the first chip 10 includes a control signal line 3120 extending in the X direction, which is disposed on the negative side of the Y direction from the control signal line 3110, a power supply line 1120 extending in the X direction, and a power supply line 1130 extending in the X direction. In the example of FIG. 8, the control signal line 3120 is located closer to the control signal line 3110 than the power supply line 1120, and the power supply line 1120 is located closer to the control signal line 3110 than the power supply line 1130. For example, the power supply line 1120 corresponds to a VDD wiring electrically connected to the second power supply pad 82, and the power supply line 1130 corresponds to a VSS wiring. The control signal line 3120 is connected between the second drive buffer 42 and the gate of the second switch transistor 52. The control signal line 3120, the power supply line 1120, and the power supply line 1130 are disposed outside the second power domain 31B. The arrangement of each control signal line and each power supply line is not limited to the example of FIG. 8, and may be changed as appropriate.

[0049] 10 and 11, a plurality of grooves extending in the X direction are formed in the substrate 11, and the control signal line 3110, the power line 2160, the power line 2170, the control signal line 3120, the power line 1120, and the power line 1130 are formed in these grooves. The power line 2160, the power line 2170, the power line 1120, and the power line 1130 having such a structure are sometimes called BPR (Buried Power Rail). An element isolation film (not shown) may be formed on the surface of the substrate 11. The element isolation film is formed by, for example, an STI (Shallow Trench Isolation) method. The surface of the element isolation film may be flush with the surface of the substrate 11, or may not be flush with it.

[0050] Although not shown in FIGS. 8 to 11, circuits such as the standard cell 56 are connected between the power supply line 2160 and the power supply line 2170 in the second power domain 31B.

[0051] Also, although not shown in Figures 8 to 11, a first power domain 31A is arranged outside the second power domain 31B, and within the first power domain 31A, a first drive buffer 41, a second drive buffer 42, and circuits such as their control circuits are connected between a power line 1120 and a power line 1130.

[0052] The first wiring layer 12 includes control signal lines 4110 and 4120 arranged above the control signal line 3110, the power line 2160, the power line 2170, the control signal line 3120, the power line 1120, and the power line 1130. In the first wiring layer 12, a via 4111 that connects the control signal line 4110 and the control signal line 3110, and a via 4121 that connects the control signal line 4120 and the control signal line 3120 are formed. The via 4111 is formed under the control signal line 4110, and the via 4121 is formed under the control signal line 4120.

[0053] In the substrate 11, vias 1121, 1131, 2161, 2171, 3111, and 3121 are formed which penetrate the substrate 11 to the rear surface. The via 1121 is formed under the power supply line 1120, the via 1131 is formed under the power supply line 1130, the via 2161 is formed under the power supply line 2160, and the via 2171 is formed under the power supply line 2170. The via 3111 is formed under the control signal line 3110, and the via 3121 is formed under the control signal line 3120.

[0054] [Second Chip 20] As shown in Figures 10 and 11, the second chip 20 has, for example, an insulating layer 25, a first sub-wiring layer 201 formed on the surface portion of the insulating layer 25, and a second sub-wiring layer 202 formed inside the insulating layer 25.

[0055] The first sub-wiring layer 201 includes a power line 5120, a power line 5130, a power line 5160, a control signal line 7110, and a control signal line 7120. The power line 5120, the power line 5130, the power line 5160, the control signal line 7110, and the control signal line 7120 extend in the Y direction. For example, in a region overlapping with the second power domain 31B in a plan view, the power line 5160 is located between the two control signal lines 7110, and the control signal line 7110 is located between the power line 5130 and the power line 5160. For example, the power line 5130 is formed from below the power lines 2160 and 2170 to below the power line 1130. For example, the power line 5160 is formed in a region overlapping with the second power domain 31B in a plan view. For example, the power supply line 5120 is formed outside the area overlapping with the second power domain 31B in a plan view, on an extension of the power supply line 5160. For example, the power supply line 5120 corresponds to a VDD wiring electrically connected to the second power supply pad 82, the power supply line 5130 corresponds to a VSS wiring, and the power supply line 5160 corresponds to a VVDD wiring.

[0056] The second sub-wiring layer 202 includes a power line 6110, a power line 6120, and a power line 6160. The power lines 6110, 6120, and 6160 extend in the X direction. For example, the power line 6110 is located below the power line 2170, and the power line 6160 is located below the power line 2160. The power line 6120 has a portion overlapping with the power line 5120 in a plan view. In the insulating layer 25, a via 5121 that connects the power line 5120 and the power line 6120, and a via 5161 that connects the power line 5160 and the power line 6160 are formed. For example, the power line 6110 corresponds to a VDD wiring electrically connected to the first power pad 81, the power line 6120 corresponds to a VDD wiring electrically connected to the second power pad 82, and the power line 6160 corresponds to a VVDD wiring.

[0057] In the insulating layer 25, a plurality of semiconductor layers 213 are formed in a region overlapping with the second power domain 31B in a plan view, the semiconductor layers 213 being overlapped with the pair of adjacent power lines 6110 and 6160 in a plan view. The semiconductor layers 213 are connected to the power lines 6110 and 6160. A gate insulating film 214 is formed on the semiconductor layer 213, and a gate electrode 215 is formed on the gate insulating film 214. The gate insulating film 214 contacts the semiconductor layer 213 and the gate electrode 215. The gate electrode 215 is located between the power line 6110 and the power line 6160 in a plan view. In the insulating layer 25, a via 7111 is formed to connect the control signal line 7110 and each gate electrode 215. The semiconductor layer 213, the gate insulating film 214, and the gate electrode 215 are included in the first switch transistor 51.

[0058] In the insulating layer 25, a plurality of semiconductor layers 223 are formed that overlap the pair of adjacent power lines 6110 and 6120 in a plan view. The semiconductor layers 223 may be disposed outside or within the region that overlaps with the second power domain 31B in a plan view. The semiconductor layers 223 are connected to the power lines 6110 and 6120. A gate insulating film 224 is formed on the semiconductor layer 223, and a gate electrode 225 is formed on the gate insulating film 224. The gate insulating film 224 contacts the semiconductor layer 223 and the gate electrode 225. The gate electrode 225 is located between the power line 6110 and the power line 6120 in a plan view. In the insulating layer 25, a via 7121 that connects the control signal line 7120 and each gate electrode 225 is formed. The semiconductor layers 223, the gate insulating film 224, and the gate electrode 225 are included in the second switch transistor 52.

[0059] A power supply potential VDD and a power supply potential VSS are supplied from the outside through a plurality of pads 23 provided on the back surface of the second chip 20. In addition, signals processed by the semiconductor device are output to the outside through the plurality of pads 23.

[0060] In the semiconductor device according to the first embodiment thus configured, when it is not necessary to operate the standard cell 56, the first switch transistor 51 is turned off. That is, a control signal for making the power supply line 6110 and the power supply line 6160 non-conductive is input to the gate electrode 215. As a result, the power supply line 6160 (VVDD wiring) is insulated from the first power supply pad 81 and the second power supply pad 82, and the supply of the power supply potential from the power supply line 6110 (VDD wiring) to the power supply line 6160 (VVDD wiring) is cut off.

[0061] When the standard cell 56 is to be operated, the second switch transistor 52 is turned off, and then the first switch transistor 51 is turned on. That is, a control signal for making the power supply line 6110 and the power supply line 6120 non-conductive is input to the gate electrode 225, and then a control signal for making the power supply line 6110 and the power supply line 6160 conductive is input to the gate electrode 215. As a result, the power supply line 6120 (VDD wiring) is insulated from the power supply line 6110 (VDD wiring), and the power supply line 6160 (VVDD wiring) is electrically connected to the first power supply pad 81 via the power supply line 6110 (VDD wiring), and the power supply potential of VDD is supplied to the power supply line 6160 (VVDD wiring).

[0062] When the power supply potential of VDD is supplied to the power supply line 6160 (VVDD wiring), the standard cell 56 starts to operate. At this time, if the second switch transistor 52 is in an ON state, the power supply potential of VDD is also supplied to the second power domain 31B from the second power pad 82, and noise is generated due to the sudden supply of the power supply potential, and this noise may reach the first power domain 31A. Such a sudden supply of the power supply potential is sometimes called a rush current. In contrast, in this embodiment, since the second switch transistor 52 is in an OFF state, the rush current is suppressed and the generation of noise is suppressed.

[0063] After the standard cell 56 starts operating, when the fluctuation of the power supply potential of VDD supplied to the second power domain 31B settles down, the second switch transistor 52 is turned on. That is, a control signal for establishing conduction between the power supply line 6110 and the power supply line 6120 is input to the gate electrode 225. As a result, a stable power supply potential of VDD is supplied to the first power domain 31A and the second power domain 31B.

[0064] In this way, according to this embodiment, the influence of noise due to rush current on an operating domain can be suppressed.

[0065] (First Modification of the First Embodiment) Next, a first modified example of the first embodiment will be described. The first modified example differs from the first embodiment mainly in the layout of the second switch transistor. Fig. 12 is a schematic diagram showing a planar configuration of a semiconductor device according to the first modified example of the first embodiment. Fig. 12 mainly shows the parts of the first modified example that differ from the first embodiment, and omits illustration of other parts.

[0066] 12, in the first modification, a power supply line 6120 extending in the X direction is disposed on both the Y direction positive side and the Y direction negative side of the second power domain 31B in a plan view. Then, outside the region overlapping with the second power domain 31B in a plan view, a plurality of semiconductor layers 223 are formed so as to overlap with pairs of power supply lines 6110 and 6120 adjacent to each other in the Y direction in a plan view. A gate insulating film 224 (see FIG. 11) and a gate electrode 225 are formed on the semiconductor layer 223. The semiconductor layer 223, the gate insulating film 224, and the gate electrode 225 are included in the second switch transistor 52.

[0067] Further, a plurality of power supply lines 6110 extending in the X direction are arranged in a region overlapping with the second power domain 31B in a plan view. A power supply line 6120 extending in the X direction is arranged on an extension line of the power supply lines 6110 on both the positive side in the X direction and the negative side in the X direction of the second power domain 31B in a plan view. Then, a plurality of semiconductor layers 223 are formed outside the region overlapping with the second power domain 31B in a plan view, overlapping with pairs of the power supply lines 6110 and 6120 adjacent to each other in the X direction in a plan view. A gate insulating film 224 (see FIG. 11) and a gate electrode 225 are formed on the semiconductor layer 223. The semiconductor layer 223, the gate insulating film 224, and the gate electrode 225 are included in the second switch transistor 52.

[0068] A power supply line 5120 extending in the Y direction is disposed on both the positive side in the X direction and the negative side in the X direction of the second power domain 31B in a plan view. The power supply line 5120 is orthogonal to a plurality of power supply lines 6120 in a plan view, and the power supply line 5120 and the power supply line 6120 orthogonal to the power supply line 5120 are connected to each other through vias 5121.

[0069] 12, the via 7121, the control signal line 7120, and the like are omitted. That is, the via 7121, the control signal line 7120, and the like are arranged in each of the second switch transistors 52. Although not shown in FIG. 12, the first switch transistor 51 is connected between the power supply line 6110 and the power supply line 6160 adjacent to each other in the Y direction.

[0070] The other configuration is similar to that of the first embodiment.

[0071] The first modified example can also provide the same effects as the first embodiment.

[0072] The second switch transistor 52 does not need to be arranged on all of the positive side in the X direction, the negative side in the X direction, the positive side in the Y direction, and the negative side in the Y direction of the second power domain 31B. For example, the second switch transistor 52 may be arranged only on the positive side in the X direction and the negative side in the X direction of the second power domain 31B. Also, the second switch transistor 52 may be arranged only on the positive side in the Y direction and the negative side in the Y direction of the second power domain 31B.

[0073] Furthermore, a part of the power supply lines 6110 and 6120 does not have to be directly connected to the second switch transistor 52, and may be connected to the second switch transistor 52 via other wiring.

[0074] (Second Modification of the First Embodiment) Next, a second modified example of the first embodiment will be described. The second modified example differs from the first embodiment mainly in the layout of the second switch transistor. Fig. 13 is a schematic diagram showing a planar configuration of a semiconductor device according to the second modified example of the first embodiment. Fig. 13 mainly shows the parts of the second modified example that differ from the first embodiment, and the illustration of other parts is omitted.

[0075] 13, in the second modification, the ends of the power lines 6110 on the positive side in the X direction in the first modification are connected to each other, and the ends of the power lines 6110 on the negative side in the X direction in the first modification are connected to each other. That is, the power lines 6110 have a ladder-like planar shape. The power lines 6110 have a ring-shaped portion in a plan view, and a portion that extends in the X direction inside the ring-shaped portion and is connected to the ring-shaped portion. In addition, a power line 6120 that is ring-shaped in a plan view is disposed outside the ring-shaped portion of the power line 6110.

[0076] A semiconductor layer 223 that overlaps in a plan view with a pair of a part of the power supply lines 6110 and a part of the power supply lines 6120 adjacent to each other in the Y direction is formed to extend in the X direction. A gate insulating film 224 (see FIG. 11) and a gate electrode 225 that extend in the X direction are formed on the semiconductor layer 223. The semiconductor layer 223, the gate insulating film 224, and the gate electrode 225 are included in a second switch transistor 52.

[0077] Further, a semiconductor layer 223 overlapping in a plan view with a pair of a part of the power supply lines 6110 and a part of the power supply lines 6120 adjacent to each other in the X direction is formed so as to extend in the Y direction. A gate insulating film 224 (see FIG. 11) and a gate electrode 225 extending in the Y direction are formed on the semiconductor layer 223. The semiconductor layer 223, the gate insulating film 224, and the gate electrode 225 are included in the second switch transistor 52.

[0078] 13, the via 7121, the control signal line 7120, and the like are omitted. That is, the via 7121, the control signal line 7120, and the like are arranged in each of the second switch transistors 52. Although not shown in FIG. 13, the first switch transistor 51 is connected between the power supply line 6110 and the power supply line 6160 adjacent to each other in the Y direction.

[0079] The other configuration is similar to that of the first embodiment.

[0080] The second modified example can also provide the same effects as the first embodiment.

[0081] The power line 6110 may not have a ring-shaped portion, but may have a portion extending in the X direction and a portion extending in the Y direction, and the semiconductor layer 223 extending in the X direction and the semiconductor layer 223 extending in the Y direction may be disposed. The power line 6120 may not have a ring-shaped planar shape, but may have a portion extending in the X direction and a portion extending in the Y direction, and the semiconductor layer 223 extending in the X direction and the semiconductor layer 223 extending in the Y direction may be disposed.

[0082] Furthermore, the semiconductor layer 213, the gate insulating film 214, and the gate electrode 215 included in the first switch transistor 51 may extend in the X direction.

[0083] (Third Modification of the First Embodiment) Next, a third modified example of the first embodiment will be described. The third modified example differs from the first embodiment mainly in the configuration of the second wiring layer 22. Fig. 14 is a cross-sectional view showing a semiconductor device according to the third modified example of the first embodiment. Fig. 14 mainly shows the parts of the third modified example that differ from the first embodiment, and the illustration of the other parts is omitted.

[0084] As shown in FIG. 14, in the third modified example, the second wiring layer 22 further includes a third sub-wiring layer 203 below the second sub-wiring layer 202. That is, the third sub-wiring layer 203 is formed farther away from the first chip 10 than the second sub-wiring layer 202. The third sub-wiring layer 203 includes, for example, a power line 8110 and a power line 8120. The power line 8110 and the power line 8120 extend in the Y direction. The power line 8110 has a portion overlapping with the power line 6110 in a plan view. The power line 8120 has a portion overlapping with the power line 6120 in a plan view. In the insulating layer 25, a via 6111 connecting the power line 6110 and the power line 8110, and a via 6121 connecting the power line 6120 and the power line 8120 are formed. For example, the power supply line 8110 corresponds to the VDD wiring electrically connected to the first power supply pad 81, and the power supply line 8120 corresponds to the VDD wiring electrically connected to the second power supply pad .

[0085] In the insulating layer 25, a plurality of semiconductor layers 233 are formed that overlap the pair of adjacent power lines 8110 and 8120 in a plan view outside the region that overlaps with the second power domain 31B in a plan view. The semiconductor layer 233 is connected to the power lines 8110 and 8120. A gate insulating film 234 is formed on the semiconductor layer 233, and a gate electrode 235 is formed on the gate insulating film 234. The gate insulating film 234 contacts the semiconductor layer 233 and the gate electrode 235. The gate electrode 235 is located between the power line 8110 and the power line 8120 in a plan view. In the insulating layer 25, a via or the like (not shown) that connects the control signal line 7120 and the gate electrode 235 is formed. The semiconductor layer 233, the gate insulating film 234, and the gate electrode 235 are included in the second switch transistor 52.

[0086] The other configuration is similar to that of the first embodiment.

[0087] The third modification can also provide the same effects as those of the first embodiment. According to the third modification, the power supply potential can be further stabilized.

[0088] The semiconductor layer 233, the gate insulating film 234, and the gate electrode 235 do not necessarily have to be provided.

[0089] (Fourth Modification of the First Embodiment) Next, a fourth modified example of the first embodiment will be described. The fourth modified example differs from the first embodiment mainly in the configuration of the second wiring layer 22. Fig. 15 is a circuit diagram showing the configuration of an example of a circuit included in a semiconductor device according to the fourth modified example of the first embodiment. Fig. 15 mainly shows the parts of the fourth modified example that differ from the first embodiment, and omits illustration of other parts.

[0090] 15, in the fourth modified example, the second wiring layer 22 includes a first sub-wiring layer 201 and a second sub-wiring layer 202. A first switch transistor 51 and a third switch transistor 53 are arranged in the first sub-wiring layer 201. A second switch transistor 52 and a fourth switch transistor 54 are arranged in both the first sub-wiring layer 201 and the second sub-wiring layer 202.

[0091] The fourth modified example having such a circuit configuration can also provide the same effects as the first embodiment.

[0092] (Fifth Modification of the First Embodiment) Next, a fifth modified example of the first embodiment will be described. The fifth modified example differs from the first embodiment mainly in the configuration of the switch transistor. FIGS. 16 and 17 are schematic diagrams showing a planar configuration of a semiconductor device according to the fifth modified example of the first embodiment. FIG. 16 shows the internal configuration of the first chip 10 and the second chip 20, and FIG. 17 shows the internal configuration of the second chip 20. FIGS. 16 and 17 mainly show the parts of the fifth modified example that differ from the first embodiment, and the illustration of other parts is omitted.

[0093] 16 and 17, in the fifth modification, the second sub-wiring layer 202 has a power line 6130 extending in the X direction. For example, the power line 6130 corresponds to a VSS wiring. The power line 6130 is perpendicular to the power line 5130 in a plan view, and the power line 5130 and the power line 6130 perpendicular to the power line 5130 are connected to each other through a via 5131.

[0094] The first sub-wiring layer 201 has a power line 5170 extending in the Y direction. For example, the power line 5170 corresponds to a VDD wiring electrically connected to the first power pad 81. For example, the power line 5170 is perpendicular to the power line 6110, and the power line 5170 and the power line 6110 perpendicular to the power line 5170 are connected to each other through a via 5171.

[0095] In a region overlapping with the second power domain 31B in plan view, a control signal line 7110 is disposed between the power supply line 5160 and the power supply line 5170. The semiconductor layer 213 is formed above the power supply line 6130 so as to overlap with the power supply line 5160, the control signal line 7110, and the power supply line 5170 in plan view. Below the control signal line 7110, a gate insulating film 214 (see FIG. 11) and a gate electrode 215 are formed on the semiconductor layer 213. The gate electrode 215 is connected to the control signal line 7110 through a via 7111. The semiconductor layer 213 is connected to the power supply line 5160 through a via 5162 on the negative side in the X direction from the gate electrode 215, and is connected to the power supply line 5170 through a via 5172 on the positive side in the X direction from the gate electrode 215. The via 5162 is formed below the power supply line 5160, and the via 5172 is formed below the power supply line 5170.

[0096] Outside the region overlapping with the second power domain 31B in plan view, the control signal line 7120 is disposed between the power supply line 5120 and the power supply line 5170. The semiconductor layer 223 is formed to overlap with the power supply line 5120, the control signal line 7120, and the power supply line 5170 in plan view. Below the control signal line 7120, the gate insulating film 224 (see FIG. 11) and the gate electrode 225 are formed on the semiconductor layer 223. The gate electrode 225 is connected to the control signal line 7120 through a via 7121. The semiconductor layer 223 is connected to the power supply line 5120 through a via 5123 on the negative side in the X direction from the gate electrode 225, and is connected to the power supply line 5170 through a via 5173 on the positive side in the X direction from the gate electrode 225. The via 5123 is formed below the power supply line 5120, and the via 5173 is formed below the power supply line 5170.

[0097] The other configuration is similar to that of the first embodiment.

[0098] The fifth modified example can also provide the same effects as the first embodiment.

[0099] Note that a planar configuration such as the first modified example (see FIG. 12) or the second modified example (see FIG. 13) may be adopted. Also, the first switch transistor 51 and the second switch transistor 52 may be formed in the second sub-wiring layer 202.

[0100] (Sixth Modification of the First Embodiment) Next, a sixth modified example of the first embodiment will be described. The sixth modified example mainly differs from the first embodiment in that a fourth switch transistor is included. Fig. 18 is a schematic diagram showing a planar configuration of a semiconductor device according to the sixth modified example of the first embodiment. Fig. 18 mainly shows the parts of the sixth modified example that differ from the first embodiment, and the illustration of other parts is omitted.

[0101] The semiconductor device according to the sixth modification includes a fourth switch transistor 54 in addition to the first switch transistor 51 and the second switch transistor 52.

[0102] As shown in FIG. 18, in the sixth modified example, a power supply line 6220 extending in the X direction is arranged on both the Y direction positive side and the Y direction negative side of the second power domain 31B in a plan view. In addition, a plurality of power supply lines 6210 extending in the X direction are arranged in a region overlapping with the second power domain 31B in a plan view. The power supply lines 6210 and 6220 are included in the second sub-wiring layer 202. For example, the power supply line 6210 corresponds to a VSS wiring electrically connected to the third power supply pad 83, and the power supply line 6220 corresponds to a VSS wiring electrically connected to the fourth power supply pad 84. Then, a plurality of semiconductor layers 243 overlapping with the pair of the power supply lines 6210 and 6220 adjacent to each other in the Y direction in a plan view are formed outside the region overlapping with the second power domain 31B in a plan view. A gate insulating film (not shown) and a gate electrode 245 are formed on the semiconductor layer 243. The semiconductor layer 243, a gate insulating film (not shown), and a gate electrode 245 are included in the fourth switch transistor .

[0103] The first sub-wiring layer 201 has a power line 5220 extending in the Y direction. For example, the power line 5220 corresponds to a VSS wiring. The power line 5220 is orthogonal to a plurality of power lines 6210 in a plan view, and the power line 5220 and the power line 6210 orthogonal to the power line 5220 are connected through vias 5221.

[0104] 18, the via 7121, the control signal line 7120, etc. are omitted. That is, in each of the second switch transistors 52, the via 7121, the control signal line 7120, etc. are arranged. In the fourth switch transistor 54 in FIG. 18, the via and the control signal line, etc. connected to the gate electrode 245 are omitted. That is, in each of the fourth switch transistors 54, the via and the control signal line, etc. are arranged. In addition, although not shown in FIG. 18, the first switch transistor 51 is connected between the power supply line 6110 and the power supply line 6160 adjacent to each other in the Y direction.

[0105] The other configuration is similar to that of the first embodiment.

[0106] In the semiconductor device according to the sixth modified example thus configured, the first switch transistor 51 is turned off when it is not necessary to operate the standard cell 56. As a result, the power supply line 6160 (VVDD wiring) is insulated from the first power supply pad 81 and the second power supply pad 82, and the supply of power supply potential from the power supply line 6110 (VDD wiring) to the power supply line 6160 (VVDD wiring) is cut off (see FIGS. 8 to 11).

[0107] When the standard cell 56 is to be operated, the second switch transistor 52 and the fourth switch transistor 54 are turned off, and then the first switch transistor 51 is turned on. That is, a control signal for making the power supply line 6110 and the power supply line 6120 non-conductive is input to the gate electrode 225, a control signal for making the power supply line 6210 and the power supply line 6220 non-conductive is input to the gate electrode 245, and then a control signal for making the power supply line 6110 and the power supply line 6160 conductive is input to the gate electrode 215. As a result, the power supply line 6120 (VDD wiring) is insulated from the power supply line 6110 (VDD wiring) and the power supply line 6220 (VSS wiring) is insulated from the power supply line 6210 (VSS wiring), and then the power supply potential of VDD is supplied to the power supply line 6160 (VVDD wiring).

[0108] When the power supply potential of VDD is supplied to the power supply line 6160 (VVDD wiring), the standard cell 56 starts to operate. At this time, if both the second switch transistor 52 and the fourth switch transistor 54 are in the ON state, the power supply potential of VDD is also supplied from the second power pad 82 to the second power domain 31B, and noise occurs due to the sudden supply of the power supply potential, and this noise may reach the first power domain 31A. Such a sudden supply of the power supply potential is sometimes called a rush current. On the other hand, in this embodiment, since both the second switch transistor 52 and the fourth switch transistor 54 are in the OFF state, the influence of the rush current on the domain in operation can be suppressed. Also, since the second switch transistor 52 and the fourth switch transistor 54 are in the OFF state, the generation of noise can be suppressed more than when only either the second switch transistor 52 or the fourth switch transistor 54 is in the OFF state.

[0109] After the standard cell 56 starts to operate, when the fluctuation of the power supply potential of VDD supplied to the second power domain 31B settles down, the second switch transistor 52 and the fourth switch transistor 54 are turned on. That is, a control signal for establishing conduction between the power supply line 6110 and the power supply line 6120 is input to the gate electrode 225, and a control signal for establishing conduction between the power supply line 6210 and the power supply line 6220 is input to the gate electrode 245. As a result, a stable power supply potential of VDD is supplied to the first power domain 31A and the second power domain 31B.

[0110] In this way, the sixth modified example also makes it possible to suppress the generation of noise due to rush current.

[0111] In the other embodiments and modified examples, a fourth switch transistor 54 may be provided in addition to the second switch transistor 52. If the fourth switch transistor 54 is provided, the second switch transistor 52 does not need to be provided.

[0112] Furthermore, a third switch transistor 53 may be provided in addition to the first switch transistor 51. If the third switch transistor 53 is provided, the first switch transistor 51 does not need to be provided.

[0113] Second Embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the arrangement of the switch transistors. FIGS. 19 and 20 are schematic diagrams showing a planar configuration of a semiconductor device according to the second embodiment. FIGS. 21 and 22 are cross-sectional views showing a semiconductor device according to the second embodiment. FIG. 19 mainly shows the power lines on the upper layer side, and FIG. 20 mainly shows the power lines on the lower layer side. FIG. 21 corresponds to a cross-sectional view taken along the line Y13-Y23 in FIGS. 19 and 20, and FIG. 22 corresponds to a cross-sectional view taken along the line Y14-Y24 in FIGS. 19 and 20.

[0114] The semiconductor device according to the second embodiment is composed of a single chip 30. The chip 30 has a substrate 31 and a wiring layer 36 on the substrate 31. The wiring layer 36 includes an insulating layer 35 and a plurality of power lines and vias formed in the insulating layer 35.

[0115] The chip 30 includes a power supply line 2160 extending in the X direction and a power supply line 2170 extending in the X direction. For example, the power supply line 2160 corresponds to a VVDD wiring, and the power supply line 2170 corresponds to a VSS wiring. A plurality of pairs of the power supply lines 2160 and 2170 may be arranged alternately. The power supply lines 2160 and 2170 are arranged in the second power domain 31B.

[0116] The chip 30 includes a power supply line 1120 extending in the X direction and disposed on the negative side of the Y direction relative to the power supply lines 2160 and 2170, and a power supply line 1130 extending in the X direction. The power supply line 1120 is positioned closer to the power supply line 2170 than the power supply line 1130. For example, the power supply line 1120 corresponds to a VDD wiring electrically connected to the second power supply pad 82, and the power supply line 1130 corresponds to a VSS wiring.

[0117] As shown in FIGS. 21 and 22, a plurality of grooves extending in the X direction are formed in the substrate 31, and the power supply lines 2160, 2170, 1120 and 1130 are formed in these grooves.

[0118] Although not shown in FIGS. 19 to 22, circuits such as the standard cell 56 are connected between the power supply line 2160 and the power supply line 2170 in the second power domain 31B.

[0119] Also, although not shown in Figures 19 to 22, a first power domain 31A is arranged outside the second power domain 31B, and within the first power domain 31A, a first drive buffer 41, a second drive buffer 42, and circuits such as their control circuits are connected between a power line 1120 and a power line 1130.

[0120] The wiring layer 36 includes a control signal line 7310, a control signal line 7320, a power line 5320, a power line 5330, and a power line 5360. The control signal line 7310, the control signal line 7320, the power line 5320, the power line 5330, and the power line 5360 extend in the Y direction. The power line 5320 is perpendicular to the power line 1120 in a plan view, the power line 5330 is perpendicular to the power line 1130 or 2170 in a plan view, and the power line 5360 is perpendicular to the power line 2160 in a plan view. In the insulating layer 35, a via 1321 that connects the power line 5320 and the power line 1120 and a via 1331 that connects the power line 5330 and the power line 1130 are formed. A via 2371 that connects the power supply line 5330 and the power supply line 2170, and a via 2361 that connects the power supply line 5360 and the power supply line 2160 are formed in the insulating layer 35. The control signal line 7310 is perpendicular to the power supply lines 2160 and 2170 in a plan view.

[0121] A power line 6310 is formed above the power line 2170, and a power line 6360 is formed above the power line 2160. The power lines 6310 and 6360 extend in the X direction. In the insulating layer 35, in a region overlapping with the second power domain 31B in a planar view, a plurality of semiconductor layers 273 are formed that overlap with adjacent pairs of power lines 6310 and 6360 in a planar view. A gate insulating film 274 is formed under the semiconductor layer 273, and a gate electrode 275 is formed under the gate insulating film 274. The gate insulating film 274 contacts the semiconductor layer 273 and the gate electrode 275. The gate electrode 275 is located between the power line 6310 and the power line 6360 in a planar view. In the insulating layer 35, a via 6313 connecting the semiconductor layer 273 and the power line 6310, a via 6363 connecting the semiconductor layer 273 and the power line 6360, and a via 7311 connecting the control signal line 7310 and each gate electrode 275 are formed. The semiconductor layer 273, the gate insulating film 274, and the gate electrode 275 are included in the first switch transistor 51.

[0122] Between the power line 1120 and the power line 2170 in a plan view, a power line 6320 is formed in the same sub-wiring layer as the power lines 6310 and 6360. The power line 6320 extends in the X direction. In the insulating layer 35, outside the region overlapping with the second power domain 31B in a plan view, a plurality of semiconductor layers 283 are formed that overlap with the pair of adjacent power lines 6310 and 6320 in a plan view. A gate insulating film 284 is formed under the semiconductor layer 283, and a gate electrode 285 is formed under the gate insulating film 284. The gate insulating film 284 contacts the semiconductor layer 283 and the gate electrode 285. The gate electrode 285 is located between the power line 6310 and the power line 6320 in a plan view. In the insulating layer 35, a via 6313 connecting the semiconductor layer 283 and the power line 6310, a via 6323 connecting the semiconductor layer 283 and the power line 6320, and a via 7321 connecting the control signal line 7320 and each gate electrode 285 are formed. The semiconductor layer 283, the gate insulating film 284, and the gate electrode 285 are included in the second switch transistor 52.

[0123] A power line 4360 extending in the Y direction is formed between the power line 5360 and the power line 6360. In the insulating layer 35, a via 4361 connecting the power line 6360 and the power line 4360, and a via 5361 connecting the power line 4360 and the power line 5360 are formed.

[0124] A power line 4320 extending in the Y direction is formed between the power line 5320 and the power line 6320. In the insulating layer 35, a via 4321 connecting the power line 6320 and the power line 4320, and a via 5321 connecting the power line 4320 and the power line 5320 are formed.

[0125] A power supply line 4330 extending in the Y direction is formed above a plurality of power supply lines 5330 aligned in the Y direction. The power supply line 4330 is formed in the same sub-wiring layer as the power supply lines 4320 and 4360, for example. A via 5331 connecting the power supply line 4330 and the power supply line 5330 is formed in the insulating layer 35.

[0126] 19 and 20, a power supply line 8310 extending in the Y direction may be formed above the power supply lines 6310 and 6360, and a via 6311 connecting the power supply lines 8310 and 6310 may be formed. In addition, a power supply line 8320 may be formed above the power supply line 6320, and a via 6321 connecting the power supply lines 8320 and 6320 may be formed.

[0127] In the second embodiment as well, when the standard cell 56 is to be operated, the second switch transistor 52 is turned off, and then the first switch transistor 51 is turned on. That is, a control signal for bringing the power supply line 6310 and the power supply line 6320 into non-conduction is input to the gate electrode 285, and then a control signal for bringing the power supply line 6310 and the power supply line 6360 into conduction is input to the gate electrode 275.

[0128] When the power supply potential of VDD is supplied to the power supply line 6360 (VVDD wiring), the standard cell 56 starts to operate. At this time, in this embodiment, since the second switch transistor 52 is in the off state, rush current is suppressed and noise generation is suppressed.

[0129] After the standard cell 56 starts operating, when the fluctuation of the power supply potential of VDD supplied to the second power domain 31B settles down, the second switch transistor 52 is turned on. That is, a control signal for establishing conduction between the power supply line 6310 and the power supply line 6320 is input to the gate electrode 285. As a result, a stable power supply potential of VDD is supplied to the first power domain 31A and the second power domain 31B.

[0130] In this manner, the present embodiment also makes it possible to suppress the generation of noise associated with rush current.

[0131] Here, an overview of the cross-sectional configuration of the switch transistor will be described. Figures 23 to 25 are cross-sectional views showing examples of the cross-sectional configuration of the switch transistor.

[0132] In the first example shown in FIG. 23, a base insulating film 102 is provided in an insulating layer 101, and a semiconductor layer 103, a gate insulating film 104, and a gate electrode 105 are provided on the base insulating film 102. A control signal line 110, a power line 120 corresponding to a VDD wiring, and a power line 130 corresponding to a VVDD wiring are provided on a surface layer of the insulating layer 101. The semiconductor layer 103 has a channel 103C, and a source 103S and a drain 103D sandwiching the channel 103C. The power line 120 and the source 103S are connected via a via 121, and the power line 130 and the drain 103D are connected via a via 131. A power line 123 corresponding to a VDD wiring and a power line 133 corresponding to a VVDD wiring are provided under the base insulating film 102. The power line 120 and the power line 123 are connected via a via 122, and the power line 130 and the power line 133 are connected via a via 132. The control signal line 110 is connected to the gate electrode 105 through a via 111 .

[0133] 24, a gate insulating film 204 is provided on a base insulating film 102, a semiconductor layer 103 is provided on the gate insulating film 204, and a gate electrode 205 is provided under the gate insulating film 204. The other configurations are similar to those of the first example.

[0134] 25, a power supply line 123 is provided so as to be connected to the lower surface of a source 103S of a semiconductor layer 103, and a power supply line 133 is provided so as to be connected to the lower surface of a drain 103D of a semiconductor layer 103. A power supply line 120 is connected to the power supply line 123 through a via 121, and a power supply line 130 is connected to the power supply line 133 through a via 131. The other configurations are similar to those of the first example.

[0135] The material of the base insulating film is, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, etc. The material of the semiconductor layer is, for example, InGaZnO (IGZO), ZnO, ZnSnO, InZnO, etc. The material of the gate insulating film is, for example, SiO2, SiO x N y, SiN, Al2O3, etc. The material of the gate electrode is, for example, a metal such as molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, ruthenium, scandium, etc. The material of the gate electrode may be graphene, etc.

[0136] The first to fourth switch transistors 51 to 54 provided in each of the above-described embodiments can be classified into first to third examples from the viewpoint of the stacking relationship between the gate electrodes and the semiconductor layers and the connection relationship between the semiconductor layers and the VDD wiring, as follows. That is, the first to fourth switch transistors 51 to 54 provided in the first embodiment, the first to fourth modifications of the first embodiment, and the sixth modification of the first embodiment are classified into the third example. The first to fourth switch transistors 51 to 54 provided in the fifth modification of the first embodiment are classified into the first example. The first to fourth switch transistors 51 to 54 provided in the second embodiment are classified into the second example.

[0137] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0138] 10: First Chip 20: The second tip 31A, 31B: Power domain 41, 42, 43, 44: Driving buffer 51, 52, 53, 54: Switch transistor 56: Standard cell

Claims

1. A substrate; a first wiring layer formed on a first surface of the substrate; a second wiring layer disposed opposite to a second surface of the substrate opposite to the first surface; a first power supply line formed in the second wiring layer and supplied with a first power supply potential; a second power supply line formed in the second wiring layer and supplied with a second power supply potential; a third power supply line formed in the second wiring layer and supplied with a third power supply potential; a fourth power supply line formed on the first surface side and supplied with the first power supply potential; a fifth power supply line formed on the first surface side and supplied with the second power supply potential; a sixth power supply line formed on the first surface side and supplied with the third power supply potential; a seventh power supply line formed in the second wiring layer; a first via formed in the substrate and connecting the first power supply line and the fourth power supply line; a second via formed in the substrate and connecting the second power supply line and the fifth power supply line; a third via formed in the substrate and connecting the third power supply line and the sixth power supply line; a first switch connected between the first power supply line and the second power supply line; a first circuit connected between the fifth power supply line and the sixth power supply line; having the first power supply potential is supplied to the seventh power supply line, and a second switch is connected between the first power supply line and the seventh power supply line; or a third power supply potential being supplied to the seventh power supply line, and a second switch being connected between the third power supply line and the seventh power supply line.

2. 2. The semiconductor device according to claim 1, wherein the second switch is connected between the first power supply line and the seventh power supply line.

3. The second switch is a first terminal electrically connected to the first circuit; a second terminal electrically opposite the first terminal; having 3. The semiconductor device according to claim 2, further comprising a second circuit connected between the second terminal and the sixth power supply line.

4. The second circuit includes: a first drive buffer that controls the first switch; a second drive buffer that controls the second switch; 4. The semiconductor device according to claim 3, further comprising:

5. The second wiring layer includes: an eighth power supply line to which a fourth power supply potential is supplied; a ninth power supply line to which the third power supply potential is supplied; a third switch connected between the eighth power line and the ninth power line; a fourth switch connected between the third power line and the ninth power line; having 5. The semiconductor device according to claim 3, wherein the eighth power supply line is further connected between the first circuit and the sixth power supply line.

6. The fourth switch, a third terminal electrically connected to the first circuit; a fourth terminal electrically opposite the third terminal; and having 6. The semiconductor device according to claim 5, wherein the second circuit is connected between the second terminal and the fourth terminal.

7. The second circuit includes: a first drive buffer that controls the first switch; a second drive buffer that controls the second switch; a third drive buffer that controls the third switch; a fourth drive buffer that controls the fourth switch; 7. The semiconductor device according to claim 6, further comprising:

8. 8. The semiconductor device according to claim 1, wherein the third power supply line is a ground wiring to which a ground potential is supplied.

9. The first power supply line has a first wiring, the seventh power supply line has a second wiring, the second power supply line has a third wiring, the second switch is provided between the first wiring and the second wiring, The first switch is provided between the second wiring and the third wiring.

9. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

10. the first wiring and the second wiring extend in a first direction in a plan view, A plurality of the second switches are arranged along the first direction.

10. The semiconductor device according to claim 9.

11. the second wiring and the third wiring extend in the first direction in a plan view, the second wiring and the third wiring are arranged alternately in a second direction different from the first direction in a plan view; 11. The semiconductor device according to claim 10, wherein the first switch is a plurality of first switches arranged between the second wiring and the third wiring.

12. the third power supply line has a fourth wiring that is disposed above the first wiring, the second wiring, and the third wiring and extends in the second direction in a plan view; the first power supply line includes a fifth wiring that is connected to the first wiring, is disposed above the first wiring, and extends in the second direction in a plan view; the second power supply line includes a sixth line that is connected to the third line, that is disposed above the second line and the third line, and that extends in the second direction in a plan view; The fifth wiring is disposed on an extension line of the sixth wiring along the second direction.

12. The semiconductor device according to claim 11.

13. the first wiring is arranged to surround a first region including the first circuit in a plan view; The second wiring is disposed so as to overlap at least a portion of the first region in a plan view.

10. The semiconductor device according to claim 9.

14. the second wiring layer has a plurality of sub-wiring layers stacked on top of each other; The second switches are provided in the plurality of sub-wiring layers.

14. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

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