Pixel driving circuit and display panel

Abstract

In this application, a pixel driving circuit and a display panel are provided. The pixel driving circuit (100) includes a light emitting device (OLED), a driving transistor (M), a reset loop (L1), a pre-charge module (10) and a threshold compensation loop (L2). The driving transistor (M) is connected in series with the light emitting device (OLED). The reset loop (L1) is conductive in a reset stage to reset the control end of the driving transistor (M). The second capacitor (C2) is electrically connected with the control end of the first switch tube (T1). The pre-charge module (10) charges the voltage of the second capacitor (C2) to a first voltage in the reset stage. The voltage of the control end of the first switch tube (T1) continues to rise from the first voltage according to a first scanning signal, and the threshold compensation loop (L2) is accordingly conductive.

Description

[Technical field]

[0001] REFERENCE TO RELATED APPLICATIONS This application claims priority to China Patent Application No. 202210515982.2, filed on May 12, 2022, for the invention titled "Pixel Driving Circuit and Display Panel," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of display technology, in particular to pixel driving circuits and display panels. [Background technology]

[0003] The discussion herein provides only background information relevant to the present application and does not necessarily constitute prior art. Organic light-emitting diode (OLED) displays have the advantages of low power consumption, fast response speed, wide viewing angle, etc., and therefore the applications of OLED displays are becoming more and more widespread. OLED display devices can be divided into two types, passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), depending on the driving method.

[0004] In an AMOLED display panel, pixel driving circuits are arranged in an array. Early pixel driving circuits adopted a 2T1C structure, i.e., each pixel driving circuit has two transistors (T) and one capacitor (C). However, the transistors have a problem of threshold voltage drift. To solve the problem of threshold voltage drift of transistors, pixel driving circuits of types such as 5T2C, 7T1C, and 8T1C that adopt threshold voltage compensation have been derived. However, because a threshold voltage compensation stage is added to the scanning period of each frame, the scanning period of one frame is long and the charging speed of the pixel driving circuit is slow, which is disadvantageous for realizing a high refresh rate. Summary of the Invention

[0005] In the present application, a pixel driving circuit is provided. The pixel driving circuit includes a light emitting element, a driving transistor, a reset loop, a first capacitor, a first switch tube, a second capacitor, a precharge module, and a threshold compensation loop. The first end of the light emitting element is electrically connected to a reference voltage end, and the pixel driving circuit is configured to drive the light emitting element to emit light. The driving transistor is electrically connected to a second end of the light emitting element. The first capacitor is connected in series in the reset loop, and the first end of the first capacitor is electrically connected to a control end of the driving transistor. The reset loop is conductive in a reset stage and receives a reset voltage to charge the first capacitor, thereby increasing the voltage of the first end of the first capacitor, thereby resetting the voltage of the control end of the driving transistor to the reset voltage through the first capacitor. The first switch tube is connected in parallel with both ends of the light emitting element. The first end of the second capacitor is electrically connected to the control end of the first switch tube. The pre-charge module is electrically connected to the first end of the second capacitor and configured to charge the second capacitor in the reset stage to raise the voltage of the first end of the second capacitor to a first voltage, the first voltage being lower than the sum of the voltage of the reference voltage end and the threshold voltage of the first switch tube. The threshold compensation loop includes a first capacitor, a driving transistor, and a first switch tube electrically connected in series, the second capacitor continues to charge according to the first scanning signal in the threshold compensation stage, the voltage of the control end of the first switch tube continues to rise from the first voltage accordingly, as a result, the first switch tube becomes conductive, and the threshold compensation loop becomes conductive. The first capacitor discharges through the conductive threshold compensation loop, the voltage of the control end of the driving transistor accordingly decreases from the reset voltage to a second voltage, and the driving transistor is in a critical conductive state when the voltage of its control end is equal to the second voltage, and the second voltage is equal to or lower than the reset voltage.

[0006] In the pixel driving circuit provided in the present application, the voltage of the first end of the second capacitor is precharged to a first voltage through the precharge module in the reset stage, so that the second capacitor can continue to be charged from the first voltage after receiving the first scanning signal, and does not need to start charging from the initial low level, thereby shortening the time of the threshold compensation stage, i.e., shortening the time of the scanning period per frame, which is favorable for realizing a high refresh rate.

[0007] In the present application, a display panel is further provided. The display panel includes a substrate and a pixel driving circuit. The substrate includes a display area, and several pixel driving circuits are arranged in an array in the display area of ​​the substrate. The pixel driving circuit includes a light-emitting element, a driving transistor, a reset loop, a first capacitor, a first switch tube, a second capacitor, a precharge module, and a threshold compensation loop. A first end of the light-emitting element is electrically connected to a reference voltage end, and the pixel driving circuit is configured to drive the light-emitting element to emit light. The driving transistor is electrically connected to a second end of the light-emitting element. The first capacitor is connected in series in the reset loop, and the first end of the first capacitor is electrically connected to a control end of the driving transistor. The reset loop is conductive in a reset stage, and receives a reset voltage to charge the first capacitor, thereby increasing the voltage of the first end of the first capacitor, and thereby resetting the voltage of the control end of the driving transistor to the reset voltage through the first capacitor. The first switch tube is connected in parallel with both ends of the light-emitting element. The first end of the second capacitor is electrically connected to the control end of the first switch tube. The pre-charge module is electrically connected to the first end of the second capacitor and configured to charge the second capacitor in a reset stage to raise the voltage of the first end of the second capacitor to a first voltage, the first voltage being lower than the sum of the voltage of the reference voltage end and the threshold voltage of the first switch tube. The threshold compensation loop includes a first capacitor, a driving transistor, and a first switch tube electrically connected in series, the second capacitor continues to charge according to the first scanning signal in the threshold compensation stage, the voltage of the control end of the first switch tube continues to rise from the first voltage accordingly, as a result, the first switch tube becomes conductive, and the threshold compensation loop becomes conductive. The first capacitor discharges through the conductive threshold compensation loop, the voltage of the control end of the driving transistor accordingly decreases from the reset voltage to a second voltage, and the driving transistor is in a critical conductive state when the voltage of its control end is equal to the second voltage, and the second voltage is equal to or lower than the reset voltage.

[0008] Additional aspects and advantages of the present application will be set forth in part in the description that follows, and in part will be apparent from the description, or may be learned by practice of the present application. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram showing the structure of a display panel according to an embodiment of the present application. [Diagram 2] FIG. 2 is a schematic diagram showing the structure of a first type pixel driving circuit according to an embodiment of the present application. [Diagram 3] FIG. 3 is a timing chart showing the operation of the pixel driving circuit shown in FIG. [Figure 4a] FIG. 4a is a circuit schematic diagram of the pixel driving circuit shown in FIG. 2 at stage t12. [Figure 4b] FIG. 4b is a circuit schematic diagram of the pixel driving circuit shown in FIG. 2 at stage t2. [Figure 4c] FIG. 4c is a circuit schematic diagram of the pixel driving circuit shown in FIG. 2 at stage t3. [Figure 4d] FIG. 4d is a circuit schematic diagram of the pixel driving circuit shown in FIG. 2 at stage t4. [Diagram 5] FIG. 5 is a schematic diagram showing the structure of a second type pixel driving circuit according to an embodiment of the present application. [Figure 6] FIG. 6 is a timing chart showing the operation of the pixel driving circuit shown in FIG. [Figure 7] FIG. 7 is a schematic diagram showing the structure of a third type pixel driving circuit according to an embodiment of the present application. [Figure 8] FIG. 8 is a timing chart showing the operation of the pixel driving circuit shown in FIG.

[0010] Specific embodiments of the present application are further described below in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the technical solutions of the embodiments of the present application will be described clearly and comprehensively with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments that a person skilled in the art can obtain without creative efforts all belong to the protection scope of the present application.

[0012] In the description of this application, the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", etc. are directions or positional relationships indicated based on the drawings, and are merely for the purpose of explaining and simplifying the description of this application, and are not intended to indicate or imply that the indicated devices or elements necessarily have a specific direction, are constructed or operate in a specific direction, and therefore cannot be understood as limitations on this application. In addition, the terms "first", "second", etc. are used for explanation purposes only, and cannot be understood as indicating or implying relative importance.

[0013] Referring to FIG. 1, the present application provides a display panel 1 including a substrate 1000. The substrate 1000 has a display area 1001 and a non-display area 1002. A number of pixel driving circuits 100 arranged in an array are provided in the display area 1001, and each pixel driving circuit 100 constitutes one pixel unit. A scanning signal generating circuit 110 (also called a gate driver) is provided in the non-display area 1002. The scanning signal generating circuit 110 is electrically connected to the pixel driving circuits 100 of each row via a number of scanning lines 111, and is configured to generate a number of scanning signals corresponding to the pixel driving circuits 100 of each row.

[0014] In an embodiment of the present application, the display panel 1 further includes a data signal generation circuit 120 (also referred to as a source driver). The data signal generation circuit 120 is electrically connected to the pixel driving circuits 100 of each row via a plurality of data lines 121. The data signal generation circuit 120 is configured to generate one data signal DATA corresponding to the pixel driving circuit of each column, and output the data signal DATA to each pixel driving circuit 100 of the pixel driving circuit of the column.

[0015] Specifically, referring to FIG. 2, the pixel driving circuit 100 includes a light-emitting element. The pixel driving circuit 100 is configured to drive the light emission of the light-emitting element. In an embodiment of the present application, the light-emitting element is an organic light-emitting diode (OLED), and the first end and the second end of the light-emitting element correspond one-to-one to the cathode and the anode of the OLED. In another embodiment, the light-emitting element may be a light-emitting diode (LED), and may be a micro LED (MicroLED) or a mini LED (MiniLED).

[0016] Next, the circuit configuration and operation principle of the pixel driving circuit 100 will be described in conjunction with FIG. 3 and FIG. 4a to FIG. 4d.

[0017] As shown in FIG. 3, the pixel driving circuit 100 operates in the order of a reset stage (tl stage), a threshold compensation stage (t2 stage), a data writing stage (t3 stage), and a light emission stage (t4 stage) in one frame scanning period.

[0018] As shown in FIG. 4(a), the pixel driving circuit 100 includes a reset loop L1. The reset loop L1 includes a third switch tube T3, a fourth switch tube T4, a first capacitor C1, and a fifth switch tube T5, which are connected in series. Specifically, the first connection end of the third switch tube T3 is configured to receive a reset voltage V0 in a reset stage. The second connection end of the third switch tube T3 is electrically connected to the first connection end (i.e., the drain electrode) of the driving transistor M and the first connection end of the fourth switch tube T4, respectively. The second connection end of the fourth switch tube T4 is electrically connected to the control end (i.e., the gate electrode) of the driving transistor M and the first end of the first capacitor C1. The second end of the first capacitor C1 is electrically connected to the first connection end of the fifth switch tube T5. The second connection end of the fifth switch tube T5 is electrically connected to the reference voltage end VSS. In the embodiment of the present application, the connection node between the control end of the driving transistor M and the first end of the first capacitor C1 is denoted as a first node G1. The reference voltage terminal VSS is configured to output a reference voltage VSS. In the embodiment of the present application, the potential of the reference voltage VSS is a low level, for example, the ground potential.

[0019] 4d, the pixel driving circuit 100 further includes a light emitting loop L4. The light emitting loop L4 includes a third switch tube T3, a driving transistor M, and a light emitting element OLED, which are connected in series in order. A first end of the light emitting element OLED is electrically connected to the reference voltage terminal VSS, and a second end of the light emitting element OLED is electrically connected to the second connection terminal (i.e., the source electrode) of the driving transistor M.

[0020] As shown in FIG. 4a, in the reset stage, the third switch tube T3 is turned on according to the second scanning signal SCAN2 received at its control end, the fourth switch tube T4 is turned on according to the third scanning signal SCAN3 received at its control end, and the fifth switch tube T5 is turned on according to the third scanning signal SCAN3 received at its control end, so that the reset loop L1 is turned on and receives the reset voltage V0 to charge the first capacitor C1, thereby increasing the voltage at the first end of the first capacitor C1, thereby resetting the voltage at the control end of the driving transistor M to the reset voltage V0 through the first capacitor C1. At this time, the gate voltage Vg of the driving transistor M is V0, and the source voltage Vs is V 0LED Therefore, the driving transistor M becomes conductive when the gate-source voltage Vgs is greater than its threshold voltage Vth1. The driving transistor M and the switch tubes T3 to T5 are all transistors that are conductive at a high level, for example, n-type metal-oxide-semiconductor (NMOS) transistors. Of course, in other embodiments, transistors that are conductive at a low level, for example, p-type metal-oxide-semiconductor (PMOS) transistors, may be used as each of the transistors. As each of the transistors, an amorphous silicon thin film transistor (a-Si TFT), a low-temperature polycrystalline silicon TFT (LTPS TFT), or an oxide semiconductor thin film transistor (oxide TFT) can be used. Of these, an oxide semiconductor (oxide) such as indium gallium zinc oxide (IGZO) can be used as the active layer of the oxide TFT. The second scanning signal SCAN2 and the third scanning signal SCAN3 are both high level signals.

[0021] In the reset stage, the third switch tube T3 and the driving transistor M are conductive, so that the light emitting loop L4 is conductive, and the light emitting element OLED emits light for a short period of time, which is too short to be perceived by the naked eye.

[0022] In addition, since each scan line is long in an actual product and resistance-capacitance loading (RC loading) occurs, when the scan signal generating circuit 110 switches from outputting a low level signal to outputting a high level signal to the pixel driving circuit 100 through the scan line, it must first charge the scan line, that is, a certain charging time is required for the voltage on the scan line to rise from a low level to a high level. Similarly, when the scan signal generating circuit 110 switches from outputting a high level signal to outputting a low level signal to the pixel driving circuit 100 through the scan line, it must first discharge the scan line, that is, a certain discharging time is required for the voltage on the scan line to fall from a high level to a low level. Therefore, the scan signal received by the pixel driving circuit 100 is not an ideal square wave but a trapezoidal wave as shown in FIG. 3.

[0023] In an embodiment of the present application, the pixel driving circuit 100 further includes a first switch tube T1, a second capacitor C2, and a pre-charge module 10. The first switch tube T1 is electrically connected in parallel with both ends of the light emitting element OLED. A first end of the second capacitor C2 is electrically connected to the control end of the first switch tube T1, and a second end of the second capacitor C2 is electrically connected to the reference voltage end VSS. The pre-charge module 10 is configured to pre-charge C2 in a reset stage. Specifically, the pre-charge module 10 is configured to receive a charging voltage VAA during a preset period of the reset stage to charge the second capacitor C2, so that the voltage of the first end of the second capacitor C2 rises to a first voltage V1. The first voltage V1 is lower than the sum of the voltage VSS of the reference voltage end and the threshold voltage Vth2 of the first switch tube T1. In other words, the gate-source voltage V1-VSS of the first switch tube T1 is lower than the threshold voltage Vth2. Accordingly, the first switch tube T1 continues to be in the off state during the reset stage, preventing a short circuit of the display panel 1. Note that the first switch tube T1 is a transistor that conducts at a high level, for example, an NMOS.

[0024] The pre-charge module 10 includes a second switch tube T2 and a conduction signal generating module 101. In the embodiment of the present application, the connection node between the control end of the second switch tube T2 and the first end of the second capacitor C2 is referred to as a second node G2.

[0025] The first connection end of the second switch tube T2 is configured to receive the charging voltage VAA, and the second connection end of the second switch tube T2 is electrically connected to the control end of the first switch tube T1. The conduction signal generating module 101 is configured to generate a conduction signal during a preset period of the reset stage to make the second switch tube T2 conductive, and the second capacitor C2 is charged by receiving the charging voltage VAA through the conductive second switch tube T2, and the voltage of the first end of the second capacitor C2 is charged to the first voltage V1.

[0026] In this embodiment, the t1 stage includes three stages, t11, t12 and t13. The conduction signal generating module 101 includes a T flip-flop U1. The clock signal end c1 of the T flip-flop U1 is configured to receive the first clock signal CP1 during a preset period of the reset stage. The input end 1T of the T flip-flop U1 is configured to receive a high-level voltage. The output end Q of the T flip-flop U1 is electrically connected to the control end of the second switch tube T2. In the embodiment of the present application, the input end 1T of the T flip-flop U1 is electrically connected to the first connection end of the third switch tube T3 through a resistor R and configured to receive a high-level voltage. The duration of the first clock signal CP1 is two preset clock periods, that is, the first clock signal CP1 comprises a pulse signal of two clock periods. The resistor R is a current-limiting resistor for protecting the T flip-flop U1. Exemplarily, the resistor R has a resistance value of 100Ω to 1KΩ.

[0027] At the stage t11, the input terminal 1T of the T flip-flop U1 receives a high-level voltage, and when there is no input of a pulse signal, the output terminal Q of the T flip-flop U1 outputs a low level, and the second switch tube T2 is turned off accordingly. When the first pulse signal of the first clock signal CP1 arrives, the T flip-flop U1 enters the stage t12 and outputs a conducting signal through its output terminal Q, so that the second switch tube T2 is turned on. When the second pulse signal of the first clock signal CP1 arrives, the T flip-flop U1 enters the stage t13 and stops outputting the conducting signal, so that the second switch tube T2 is turned off. At the stage t12, the second switch tube T2 is turned on and draws the charging voltage VAA to charge the second capacitor, so that the voltage at the first terminal of the second capacitor C2 rises to the first voltage V1. At the stages t11, t13, and t2 to t4, the second switch tube T2 maintains the off state. In the embodiment of the present application, the second switch tube T2 is a transistor that is conductive at a high level, and the conductive signal is a high-level signal. Note that, in the t12 stage, charging the voltage at the first end of the second capacitor C2 to the preset first voltage V1 can be achieved by adjusting the voltage value of the charging voltage VAA and / or adjusting the period of the first clock signal CP1. Note that, in other embodiments, the t1 stage may include only the t12 stage, may include only the t11 stage and the t12 stage, or may include only the t12 stage and the t13 stage, and is not limited here.

[0028] 4(b), the pixel driving circuit 100 further includes a threshold compensation loop L2. The threshold compensation loop L2 includes a fifth switch tube T5, a first capacitor C1, a fourth switch tube T4, a driving transistor M and a first switch tube T1 connected in series in this order.

[0029] In the threshold compensation step, the fourth switch tube T4 is turned on according to the third scanning signal SCAN3 received at its control end, and the fifth switch tube T5 is turned on according to the third scanning signal SCAN3 received at its control end. The second capacitor C2 continues to charge according to the first scanning signal SCAN1, so that the voltage at the control end of the first switch tube T1 continues to rise from the first voltage V1, and when the drain-source voltage of the first switch tube T1 is higher than its threshold voltage Vth2 (i.e., when the voltage at the control end of the first switch tube T1 is higher than VSS+Vth2), the first switch tube T1 is turned on, and the threshold compensation loop L2 is turned on. The first capacitor C1 is discharged through the conductive threshold compensation loop L2, so that the voltage of the control end (i.e., the first node G1) of the driving transistor M gradually decreases from the reset voltage V0 to the second voltage V2 (at this time, the gate-source voltage Vgs of the driving transistor M=Vth1), and thus the driving transistor M enters a critical conduction state, at which point the voltage of the first end of the first capacitor C1 is maintained at the second voltage V2, thereby compensating for the threshold voltage of the driving transistor M. Here, the second voltage V2 is less than the reset voltage V0, V2=VSS+Vth1. During the threshold compensation stage, the light emitting element OLED is short-circuited by the conductive first switch tube T1 and does not emit light.

[0030] The pixel driving circuit 100 provided in the present application precharges the voltage at the first end of the second capacitor C2 to the first voltage V1 through the precharge module 10 in the reset stage. Therefore, the second capacitor C2 can continue to charge from the first voltage V1 when receiving the first scan signal SCAN1, and does not need to start charging from an initial low level (e.g., 0V). In this way, the duration of the t2 stage can be shortened by Δt, i.e., the scanning period per frame can be shortened by Δt, which is advantageous for realizing a high refresh rate.

[0031] As shown in FIG. 4c, the pixel driving circuit 100 further includes a data write loop L3. The data write loop L3 includes a sixth switch tube T6 and a first capacitor C1 electrically connected in series. A first connection end of the sixth switch tube T6 is configured to receive a data signal DATA, and a second connection end of the sixth switch tube T6 is electrically connected to the second end of the first capacitor C1. The voltage of the data signal DATA is a data voltage V DATA It is.

[0032] In the data writing stage, the switch tubes T1 to T5 are all turned off, and the sixth switch tube T6 is turned on according to the fourth scanning signal SCAN4 received at its control end, so that the data writing loop L3 is turned on, and the voltage at the second end of the first capacitor C1 becomes the data voltage V DATA In the data writing stage, the voltage at the second end of the first capacitor C1 is increased by V DATA -VSS, and due to the coupling effect of the first capacitor C1, the change in voltage at the first end of the first capacitor C1 is equal to the change in voltage at the second end of the first capacitor C1, so the voltage at the first end of the first capacitor C1 rises to a third voltage V3, V3=(V DATA -VSS) + V2 = V DATA +Vth1 The fourth scan signal SCAN4 is a high level signal.

[0033] As shown in Fig. 4d, in the light-emitting stage, the third switch tube T3 is turned on according to the second scanning signal SCAN2 received at its control end, and receives the driving voltage VDD through the first connection end, so that the light-emitting loop L4 is turned on and drives the light-emitting element OLED to emit light by the received driving voltage VDD. In this embodiment, the reset voltage V0 received by the third switch tube T3 in the reset stage is equal to the driving voltage VDD received by the third switch tube T3 in the light-emitting stage. In another embodiment, the reset voltage V0 may be smaller than the driving voltage VDD.

[0034] Specifically, in the light emission stage, the gate voltage of the driving transistor M is Vg=V3=V DATA +Vth1, its source voltage Vs=VSS+V OLED , and the gate-source voltage Vgs=Vg-Vs=V DATA +Vth1-VSS-V OLED >Vth1, so that the drive transistor M becomes conductive.

[0035] In addition, in the embodiment of the present application, in the light emitting stage, the third switch tube T3 operates in a linear region and the driving transistor M operates in a saturation region, so that the magnitude of the current flowing through the light emitting element OLED mainly depends on the current Ids between the source electrode and the drain electrode of the driving transistor M. From the operating characteristics of the transistor, it can be seen that the current Ids and the gate-source voltage Vgs have the following relationship: Ids=(K / 2)(Vgs-Vth1). 2 =(K / 2)(V DATA -VSS-V OLED ) 2 where K=Cox×μ×W / L, where Cox is the gate capacitance per unit area, μ is the electron mobility in the channel, and W / L is the width-to-length ratio of the channel of the drive transistor M.

[0036] As can be seen from the above formula, the threshold compensation loop L3 can compensate the voltage of the control end of the driving transistor M to the second voltage V2 in the threshold compensation step. As a result, the current Ids flowing through the light emitting element OLED is independent of the threshold voltage Vth1 of the driving transistor M. Therefore, the current Ids can be increased to increase the luminance of the light emitting element OLED, while uneven display luminance caused by the difference in the threshold voltage Vth1 of the driving transistor M of different driving circuits can be eliminated.

[0037] 5-6, FIG. 5 is a schematic diagram showing the structure of a second type pixel driving circuit 100 according to an embodiment of the present application. FIG. 6 is a timing chart showing the operation of the pixel driving circuit 100 shown in FIG. 5. The pixel driving circuit 100 shown in FIG. 5 has a circuit configuration similar to that of the pixel driving circuit 100 shown in FIG. 3, but differs in that the conductive signal generating module 101 shown in FIG. 5 includes a D flip-flop U2 and an inverter D1. Compared with the T flip-flop U1, the D flip-flop U2 needs to receive a pulse signal of three clock cycles, but the circuit configuration of the D flip-flop U2 is simpler. In another embodiment, the conductive signal generating module 101 may adopt a JK flip-flop, but is not limited thereto.

[0038] Specifically, the clock signal end c1 of the D flip-flop U2 is configured to receive the second clock signal CP2 during the preset period of the reset stage. The output end Q of the D flip-flop U2 is electrically connected to the control end of the second switch tube T2. The input end of the inverter D1 is electrically connected to the output end Q of the D flip-flop U2. The output end of the inverter D1 is electrically connected to the input end D of the D flip-flop U2. In the embodiment of the present application, the duration of the second clock signal CP2 is three preset clock periods, that is, the second clock signal CP2 comprises a pulse signal of three clock periods.

[0039] At time t11, before receiving the second clock signal CP2, the D flip-flop U2 does not output a signal from its output end Q, and the second switch tube T2 is turned off. When the rising edge of the first pulse signal of the second clock signal CP2 arrives, the D flip-flop U2 outputs a low level signal through its output end Q according to the low level of its input end D, so that the second switch tube T2 remains in the off state. At the same time, the inverter D1 inverts the phase of the low level signal to obtain a high level signal, which is output to the input end D of the D flip-flop U2.

[0040] When the rising edge of the second pulse signal of the second clock signal CP2 arrives, the D flip-flop U2 enters the phase t12 and outputs a conducting signal through its output end Q according to the high level of its input end D, so that the second switch tube T2 is conducting. At the same time, the inverter D1 inverts the phase of the conducting signal to obtain a low level signal, which is output to the input end D of the D flip-flop U2.

[0041] When the rising edge of the third pulse signal of the second clock signal CP2 arrives, the D flip-flop U2 enters the stage t13, and outputs a low level signal through its output end Q according to the low level of its input end D, so that the second switch tube T2 is turned off.

[0042] 7 to 8, Fig. 7 is a schematic diagram showing a structure of a third type pixel driving circuit 100 according to an embodiment of the present application. Fig. 8 is a timing chart showing the operation of the pixel driving circuit 100 shown in Fig. 7. The pixel driving circuit 100 shown in Fig. 7 has a circuit configuration similar to that of the pixel driving circuit 100 shown in Fig. 3, except that the light emitting loop L4 further includes a seventh switch tube T7 electrically connected in series between the driving transistor M and the light emitting element OLED.

[0043] Specifically, the circuit in which the seventh switch tube T7 and the light-emitting element OLED are connected in series is electrically connected in parallel with the first switch tube T1, that is, the first connection end of the seventh switch tube T7 is electrically connected to the second connection end of the driving transistor M, and the second connection end of the seventh switch tube T7 is electrically connected to the anode of the light-emitting element OLED.

[0044] In the reset stage, the seventh switch tube T7 is turned off, and therefore the light-emitting loop L4 is turned off, so that the light-emitting element OLED can be prevented from emitting light in the reset stage, and the display effect of the display panel 1 can be improved.

[0045] In the light-emitting stage, the seventh switch tube T7 is turned on according to the fifth scanning signal SCAN5 received at its control end, so that the light-emitting loop L4 is turned on. The fifth scanning signal SCAN5 is a high level signal.

[0046] Although the embodiments of the present application have been shown and described above, it will be understood by those skilled in the art that various modifications, alterations, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is limited by the claims and their equivalents.

Claims

1. A pixel driving circuit, comprising: a light emitting element, a driving transistor, a reset loop, a first capacitor, a first switch tube, a second capacitor, a pre-charge module, and a threshold compensation loop; A first terminal of the light-emitting element is electrically connected to a reference voltage terminal, and the pixel driving circuit is configured to drive the light-emitting element to emit light; the driving transistor is electrically connected to a second terminal of the light emitting element; The first capacitor is connected in series in the reset loop, and a first end of the first capacitor is electrically connected to the control end of the driving transistor, and the reset loop is conductive in a reset stage and receives a reset voltage to charge the first capacitor, thereby increasing the voltage of the first end of the first capacitor, thereby resetting the voltage of the control end of the driving transistor to the reset voltage via the first capacitor; The first switch tube is connected in parallel to both ends of the light emitting element, a first end of the second capacitor electrically connected to a control end of the first switch tube; the pre-charge module is electrically connected to the first end of the second capacitor and configured to charge the second capacitor in the reset stage to raise a voltage of the first end of the second capacitor to a first voltage, the first voltage being lower than a sum of a voltage of the reference voltage end and a threshold voltage of the first switch tube; the threshold compensation loop comprises the first capacitor, the driving transistor and the first switch tube electrically connected in series, the second capacitor continues to charge according to a first scanning signal in a threshold compensation stage, the voltage of the control end of the first switch tube continues to rise from the first voltage accordingly, so that the first switch tube becomes conductive, thereby making the threshold compensation loop conductive, the first capacitor discharges through the conductive threshold compensation loop, the voltage of the control end of the driving transistor correspondingly drops from the reset voltage to a second voltage, and the driving transistor is in a critical conductive state when the voltage of its control end is equal to the second voltage, and the second voltage is equal to or less than the reset voltage; 2. A pixel drive circuit comprising:

2. The pre-charge module includes a second switch tube and a conduction signal generating module; A first connection end of the second switch tube is configured to receive a charging voltage, and a second connection end of the second switch tube is electrically connected to a control end of the first switch tube; the conduction signal generating module is electrically connected to a control end of the second switch tube, and the conduction signal generating module is configured to generate a conduction signal during a preset period of the reset step to make the second switch tube conductive, and the second capacitor is charged by receiving the charging voltage through the conductive second switch tube, so that a voltage of a first end of the second capacitor is charged to the first voltage; 2. The pixel driving circuit according to claim 1 .

3. the conduction signal generating module comprises a T flip-flop, a clock signal end of the T flip-flop is configured to receive a first clock signal during the preset period of the reset stage, an input end of the T flip-flop is configured to receive a high-level voltage, an output end of the T flip-flop is electrically connected to the control end of the second switch tube, and a duration of the first clock signal is twice the preset clock period; the T flip-flop is configured to generate and output the conduction signal during a preset period of the reset stage in response to the first clock signal; 3. The pixel driving circuit according to claim 2.

4. The conduction signal generating module includes a D flip-flop and an inverter; a clock signal end of the D flip-flop is configured to receive a second clock signal during a preset period of the reset step, an output end of the D flip-flop is electrically connected to a control end of the second switch tube, and a duration of the second clock signal is three times the preset clock period; an input terminal of the inverter is electrically connected to an output terminal of the D flip-flop, and an output terminal of the inverter is electrically connected to an input terminal of the D flip-flop; the D flip-flop is configured to generate and output the conduction signal during a preset period of the reset stage in response to the second clock signal; 3. The pixel driving circuit according to claim 2.

5. the reset loop further comprises a third switch tube, a fourth switch tube and a fifth switch tube connected in series; a first connection end of the third switch tube configured to receive the reset voltage in the reset stage, and a second connection end of the third switch tube electrically connected to the driving transistor; the fourth switch tube is electrically connected between the second connection end of the third switch tube and the control end of the driving transistor; the fifth switch tube is electrically connected between the second end of the first capacitor and the reference voltage end; 2. The pixel driving circuit according to claim 1 .

6. In the reset stage, the third switch tube is made conductive according to the second scanning signal received at its control end, the fourth switch tube is made conductive according to the third scanning signal received at its control end, and the fifth switch tube is made conductive according to the third scanning signal received at its control end, so that the reset loop is made conductive.

6. A pixel driving circuit as claimed in claim 5.

7. the threshold compensation loop further comprises the fourth switch tube and the fifth switch tube; 7. A pixel driving circuit according to claim 6.

8. In the threshold compensation step, the fourth switch tube is made conductive according to the third scanning signal received at its control end, and the fifth switch tube is made conductive according to the third scanning signal received at its control end, so that the reset loop is made conductive.

8. A pixel driving circuit as claimed in claim 7.

9. The pixel driving circuit further comprises a data writing loop, the data writing loop comprising a sixth switch tube and the first capacitor electrically connected in series, a first connection end of the sixth switch tube configured to receive a data voltage, and a second connection end of the sixth switch tube electrically connected to a second end of the first capacitor.

9. A pixel driving circuit as claimed in claim 8.

10. In a data writing stage, the fifth switch tube is turned off, and the sixth switch tube is turned on according to a fourth scanning signal received at its control end, so that the data writing loop is turned on and the voltage of the second end of the first capacitor is increased to the data voltage; 10. A pixel driving circuit as claimed in claim 9.

11. The pixel driving circuit further includes a light emitting loop, the light emitting loop including the third switch tube, the driving transistor and the light emitting element connected in series.

11. A pixel driving circuit as claimed in claim 10.

12. In a light emitting stage, the third switch tube is turned on according to the second scanning signal received at its control end, so that the light emitting loop is turned on and receives a driving voltage to drive the light emitting element to emit light.

12. A pixel driving circuit as claimed in claim 11.

13. The light emitting loop further includes a seventh switch tube electrically connected in series between the driving transistor and the light emitting element, and the seventh switch tube and the light emitting element are connected in series to form a circuit, and the seventh switch tube and the light emitting element are electrically connected in parallel to the first switch tube.

13. A pixel driving circuit as claimed in claim 12.

14. In the reset stage, the seventh switch tube is turned off, so that the light emitting loop is turned off; 14. A pixel driving circuit as claimed in claim 13.

15. In the light emitting step, the seventh switch tube is turned on according to the fifth scanning signal received at its control end, so that the light emitting loop is turned on; 14. A pixel driving circuit as claimed in claim 13.

16. A display panel comprising a substrate and a number of pixel driving circuits, the substrate has a display area, and some of the pixel driving circuits are arranged in an array in the display area of ​​the substrate; The pixel driving circuit includes a light emitting element, a driving transistor, a reset loop, a first capacitor, a first switch tube, a second capacitor, a pre-charge module, and a threshold compensation loop; A first terminal of the light-emitting element is electrically connected to a reference voltage terminal, and the pixel driving circuit is configured to drive the light-emitting element to emit light; the driving transistor is electrically connected to a second terminal of the light emitting element; The first capacitor is connected in series in the reset loop, and a first end of the first capacitor is electrically connected to the control end of the driving transistor, and the reset loop is conductive in a reset stage and receives a reset voltage to charge the first capacitor, thereby increasing the voltage of the first end of the first capacitor, thereby resetting the voltage of the control end of the driving transistor to the reset voltage via the first capacitor; The first switch tube is connected in parallel to both ends of the light emitting element, a first end of the second capacitor electrically connected to a control end of the first switch tube; the pre-charge module is electrically connected to the first end of the second capacitor and configured to charge the second capacitor in the reset stage to raise a voltage of the first end of the second capacitor to a first voltage, the first voltage being lower than a sum of a voltage of the reference voltage end and a threshold voltage of the first switch tube; the threshold compensation loop comprises the first capacitor, the driving transistor and the first switch tube electrically connected in series, the second capacitor continues to charge according to a first scanning signal in a threshold compensation stage, the voltage of the control end of the first switch tube continues to rise from the first voltage accordingly, so that the first switch tube becomes conductive, thereby making the threshold compensation loop conductive, the first capacitor discharges through the conductive threshold compensation loop, the voltage of the control end of the driving transistor correspondingly drops from the reset voltage to a second voltage, and the driving transistor is in a critical conductive state when the voltage of its control end is equal to the second voltage, and the second voltage is equal to or less than the reset voltage; A display panel characterized by:

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