Display device

Abstract

To provide a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability, and a method for manufacturing the semiconductor device with high mass productivity.SOLUTION: A semiconductor layer is an oxide semiconductor film containing In, Ga, and Zn, and includes an inverted staggered (bottom gate structure) thin film transistor in which a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer with a higher carrier concentration than the semiconductor layer between the source and drain electrode layer and the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] A thin-film transistor (hereafter referred to as TFT) that uses an oxide semiconductor film in the channel formation region. The present invention relates to a semiconductor device having a circuit and a manufacturing method thereof. The components are electro-optical devices such as LEDs and light-emitting display devices with organic light-emitting elements. Regarding electronic devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, a switching element made of a TFT has been installed for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices, light-emitting display devices, and electrophoretic display devices) Active matrix display devices are made up of pixels (or one dot). ) has a switching element, which increases pixel density compared to the simple matrix method. This is advantageous because it can be driven at a low voltage when the

[0004] In addition, thin film transistors (TFTs) and the like are fabricated using oxide semiconductor films in the channel formation region. The technology of fabricating oxide semiconductors and applying them to electronic and optical devices is attracting attention. TFTs that use zinc oxide (ZnO) as the thin film, and InGaO3 (ZnO) m Using T TFTs using these oxide semiconductor films are formed on a light-transmitting substrate. The technology for forming the semiconductor device and using it as a switching element for an image display device is described in Patent Documents 1 and 2. This is disclosed in. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors using an oxide semiconductor film for a channel formation region have high operating speed and The manufacturing process is relatively simple and sufficient reliability is required.

[0007] In forming a thin film transistor, the source electrode and the drain electrode are made of a low-resistance metal material. In particular, when manufacturing a display device that displays a large area, the resistance of the wiring can cause the signal Therefore, gold, which has a low electrical resistance, is used as the material for wiring and electrodes. It is preferable to use a metal material for the source and drain electrodes. When a thin film transistor structure is used in which the doped electrode and the oxide semiconductor film are in direct contact with each other, The contact resistance may become high. The cause of the high contact resistance is the One of the reasons is that a Schottky junction is formed at the contact surface between the electrode and the oxide semiconductor film. It is possible.

[0008] In addition, a capacitance is generated at the portion where the source electrode and the drain electrode are in direct contact with the oxide semiconductor film. This results in a lower frequency characteristic (called the f characteristic), enabling high-speed operation of thin-film transistors. There is a risk of hindering it.

[0009] An oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is used. In a thin film transistor, the contact resistance of a source electrode or a drain electrode is reduced. It is another object of the present invention to provide a thin film transistor and a manufacturing method thereof.

[0010] In addition, the operating characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn One of the challenges is to improve the reliability of the system.

[0011] In addition, the electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn In particular, in liquid crystal display devices, it is necessary to reduce the variation in individual If there is a large variation between elements, the display will be uneven due to the variation in the TFT characteristics. There is a risk that this may happen.

[0012] In addition, in a display device having a light-emitting element, the pixel electrodes are arranged so that a constant current flows through them. The on-chip TFT (which supplies current to the driver circuit or the light-emitting element arranged in the pixel) Current (I on If the variation in the brightness of the display screen is large, the brightness of the display screen may vary. There is a problem.

[0013] As described above, an object of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0014] In one embodiment of the present invention, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, An inverted staggered type in which a buffer layer is provided between a semiconductor layer and a source electrode layer and a drain electrode layer The present invention relates to a thin film transistor having a bottom gate structure.

[0015] In this specification, a semiconductor formed using an oxide semiconductor film containing In, Ga, and Zn is The semiconductor layer is also referred to as the "IGZO semiconductor layer."

[0016] The source electrode layer and the IGZO semiconductor layer must have an ohmic contact. It is desirable to reduce the contact resistance as much as possible. An ohmic contact is required with the semiconductor layer, and the contact resistance is extremely low. It is desirable to reduce the force.

[0017] Therefore, an IGZO semiconductor is provided between the source electrode layer, the drain electrode layer and the IGZO semiconductor layer. By intentionally providing a buffer layer with a higher carrier concentration than the Form a contact.

[0018] The buffer layer is an oxide semiconductor film having n-type conductivity and containing In, Ga, and Zn. The buffer layer may contain an impurity element that imparts n-type conductivity. , for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, Scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. Magnesium, aluminum, titanium, etc. can be included in the buffer layer. and oxygen blocking effect. The concentration can be kept within the optimum range.

[0019] The buffer layer functions as an n+ layer and can also be called a drain region or a source region. do.

[0020] In order to reduce the variation in the electrical characteristics of thin-film transistors, the IGZO semiconductor layer is It is preferably in a fast state.

[0021] One embodiment of a semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate electrode layer. A semiconductor layer is formed on the gate insulating layer, and a buffer layer having an n-type conductivity is formed on the semiconductor layer. a thin film transistor including a source electrode layer and a drain electrode layer on the semiconductor layer; The buffer layer is an oxide semiconductor layer containing indium, gallium, and zinc. The carrier concentration of the semiconductor layer is higher than that of the source electrode layer and the drain electrode layer. The inner electrode layer is electrically connected via a buffer layer.

[0022] One embodiment of a semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate electrode layer. A semiconductor layer is formed on the gate insulating layer, and a buffer layer having an n-type conductivity is formed on the semiconductor layer. a thin film transistor including a source electrode layer and a drain electrode layer on the semiconductor layer; The buffer layer is an oxide semiconductor layer containing indium, gallium, and zinc, and the semiconductor layer is A thin region is included between the source electrode layer and the drain electrode layer, and the carrier concentration of the buffer layer is The carrier concentration is higher than the carrier concentration of the semiconductor layer, and the semiconductor layer and the source electrode layer and the drain electrode layer are are electrically connected via a buffer layer.

[0023] In the above-mentioned structure, a carrier concentration between the semiconductor layer and the buffer layer is higher than that of the semiconductor layer, A second buffer layer may be provided that is lower than the n-type buffer layer. - Layer as machine It works.

[0024] As the carrier concentration of an oxide semiconductor film containing In, Ga, and Zn (IGZO film) increases, As the amount of In, Ga, and Zn increases, the hole mobility also increases. The relationship between the carrier concentration and the hole mobility of the oxide semiconductor film is shown in FIG. The carrier concentration range of the IGZO film suitable for the channel of the layer (channel concentration range 1) is 1 ×10 17 atoms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 Below Top), Carrier concentration range of IGZO film suitable as a buffer layer (Buffer layer concentration range 2) is 1 x 10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 (below) is preferred The carrier concentration of the IGZO film is preferably 1000 nm at room temperature when used as a semiconductor layer. , the values ​​are those with no drain and gate voltages applied.

[0025] If the carrier concentration range of the IGZO film for the channel exceeds the above range, the thin film transistor Therefore, in the carrier concentration range disclosed in this specification, By using GZO film as the channel of the semiconductor layer, a highly reliable thin-film transistor can be achieved. It is possible.

[0026] In addition, it is preferable to use a titanium film for the source electrode layer and the drain electrode layer. The laminated layer of the tantalum film, the aluminum film, and the titanium film has low resistance, and the aluminum film Hillocks are less likely to occur.

[0027] According to one embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, forming a gate insulating layer on the layer; forming a semiconductor layer on the gate insulating layer; and forming an n-type A buffer layer having a conductivity type is formed, and a source electrode layer and a drain electrode layer are formed on the buffer layer. The semiconductor layer and the buffer layer are formed of an oxide semiconductor containing indium, gallium, and zinc. The buffer layer has a carrier concentration higher than that of the semiconductor layer. The conductor layer is electrically connected to the source electrode layer and the drain electrode layer via a buffer layer.

[0028] A gate insulating layer, a semiconductor layer, a buffer layer having an n-type conductivity, a source electrode layer, and a drain electrode layer. The electrode layer can be formed continuously without exposure to the atmosphere. This can reduce defects caused by impurities in the air being mixed into the interface.

[0029] A gate insulating layer, a semiconductor layer, a buffer layer having an n-type conductivity, a source electrode layer, and a drain electrode layer. The electrode layer may be formed by a sputtering method. is an n-type conductive material in an oxygen atmosphere (or oxygen 90% or more, rare gas (argon) 10% or less). The buffer layer having the mold is preferably formed in a rare gas (argon) atmosphere.

[0030] By using the sputtering method to continuously form films in this way, productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere, so that they contain a lot of oxygen. This can lead to a decrease in reliability due to degradation and a shift in thin-film transistor characteristics to the normally-on side. This can reduce the shift in the load.

[0031] According to one embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, forming a gate insulating layer on the layer; forming a semiconductor layer on the gate insulating layer; and forming an n-type A buffer layer having a conductivity type is formed, and a source electrode layer and a drain electrode layer are formed on the buffer layer. The semiconductor layer and the buffer layer are formed of an oxide semiconductor containing indium, gallium, and zinc. The buffer layer has a carrier concentration higher than that of the semiconductor layer. The conductor layer is electrically connected to the source electrode layer and the drain electrode layer via a buffer layer. The insulating layer, the semiconductor layer, the buffer layer, the source electrode layer, and the drain electrode layer are not exposed to the air. Form continuously. Effect of the Invention

[0032] According to one aspect of the present invention, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained. It is possible to obtain a thin film transistor having good dynamic characteristics. Thus, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. can be done. [Brief description of the drawings]

[0033] [Figure 1] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 2] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 6] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 7] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 8] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 11]1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 13] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 14] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 15] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 16] FIG. 2 is a diagram illustrating a configuration of a shift register. [Figure 17] 17 is a diagram for explaining a connection configuration of the flip-flop shown in FIG. 16 . [Figure 18] Schematic top view of a multi-chamber manufacturing device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 21] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 22] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 23] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] FIG. 1 is a diagram illustrating the relationship between Hall mobility and carrier concentration. [Figure 28] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 29] FIG. 1 is an external view showing an example of an electronic book. [Diagram 30] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Diagram 31] FIG. 1 is an external view showing an example of a gaming machine. [Diagram 32] FIG. 1 is an external view showing an example of a mobile phone. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention is not limited to the contents described below. In the drawings, the same reference numerals are used to denote the same parts or parts having similar functions. , and a repeated explanation will be omitted.

[0035] (Embodiment 1) In this embodiment mode, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS. explain.

[0036] FIG. 1 shows thin film transistors 170a, 170b, and 170c having a bottom gate structure according to the present embodiment. 1 and 2. FIG. 1(A1) is a plan view, and FIG. 1(A2) is a schematic view of FIG. 1(A1). FIG. 1(B1) is a cross-sectional view taken along line A1-A2. FIG. 1(B2) is a plan view. 2(A1) is a plan view, and FIG. 2(A2) is a cross-sectional view taken along line B1-B2 in FIG. 3 is a cross-sectional view taken along line C1-C2 in FIG. 2(A1).

[0037] In FIG. 1, a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, and a gate insulating layer 104 are formed on a substrate 100. 03, buffer layers 104a and 104b having n-type conductivity, a source electrode layer or a drain electrode layer A thin film transistor 170a is provided that includes electrode layers 105a, 105b.

[0038] The semiconductor layer 103 is an oxide semiconductor film containing In, Ga, and Zn. or between the drain electrode layers 105a, 105b and the semiconductor layer 103 which is an IGZO semiconductor layer. In addition, the buffer layers 104a and 104b, which have a higher carrier concentration than the semiconductor layer 103, are intentionally formed. By providing this, an ohmic contact is formed.

[0039] The buffer layers 104a and 104b are made of In, Ga, and Zn having n-type conductivity. The buffer layers 104a and 104b are formed of an oxide semiconductor film containing an impurity element that imparts n-type conductivity. Impurity elements may include, for example, magnesium, aluminum, titanium, Iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium The following can be used: nium, boron, thallium, lead, etc. Magnesium, aluminum If titanium or other materials are included in the buffer layer, it has an oxygen blocking effect, and after the film is formed, The oxygen concentration in the semiconductor layer can be maintained within an optimum range by heat treatment or the like.

[0040] In this embodiment, the carrier concentration range of the semiconductor layer is 1×10 17 atoms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 or more), the carrier concentration of the buffer layer Degree range is 1×10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 below ) is preferred.

[0041] If the carrier concentration range of the IGZO film for the channel exceeds the above range, the thin film transistor Therefore, in the carrier concentration range of this embodiment, the IGZ By using an O film as the channel of the semiconductor layer, a highly reliable thin-film transistor can be achieved. can be done.

[0042] In addition, between the semiconductor layer and the buffer layer, the carrier concentration is higher than that of the buffer layer which functions as an n-layer. In the case where a second buffer layer having a low conductivity and a higher carrier concentration than the semiconductor layer is provided, the second buffer layer The carrier concentration of the buffer layer should be in the range between the carrier concentrations of the semiconductor layer and the buffer layer. stomach.

[0043] The buffer layers 104a and 104b function as n+ layers and are connected to the drain and source regions. The buffer layers 104a and 104b have tapered ends. In the plan views of FIG. 1(A1) and FIG. 1(B1), the buffer layers 104a and 104b are Therefore, in the plan views of FIG. 1(A1) and FIG. 1(B1), In this case, the end of the gate electrode layer 101 is aligned with the end of the buffer layers 104a and 104b. As shown in FIG. 1(A2) and FIG. 1(B2), the gate electrode layer 101 and The buffer layers 104a and 104b overlap each other. The same is true for

[0044] The thin film transistor 170a in FIG. 1(A1) and (A2) includes buffer layers 104a and 104b. The source and drain electrode layers 105a and 105b are etched using different masks. This is an example of processing in which the buffer layers 104a and 104b and the source electrode layer or the drain electrode layer 1 The shape is different from 05a and 105b.

[0045] The thin film transistor 170b in FIG. 1B1 and FIG. 1B2 includes buffer layers 104a and 104b. The source and drain electrode layers 105a and 105b are etched using the same mask. This is an example of processing in which the buffer layers 104a and 104b and the source electrode layer or the drain electrode layer 1 05a and 105b reflect a similar shape.

[0046] In addition, the thin film transistors 170a and 170b in FIGS. On the semiconductor layer 103, the ends of the source and drain electrode layers 105a and 105b are The end of the buffer layer 104a, 104b does not match the end of the buffer layer 104a, 104b. This is an example where some of the structure is exposed.

[0047] On the other hand, the thin film transistor 170c in FIG. 2(A1) and (A2) has a semiconductor layer 103 and a buffer This is an example in which the layers 104a and 104b are etched using the same mask. The ends of the buffer layers 104a and 104b are aligned with each other. The thin film transistor 170c has a source electrode layer or a drain electrode layer on the semiconductor layer 103. In this example, the ends of the electrode layers 105a and 105b are aligned with the ends of the buffer layers 104a and 104b. be.

[0048] Furthermore, a thin film transistor 170d in which the source electrode layer or the drain electrode layer has a stacked structure is FIG. 11 shows the thin film transistor 170d. , 105a2, 105a3, and the source or drain electrode layers 105b1, 105 For example, the source or drain electrode layer 105 a1, 105b1 as titanium film, 105a2, 105b2 as aluminum film, 10 A titanium film can be used as 5a3 and 105b3.

[0049] In the thin film transistor 170d, the source and drain electrode layers 105a1 and 105b 1 as an etching stopper, the source or drain electrode layer 105a2, 105a3, 105b2, and 105b3 are formed by wet etching. The source electrode layer or the drain electrode layer is then etched using the same mask as that used in the wet etching. 105a1, 105b1, the buffer layers 104a, 104b, and the semiconductor layer 103 are dry etched. The film is formed by etching using a tin.

[0050] Therefore, the source or drain electrode layer 105a1 is connected to the end of the buffer layer 104a and the The source electrode layer or drain electrode layer 105b1 is aligned with the edge of the buffer layer 104b. The source or drain electrode layers 105a2 and 105a3 are The drain electrode layers 105b2 and 105b3 are the source or drain electrode layers 105a1, The end is set back from 105b1.

[0051] In this manner, the conductive film used for the source electrode layer and the drain electrode layer, the buffer layer, and the semiconductor If the layer has a low selectivity in the etching process, it functions as an etching stopper. To this end, a conductive film having different etching conditions may be stacked and etching steps may be performed a number of times.

[0052] The method for manufacturing the thin film transistor 170a shown in FIG. 1A-A2 will be described with reference to FIGS. I will use this to explain.

[0053] A gate electrode layer 101, a gate insulating layer 102, and a semiconductor film 111 are formed on a substrate 100 ( See FIG. 3(A). The substrate 100 is made of barium borosilicate glass, aluminoborosilicate glass, etc. Glass or aluminosilicate glass, made by the fusion or float process. In addition to alkali-free glass and ceramic substrates, we also offer heat-resistant substrates that can withstand the processing temperatures of this manufacturing process. A plastic substrate having a metal substrate such as a stainless steel alloy may be used. A substrate having an insulating film on the surface of the plate may be used. The size of the substrate 100 is 320 mm× 400mm, 370mm×470mm, 550mm×650mm, 600mm×720m m, 680mm x 880mm, 730mm x 920mm, 1000mm x 1200mm, 1100mm×1250mm, 1150mm×1300mm, 1500mm×1800m m, 1900mm x 2200mm, 2160mm x 2460mm, 2400mm x 280 0mm, or 2850mm x 3050mm, etc. can be used.

[0054] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a CVD method or the like. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed by using a sputtering method or the like. The insulating film may be formed as a single layer or a multilayer.

[0055] The gate electrode layer 101 may be made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode layer 101 is formed using a metal material such as sulphur dioxide or an alloy material thereof. A conductive film is formed on the substrate 100 by a sputtering method or a vacuum deposition method, and then photolithography is performed on the conductive film. A mask is formed by a printing technique or an inkjet method, and a conductive film is etched using the mask. It can be formed by etching. It can also be formed by using conductive nanoparticles such as silver, gold, and copper. The gate electrode layer 101 is formed by discharging the ink by an ink-jet method and baking the ink. In addition, the adhesion of the gate electrode layer 101 to the substrate and the underlayer can be improved. As a barrier metal for preventing the diffusion of the material forming the first layer, a nitride film of the above metal material is formed on the substrate 100. The gate electrode layer 101 may be provided between the insulating layer 102 and the gate electrode layer 101. For example, a molybdenum film and an aluminum film may be formed on the substrate 100 side. Lamination, lamination of molybdenum film and alloy film of aluminum and neodymium, titanium film and aluminum A laminate with a titanium film, a laminate with an aluminum film and a titanium film, etc. can be used. Cut.

[0056] Since a semiconductor film and wiring are formed on the gate electrode layer 101, the edge of the gate electrode layer 101 is cut to prevent a step. It is preferable to process it so that it has a tapered shape.

[0057] The gate insulating layer 102 and the semiconductor film 111 can be formed in succession without exposure to the air. When films are formed continuously, they can be contaminated by atmospheric components and impurity elements suspended in the air. Each lamination interface can be formed without any problem.

[0058] In active matrix display devices, the electrical properties of thin film transistors that make up the circuits are The characteristics are important, and these electrical characteristics determine the performance of the display device. Among the electrical characteristics of , the threshold voltage (Vth) is important. If the threshold voltage is high or negative, the circuit cannot control it. It is difficult to achieve this. In the case of a thin-film transistor, when the driving voltage is low, it does not function as a switching element. If the threshold voltage is negative, Even if the gate voltage is 0V, current flows between the source and drain electrodes. This is called normally-on. This is likely to happen.

[0059] In the case of an n-channel thin-film transistor, a positive voltage must be applied as the gate voltage before A transistor in which a channel is formed and a drain current flows out is desirable. There are transistors in which the channel does not form unless the voltage is low, and transistors in which the channel forms even under negative voltage conditions. A transistor in which the drain current flows through the gate is not suitable as a thin-film transistor for use in circuits. It is.

[0060] Therefore, the gate of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn is It is desirable to form a channel with a positive threshold voltage as close to 0V as possible.

[0061] The threshold voltage of a thin film transistor is determined by the interface between the oxide semiconductor layer, that is, the interface between the oxide semiconductor layer and the gate electrode. This is thought to have a significant effect on the interface of the gate insulating layer.

[0062] Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin film transistors can be improved. This improves the manufacturing process and prevents the manufacturing process from becoming complicated, achieving both mass production and high performance. A thin film transistor having the above structure is realized.

[0063] In particular, when moisture in the air is present at the interface between the oxide semiconductor layer and the gate insulating layer, the thin film transistor The electrical characteristics of the transistors deteriorate, the threshold voltage varies, and the transistors tend to be normally on. By successively forming the oxide semiconductor layer and the gate insulating layer, such hydrogen The compound can be eliminated.

[0064] Therefore, the gate insulating layer 102 and the semiconductor film 111 are formed by sputtering without being exposed to the air. By continuously forming the films under reduced pressure, the interface is excellent, the leakage current is low, and the current driving capability is high. Thus, a high-power thin film transistor can be realized.

[0065] The gate insulating layer 102 and the semiconductor layer 103 are oxide semiconductor films containing In, Ga, and Zn. The film 111 is heated under an oxygen atmosphere (or oxygen 90% or more, rare gas (argon, helium, etc.) It is preferable to form the film at a concentration of 10% or less.

[0066] By using the sputtering method to continuously form films in this way, productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere, so that they contain a lot of oxygen. Doing so may result in a decrease in reliability due to degradation, or the thin-film transistor becoming normally on. and can be reduced.

[0067] The gate insulating layer 102 is formed by depositing a silicon oxide film, a silicon nitride film, an oxide film, or a silicon nitride film by using a CVD method, a sputtering method, or the like. It can be formed of a silicon nitride film or a silicon oxynitride film. The thin film transistor 170c shown is an example in which the gate insulating layer 102 is laminated.

[0068] The gate insulating layer 102 is made of a silicon nitride film or a silicon nitride oxide film, and a silicon oxide film or an oxide The gate insulating layer 102 can be formed by stacking a silicon nitride film and a silicon nitride film in that order. A silicon nitride film or a silicon nitride oxide film, and a silicon oxide film or a silicon oxynitride film are formed on the substrate side. The insulating film can be formed by laminating a silicon nitride film or a silicon nitride oxide film in this order. The gate insulating layer 102 is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed of a single layer of bare film.

[0069] In addition, a gate insulating layer 102 is formed by nitriding a nitride film on the gate electrode layer 101 by a plasma CVD method. Alternatively, a silicon film may be formed, and a silicon oxide film may be laminated on the silicon nitride film by sputtering. A silicon nitride film and a silicon oxide film are laminated in this order on the gate electrode layer 101 by the micro-CVD method, and the silicon oxide film is A silicon oxide film may be further laminated on the base film by sputtering.

[0070] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. The concentration range is 55 to 65 atomic percent for oxygen, 1 to 20 atomic percent for nitrogen, and 25 to 40 atomic percent for silicon. 35 atomic % and hydrogen in the range of 0.1 to 10 atomic %. Silicon oxynitride A bare film is a film whose composition contains more nitrogen than oxygen, and the concentration range is Oxygen is 15-30 atomic %, nitrogen is 20-35 atomic %, Si is 25-35 atomic %, and hydrogen is This refers to a content in the range of 15 to 25 atomic %.

[0071] The gate insulating layer 102 may be formed of an oxide of aluminum, yttrium, or hafnium. At least two of the following compounds are used: Compounds including those mentioned above can also be used.

[0072] The gate insulating layer 102 may contain halogen elements such as chlorine and fluorine. The concentration of halogen elements in the insulating layer 102 is 1×10 15 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following would suffice.

[0073] As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed. For example, the semiconductor film 111 may be formed by sputtering an oxide semiconductor containing In, Ga, and Zn. The conductive film may be formed to a thickness of 50 nm. Using an oxide semiconductor target containing Ga and Zn, the distance between the substrate and the target was Distance 170 mm, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, argon or oxygen atmosphere In addition, the use of a pulsed direct current (DC) power supply reduces dust. This is preferable because the film thickness distribution becomes uniform.

[0074] Next, the semiconductor film 111 is processed by etching using a mask 113, and the semiconductor layer 112 is The semiconductor layer 112 is formed by photolithography or droplet deposition. A mask 113 is formed by a discharge method, and the semiconductor film 111 is etched using the mask 113. It can be formed by applying

[0075] The end of the semiconductor layer 112 is etched into a tapered shape, so that the step shape This can prevent the wiring from being cut off.

[0076] Next, In, Ga, and A semiconductor film 114 having n-type conductivity, which is an oxide semiconductor film containing Zn, is formed (FIG. 3). A mask 116 is formed on a semiconductor film 114 having an n-type conductivity. The mask 116 is formed by photolithography or inkjet printing. The conductive semiconductor film 114 is processed by etching using a mask 116 to form an n-type A semiconductor film 115 having n-type conductivity is formed (see FIG. 3D). The thickness of the semiconductor film 115 may be 2 to 100 nm (preferably 20 to 50 nm). The semiconductor film 114 having the above conductivity type is formed in a rare gas (preferably argon) atmosphere. is preferred.

[0077] Sputtering of oxide semiconductor films such as the semiconductor film 111 and the semiconductor film 115 having n-type conductivity Other deposition methods include pulsed laser deposition (PLD) and electron beam deposition. Among the gas phase methods, the composition of the material system can be easily controlled. In this case, the PLD method is suitable, but from the viewpoint of mass production, the sputtering method is suitable as described above.

[0078] In addition, the IGZO semiconductor film such as the semiconductor film 111 and the semiconductor film 115 having an n-type conductivity For etching, organic acids such as citric acid and oxalic acid can be used as etchants. For example, a 50 nm semiconductor film 111 was formed in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Ltd.). Can be etched.

[0079] A conductive film 117 is formed over a semiconductor film 115 having n-type conductivity (see FIG. 3(E)). .

[0080] The conductive film 117 is made of aluminum, copper, silicon, titanium, neodymium, scandium, or the like. Aluminum to which elements for improving heat resistance or elements for preventing hillocks, such as aluminum or molybdenum, have been added. It is preferable to form the semiconductor layer by a single layer or a multilayer of a silicon alloy. The film on the side in contact with the film is made of titanium, tantalum, molybdenum, tungsten, or any of these elements. A laminated structure formed of a nitride of the base material and then forming aluminum or an aluminum alloy on top of it. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be coated with titanium. , tantalum, molybdenum, tungsten, or nitrides of these elements. Here, the conductive film 117 may be formed using a titanium film, an aluminum film, or a titanium A laminated conductive film of the film is used.

[0081] A laminate of a titanium film, an aluminum film, and a titanium film provides low resistance and also provides a high resistance to aluminum. Hillocks are unlikely to occur on the film.

[0082] The conductive film 117 is formed by a sputtering method or a vacuum deposition method. Conductive nano paste such as copper is used to print the film using screen printing, inkjet printing, etc. It may be formed by baking.

[0083] Next, a mask 118 is formed over the conductive film 117. The source and drain electrode layers 105a and 105b are formed by etching and separating the layers. (See FIG. 3(F)). As shown in FIG. 3 of this embodiment, the conductive film 117 is wet-etched. Then, the conductive film 117 is isotropically etched, so that the end of the mask 118 and the source The edges of the drain electrode layers 105a, 105b are less coincident and more recessed. Next, the semiconductor film 115 having n-type conductivity is etched using the mask 118 to form a barrier layer. Then, the buffer layers 104a and 104b are formed (see FIG. 3(G)). In the etching process of the semiconductor film 115 having n-type conductivity, The exposed area of ​​the buffer layer 104a is also partially etched away to become the semiconductor layer 103. The channel region of the semiconductor layer 103 between 104b and 104b is a thin region as shown in FIG. In the semiconductor layer 103, which is an IGZO semiconductor layer, the thin film region is 2 nm thick. The thickness is set to 200 nm or more, and preferably 20 nm or more and 150 nm or less.

[0084] Furthermore, a plasma treatment may be performed on the semiconductor layer 103. This makes it possible to repair the damage caused by etching of the semiconductor layer 103. It is preferable to carry out the reaction in an atmosphere of O2, N2O, or preferably N2 containing oxygen, He, or Ar. Alternatively, the plasma treatment may be performed in an atmosphere containing Cl2 and CF4. The process is preferably performed without bias.

[0085] The end portions of the source and drain electrode layers 105a and 105b and the buffer layers 104a and 104b are The ends of the source and drain electrode layers 105a and 105b are not aligned with each other. Outside the end of b, the ends of the buffer layers 104a and 104b are formed.

[0086] After this, the mask 118 is removed. Through the above steps, a thin film transistor 170a is formed. It is possible.

[0087] Next, a manufacturing process of the thin film transistor 170b shown in FIG. 1(B1) and (B2) is shown in FIG.

[0088] FIG. 4A shows a state in which the mask 113 has been removed in the process of FIG. A semiconductor film 114 having n-type conductivity and a conductive film 121 are laminated in this order on the substrate 12 (FIG. 4( In this case, the conductive semiconductor film 114 and the conductive film 121 are not exposed to the air. The films can be formed continuously by sputtering in a short time.

[0089] A mask 122 is formed on the semiconductor film 114 having n-type conductivity and the conductive film 121. The conductive film 121 is wet-etched using 122 to form a source electrode layer or a drain electrode layer. The pole layers 105a and 105b are formed (see FIG. 4(C)).

[0090] Next, the semiconductor film 114 having n-type conductivity is dry-etched to form the buffer layer 10 In the same process, a part of the semiconductor layer 112 is also etched. As shown in FIG. 4, the buffer layers 104a and 104b are The same mask is used for etching to form the source electrode layer and the drain electrode layer 105a, 105b. By using this method, the number of masks can be reduced, which simplifies the process and reduces costs.

[0091] An insulating film may be formed as a protective film on the thin film transistors 170a, 170b, and 170c. The protective film can be formed in the same manner as the gate insulating layer. It is to prevent the intrusion of contaminating impurities such as suspended organic matter, metals, and water vapor. A dense film is preferred. For example, a protective film is provided on the thin film transistors 170a, 170b, and 170c. The film may be a laminate of a silicon oxide film and a silicon nitride film.

[0092] In addition, oxide semiconductor films such as the semiconductor layer 103 and the buffer layers 104a and 104b are formed. The heat treatment may be performed at any step after the film formation. However, this can be performed immediately after the film is formed, after the conductive film 117 is formed, after the protective film is formed, or the like. The heating temperature is preferably 300° C. or higher and 400° C. or lower. The temperature may be set to about 350° C. As shown in FIG. When the semiconductor layer 1 and the semiconductor layer 4b are successively formed, a heat treatment may be performed after the lamination. The deposition of the buffer layers 104a and 104b may be performed multiple times in separate steps.

[0093] The end portions of the source and drain electrode layers 105a and 105b and the buffer layers 104a and 104b are The ends of the source electrode layer 104b are not aligned but are shifted from each other. Since the distance between the ends of the source electrode layer 105a and the drain electrode layer 105b is large, This prevents leakage current and short circuits between the 105b and 105c. This makes the device highly reliable. In addition, a thin film transistor with high withstand voltage can be manufactured.

[0094] Also, as in the thin film transistor 170c of FIG. The end of 104b may be formed to coincide with the end of the source electrode and the drain electrode. Etching and buffering for forming the source and drain electrode layers 105a and 105b When the etching for forming the silicide layers 104a and 104b is performed by dry etching, the silicide layers 104a and 104b are formed as shown in FIG. A1) (A2) can be shaped like the thin film transistor 170c. The semiconductor film 115 having the conductive type is connected to the source electrode and the drain electrode 105a, 105b. The buffer layers 104a and 104b are formed by etching using the mask. A2) can be shaped like the thin film transistor 170c.

[0095] A buffer layer (an oxide semiconductor layer containing In, Ga, and Zn and having n-type conductivity) is provided. The gate electrode layer, gate insulating layer, and semiconductor layer (oxide semiconductor containing In, Ga, and Zn) In the case of a laminated structure of a gate electrode layer, a source electrode layer, and a drain electrode layer, The distance between the source electrode layer and the drain electrode layer becomes short, and the parasitic capacitance between them increases. Furthermore, this increase in parasitic capacitance becomes more pronounced as the semiconductor layer becomes thinner. In one embodiment, the oxide semiconductor layer has an n-type conductivity type and contains In, Ga, and Zn. A buffer layer with a high carrier concentration is provided. A thin film transistor having a laminated structure of a buffer layer, a source electrode layer, and a drain electrode layer. Therefore, even if the semiconductor layer is thin, the parasitic capacitance can be suppressed.

[0096] According to the present embodiment, a thin-film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio is obtained. Thus, a thin film transistor having good dynamic characteristics can be obtained. As a result, it is possible to provide a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability. can.

[0097] (Embodiment 2) This embodiment is an example of a thin film transistor having a multi-gate structure. It can be carried out in the same manner as in embodiment 1, and has the same parts as in embodiment 1 or parts having similar functions; The description of the repetition of steps will be omitted.

[0098] In this embodiment, a thin film transistor used in a semiconductor device will be described with reference to FIGS. 7(A) and (B) will be used to explain the above.

[0099] FIG. 5(A) is a plan view showing a thin film transistor, and FIG. 5(B) is a plan view showing the thin film transistor in FIG. 1 corresponds to a cross-sectional view showing the thin film transistor 171a along line E1-E2.

[0100] As shown in FIG. 5(A) and (B), gate electrode layers 151a and 151b, a semiconductor layer 151a, and a semiconductor layer 151b are formed on a substrate 150. Conductor layers 153a, 153b, buffer layers 154a, 154b, 154c, source electrode layers or A thin film transistor 171 having a multi-gate structure including drain electrode layers 155a and 155b is a is provided.

[0101] The semiconductor layers 153a and 153b are oxide semiconductor layers containing In, Ga, and Zn. The buffer layers 154a, 154b, and 154c are made of In, Ga, and Zn having n-type conductivity. The buffer layer functions as a source region or a drain region (n+ layer). The layers 154a, 154b, and 154c have a higher carrier concentration than the semiconductor layers 153a and 153b. is high.

[0102] The semiconductor layer 153a and the semiconductor layer 153b are electrically connected to each other via a buffer layer 154c. On the other hand, the semiconductor layer 153a is connected to the source electrode 152 via the buffer layer 154a. The positive or drain electrode layer 155a and the semiconductor layer 153b are connected via a buffer layer 154b. The source electrode layer or drain electrode layer 155b is electrically connected to the source electrode layer or drain electrode layer 155c.

[0103] FIG. 6 shows a thin film transistor 171b having a multi-gate structure having another configuration. FIG. 6(A) shows FIG. 6B is a plan view showing a thin-film transistor 171b, and FIG. 6B is a plan view showing a thin-film transistor 171b along a line F in FIG. 1-F2 corresponds to a cross-sectional view showing the thin film transistor 171b of FIG. In 171b, a source or drain electrode layer 155a is formed on a buffer layer 154c. A wiring layer 156 is formed in the same process as the semiconductor layer 155b. The buffer layer 154c and the wiring layer 156 are electrically connected to the electrode 53b.

[0104] FIG. 7 shows a thin film transistor 171c having a multi-gate structure having another configuration. FIG. 7(A) shows FIG. 7B is a plan view showing a thin-film transistor 171c, and FIG. 7B is a plan view showing a thin-film transistor 171c along a line G in FIG. 1-G2 corresponds to a cross-sectional view of the thin film transistor 171c of FIG. In the semiconductor layer 171c, the semiconductor layer 153a and the semiconductor layer 153b are continuous to form a single semiconductor layer. The semiconductor layer 153 is formed as a gate insulating layer 152. It is provided so as to straddle the gate electrode layers 151a and 151b.

[0105] In this way, in a thin film transistor having a multi-gate structure, a gate electrode layer is formed on each gate electrode layer. The semiconductor layer may be provided continuously or may be provided in a plurality of layers with a buffer layer, a wiring layer, etc. interposed therebetween. The semiconductor layers may be provided in electrical contact with each other.

[0106] The thin film transistor having a multi-gate structure according to this embodiment has a small off-current. Semiconductor devices including thin film transistors can have high electrical characteristics and high reliability. .

[0107] In this embodiment, a double-gate structure having two gate electrode layers is used as an example of the multi-gate structure. However, it can also be applied to triple gate structures with more gate electrode layers. can.

[0108] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0109] (Embodiment 3) This embodiment is an example in which a buffer layer is laminated in a thin film transistor. can be carried out in the same manner as in embodiment 1 or embodiment 2, Descriptions of parts that are the same as those in 2 or parts having similar functions, and repeated steps will be omitted.

[0110] In this embodiment, a thin film transistor 173 used in a semiconductor device will be described with reference to FIG. I will explain it below.

[0111] As shown in FIG. 8, a gate electrode layer 101, a semiconductor layer 103, a buffer layer 104, and a semiconductor layer 105 are formed on a substrate 100. 106a, 106b, buffer layers 104a, 104b, source electrode layer or drain electrode layer A thin film transistor 173 including 105a and 105b is provided.

[0112] The thin film transistor 173 of this embodiment is made up of a semiconductor layer 103 and buffer layers 104a and 10 Buffer layers 106a and 106b are provided between the first and second buffer layers 106a and 106b, respectively. is.

[0113] The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn. The buffer layers 106a and 106b are made of In, Ga, and The oxide semiconductor layer contains Zn.

[0114] A second buffer layer ( The buffer layers 106a and 106b have a higher carrier concentration than the semiconductor layer 103. The buffer layers 104a and 104b function as n+ layers. On the other hand, the second buffer layer (buffer layers 106a and 106b) functions as an n-layer. do.

[0115] In this embodiment, the carrier concentration range suitable for the semiconductor layer 103 is 1×10 17 a toms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 (above), Buff The carrier concentration range suitable for the GaN layer is 1×10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 (see below) is preferred.

[0116] If the carrier concentration range of the semiconductor layer 103 for the channel exceeds the above range, the thin film transistor Therefore, in the carrier concentration range of this embodiment, the IG By using the ZO film as the channel of the semiconductor layer 103, a highly reliable thin film transistor can be obtained. It is possible.

[0117] The concentration range suitable for the buffer layers 106a and 106b functioning as the n-layer is The buffer layers 104a and 104b functioning as the semiconductor layer 103 have a lower carrier concentration than the buffer layers 104a and 104b. The carrier concentration may be in a high concentration range.

[0118] In this way, the buffer layer provided between the semiconductor layer and the source electrode layer or the drain electrode layer The carrier concentration of the semiconductor layer may be a layered structure. The temperature is controlled so that it increases toward the polar layer.

[0119] The thin film transistor having the stacked buffer layer of this embodiment has a small off-state current. A semiconductor device including such a thin film transistor can have high electrical characteristics and high reliability. Cut.

[0120] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0121] (Embodiment 4) In this embodiment, the shape and manufacturing method of the thin film transistor are partially different from those in the first embodiment. Therefore, the rest can be performed in the same manner as in the first embodiment, and the same Descriptions of parts or parts having similar functions and repetitive steps will be omitted.

[0122] In this embodiment mode, a thin film transistor 174 used in a display device and a manufacturing process thereof will be described. 9 and 10. FIG. 9(A1) is a plan view of a thin film transistor 174. 9(A2) and 10 are thin film transistors of the line D1-D2 in FIG. 9(A1) and 1A to 1C are cross-sectional views showing the manufacturing process thereof.

[0123] As shown in FIGS. 9A and 9B, a gate electrode layer 101, a semiconductor layer 103, and a gate electrode layer 104 are formed on a substrate 100. , buffer layers 104a and 104b, source and drain electrode layers 105a and 105b A thin film transistor 174 including a

[0124] The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn. 4a and 104b are oxide semiconductor layers having n-type conductivity and containing In, Ga, and Zn. The buffer layers 104a and 104b function as source and drain regions (n+ layers). The layer b has a higher carrier concentration than the semiconductor layer 103 .

[0125] The semiconductor layer 103 is connected to a source electrode layer or a drain electrode layer 105a via a buffer layer 104a. The source electrode layer or the drain electrode layer 105b is electrically connected to the buffer layer 104b. It continues.

[0126] A manufacturing process of the thin film transistor 174 will be described with reference to FIG. Next, a gate insulating layer 102, In, G a, and a semiconductor film 131 which is a semiconductor film that is an oxide semiconductor film containing Zn; The semiconductor film has an n-type conductivity and is an oxide semiconductor film containing In, Ga, and Zn. A film 132 and a conductive film 133 are formed in this order (see FIG. 10A).

[0127] A gate insulating layer 102, a semiconductor film 131 which is an oxide semiconductor film containing In, Ga, and Zn, an oxide semiconductor film containing In, Ga, and Zn having n-type conductivity; The semiconductor film 132 and the conductive film 133 are successively formed without being exposed to the air. By continuously forming the film without exposing it to the air, atmospheric components and airborne substances can be prevented. Since each layer interface can be formed without being contaminated by impurity elements, The variation in transistor characteristics can be reduced.

[0128] In this embodiment, an example is given in which exposure is performed using a high-resolution mask to form the mask 135. A resist is formed to form a mask 135. The resist may be a positive resist or A positive resist is used here.

[0129] Next, a multi-tone mask is used as a photomask to irradiate the resist with light. Expose.

[0130] A multi-tone mask has three exposure levels for the exposed, intermediate and unexposed parts. This is a mask that can produce multiple (typically two types) It is possible to form a resist mask having a region of thickness of 100 nm or more. By using this mask, it is possible to reduce the number of photomasks.

[0131] Typical examples of multi-tone masks include gray-tone masks and half-tone masks.

[0132] The gray-tone mask is a mask that includes a light-transmitting substrate and a light-shielding portion and a diffraction grating formed thereon. The light transmission rate in the light-shielding area is 0%. The spacing between light-transmitting parts such as dots, meshes, etc. is set to be equal to or less than the resolution limit of the light used for exposure. By doing so, the amount of light transmitted can be controlled. Use either slits, dots, meshes, or non-periodic slits, dots, meshes It is possible.

[0133] The light-transmitting substrate may be a light-transmitting substrate such as quartz. The diffraction grating can be made of light-absorbing, light-shielding materials such as chromium or chromium oxide. do.

[0134] When the gray-tone mask is irradiated with exposure light, the amount of light transmitted through the light-shielding portion is 0%. In other words, the light transmittance is 100% in the area where the light shielding portion and the diffraction grating are not provided. In the case of a diffraction grating, the light transmittance can be adjusted in the range of 10 to 70%. The adjustment of the excess amount is achieved by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating. It is more possible.

[0135] The halftone mask is a mask that includes a light-transmitting substrate and a semi-transmitting portion and a light-shielding portion formed thereon. The semi-transparent part is made up of MoSiN, MoSi, MoSiO, MoSiON, and Cr The light-shielding part is made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed using materials.

[0136] When exposure light is irradiated onto a half-tone mask, the amount of light transmitted through the light-shielding portion is 0%. In other words, the light transmittance is 100% in the area where the light-shielding portion and the semi-transmitting portion are not provided. In the semi-transmitting portion, the light transmittance can be adjusted in the range of 10 to 70%. The excess amount can be adjusted by adjusting the material of the semi-transparent portion.

[0137] After exposure using a multi-tone mask, the film is developed to have a thickness of 100 μm, as shown in FIG. 10(B). A mask 135 having different regions can be formed.

[0138] Next, the semiconductor film 131, the semiconductor film 132 having n-type conductivity, and the conductive film 133 are removed by a mask 135. The conductive film 133 is etched and separated. As a result, the semiconductor film 136 has an n-type conductivity. A semiconductor film 137 and a conductive film 138 can be formed (see FIG. 10B).

[0139] Next, the mask 135 is ashed. As a result, the area of ​​the mask is reduced and the thickness is reduced. At this time, the resist of the mask in the thin region (which overlaps a part of the gate electrode layer 101) is The regions (areas where the mask is to be removed) can be removed to form a separate mask 139 (see FIG. 10(C)). Light. ).

[0140] The conductive film 138 is etched using the mask 139, and the source or drain electrode layer 1 As in the present embodiment, the conductive film 138 is formed by wet etching. Then, the conductive film 138 is isotropically etched, so that the end of the mask 139 and the source The ends of the drain electrode layers 105a and 105b are not aligned but are recessed. The semiconductor film 137 having n-type conductivity is provided on the outside of the drain electrode layers 105a and 105b. Then, a mask 139 is used to form an n-type conductive film. The semiconductor film 137 and the semiconductor film 136 are etched to remove the buffer layers 104a and 10 4b, the semiconductor layer 103 is formed (see FIG. 10(D)). Note that the semiconductor layer 103 is partially Only the surface is etched, resulting in a semiconductor layer having a groove.

[0141] The buffer layers 104a and 104b are formed in the same process as the grooves in the semiconductor layer 103. Similarly, the end portion of the semiconductor layer 103 can be partially etched and exposed. After that, the mask 139 is removed.

[0142] Through the above steps, the thin film transistor 174 shown in FIGS. .

[0143] As in the present embodiment, a multi-tone mask is used to form a multi-layer mask having a plurality of thicknesses (typically, two types). By using a resist mask having regions, the number of resist masks can be reduced. This simplifies the process and reduces costs.

[0144] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0145] (Embodiment 5) In this embodiment, in a display device which is an example of a semiconductor device of the invention disclosed in this specification, At least a part of the driver circuit and a thin film transistor to be arranged in the pixel portion are fabricated on the same substrate. An example of this is described below.

[0146] The thin film transistor disposed in the pixel portion is according to any one of the first to fourth embodiments. In addition, the thin film transistor shown in any one of the first to fourth embodiments is formed as follows. Since the photodiode is an n-channel TFT, the driver circuit is composed of n-channel TFTs. A part of the driver circuit capable of performing this is formed on the same substrate as the thin film transistor of the pixel portion.

[0147] An active matrix liquid crystal display device which is an example of the semiconductor device of the invention disclosed in this specification. An example of a block diagram of the display device shown in FIG. A pixel portion 5301 having a plurality of pixels each having a display element on a substrate 5300 and a scanning line driver for selecting each pixel. A signal line driver circuit 5302 controls the input of a video signal to a selected pixel. 03.

[0148] In addition, the thin film transistor shown in any one of the first to fourth embodiments is an n-channel The signal line driver circuit is configured with n-channel TFTs. He explains.

[0149] The signal line driver circuit shown in FIG. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0150] The pixel portion 5301 includes a signal line driver circuit 5303 and a plurality of signal lines arranged in a column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. Signal line Sj (any one of signal lines S1 to Sm), scanning line Gi (any one of scanning lines G1 to Gn) Either one of them is connected.

[0151] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 56 13 and wiring 5621_1 to 5602_M corresponding to the switch groups 5602_1 to 5602_M, respectively. 5621_M. Each of the wirings 5621_1 to 5621_M is connected to the first a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 562 in the Jth column is connected to three signal lines via a transistor 5603c. 1_J (one of the wirings 5621_1 to 5621_M) is a switch group 560 The first thin film transistor 5603a and the second thin film transistor 5603b included in 2_J and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line Connected to Sj+1.

[0152] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0153] It is preferable that the driver IC 5601 is formed on a single crystal substrate. The switch group 5602_1 to 5602_M is formed on the same substrate as the pixel section. Therefore, the driver IC 5601 and the switch group 5602_1 to 5602_ It is recommended to connect to M via an FPC or similar.

[0154] Next, the operation of the signal line driver circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. The timing chart of FIG. 14 is explained with reference to the timing chart when the i-th scanning line Gi is selected. Further, during the selection period of the i-th scanning line Gi, is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driver circuit of FIG. In this case, the same operation as in FIG. 14 is performed.

[0155] In the timing chart of FIG. 14, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0156] In the timing chart of FIG. 14, the timing when the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the wiring 5621_J of the Jth row. 5 shows signal 5721_J.

[0157] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and is input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the line 5621 is connected to the line Sj during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. In the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0158] As shown in FIG. 14, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a is turned on. and the third thin film transistor 5603c are turned off. At this time, the input The Data_j to be output is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 03c and input to the signal line Sj+1.

[0159] From the above, the signal line driver circuit in FIG. 13 divides one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the pixel area is formed and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0160] As shown in FIG. 13, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0161] For example, three or more signal lines are connected to one wiring during each of three or more sub-selection periods. When a video signal is input to each of them, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or It is preferably divided into three sub-selection periods.

[0162] As another example, as shown in the timing chart of FIG. 15, one selection period is precharged. The first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 15, the i-th scanning line Gi is selected. the timing of turning on and off the first thin film transistor 5603a; a, the on-off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the wiring 562 of the Jth column 15, the signal 5821_J input to the precharge In the period Tp, the first thin film transistor 5603a and the second thin film transistor 5603 At this time, the input to the wiring 5621_J is turned on. The input precharge voltage Vp is applied to the first thin film transistor 5603a, the second thin film transistor 5603b, and the and a third thin film transistor 5603c are connected to the signal line Sj- 1, signal line Sj, and signal line Sj+1. The thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the signal Dat input to the wiring 5621_J is turned off. a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j input to the wiring 5621_J is input to the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor The first thin film transistor 5603a and the second thin film transistor 5603c are turned on. At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0163] From the above, the signal line driver circuit of FIG. 13 to which the timing chart of FIG. 15 is applied By providing a precharge selection period before the sub selection period, the signal lines can be precharged. This allows high-speed writing of video signals to the pixels. In this embodiment, the same reference numerals are used for the same parts as those in FIG. 14, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0164] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP ) is input, the selection signal is generated. The generated selection signal is buffered The signal is buffered and amplified in the 10-bit signal line and then fed to the corresponding scan line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be capable of passing a large current. Used.

[0165] One form of a shift register used as a part of a scanning line driving circuit is shown in FIG. 16 and FIG. 17. He explains.

[0166] The circuit configuration of the shift register is shown in Figure 16. The shift register shown in Figure 16 has multiple free It is composed of flip-flop 5701_i (flip-flops 5701_1 to 5701_n). In addition, a first clock signal, a second clock signal, a start pulse signal, and a reset signal The number is entered and the device operates.

[0167] The connection relationship of the shift register in Fig. 16 will be described. The shift register in Fig. 16 has i-stage The first flip-flop 5701_i (flip-flops 5701_1 to 5701_n In either one of them, the first wiring 5501 shown in FIG. 17 is connected to the seventh wiring 5717_i-1. 17 is connected to the seventh wiring 5717_i+1. 17 is connected to the seventh wiring 5717_i, The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0168] In addition, the fourth wiring 5504 shown in FIG. 17 corresponds to the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0169] However, the first wiring 5501 shown in FIG. 17 of the first-stage flip-flop 5701_1 is 17 of the n-th flip-flop 5701_n. The second wiring 5502 is connected to the sixth wiring 5716 .

[0170] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the third power supply line. This may also be called the power line 2.

[0171] Next, the details of the flip-flop shown in FIG. 16 are shown in FIG. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a seventh thin film transistor 5576, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). When this occurs, the device is in a conductive state.

[0172] Next, the connection configuration of the flip-flop shown in FIG. 16 will be described below.

[0173] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0174] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0175] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0176] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506. The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0177] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0178] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0179] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0180] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5543, a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0181] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It may be called a line.

[0182] In addition, the signal line driver circuit and the scanning line driver circuit may be any one of the first to fourth embodiments. It is also possible to manufacture the device using only the n-channel TFT shown in the embodiment 1 to the embodiment 2. The n-channel TFT shown in any one of the four modes has a high transistor mobility, so it is easy to drive It is possible to increase the driving frequency of the circuit. The n-channel TFT shown in any one of the above is made of indium, gallium, and zinc having n-type. The buffer layer, which is an oxide semiconductor layer containing For example, the n The scanning line driver circuit using the channel type TFT can operate at high speed, so it is suitable for frame-type TFTs. It is also possible to increase the frame rate or insert a black screen. come.

[0183] Furthermore, the channel width of the transistor of the scanning line driving circuit is increased, and multiple scanning lines By arranging the drive circuit, it is possible to achieve even higher frame frequencies. When multiple scanning line driving circuits are arranged, a scanning line driving circuit for driving the even-numbered scanning lines is provided. The circuit is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the opposite side. By placing the pixel clock in the pixel clockwise direction, it is possible to realize a high frame frequency.

[0184] In addition, an active matrix type light emitting display, which is an example of the semiconductor device of the invention disclosed in this specification, In manufacturing a display device, a plurality of thin film transistors are arranged in at least one pixel. It is preferable that a plurality of scanning line driving circuits are arranged. An example of a block diagram is shown in FIG.

[0185] The light-emitting display device shown in FIG. 12B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403.

[0186] In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 12(B) is in a digital format, When a pixel is turned on, the transistor is switched on and off to make it either emitting light or not. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time when the pixel emits light. This is a driving method that displays gradations by controlling the period during which the liquid crystal display is turned on.

[0187] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0188] In the light-emitting display device shown in FIG. 12B, a switching TFT and a When two TFTs are arranged, the first TFT, which is the gate wiring of the switching TFT, The signal input to the scanning line is generated by the first scanning line driver circuit 5402, and the current control TFT A signal input to the second scanning line, which is a gate wiring, is generated by a second scanning line driver circuit 5404. In this example, the signal input to the first scanning line and the signal input to the second scanning line are The signals for the scanning lines may be generated by a single scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. A plurality of first scan lines may be provided for each pixel. All the signals input to the multiple first scanning lines may be generated by one scanning line driver circuit. , may be generated by a plurality of scanning line driving circuits.

[0189] In addition, in the light-emitting display device, the driver circuit may be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those in any one of the first to fourth embodiments. It is also possible to fabricate the device using only the n-channel TFT shown in FIG.

[0190] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in devices with switching elements and It may also be used in electronic paper, where electrically connected elements are used to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0191] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0192] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Electrophoretic displays do not require polarizing plates or opposing substrates, which are necessary for display devices, and are half the thickness and weight. Reduce.

[0193] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0194] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. 4. An active matrix substrate obtained by using any one of the thin film transistors It is possible.

[0195] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0196] Through the above steps, a display device with high reliability as a semiconductor device can be manufactured.

[0197] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0198] (Embodiment 6) Here, at least the gate insulating layer and the oxide semiconductor layer are stacked without being exposed to the air. An example of the fabrication of an inverted staggered thin film transistor by successive film formation is shown below. The steps up to the step of performing the above are shown, and the steps thereafter are the same as those in any of the first to fourth embodiments. A thin film transistor can be fabricated according to the above method.

[0199] In this specification, continuous film formation refers to a process from a first film formation process performed by sputtering to a second film formation process performed by sputtering. During the series of processes up to the film formation process, the atmosphere in which the substrate is placed is a polluted atmosphere such as air. Always keep the device in a vacuum or inert gas atmosphere (nitrogen or rare gas atmosphere) without exposing it to air. By performing continuous film formation, the substrate to be treated is cleaned. Film formation can be performed while avoiding re-adhesion of moisture, etc., to the plate.

[0200] A series of processes from the first film formation process to the second film formation process are carried out in the same chamber. is within the scope of continuous film formation in this specification.

[0201] In addition, a series of processes from the first film formation process to the second film formation process are carried out in different chambers. In this case, after the first film formation process is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second film is also considered to be within the scope of successive film formation in this specification.

[0202] Between the first and second film formation processes, a substrate transfer process, an alignment process, and a slow cooling process are performed. or a step of heating or cooling the substrate to a temperature required for the second step. However, such a method is considered to be within the scope of continuous film formation in this specification.

[0203] However, the first step involves processes that use liquids, such as cleaning, wet etching, and resist formation. If the film formation step is between the first film formation step and the second film formation step, it does not fall within the scope of continuous film formation as used in this specification. Let's say that's not the case.

[0204] When performing continuous film formation without exposure to the atmosphere, a multi-chamber production system as shown in Figure 18 is used. It is preferable to use a manufacturing device.

[0205] The manufacturing apparatus is provided at its center with a transport mechanism (typically a transport robot 81) for transporting substrates. The transfer chamber 80 is provided with a transfer chamber 81 for transferring a plurality of substrates to and from the transfer chamber. A cassette chamber 82 for setting a cassette case to be stored is connected.

[0206] In addition, a plurality of processing chambers are connected to the transfer chamber 80 via gate valves 84 to 88, respectively. Here, an example is shown in which five processing chambers are connected to a transfer chamber 80 having a hexagonal top surface. By changing the shape of the top surface of the transfer chamber, the number of processing chambers that can be connected can be changed. For example, a square shape can connect three processing chambers, and an octagon shape can connect seven processing chambers. do.

[0207] At least one of the five processing chambers is a sputtering chamber for sputtering. The sputtering chamber is provided with at least a sputtering target, The device includes a power application mechanism for sputtering the target, a gas introduction means, and a means for holding the substrate in a predetermined position. The sputtering chamber is also equipped with a substrate holder. The sputtering chamber is provided with a pressure control means for controlling the pressure within the chamber.

[0208] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0209] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0210] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0211] The sputtering chamber is suitably used for the various sputtering methods described above.

[0212] In addition, the film formation method involves chemically reacting the target material with the sputtering gas components during film formation. The reactive sputtering method for forming these compound thin films and the application of voltage to the substrate during film formation are also used. There is also a bias sputtering method.

[0213] In addition, one of the five processing chambers is used for preheating the substrate before sputtering. a heating chamber for performing sputtering, a cooling chamber for cooling the substrate after sputtering, or This chamber performs plasma processing.

[0214] Next, an example of the operation of the manufacturing apparatus will be described.

[0215] A substrate cassette containing substrates 94 with the film-forming surface facing downward is set in the cassette chamber 82. The cassette chamber 82 is then placed in a decompressed state by a vacuum exhaust means provided in the cassette chamber 82. The inside of each processing chamber and the transfer chamber 80 is previously depressurized by a vacuum exhaust means provided therein. This prevents the substrate from coming into contact with the atmosphere while being transported between the processing chambers. It is possible to maintain a clean state without

[0216] The substrate 94 with the film-forming surface facing downward is provided with at least a gate electrode. For example, a silicon nitride film or a nitriding oxide film obtained by the plasma CVD method is used between the substrate and the gate electrode. A base insulating film such as a silicon nitride film may be provided. When a silicon substrate is used, the insulating film underneath is designed to prevent mobile ions such as sodium from the substrate from It penetrates into the body region and has the effect of suppressing changes in the electrical characteristics of the TFT.

[0217] Here, a silicon nitride film that covers the gate electrode is formed by plasma CVD, and the first gate layer is The silicon nitride film formed by the plasma CVD method is dense. By using it as the first gate insulating film, it is possible to prevent pinholes from occurring. In this example, the gate insulating film is a laminated film, but is not limited thereto. The above laminated layers may be used.

[0218] Next, the gate valve 83 is opened and the first substrate 94 is loaded into the cassette by the transfer robot 81. Then, the gate valve 84 is opened and the wafer is transferred into the first processing chamber 89. In the first processing chamber 89, the substrate is heated by a heater or a lamp heater. In particular, if the gate insulating film contains moisture, it can damage the TFT. Heating before sputtering is effective because the thermal properties may change. If the moisture is sufficiently removed at the stage when the substrate is set in the chamber 82, this heat treatment can be performed without It is not necessary.

[0219] In addition, a plasma processing means is provided in the first processing chamber 89, and a plasma is applied to the surface of the first gate insulating film. In addition, a heating means may be provided in the cassette chamber 82 to heat the cassette chamber 82. Heating may be performed to remove the residue.

[0220] Next, the gate valve 84 is opened and the substrate is transported to the transport chamber 80 by the transport robot 81. The gate valve 85 is opened, the substrate is transferred into the second processing chamber 90, and the gate valve 85 is closed.

[0221] Here, the second processing chamber 90 is a sputtering chamber using an RF magnetron sputtering method. In the second processing chamber 90, a silicon oxide film (SiO As the second gate insulating film, in addition to the silicon oxide film, aluminum oxide is also deposited. Al2O3 film, magnesium oxide film (MgOx film), aluminum nitride film ( For example, an yttrium oxide film (YOx film) or an yttrium oxide film (AlNx film) can be used.

[0222] In addition, small amounts of halogen elements, such as fluorine or chlorine, are added to the second-layer gate insulating film. Alternatively, mobile ions such as sodium may be immobilized. A gas containing a halogen element is introduced into the chamber to perform sputtering. When introducing a gas containing such a gas, it is necessary to provide a detoxification device in the exhaust means of the chamber. The concentration of halogen elements contained in the insulating film was measured using a SIMS (secondary ion mass spectrometer). The concentration peak obtained by analysis is 1×10 15 cm -3 More than 1×10 20 cm -3 below It is preferable to keep it within the range.

[0223] When obtaining a SiOx film, artificial quartz is used as the target, and a rare gas, typically argon, is used. A sputtering method using a silicon target and a chemical reaction with oxygen gas. A reactive sputtering method can be used to obtain a SiOx film by sputtering oxygen. In order to include as much oxygen as possible in the SiOx film, artificial quartz is used as the target. Sputtering was performed in an atmosphere containing 90% or more oxygen and 10% or less Ar. A SiOx film containing excess oxygen is formed by etching.

[0224] After the SiOx film is formed, the gate valve 85 is opened without exposing the substrate to the air, and the transfer robot 8 1 to the transfer chamber 80, and then the gate valve 86 is opened to transfer the substrate into the third processing chamber 91. Then, the gate valve 86 is closed.

[0225] Here, the third processing chamber 91 is a sputtering chamber using a DC magnetron sputtering method. In the third processing chamber 91, a metal oxide layer (IGZO film) is formed as a semiconductor layer. Using an oxide semiconductor target containing In, Ga, and Zn, In this case, the IGZO film can be formed in an oxygen atmosphere or in an atmosphere where as much oxygen as possible is introduced into the film. In order to incorporate In, Ga, and Zn, an oxide semiconductor containing In, Ga, and Zn was used as a target. Pulse is heated in an atmosphere of only nitrogen or in an atmosphere of 90% or more oxygen and 10% or less Ar. A DC sputtering method is used to form an oxygen-excess IGZO film.

[0226] In this way, the oxygen-rich SiOx film and the oxygen-rich IGZO film are formed without being exposed to the air. By forming the films successively, the interface between the films containing excess oxygen is stabilized, improving the reliability of the TFT. If the substrate is exposed to the air before the IGZO film is formed, moisture, etc. Adhesion can adversely affect the interface state, resulting in variations in threshold voltage, deterioration of electrical characteristics, and This can cause problems such as the TFT turning on. By continuously depositing the film without exposure to the air, hydrogen compounds exist at the interface. Therefore, by forming the films continuously, the variation in the threshold voltage can be reduced. In addition, it is possible to prevent deterioration of electrical characteristics, reduce the shift of the TFT to the normally-on side, and Or shifting can be eliminated.

[0227] In addition, a synthetic quartz target and In, Ga, and Zn-containing oxide semiconductor targets were placed, and stacked in sequence using a shutter. It is also possible to perform lamination in the same chamber by successively depositing films using the shutter. The shutter is placed between the target and the substrate, and the target that is to be deposited is opened to deposit the film. The advantage of stacking in the same chamber is that This reduces the number of chambers used and reduces the amount of paper required to transport substrates between different chambers. The advantage is that it is possible to prevent tickles and the like from adhering to the substrate.

[0228] Next, the gate valve 86 is opened and the substrate is transferred by the transfer robot 81 without being exposed to the atmosphere. is transported to the transport chamber 80.

[0229] If the process does not use a gray-tone mask, the mask is transferred from the manufacturing equipment to the cassette room at this stage. The substrate is then removed and the oxygen-rich IGZO film is patterned using photolithography. However, if a gray-tone mask is used, the following continuous film formation is performed. cormorant.

[0230] Next, the gate valve 87 is opened and the substrate is transferred into the fourth processing chamber 92 without being exposed to the atmosphere. Then, close the gate valve 87.

[0231] Here, the fourth processing chamber 92 is a sputtering chamber using a DC magnetron sputtering method. In the fourth processing chamber 92, sputtering is performed using a pulse DC sputtering method under an atmosphere of only a rare gas. Then, a second IGZO film was formed on the oxygen-rich IGZO film as a buffer layer. This second IGZO film has a lower oxygen concentration than the oxygen-excess IGZO film. In addition, the second IGZO film is to have a higher carrier concentration than the oxygen-excess IGZO film. It is preferable that the target further includes an oxide semiconductor containing In, Ga, and Zn. A target containing Mg, Al, or Ti may be used. Mg, Al, and Ti are easily oxidized. When these materials are included in the second IGZO film, the oxygen blocking effect is enhanced. Even if heat treatment is performed after film formation, the oxygen concentration in the semiconductor layer remains within the optimal range. This second IGZO film functions as the source or drain region.

[0232] Next, the gate valve 87 is opened and the substrate is transferred by the transfer robot 81 without being exposed to the atmosphere. The wafer is transferred to the transfer chamber 80, the gate valve 88 is opened, the wafer is transferred to the fifth processing chamber 93, and the gate Close valve 88.

[0233] Here, the fifth processing chamber 93 is a sputtering chamber using a DC magnetron sputtering method. In the fifth treatment chamber 93, a metal multilayer film that will become a source electrode layer or a drain electrode layer is formed. A titanium target is placed in the sputtering chamber of the fifth processing chamber 93. Both the aluminum target and the aluminum target are installed, and the shutter is used to stack them one after another. In this example, aluminum is deposited on a titanium film. A titanium film is then laminated on the aluminum film.

[0234] In this way, when using a gray-tone mask, oxygen-rich Si It is possible to continuously deposit an Ox film, an oxygen-rich IGZO film, a second IGZO film, and a metal multilayer film. In particular, the interface state of the oxygen-rich IGZO film becomes more stable, improving the reliability of the TFT. If the substrate is exposed to the air before or after the IGZO film is formed, moisture may adhere to it. This adversely affects the interface state, resulting in variations in threshold voltage, deterioration of electrical characteristics, and normally-on. This may cause symptoms such as TFT. Moisture is a hydrogen compound, and By continuously depositing the film without touching the substrate, hydrogen compounds are prevented from existing at the interface of the IGZO film. Therefore, by successively depositing four layers, the threshold voltage is reduced. Reduction of ragging, prevention of deterioration of electrical characteristics, and shift of TFT to the normally-on side. The shift can be reduced, and preferably eliminated.

[0235] In addition, the second IGZO film, which acts as a buffer layer, the source electrode layer, and the drain electrode layer are formed without being exposed to the air. The second IGZO film and the metal multilayer film that will become the rain electrode layer are successively deposited. A good interface state can be achieved with the metal multilayer film, and contact resistance can be reduced.

[0236] In addition, a synthetic quartz target and In, Ga, and Zn-containing oxide semiconductor targets were installed and introduced sequentially using a shutter. By switching the gas used to deposit three layers in succession, the layers can be stacked in the same chamber. The advantage of stacking in the same chamber is that it reduces the number of chambers used. In addition, particles may adhere to the substrate while it is being transported between different chambers. The point is that this can be prevented.

[0237] The above steps are repeated to perform film formation on the substrates in the cassette case, and multiple substrates are processed. After completion, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and cassette are removed.

[0238] In addition, in the first processing chamber 89, a heat treatment after the formation of the oxygen-excessive IGZO film, specifically, 30 Heat treatment can be performed at 0°C to 400°C, preferably at 350°C or higher. By carrying out the heat treatment, the electrical characteristics of the inverted staggered thin film transistor can be improved. This heat treatment is not particularly limited as long as it is performed after the formation of an oxygen-excess IGZO film. For example, it can be performed immediately after forming an oxygen-excessive IGZO film or immediately after forming a metal multilayer film.

[0239] Next, each laminated film is patterned using a gray-tone mask. It may be formed by wet etching, or by performing multiple etchings separately and selectively. Selective etching may also be performed.

[0240] The subsequent steps are the same as those of the first to fourth embodiments described above. This makes it possible to fabricate thin film transistors of this type.

[0241] Here, we have taken the example of a multi-chamber manufacturing device, but if the sputtering chamber is Using in-line manufacturing equipment connected in series, continuous film formation is performed without exposure to the atmosphere. This is also fine.

[0242] The apparatus shown in FIG. 18 is a so-called face-down type in which the substrate is set with the surface on which the film is to be formed facing downward. However, the substrate may be placed vertically in the processing chamber. The advantage of this treatment chamber is that it has a smaller footprint than a face-down treatment chamber. Furthermore, this is effective when using a large-area substrate that may bend due to its own weight.

[0243] (Embodiment 7) The thin film transistor of the invention disclosed in this specification is manufactured, and the thin film transistor is used as a pixel portion, Furthermore, a semiconductor device (also called a display device) having a display function can be manufactured by using the semiconductor device in a driver circuit. In addition, the thin film transistor of the invention disclosed in this specification can be used as a part of a driving circuit or The entire display can be integrated onto the same substrate as the pixel section to form a system-on-panel. .

[0244] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0245] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above-mentioned is mounted. Regarding the element substrate, which corresponds to one form before the display element is completed in the process of manufacturing a display device The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, the substrate may be in a state where only pixel electrodes of the display element are formed, or the substrate may be in a state where only pixel electrodes of the display element are formed. After the conductive film that will become the electrode is formed, but before etching is performed to form the pixel electrode. It's fine to have one, and any form is acceptable.

[0246] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0247] In this embodiment, a liquid crystal display device is exemplified as a semiconductor device of the invention disclosed in this specification. .

[0248] 19(A) and (B) show an active matrix type liquid crystal display to which the invention disclosed in this specification is applied. FIG. 19(A) is a plan view of the liquid crystal display device, and FIG. 19(B) is a schematic diagram of the liquid crystal display device. 1A is a cross-sectional view of a thin film transistor 20 used in a semiconductor device. The thin film transistor 1 can be manufactured in the same manner as in the second embodiment, and is an IGZO semiconductor layer. and a highly reliable thin-film transistor that includes an IGZO semiconductor layer with n-type conductivity. The thin film transistor shown in the first embodiment, the third embodiment, or the fourth embodiment may also be used in the present embodiment. The present invention can also be applied to the thin film transistor 201 in the present embodiment.

[0249] The liquid crystal display device of this embodiment shown in FIG. 19(A) includes a source wiring layer 202 and a multi-gate structure. The thin film transistor 201 includes a reverse staggered type, a gate wiring layer 203, and a capacitance wiring layer 204. .

[0250] In addition, in FIG. 19B, the liquid crystal display device of the present embodiment has a thin film transistor having a multi-gate structure. A transistor 201, an insulating layer 211, an insulating layer 212, an insulating layer 213, and a display element The substrate 2 is provided with an electrode layer 255, an insulating layer 261 that functions as an alignment film, and a polarizing plate 268. 00, an insulating layer 263 that functions as an alignment film, an electrode layer 265 used for a display element, A colored layer 264 functioning as a filter, a substrate 266 provided with a polarizing plate 267, and a liquid crystal layer 268 are arranged in the liquid crystal layer 268. 62 and has a liquid crystal display element 260.

[0251] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 262. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to 1 It is optically isotropic, so alignment processing is unnecessary and viewing angle dependency is small. .

[0252] Although FIG. 19 shows an example of a transmissive liquid crystal display device, a semi-transmissive liquid crystal display device may also be used in a reflective liquid crystal display device. This can also be applied to display devices.

[0253] In the liquid crystal display device of FIG. 19, a polarizing plate 267 is provided on the outer side (the viewing side) of the substrate 266. In the example shown, a colored layer 264 and an electrode layer 265 used for a display element are provided in this order on the inside. The plate 267 may be provided on the inside of the substrate 266. Also, the laminated structure of the polarizing plate and the colored layer may be the same as that shown in FIG. However, the present invention is not limited to these values, and may be appropriately set depending on the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. In addition, a light-shielding film that functions as a black matrix may be provided.

[0254] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the transistor, the thin film transistor obtained in the first embodiment is provided with a protective film or The insulating layer 211, the insulating layer 212, and the insulating layer 213 function as a planarizing insulating film. The protective film is made of a material that can withstand organic matter, metals, water vapor, and other substances suspended in the air. The purpose of the protective film is to prevent the intrusion of contaminating impurities, and a dense film is preferable. A single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed by using the above method. The protective film can be formed by laminating organic silane gas and oxygen in the process gas. A silicon oxide film may be formed by plasma CVD using the same.

[0255] Organosilanes are ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethyl Silane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (T MCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilane (HMDS), triethoxysilane (SiH(OC2H5)3), or tris(dimethylamino)silane (TDS). Compounds such as ethylaminosilane (SiH(N(CH3)2)3).

[0256] An insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is a hiroma of an aluminum film. Here, the insulating layer 211 is made of an oxide film using a plasma CVD method. A silicon film is formed. TEOS and O2 are used as process gases for forming the silicon oxide film. The flow rate ratio is TEOS\O2=15\750 (sccm). The temperature is 300℃.

[0257] In addition, an insulating layer 212 is formed as the second layer of the protective film. Silicon nitride film is formed using plasma CVD. The process gas for forming silicon nitride film is , SiH4, N2, NH3 and H2 are used. A silicon nitride film is used as one layer of the protective film. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the above from happening.

[0258] After forming the protective film, the IGZO semiconductor layer is annealed (300°C to 400°C). This is also possible.

[0259] Further, an insulating layer 213 is formed as a planarizing insulating film. The insulating layer 213 is made of polyimide. Heat-resistant organic materials such as acrylic, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low-k materials, silicon materials, etc. can be used. Use oxyxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. Siloxane resins can have hydrogen, fluorine, alkyl groups, or aryl groups as substituents. The insulating film formed of these materials may have at least one of the following groups: The insulating layer 213 may be formed by stacking a plurality of layers.

[0260] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. Siloxane-based resins contain hydrogen, fluorine, alkyl, and aryl groups as substituents. The alkyl group may have at least one of a cyclic group, a cyclic group, or an aromatic hydrocarbon.

[0261] The insulating layer 213 can be formed by a CVD method, a sputtering method, a SOG method, a spin-on method, or the like, depending on the material. Coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater When the insulating layer 213 is formed using a material liquid, a baking process is performed. At the same time, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed. By combining the firing process of the layer 213 with the annealing process of the IGZO semiconductor layer, a semiconductor device can be efficiently manufactured. It becomes possible to create it.

[0262] The electrode layers 255 and 265 functioning as pixel electrode layers are made of indium tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material having such a property can be used.

[0263] The electrode layers 255 and 265 are made of a conductive material including a conductive polymer. The pixel electrode formed by using the conductive composition can be formed by the following steps: Sheet resistance is 10,000 Ω / □ or less, and light transmittance at a wavelength of 550 nm is 70% or more. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm. It is preferable that:

[0264] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0265] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0266] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0267] (Embodiment 8) In this embodiment, an example of an electronic paper will be shown as a semiconductor device of the invention disclosed in this specification. .

[0268] FIG. 26 shows an active matrix semiconductor device as an example of the semiconductor device to which the invention disclosed in this specification is applied. The semiconductor device includes a thin film transistor 581, The thin film transistor can be manufactured in the same manner as in the second embodiment. The thin film transistor is highly reliable and includes an IGZO semiconductor layer having an electrochemical type. The thin film transistor shown in the first embodiment, the third embodiment, or the fourth embodiment is also a thin film transistor of this embodiment. It can also be applied as a transistor 581.

[0269] The electronic paper in FIG. 26 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0270] The thin film transistor 581 on the substrate 580 is a multi-gate structure inverted staggered type thin film transistor. The first electrode layer 587 and the insulating layer 588 are connected by a source electrode layer or a drain electrode layer. The first electrodes 83, 584, and 585 are in contact with each other through openings formed therein and are electrically connected. Between the electrode layer 587 and the second electrode layer 588 provided on the substrate 596 is a black region 590a. and a spherical shape having a white region 590b and a cavity 594 filled with liquid around it. The spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin. (See Figure 26.)

[0271] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0272] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0273] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0274] (Embodiment 9) In this embodiment mode, an example of a light-emitting display device will be described as a semiconductor device of the invention disclosed in this specification. The display device has a display element that uses electroluminescence. The light-emitting element that uses electroluminescence is an organic light-emitting material. They are classified according to whether they are chemical compounds or inorganic compounds. Generally, the former are organic electroluminescence (EL) elements. The latter is called an inorganic EL element.

[0275] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0276] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0277] 22(A) and (B) show an active layer as an example of a semiconductor device to which the invention disclosed in this specification is applied. FIG. 22(A) is a plan view of a light-emitting display device. FIG. 22B is a cross-sectional view taken along line YZ in FIG. 22A. 1 shows an equivalent circuit of the light-emitting display device shown in FIG.

[0278] The thin film transistors 301 and 302 used in the semiconductor device are the same as those in the first embodiment and the second embodiment. The thin film transistor can be fabricated in the same manner as in the second embodiment. The present invention relates to a highly reliable thin film transistor including an IGZO semiconductor layer having a morphology. The thin film transistor shown in the third embodiment or the fourth embodiment is also the thin film transistor 301 of this embodiment. It can also be applied as 302.

[0279] The light-emitting display device of this embodiment shown in FIG. 22(A) and FIG. 23 is a thin film having a multi-gate structure. A transistor 301, a thin film transistor 302, a light emitting element 303, a capacitor element 304, a The thin film transistor 301 includes a gate wiring layer 305, a gate wiring layer 306, and a power supply line 307. 302 is an n-channel thin film transistor.

[0280] In addition, in FIG. 22(B), the light emitting display device of the present embodiment has a thin film transistor on a substrate 300. The transistor 302, the insulating layer 311, the insulating layer 312, the insulating layer 313, the partition wall 321, and the light-emitting The element 303 includes a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323. is.

[0281] The insulating layer 313 is made of an organic resin such as acrylic, polyimide, or polyamide, or siloxane. It is preferable to form the insulating film using the above method.

[0282] In this embodiment, since the thin film transistor 302 of the pixel is an n-type transistor, the first It is preferable to use a cathode as the first electrode layer 320. Materials with small functions, such as Ca, Al, CaF, MgAg, and AlLi, can be used. can.

[0283] The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. A photosensitive material is used to form an opening on the first electrode layer 320, and the sidewall of the opening is continuous. It is preferable to form the inclined surface so as to have a continuous curvature.

[0284] The electroluminescent layer 322 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0285] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The electrode layer 323 is made of a conductive material having light transmission properties as listed in the seventh embodiment for the pixel electrode layer. In addition to the above-mentioned transparent conductive film, a titanium nitride film or A titanium film may be used for the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 32 3 are overlapped to form the light emitting element 303. The second electrode layer 323 and the partition wall 32 are provided to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the A protective film may be formed on the substrate 1. Examples of the protective film include a silicon nitride film, a silicon oxynitride film, and a DLC film. A film or the like can be formed.

[0286] Furthermore, in practice, once the process is completed up to Fig. 22(B), the structure is made airtight to prevent it from being exposed to the outside air. Protective films with high heat resistance and low degassing (laminated films, UV curable resin films, etc.) It is preferable to package (enclose) the container in a container-type container or a cover material.

[0287] Next, the configuration of the light-emitting element will be described with reference to FIG. 24. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figures 24(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are The thin film transistor can be fabricated in the same manner as in the first embodiment. The present invention relates to a highly reliable thin film transistor including an IGZO semiconductor layer having a morphology. The thin film transistor shown in the second embodiment, the third embodiment, or the fourth embodiment is TFT7001, It can also be applied as 011, 7021.

[0288] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light emitting elements with a dual emission structure in which light is emitted from the side of the substrate. The present invention can also be applied to a light emitting element having an emission structure.

[0289] A light emitting element having a top emission structure will be described with reference to FIG.

[0290] In FIG. 24A, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 24(A) shows a cross-sectional view of a pixel when the light incident thereon exits to the anode 7005 side. A cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. 7003 uses various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers may be laminated. When the cathode 7003 is composed of multiple layers, the electron injection layer 7004 is disposed on the cathode 7003. The layers are laminated in this order: electron transport layer, light emitting layer, hole transport layer, and hole injection layer. It is not necessary to provide all of the anodes. The anode 7005 is made of a conductive material that transmits light. For example, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, oxide A light-transmitting conductive film such as indium tin oxide doped with indium may be used.

[0291] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 24(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0292] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is an n-type light emitting element and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, FIG. 24B shows a cross-sectional view of a pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 15 has a light-transmitting property, a shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 may be composed of a single layer, as in FIG. 24(A), or may be composed of multiple layers. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 24(A), the insulating film 24 can be formed using a conductive material having light-transmitting properties. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0293] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 24B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0294] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In this example, a conductive film 7027 having a light-transmitting property and electrically connected to the driving TFT 7021 is formed on the substrate 7022. A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0295] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 24C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0296] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0297] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light-emitting element is electrically connected has been shown, the current between the driving TFT and the light-emitting element is A control TFT may be connected.

[0298] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications are possible based on the technical ideas of the invention disclosed in this specification.

[0299] Through the above steps, a light-emitting display device having high reliability as a semiconductor device can be manufactured. .

[0300] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0301] (Embodiment 10) Next, a structure of a display panel, which is one embodiment of a semiconductor device, will be described below. In the present embodiment, a liquid crystal display panel (LCD panel) is a type of liquid crystal display device having liquid crystal elements as display elements. A light-emitting display, which is one type of semiconductor device having light-emitting elements as display elements, is also called a liquid crystal panel. Next, a display panel (also called a light-emitting panel) will be described.

[0302] Next, the appearance and structure of a light-emitting display panel, which corresponds to one embodiment of a semiconductor device of the invention disclosed in this specification, will be described. The cross section of the IGZ formed on the first substrate will be described with reference to FIG. A highly reliable thin-film transistor including an IGZO semiconductor layer having an n-type conductivity and an IGZO semiconductor layer having an n-type conductivity. FIG. 1 is a top view of a panel in which a light emitting element and a second substrate are sealed with a sealant. FIG. 25B corresponds to a cross-sectional view taken along line HI in FIG. 25A.

[0303] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. 4507. It is sealed together with the filler material 4507 by

[0304] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 25B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0305] The thin film transistors 4509 and 4510 are I-type transistors having an IGZO semiconductor layer and an n-type conductivity type. This corresponds to a thin film transistor including a GZO semiconductor layer, and is the same as in the first embodiment, the second embodiment, and the third embodiment. The thin film transistor described in Embodiment 3 or 4 can be used. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors. do.

[0306] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is not limited to that shown in this embodiment mode. The structure of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. The composition can be changed as appropriate.

[0307] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0308] In this embodiment mode, the connection terminal 4515 is formed from the same conductive film as the second electrode layer 4512. The wiring 4516 is made of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. has been formed.

[0309] The connection terminal 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive film 4519. are electrically connected.

[0310] The substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film, or an acrylic film. A light-transmitting material such as a film is used.

[0311] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler. was used.

[0312] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0313] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the circuit or only a part of the circuit may be separately formed and mounted. In this embodiment, the circuit shown in FIG. Not limited.

[0314] Next, the appearance and structure of a liquid crystal display panel, which corresponds to one embodiment of the semiconductor device of the present invention disclosed in this specification, will be described. The cross section will be described with reference to FIG. 20. FIG. 20 shows a cross section of a semiconductor device formed on a first substrate 4001. A highly reliable thin film including an IGZO semiconductor layer having a high conductivity type and an IGZO semiconductor layer having an n-type conductivity type. The transistors 4010 and 4011 and the liquid crystal element 4013 are disposed between the second substrate 4006 and the FIG. 20(B) is a top view of the panel sealed with a sealant 4005. (A1) corresponds to the cross-sectional view at MN in (A2).

[0315] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0316] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 20A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0317] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 20B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The following are given as examples:

[0318] The thin film transistors 4010 and 4011 are I-type transistors having an IGZO semiconductor layer and an n-type conductivity type. This corresponds to a thin film transistor including a GZO semiconductor layer, and is the same as in the first embodiment, the second embodiment, and the third embodiment. The thin film transistor described in Embodiment 3 or 4 can be used. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. do.

[0319] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0320] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, polyester film Alternatively, acrylic resin film can be used. Aluminum foil can also be used as a PVF film. A sheet having a structure sandwiched between films or polyester films can also be used.

[0321] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may also be used.

[0322] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0323] In this embodiment, the connection terminal 4015 is connected to the pixel electrode layer 4030 of the liquid crystal element 4013. The wiring 4016 is formed from the same conductive film as the thin film transistors 4010 and 4011. The gate electrode layer is formed from the same conductive film.

[0324] The connection terminal 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0325] In FIG. 20, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0326] FIG. 21 shows a semiconductor device using a TFT substrate 2600 produced by applying the invention disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0327] FIG. 21 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604, a colored layer 2605, and a polarizing plate 2606 are provided to form a display area. The color layer 2605 is necessary for color display. In the case of the RGB method, it is red, green, A colored layer corresponding to each color of blue and blue is provided for each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed on the outer side of the optical substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611. The circuit board 2612 is , and is connected to a wiring circuit section 2608 of the TFT substrate 2600 via a flexible wiring substrate 2609. It also includes external circuits such as a control circuit and a power supply circuit. The liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0328] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic) ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid C rystal) mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0329] Through the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0330] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0331] (Embodiment 11) The semiconductor device of the invention disclosed in this specification can be applied as electronic paper. The child paper can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. This can be applied to in-vehicle advertisements, displays on various cards such as credit cards, etc. An example of the electronic device is shown in Figures 28 and 29.

[0332] FIG. 28(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisement exchange is done manually, but the invention disclosed in this specification By using electronic paper with lighting, advertisement display can be changed in a short time. The display is stable and the image is not distorted. The poster can send and receive information wirelessly. It may be configured so that

[0333] FIG. 28(B) shows an advertisement 2632 on a train or other vehicle. In the case of paper-based printed matter, the advertisements are exchanged manually. By using electronic paper to which the invention is applied, advertisements can be displayed in a short time without much manpower. You can change it. You can also get a stable image without the display collapsing. The device may be configured to transmit and receive information wirelessly.

[0334] FIG. 29 also shows an example of an electronic book 2700. For example, the electronic book 2700 is The device is made up of two housings, a housing 2701 and a housing 2703. The body 2703 is integrated with a shaft portion 2711, and the opening and closing movement is performed around the shaft portion 2711. This configuration allows the device to operate like a paper book. It becomes.

[0335] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 29) and An image can be displayed on the display unit 2707 in FIG.

[0336] FIG. 29 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0337] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0338] (Embodiment 12) The semiconductor device according to the invention disclosed in this specification is applicable to various electronic devices (including game machines). The electronic device can be used, for example, a television device (television, or television) (also called revision receivers), computer monitors, digital cameras, digital Video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) ), portable game machines, personal digital assistants, audio playback devices, pachinko machines and other large game machines, etc. Examples include:

[0339] FIG. 30(A) shows an example of a television device 9600. The display unit 9703 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0340] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0341] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0342] FIG. 30B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0343] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0344] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0345] FIG. 31(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 31(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the present invention is It is sufficient that the semiconductor device is provided in one embodiment, and other auxiliary equipment is appropriately provided. The portable game machine shown in FIG. 31(A) can be configured as a game machine having a game data recorded on a recording medium. The function of reading out programs or data and displaying them on the display unit, as well as wireless communication with other portable gaming machines, The portable gaming machine shown in FIG. 31(A) has a function of communicating with the user and sharing information. The functions are not limited to these, and the device may have a variety of functions.

[0346] FIG. 31(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. However, the present invention is not limited to the above, and may be configured to include at least one aspect of the semiconductor device according to the present invention. In addition, other auxiliary equipment may be provided as appropriate.

[0347] FIG. 32 shows an example of a mobile phone 1000. The mobile phone 1000 has a housing 100 In addition to the display unit 1002 incorporated in the device 1, the device 1002 also includes an operation button 1003, an external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0348] The mobile phone 1000 shown in FIG. 32 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or typing an e-mail can be performed by the display unit 100. This can be done by touching 2 with a finger or other object.

[0349] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0350] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0351] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0352] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0353] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0354] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

Claims

1. A display device having a pixel including a transistor and a capacitor, a first conductive layer located over a first substrate and functioning as a gate electrode of a transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; a first semiconductor layer having a region located on the first insulating layer and having a channel formation region of the transistor; a second semiconductor layer having a region located on the first semiconductor layer; a third semiconductor layer having a region located on the first semiconductor layer; a second conductive layer having a region in contact with a top surface of the second semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor and as an electrode of the capacitor; a third conductive layer having a region in contact with a top surface of the third semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a second insulating layer having a region located on the second conductive layer and the third conductive layer, a region in contact with an upper surface of the second semiconductor layer, and a region in contact with an upper surface of the third semiconductor layer; When viewed in a cross section of the transistor in a channel length direction, the second semiconductor layer has a portion that protrudes toward the channel formation region beyond an end of the second conductive layer, When viewed in a cross section of the transistor in a channel length direction, the third semiconductor layer has a portion that protrudes toward the channel formation region beyond an end of the third conductive layer, the second conductive layer has a region in contact with a top surface of the first insulating layer and a region in contact with a side surface of the second semiconductor layer; the third conductive layer has a region in contact with an upper surface of the first insulating layer and a region in contact with a side surface of the third semiconductor layer.

2. A display device having a pixel including a transistor and a capacitor, a first conductive layer located over a first substrate and functioning as a gate electrode of a transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; a first semiconductor layer having a region located on the first insulating layer and having a channel formation region of the transistor; a second semiconductor layer having a region located on the first semiconductor layer; a third semiconductor layer having a region located on the first semiconductor layer; a second conductive layer having a region in contact with a top surface of the second semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor and as an electrode of the capacitor; a third conductive layer having a region in contact with a top surface of the third semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a second insulating layer having a region located on the second conductive layer and the third conductive layer, a region in contact with an upper surface of the second semiconductor layer, and a region in contact with an upper surface of the third semiconductor layer; When viewed in a cross section of the transistor in a channel length direction, the second semiconductor layer has a portion that protrudes toward the channel formation region beyond an end of the second conductive layer, When viewed in a cross section of the transistor in a channel length direction, the third semiconductor layer has a portion that protrudes toward the channel formation region beyond an end of the third conductive layer, the second conductive layer has a region in contact with a top surface of the first insulating layer and a region in contact with a side surface of the second semiconductor layer; the third conductive layer has a region in contact with an upper surface of the first insulating layer and a region in contact with a side surface of the third semiconductor layer, A display device, wherein a thickness of a region of the first semiconductor layer that overlaps with the second semiconductor layer is greater than a thickness of the channel formation region, and a thickness of a region of the first semiconductor layer that overlaps with the third semiconductor layer is greater than a thickness of the channel formation region.

Images