Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing deterioration in forward voltage and loss in turning on.SOLUTION: A vertical type MOSFET comprises a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer 1 of the first conductivity type, a second conductor layer 16 of a second conductivity type, a first semiconductor region 17 of the first conductivity type, a second semiconductor region 3 of the second conductivity type, a third semiconductor region 4 of the second conductivity type, a first trench 31 and a second trench 32, a gate electrode 20 provided inside the first trench 31 across a gate insulation film 19, and a Schottky electrode 26 provided inside the second trench 32. In a region 41 between an active region 40 where a current flows in an ON state and an edge region 42 which surrounds the active region 40 to stay voltage-withstanding, a side wall of the second trench 32 is in contact with neither of the second semiconductor region 3 and third semiconductor region 4.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, vertical MOSFETs (Metal Oxidized Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) in power semiconductor elements to reduce the on-resistance of the elements. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface can increase the cell density per unit area compared to a planar structure in which the channel is formed parallel to the substrate surface, and therefore the current density per unit area can be increased, which is advantageous in terms of cost.

[0003] Vertical MOSFETs incorporate a parasitic pn diode formed by a p-type base layer and an n-type drift layer as a body diode between the source and drain. This allows the free wheeling diode (FWD) used in inverters to be omitted, contributing to cost reduction and miniaturization. However, when a silicon carbide substrate is used as the semiconductor substrate, the parasitic pn diode has a higher built-in potential than when a silicon (Si) substrate is used, which increases the on-resistance of the parasitic pn diode and leads to increased loss. In addition, when the parasitic pn diode is turned on and current is passed, the bipolar operation of the parasitic pn diode causes the characteristics to change over time (aging degradation), resulting in forward degradation and increased turn-on loss.

[0004] To address this issue, a Schottky Barrier Diode (SBD) can be connected in parallel with the MOSFET so that current flows through the SBD during freewheeling and no current flows through the parasitic pn diode. However, this increases costs because the number of SBD chips required is roughly the same as that of MOSFETs.

[0005] For this reason, a technology has been proposed in which a contact trench is formed on the surface of the substrate that penetrates the p-type channel portion, an SBD is embedded in the inner wall of the trench, and the return current flows through the built-in SBD instead of a PiN diode (see, for example, Patent Document 1 below).

[0006] Fig. 13 is a top view showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. Fig. 14 is a cross-sectional view of the C-C' portion of Fig. 13 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in Fig. 13, a silicon carbide semiconductor device 150 with an SBD built in includes an active region 140 in which an element structure is formed and through which a current flows when the device is in an on-state, an edge region 142 surrounding the periphery of the active region 140 and maintaining a breakdown voltage, and a transition region 141 between the active region 140 and the edge region 142. The active region 140 is the region surrounded by a dashed line in Fig. 13.

[0007] 14, a MOS gate having a general trench gate structure is provided on the front surface (the surface on the side of a p-type base layer 116 described later) of a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate). + Mold support substrate (hereinafter referred to as n + A silicon carbide substrate (102) is formed on the n - The n-type drift layer 101, the n-type region 115 which is a current diffusion region, and the p-type base layer 116 are formed by epitaxially growing silicon carbide layers in this order.

[0008] n + On a silicon carbide substrate 102 - The n-type drift layer 101 - The n-type layer is epitaxially grown. + The front surface (n - On the side of the drift layer 101, a p-type base layer 116 and an n-type + A MOS gate structure is provided, which is made up of a type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120. Reference numerals 118, 121, and 122 denote p ++a type contact region, an interlayer insulating film, and a source electrode.

[0009] In the n-type region 115, a first p + The n-type region 115 is provided with a first p-type region 103 so as to cover the entire bottom surface of the trench SBD 132. + A mold region 103 is selectively provided. + The type region 103 is - The edge region 142 is provided at a depth not reaching the first p drift layer 101. + The second p + A mold area 104 is provided.

[0010] Moreover, trench SBD 132 is a trench whose inner wall is covered with Schottky metal 126 connected to source electrode 122, and a Schottky is formed between the semiconductor region exposed on the inner wall and Schottky metal 126. In this manner, in Fig. 13, a parasitic Schottky diode (built-in SBD) is provided in parallel with the parasitic pn diode between the source and drain.

[0011] A positive voltage is applied to the source electrode 122, and n + When a negative voltage is applied to a drain electrode (not shown) provided on the back surface of the silicon carbide substrate 102 (when the MOSFET is off), the p-type base layer 116 and the n-type - The pn junction between the MOSFET and the type drift layer 101 is forward biased. In Fig. 13, by designing the parasitic Schottky diode to turn on before the parasitic pn diode turns on when the MOSFET is off, the bipolar operation of the parasitic pn diode can be suppressed and deterioration over time due to the bipolar operation can be prevented.

[0012] In addition, the n-type region, the first p + Type region and 2nd p + a first p-type region in a region facing a gate electrode pad connected to the gate electrode in a depth direction; +A semiconductor device is known in which the type regions are spaced apart in the width direction of the trench gate, preventing the PiN diode from operating in bipolar mode up to the current region, thereby reducing degradation of the forward voltage and loss at turn-on (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 8-204179 [Patent Document 2] JP 2019-102554 A Summary of the Invention [Problem to be solved by the invention]

[0014] 15 is a cross-sectional view of a portion A-A' in FIG. 13 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. FIG. 16 is a cross-sectional view of a portion B-B' in FIG. 13 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in FIGS. 15 and 16, in the transition region 141, the first p + The second p + The p-type region 104 is provided on the surface of the p-type base layer 116. ++ Therefore, in the transition region 141, the trench SBD 132 is surrounded by a p-type region (the p-type base layer 116, the p ++ Type contact region 118, first p + The mold region 103 and the second p + The structure is surrounded by a mold region 104).

[0015] As a result, in the transition region 141, the trench SBD 132 does not function as a parasitic Schottky diode and cannot suppress the bipolar operation of the parasitic pn diode. When the parasitic pn diode is turned on and conducts current, the bipolar operation of the parasitic pn diode causes a hole current to flow along path D in Figures 15 and 16, and stacking faults are generated and expanded by the energy generated by recombination of the hole current and electron current.

[0016] Therefore, the transition region 141 has a problem that the characteristics change over time (deterioration due to aging) due to the bipolar operation of the parasitic pn diode, and this causes forward deterioration and increased turn-on loss, more than the inside of the active region 140.

[0017] SUMMARY OF THE PRESENT EMBODIMENT In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a semiconductor device capable of reducing the degradation of the forward voltage and the loss at turn-on. [Means for solving the problem]

[0018] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer to the semiconductor substrate. A first semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer. A second semiconductor region of a second conductivity type is provided inside the first semiconductor layer. A third semiconductor region of a second conductivity type having a bottom surface in contact with the second semiconductor region is provided in a surface layer of the first semiconductor layer. A first trench and a second trench are provided, which penetrate the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer and have a bottom surface in contact with the second semiconductor region. A gate electrode is provided inside the first trench via a gate insulating film. A Schottky electrode is provided inside the second trench. In the region between an active region through which current flows in an on-state and an edge region that surrounds the active region and maintains a withstand voltage, the sidewalls of the second trench are not in contact with the second semiconductor region and the third semiconductor region. The edge region is provided with a junction termination structure for improving breakdown voltage and a fourth semiconductor region of a second conductivity type, and the width between the second semiconductor region and the fourth semiconductor region is greater than or equal to the width between adjacent second semiconductor regions in the active region and is narrower than the distance from the second semiconductor region to the junction termination structure.

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer to the semiconductor substrate. A first semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer. A second semiconductor region of a second conductivity type is provided inside the first semiconductor layer. A third semiconductor region of a second conductivity type having a bottom surface in contact with the second semiconductor region is provided in a surface layer of the first semiconductor layer. A first trench and a second trench are provided, which penetrate the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer and have a bottom surface in contact with the second semiconductor region. A gate electrode is provided inside the first trench via a gate insulating film. A Schottky electrode is provided inside the second trench. In a region between an active region through which a current flows in an on-state and an edge region surrounding the active region and maintaining a breakdown voltage, a sidewall of the second trench is not in contact with the second semiconductor region and the third semiconductor region. A fifth semiconductor region of a second conductivity type having an impurity concentration higher than that of the second semiconductor layer is selectively provided inside the second semiconductor layer and in contact with the first semiconductor region, and in the region, the fifth semiconductor region is located closer to the active region than the side surface of the second trench on the edge region side.

[0021] According to the above-mentioned invention, in the transition region, the sidewall of the trench SBD (second trench) is + The trench SBD does not contact the transition region (the second and third semiconductor regions of the second conductivity type). This allows the trench SBD to function as a parasitic Schottky diode even in the transition region. Therefore, when a negative bias is applied to the drain side of a silicon carbide semiconductor device with an SBD built in, the parasitic Schottky diode can be operated in the transition region as well, thereby suppressing the bipolar operation of the parasitic pn diode and suppressing forward degradation and increases in turn-on loss. Effect of the Invention

[0022] The semiconductor device according to the present invention has the effect of reducing the degradation of the forward voltage and the loss at the time of turn-on. [Brief description of the drawings]

[0023] [Figure 1] 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Diagram 2] 2 is a cross-sectional view taken along line AA' of FIG. 1 showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 3] 2 is a cross-sectional view taken along the line BB' of FIG. 1, showing a structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4] 2 is a cross-sectional view taken along the line CC' of FIG. 1 showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 5] 1 is a top view showing an external appearance of a silicon carbide semiconductor device according to an embodiment; [Figure 6] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). [Figure 7] 5A to 5C are cross-sectional views (part 2) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 8] 6A to 6C are cross-sectional views (part 3) illustrating a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 9] 4 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 4). FIG. [Figure 10] 5 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 5). FIG. [Figure 11] FIG. 1 is a diagram showing hole current density in a conventional silicon carbide semiconductor device with an SBD built in. [Figure 12] FIG. 4 is a diagram showing hole current density of the silicon carbide semiconductor device according to the embodiment. [Figure 13] FIG. 1 is a top view showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Figure 14]14 is a cross-sectional view taken along the line CC' of FIG. 13, showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Figure 15] 14 is a cross-sectional view taken along line AA' of FIG. 13 showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Figure 16] 14 is a cross-sectional view taken along the line BB' of FIG. 13, showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] A preferred embodiment of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the layer or region has a higher impurity concentration and a lower impurity concentration than the layer or region not prefixed with n or p. In the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0025] (Embodiment) The semiconductor device according to the present invention is configured using a semiconductor having a wider band gap than silicon (hereinafter, referred to as wide band gap semiconductor). Here, the structure of a semiconductor device (silicon carbide semiconductor device) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described as an example. FIG. 1 is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view of a portion A-A' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view of a portion B-B' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view of a portion C-C' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment.

[0026] As shown in FIG. 1, a silicon carbide semiconductor device 50 with an SBD is composed of an active region 40 in which an element structure is formed and a main current flows in the thickness direction of the substrate when the device is in an on-state, an edge region 42 that surrounds the active region 40 and maintains a breakdown voltage, and a transition region 41 between the active region 40 and the edge region 42. The active region 40 is a region surrounded by a dashed line in FIG. 1. The transition region 41 is a region in which the side of a trench gate 31 described later is covered with a p-type region and does not function as a MOS, as shown in FIG. 2. Only one unit cell (functional unit of an element) is shown in FIG. 2 and other unit cells adjacent thereto are omitted. The silicon carbide semiconductor device according to the embodiment shown in FIG. 1 to FIG. 3 is a MOSFET having a MOS gate on the front surface (the surface on the p-type base layer 16 described later) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0027] The silicon carbide substrate is a n-type silicon carbide substrate. + On a support substrate (a semiconductor substrate of a first conductivity type) 2, - The n-type drift layer (first semiconductor layer of a first conductivity type) 1 and the p-type base layer (second semiconductor layer of a second conductivity type) 16 are epitaxially grown in sequence. In the active region 40, the MOS gate is formed by epitaxially growing the p-type base layer 16 and the n-type + The n-type source region (first semiconductor region of the first conductivity type) 17, the gate insulating film 19, and the gate electrode 20 are configured as follows. - An n-type region 15 may be provided in the surface layer on the source side (the side of a source electrode 22 described later) of the drift layer 1 so as to be in contact with the p-type base layer 16. The n-type region 15 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type region 15 is provided uniformly in a direction parallel to the front surface of the substrate (front surface of the silicon carbide substrate), for example. The n-type region 15 is not shown in Figs. 2 and 3.

[0028] n-type region 15 (n-type region 15 not provided) - The inside of the first drift layer 1 (hereinafter referred to as (1)) is +In the active region 40, a first p-type region (a second semiconductor region of a second conductivity type) 3 is selectively provided. + The n-type region 3 is provided so as to be in contact with the bottom surface of a trench gate (first trench) 31 (to be described later) and the bottom surface of a trench SBD (second trench) 32 (to be described later). + A second p type region (a third semiconductor region of a second conductivity type) 4 is selectively provided. + The mold region 4 has a bottom surface of the first p + It is provided so as to be in contact with the mold region 3 .

[0029] When the n-type region 15 is provided, the first p + The p-type region 3 is connected to the n-type region 15 from a position deeper on the drain side than the interface between the p-type base layer 16 and the n-type region 15. - The first p + By providing the mold region 3, the first p + A pn junction between the first p-type region 3 and the n-type region 15(1) can be formed. + Type 3 and 2p + The p-type region 4 has a higher impurity concentration than the p-type base layer 16 .

[0030] In addition, the p-type base layer 16 includes n + The n-type source region 17 is selectively provided. + type source region 17 and p ++ A p-type contact region (a fifth semiconductor region of the second conductivity type) 18 may be selectively provided. ++ The depth of the contact region 18 is, for example, n + It may be the same depth as the n-type source region 17, + It may be deeper than the source region 17 .

[0031] The trench gate 31 is formed on the front surface of the substrate. +The gate electrode 20 is electrically connected to a gate electrode pad (not shown). The interlayer insulating film 21 is provided on the entire front surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31. The gate insulating film 19 is provided inside the trench gate 31 along the sidewall of the trench gate 31, and a gate electrode 20 is provided inside the gate insulating film 19. The source side end of the gate electrode 20 may or may not protrude outward from the front surface of the substrate. The gate electrode 20 is electrically connected to a gate electrode pad (not shown). The interlayer insulating film 21 is provided on the entire front surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31.

[0032] The trench SBD32 is formed from the front surface of the substrate + The trench SBD32 penetrates through the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The inside of the trench SBD32 is covered along the sidewall of the trench SBD32 with a Schottky metal 26 that connects to the source electrode 22, and forms a Schottky junction between the semiconductor region exposed on the inner wall and the Schottky metal 26. An oxide film, for example, silicon dioxide (SiO2), may be provided on the inside of the Schottky metal 26.

[0033] Here, as shown in FIG. 1 and FIG. 3, in the edge region 42, the first p + On the mold region 3, the second p + p-type region 4 formed + Type area (1st p + Area 3 and 2nd p + The area including the type region 4 is p + A fourth semiconductor region (5) of the second conductivity type is provided. As shown in FIG. 1, the trench gate 31 extends to an edge region 42 to connect to a gate runner (not shown). As shown in FIG. 2, the trench gate 31 does not function as a MOS in the transition region 41, so that the sidewalls and bottom surface of the trench gate 31 are connected to the first and second p-type regions 42. + It is in contact with mold regions 3 and 4.

[0034] On the other hand, as shown in FIGS. 1 to 3, in the transition region 41, the sidewall of the trench SBD 32 is +In other words, in a conventional silicon carbide semiconductor device with an SBD built in, the p + By opening a part of the n-type region 5, the sidewall of the trench SBD 32 of the embodiment is in contact with the n-type region 15(1). This allows the trench SBD 32 to function as a parasitic Schottky diode even in the transition region 41. Therefore, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD built in, the parasitic Schottky diode can be operated also in the transition region 41, thereby suppressing the bipolar operation of the parasitic pn diode, and suppressing forward degradation and an increase in turn-on loss.

[0035] 5 is a top view showing the appearance of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. 5, the trench SBD 32 and the trench gate 31 are n + The edge regions 42 are provided in stripes in the direction in which the crystal orientation of the silicon carbide substrate 1 is <11-20>. In the edge regions 42, a JTE region 43 is provided as a junction termination extension (JTE) structure in order to improve the breakdown voltage of the entire high-voltage semiconductor device by relaxing or dispersing an electric field. Outside the JTE region 43, a n-type silicon carbide substrate 41 is provided, which functions as a channel stopper. + A mold semiconductor region (not shown) is provided.

[0036] In the embodiment, p + The first p-type region 5 and the first p-type region 10 are provided at the bottom of the trench SBD 32. + The width w1 (see FIG. 3) between the first p-type regions 3 and adjacent p-type regions 3 in the active region 40 is + It is preferable that the width w1 is equal to or larger than the width w2 between the first and second regions 3 (the width of the JFET region, see FIG. 14). + It is preferable that the distance is narrower than the distance w3 (see FIG. 5) from the mold region 3 to the JTE region 43. By doing so, the embodiment can maintain the same level of withstand voltage as the conventional one.

[0037] In the conventional silicon carbide semiconductor device with an SBD built in, the surface layer of the p-type base layer 116 in the joint region 141 is provided with p ++ A type contact region 118 is provided to surround the sidewall of the trench SBD 132 (see FIGS. 13, 15, and 16). This makes it easier for a parasitic pn diode to operate in the transition region 141. ++ When the contact region 18 is provided, as shown in FIG. ++ The position of the contact region 18 is located inside (closer to the active region 40) than the side surface of the trench SBD 32 on the edge region 42 side. ++ 18, p-type base layer 16, n - The structure in which the type drift layers 1 are vertically arranged is eliminated, making it difficult for a parasitic pn diode to operate in the transition region 41.

[0038] The source electrode 22 is connected to the n-type + The p-type source region 17 is in contact with the p-type source region 17 and is electrically insulated from the gate electrode 20 by an interlayer insulating film 21. ++ When the contact region 18 is provided, the source electrode 22 is ++ The source electrode 22 also contacts the type contact region 18. A barrier metal for preventing diffusion of metal atoms from the source electrode 22 toward the gate electrode 20 may be provided between the source electrode 22 and the interlayer insulating film 21. A source electrode pad (not shown) is provided on the source electrode 22. The back surface (n + n-type drain region + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 1.

[0039] (Method of Manufacturing a Semiconductor Device According to an Embodiment) Next, a method for manufacturing the semiconductor device according to the embodiment will be described. FIGS. 6 to 9 are cross-sectional views showing a state during the manufacturing process of the silicon carbide semiconductor device according to the embodiment. First, n + n-type drain region +A silicon carbide substrate 2 is prepared. Next, + The front surface of the silicon carbide substrate 2 is - The n-type drift layer 1 is epitaxially grown. - The epitaxial growth conditions for forming the n-type drift layer 1 are as follows: - The impurity concentration of the drift layer 1 is 3×10 15 / cm 3 The state up to this point is shown in FIG.

[0040] Next, n - A lower n-type region 15a (if the n-type region 15 is not formed, the n-type drift layer 1) is formed on the - The n-type layer (hereinafter abbreviated as n-type layer) having the same impurity concentration as that of the n-type drift layer 1 is epitaxially grown. For example, the epitaxial growth conditions for forming the lower n-type region 15a are set as follows: the impurity concentration of the lower n-type region 15a is 1×10 17 / cm 3 The lower n-type region 15a is a part of the n-type region 15. Next, a first p-type impurity is formed on the surface layer of the lower n-type region 15a (n-type layer) by photolithography and ion implantation of p-type impurities. + The mold region 3 is selectively formed. For example, the first p + The dose of ions implanted to form the mold region 3 is set to 5×10 18 / cm 3 Similarly, in the transition region 41 and the edge region 42, the first p + A mold region 3 is selectively formed. The state up to this point is illustrated in FIG.

[0041] Next, the lower n-type region 15a (n-type layer), the first p +An upper n-type region 15b (n-type layer) is epitaxially grown on the n-type region 3. For example, the epitaxial growth conditions for forming the upper n-type region 15b may be set to have an impurity concentration similar to that of the lower n-type region 15a. The upper n-type region 15b is a part of the n-type region 15, and the lower n-type region 15a and the upper n-type region 15b together form the n-type region 15. Next, a second p-type impurity is formed in the surface layer of the upper n-type region 15b (n-type layer) by photolithography and ion implantation of p-type impurities. + The mold region 4 is selectively formed. For example, the second p + The dose of ions implanted to form the type region 4 is set to a value corresponding to the first p + The thickness of the first p + Type region 3 and 2p + The region including the mold region 4 is called the first and second p + The mold regions 3 and 4 are also called mold regions 3 and 4. Similarly, the second p + The mold region 4 is selectively formed. + When the mold region 4 is formed, the sidewall of the trench SBD 32 is formed in the transition region 41 so as to be the second p + It is formed so as not to come into contact with the mold region 4. The state up to this point is shown in FIG.

[0042] Next, the upper n-type region 15b and the second p + A p-type base layer 16 is epitaxially grown on the doped region 4. For example, the epitaxial growth conditions for forming the p-type base layer 16 are set as follows: the impurity concentration of the p-type base layer 16 is 4×10 17 / cm 3 The setting may be made so as to be about the same.

[0043] Next, photolithography and ion implantation of n-type impurities are performed to form n-type impurities in the surface layer of the p-type base layer 16. + The n-type source region 17 is selectively formed. For example, + The dose of ions implanted to form the source region 17 is set to 3×10 20 / cm 3 The setting may be made so as to be about the same.

[0044] Next, by photolithography and ion implantation of p-type impurities, n + The p ++ The p-type contact region 18 may be selectively formed. For example, ++ The dose of ions implanted to form the contact region 18 is set to 3×10 20 / cm 3 It may be set to about n + Type source region 17 and p ++ The order of forming the first and second contact regions 18 may be reversed. Next, the JTE region 43 is formed in the edge region 42 by photolithography and ion implantation of p-type impurities. After all ion implantation is completed, activation annealing is performed. The state up to this point is shown in FIG.

[0045] Next, by photolithography and etching, + A trench gate 31 is formed through the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The bottom of the trench gate 31 is a first p + The p-type region 3 may extend between the p-type base layer 16 and the first p + The trench gate 31 may be located within the n-type region 15(1) sandwiched between the n-type regions 3. Next, the mask used to form the trench gate 31 is removed. An oxide film is used as a mask when forming the trench. After the trench etching, isotropic etching may be performed to remove damage to the trench gate 31, and hydrogen annealing may be performed to round the corners of the bottom of the trench gate 31 and the opening of the trench gate 31. Only one of isotropic etching and hydrogen annealing may be performed. Hydrogen annealing may be performed after isotropic etching.

[0046] Next, by photolithography and etching, + A trench SBD32 is formed so as to penetrate the p-type source region 17 and the p-type base layer 16 and reach the n-type region 15(1). The bottom of the trench SBD32 is a first p +The p-type region 3 may extend between the p-type base layer 16 and the first p + The n-type region 15(1) may be located between the n-type regions 3. Then, the mask used to form the trench SBD 32 is removed. At this time, the end T of the trench gate 31 and the p + The distance w1 of the mold region 5 is equal to or greater than the interval w2 between the trench gates 31. + It is formed so as to be narrower than the width w3 between the mold region 3 and the JTE region 43. The state up to this point is shown in FIG.

[0047] Next, a gate insulating film 19 is formed along the front surface of the silicon carbide substrate and the inner wall of the trench gate 31. Next, for example, polysilicon is deposited and etched so as to fill the trench gate 31, thereby leaving polysilicon that will become the gate electrode 20 inside the trench gate 31. At that time, etching may be performed by etching back so that the polysilicon is left inside the surface part of the substrate, or patterning and etching may be performed so that the polysilicon protrudes outside the surface part of the substrate.

[0048] Next, a metal film made of, for example, titanium (Ti) is formed along the inner wall of the trench SBD 32. Next, a heat treatment (annealing) is performed in a nitrogen (N2) atmosphere at a temperature of, for example, about 500° C. or less to form a Schottky junction between the metal film and the semiconductor region on the inner wall of the trench SBD 32.

[0049] Next, an interlayer insulating film 21 is formed on the entire front surface of the silicon carbide substrate so as to cover the gate electrode 20. The interlayer insulating film 21 is formed of, for example, NSG (Non-doped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. Next, the interlayer insulating film 21 and the gate insulating film 19 are patterned to form contact holes, and n + The source region 17 is exposed. ++When the n-type contact region 18 is formed, + type source region 17 and p ++ The mold contact area 18 is exposed.

[0050] Next, a barrier metal is formed and patterned so as to cover the interlayer insulating film 21. + type source region 17 and p ++ The n-type contact region 18 is then exposed again. + A source electrode 22 is formed so as to be in contact with the type source region 17. The source electrode 22 may be formed so as to cover the barrier metal, or may be left only in the contact hole.

[0051] Next, a source electrode pad is formed so as to fill the contact hole. A part of the metal layer deposited to form the source electrode pad may be used as a gate electrode pad. + On the back surface of the silicon carbide substrate 2, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the drain electrode by sputter deposition or the like. This metal film may be a laminate of a combination of Ni films and Ti films. Then, annealing such as rapid thermal annealing (RTA) is performed so that the metal film is silicided to form an ohmic contact. Then, a thick film such as a laminate film in which a Ti film, a Ni film, and a gold (Au) are laminated in this order is formed by electron beam (EB) deposition or the like to form the drain electrode.

[0052] In the above-mentioned epitaxial growth and ion implantation, for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc., which are n-type impurities (n-type dopants) for silicon carbide, may be used. For example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., which are p-type impurities for silicon carbide, may be used. In this manner, the MOSFET shown in FIGS. 1 to 4 is completed.

[0053] Fig. 11 is a diagram showing the hole current density of a conventional silicon carbide semiconductor device with an SBD built in. Fig. 12 is a diagram showing the hole current density of a silicon carbide semiconductor device according to an embodiment. Figs. 11 and 12 show simulation results of the hole current density in a reverse bias state at Vds=-5V and 150°C. In Figs. 11 and 12, the vertical axis indicates the depth from the front surface of the silicon carbide substrate in µm. The horizontal axis indicates the length from the end of trench SBD 32 of active region 40 (T in Fig. 1) in µm.

[0054] 11 and 12, in the silicon carbide semiconductor device according to the embodiment, the hole current density in the transition region 41 is significantly lower than that in the conventional silicon carbide semiconductor device with an SBD built in. Therefore, in the silicon carbide semiconductor device according to the embodiment, n + The number of holes entering the silicon carbide substrate 1 is reduced, and the generation and expansion of stacking faults can be suppressed.

[0055] As described above, according to the embodiment, in the transition region 41, the sidewall of the trench SBD is the first and second p + The trench SBD does not contact the die region. This allows the trench SBD to function as a parasitic Schottky diode even in transition region 41. Therefore, when a negative bias is applied to the drain side of a silicon carbide semiconductor device incorporating an SBD, the bipolar operation of the parasitic pn diode can be suppressed by operating the parasitic Schottky diode even in transition region 41, thereby suppressing forward degradation and an increase in turn-on loss.

[0056] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions and impurity concentration of each part are set in various ways according to the required specifications. In addition, in each of the above-mentioned embodiments, a MOSFET is used as an example, but the present invention is not limited to this and can be widely applied to various silicon carbide semiconductor devices that conduct and cut off current by being gate-driven and controlled based on a predetermined gate threshold voltage. Examples of silicon carbide semiconductor devices that are gate-driven and controlled include IGBTs (Insulated Gate Bipolar Transistors). In each of the above-mentioned embodiments, a case where silicon carbide is used as a wide band gap semiconductor is described as an example, but the present invention can also be applied to wide band gap semiconductors other than silicon carbide, such as gallium nitride (GaN). In each of the above-mentioned embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0057] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for silicon carbide semiconductor devices with a trench gate structure. [Explanation of symbols]

[0058] 1, 101 n - Mold drift layer 2, 102 n + Silicon carbide substrate 3, 103 1st p. + type area 4, 104 2nd p. + type area 5 p + type area 15, 115 n-type region 15a Lower n-type region 15b Upper n-type region 16, 116 p-type base layer 17, 117 n +Type Source Area 18, 118 p. ++ Mold Contact Area 19, 119 Gate insulating film 20, 120 Gate electrode 21, 121 Interlayer insulating film 22, 122 Source electrode 26, 126 Schottky Metal 31, 131 Trench Gate 32, 132 Trench SBD 40, 140 active area 41, 141 Transverse region 42, 142 Edge area 43 JTE area Silicon carbide semiconductor device with built-in 50, 150 SBD

Claims

1. a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided within the second semiconductor layer and having a higher impurity concentration than the semiconductor substrate; a second semiconductor region of a second conductivity type provided within the first semiconductor layer; a third semiconductor region of a second conductivity type provided in a surface layer of the first semiconductor layer and having a bottom surface in contact with the second semiconductor region; a first trench and a second trench that penetrate the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer and have a bottom surface in contact with the second semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a Schottky electrode provided inside the second trench; Equipped with In a region between an active region through which a current flows in an on-state and an edge region surrounding the active region and maintaining a withstand voltage, a sidewall of the second trench is not in contact with the second semiconductor region and the third semiconductor region; a junction termination structure for improving a breakdown voltage and a fourth semiconductor region of a second conductivity type are provided in the edge region; A semiconductor device, characterized in that the width between the second semiconductor region and the fourth semiconductor region is greater than or equal to the width between adjacent second semiconductor regions in the active region, and is narrower than the distance from the second semiconductor region to the junction termination structure.

2. A semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided within the second semiconductor layer and having a higher impurity concentration than the semiconductor substrate; a second semiconductor region of a second conductivity type provided within the first semiconductor layer; a third semiconductor region of a second conductivity type provided in a surface layer of the first semiconductor layer and having a bottom surface in contact with the second semiconductor region; a first trench and a second trench that penetrate the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer and have a bottom surface in contact with the second semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a Schottky electrode provided inside the second trench; Equipped with In a region between an active region through which a current flows in an on-state and an edge region surrounding the active region and maintaining a withstand voltage, a sidewall of the second trench is not in contact with the second semiconductor region and the third semiconductor region; a fifth semiconductor region of a second conductivity type having an impurity concentration higher than that of the second semiconductor layer, the fifth semiconductor region being selectively provided within the second semiconductor layer and in contact with the first semiconductor region; In the region, the fifth semiconductor region is located closer to the active region than the side surface of the second trench on the edge region side.

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