3D semiconductor memory device

Abstract

To provide a three-dimensional semiconductor memory device with improved electric characteristics.SOLUTION: A memory device according to the present invention includes a substrate including a cell array region and a connection region provided to an end part of the cell array region, an electrode structure including electrodes stacked sequentially on the substrate in the cell array region and extending to the connection region, an upper insulating film provided on the electrode structure, a first horizontal insulating film extending along the electrode in the upper insulating film, and a first contact plug penetrating the upper insulating film and the first horizontal insulating film in the connection region. The first horizontal insulating film includes a material whose etching resistance is higher than that of the upper insulating film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a three-dimensional semiconductor memory device, and more particularly to a three-dimensional semiconductor memory device having improved electrical characteristics. [Background technology]

[0002] In order to meet the demands of consumers for superior performance and low prices, there is a demand for increased integration of semiconductor devices. In the case of semiconductor devices, the integration is an important factor that determines the price of the product, and therefore increased integration is particularly demanded. In the case of two-dimensional or planar semiconductor devices, the integration is mainly determined by the area occupied by a unit memory cell, and is therefore greatly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required to fine the pattern, the integration of two-dimensional semiconductor devices is increasing, but is still limited. Therefore, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,425,047 [Patent Document 2] U.S. Patent No. 9,224,475 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a three-dimensional semiconductor memory device having improved electrical characteristics. [Means for solving the problem]

[0005] In order to achieve the above object, one aspect of the present invention provides a three-dimensional semiconductor memory device comprising: a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure including electrodes stacked in sequence on the substrate in the cell array region and extending to the connection region; an upper insulating film provided on the electrode structure; a first horizontal insulating film extending along the electrode within the upper insulating film; and a first contact plug penetrating the upper insulating film and the first horizontal insulating film in the connection region, wherein the first horizontal insulating film comprises a material having a higher etch resistance than the upper insulating film.

[0006] According to another aspect of the present invention, a three-dimensional semiconductor memory device is provided, comprising: a substrate including a cell array region and a connection region provided at an end of the cell array region; electrodes and an interlayer insulating film between the electrodes, which are stacked in sequence on the substrate in the cell array region, the electrode structure extending to the connection region; an upper insulating film provided on the electrode structure; a first horizontal insulating film extending along the electrode within a topmost interlayer insulating film among the interlayer insulating films; a second horizontal insulating film extending along the electrode within the upper insulating film; a vertical structure penetrating the electrode structure and the first horizontal insulating film; and a first contact plug penetrating the upper insulating film, the first horizontal insulating film, and the second horizontal insulating film, the first horizontal insulating film and the second horizontal insulating film being vertically spaced from each other, and the second horizontal insulating film having a higher concentration of non-metallic elements other than oxygen than the upper insulating film.

[0007] According to an embodiment, a three-dimensional semiconductor memory device includes a substrate including a cell array region, a peripheral circuit region including a peripheral circuit, and a connection region between the cell array region and the peripheral circuit region, electrodes vertically stacked on the substrate in the cell array region and an interlayer insulating film between the electrodes, the electrode structure extending to the connection region, an upper insulating film provided on the electrode structure, a horizontal insulating film extending along the electrodes within the upper insulating film, a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to an upper portion of the vertical semiconductor pattern. a vertical structure penetrating the electrode structure; a bit line provided on the upper insulating film and electrically connected to the conductive pad of the vertical structure; a first contact plug penetrating one of the upper insulating film, the horizontal insulating film, and the interlayer insulating film in the connection region and connected to the electrode; a second contact plug penetrating the upper insulating film and the horizontal insulating film in the peripheral circuit region and connected to the peripheral circuit; and conductive lines respectively connected to the first and second contact plugs, wherein the horizontal insulating film has a higher concentration of non-metallic elements other than oxygen than the upper insulating film. Effect of the Invention

[0008] In the three-dimensional semiconductor memory device of the present invention, the etching resistance of a portion of the insulating film can be increased through an ion implantation process, and the maximum width of a contact having a high aspect ratio can be reduced by increasing the etching resistance of the portion of the insulating film. Therefore, the three-dimensional semiconductor memory device of the present invention can prevent electrical shorts between contacts and improve electrical characteristics. [Brief description of the drawings]

[0009] [Figure 1] 1 is a simplified circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention. [Figure 2A] 1 is a plan view of an example of a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention; [Figure 2B]FIG. 2B is a cross-sectional view of an example taken along line II' in FIG. 2A. [Figure 2C] FIG. 2B is a cross-sectional view of an example taken along line II-II' in FIG. 2A. [Figure 3A] FIG. 2C is an enlarged view of an example corresponding to part A in FIG. 2B. [Figure 3B] FIG. 2C is an enlarged view of another example corresponding to part A in FIG. 2B. [Figure 4A] FIG. 2C is an enlarged view of an example corresponding to part B in FIG. 2B. [Figure 4B] FIG. 3 is an enlarged view of another example corresponding to part B in FIG. 2B. [Diagram 5] FIG. 2C is an enlarged view corresponding to part C in FIG. 2B. [Figure 6A] 1 is a plan view of another example of a three-dimensional semiconductor memory device according to an embodiment of the present invention; [Figure 6B] FIG. 6B is a cross-sectional view of an example taken along line II' of FIG. 6A. [Figure 6C] FIG. 6B is a cross-sectional view of an example taken along line II-II' in FIG. 6A. [Figure 7] 6B is a cross-sectional view of another example taken along line II' of FIG. 6A. FIG. [Figure 8A] 2B is a cross-sectional view of another example taken along line II' of FIG. 2A. FIG. [Figure 8B] 2B is a cross-sectional view of another example taken along line II-II' of FIG. 2A. [Figure 9A] 2B is a cross-sectional view of still another example taken along line II' of FIG. 2A. [Figure 9B] 2B is a cross-sectional view of still another example taken along line II-II' of FIG. 2A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of embodiments for carrying out a three-dimensional semiconductor memory device of the present invention will be described in detail with reference to the drawings.

[0011] FIG. 1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention.

[0012] Referring to FIG. 1, a cell array of a three-dimensional semiconductor memory device includes a common source line CSL, a plurality of bit lines (BL0 to BL2), and a plurality of cell strings CSTR provided between the common source line CSL and the bit lines (BL0 to BL2).

[0013] The cell strings CSTR are two-dimensionally arranged along a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1. The cell strings CSTR each extend along a third direction D3. For example, the third direction D3 is perpendicular to the first direction D1 and the second direction D2. The bit lines BL0 to BL2 are spaced apart from each other in the first direction D1. The bit lines BL0 to BL2 each extend in the second direction D2.

[0014] A plurality of cell strings CSTR are connected in parallel to each of the bit lines (BL0 to BL2). The plurality of cell strings CSTR are commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR are provided between the plurality of bit lines (BL0 to BL2) and one common source line CSL. A plurality of common source lines CSL are provided. The plurality of common source lines CSL are arranged two-dimensionally. The same voltage is applied to the common source lines CSL, or each of the common source lines CSL is electrically controlled.

[0015] According to the present embodiment, each of the cell strings CSTR includes first and second string selection transistors SST1 and SST2 connected in series, memory cell transistors MCT, a ground selection transistor GST, and an erase control transistor ECT connected in series, and each of the memory cell transistors MCT includes a data storage element.

[0016] As an example, each cell string CSTR includes first and second string selection transistors (SST1, SST2) connected in series, and the second string selection transistor SST2 is connected to one of the bit lines (BL0 to BL2). Alternatively, each cell string CSTR may not include one string selection transistor. As another example, in each cell string CSTR, the ground selection transistor GST is composed of a plurality of MOS transistors connected in series, similar to the first and second string selection transistors (SST1, SST2).

[0017] Each cell string CSTR is composed of a plurality of memory cell transistors MCT each having a different distance from a common source line CSL. The memory cell transistors MCT are connected in series between a first string selection transistor SST1 and a ground selection transistor GST. An erase control transistor ECT is connected between the ground selection transistor GST and the common source line CSL. Each cell string CSTR further includes a dummy cell transistor DMC connected between the first string selection transistor SST1 and the top transistor of the memory cell transistors MCT, and between the ground selection transistor GST and the bottom transistor of the memory cell transistors MCT.

[0018] According to this embodiment, the first string selection transistor SST1 is controlled by first string selection lines (SSL1-1, SSL1-2, SSL1-3), and the second string selection transistor SST2 is controlled by second string selection lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors MCT are each controlled by a plurality of word lines (WL0 to WLn), and the dummy cell transistors DMC are each controlled by a dummy word line DWL. The ground selection transistor GST is controlled by ground selection lines (GSL0, GSL1, GSL2), and the erase control transistor ECT is controlled by an erase control line ECL. A plurality of erase control transistors ECT are provided. A common source line CSL is commonly connected to the sources of the erase control transistors ECT.

[0019] The gate electrodes of the memory cell transistors MCT provided at substantially the same distance from the common source line CSL are commonly connected to one of the word lines (WL0 to WLn, DWL) and are at the same potential. However, even if the gate electrodes of the memory cell transistors MCT are provided at substantially the same level from the common source line CSL, the gate electrodes provided in different rows or columns can be controlled independently.

[0020] The ground selection lines (GSL0 to GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3), and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along a first direction D1 and are spaced apart from each other in a second direction D2. The ground selection lines (GSL0 to GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3), and the second string selection lines (SSL2-1, SSL2-2, SSL2-3), which are provided at substantially the same level from a common source line CSL, are electrically separated from each other. In addition, the erase control transistors ECT of the different cell strings CSTR are controlled by a common erase control line ECL. The erase control transistor ECT generates a gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In one embodiment, during an erase operation of the memory cell array, an erase voltage is applied to the bit lines (BL0 to BL2) and / or the common source line CSL, and a gate induced leakage current is generated in the string selection transistors SST and / or the erase control transistors ECT.

[0021] 2A is a plan view of an example of a three-dimensional semiconductor memory device according to an embodiment of the present invention, and FIGs 2B and 2C are cross-sectional views taken along lines II' and II-II' of FIG. 2A, respectively.

[0022] 2A, 2B, and 2C, the substrate 10 includes a cell array region CAR, a connection region CNR, a dummy region DMY, and a peripheral circuit region PCR. The connection region CNR is located between the cell array region CAR and the peripheral circuit region PCR. The dummy region DMY is adjacent to the cell array region CAR in a first direction D1 parallel to the top surface of the substrate 10. The dummy region DMY is located between the cell array region CAR and the connection region CNR. The peripheral circuit region PCR is adjacent to the connection region CNR in the first direction D1. The peripheral circuit region PCR includes a first peripheral circuit region PCR1 and a second peripheral circuit region PCR2, and the first peripheral circuit region PCR1 is closer to the cell array region CAR than the second peripheral circuit region PCR2. However, unlike the illustrated example, the substrate 10 may further include a boundary region between the peripheral circuit region PCR and the connection region CNR.

[0023] The substrate 10 may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. An isolation film 13 is provided in the substrate 10 in the peripheral circuit region PCR to define a peripheral active region PACT. A peripheral logic circuit for writing and reading data to and from a memory cell is provided on the substrate 10 in the peripheral circuit region PCR. The peripheral logic circuit includes row and column decoders, a page buffer, and a control circuit. The peripheral logic circuit includes high-voltage or low-voltage transistors, resistors, and capacitors. According to an embodiment, high-voltage transistors are provided on the substrate 10 in the first peripheral circuit region PCR1, and low-voltage transistors are provided on the substrate 10 in the second peripheral circuit region PCR2. The high-voltage transistors are closer to the cell array region CAR than the low-voltage transistors.

[0024] A first peripheral gate stack PGS1 is provided in the first peripheral circuit region PCR1, and a second peripheral gate stack PGS2 is provided in the second peripheral circuit region PCR2. The first and second peripheral gate stacks (PGS1, PGS2) cross the peripheral active region PACT, respectively. Each of the first and second peripheral gate stacks (PGS1, PGS2) includes a gate conductive pattern PCP, a gate metal pattern PMP, and a peripheral hard mask pattern HMP, which are sequentially stacked. In addition, each of the first and second peripheral gate stacks (PGS1, PGS2) further includes a gate spacer PSP covering both side walls of the gate conductive pattern PCP, the gate metal pattern PMP, and the peripheral hard mask pattern HMP. A gate insulating film 15 is provided between the substrate 10 of the peripheral circuit region PCR and the first and second peripheral gate stacks (PGS1, PGS2). In addition, source / drain impurity regions are provided in the peripheral active region PACT on both sides of the first and second peripheral gate stacks (PGS1, PGS2). A peripheral circuit insulating film 110 covers the upper surface of the substrate 10 in the peripheral circuit region PCR. The peripheral circuit insulating film 110 includes silicon oxide or silicon oxynitride. The peripheral circuit insulating film 110 has a substantially flat upper surface.

[0025] An electrode structure ST is provided on the substrate 10 in the cell array region CAR, the dummy region DMY, and the connection region CNR. The electrode structure ST extends from the cell array region CAR to the connection region CNR along a first direction D1. The electrode structures ST are spaced apart from each other in a second direction D2. The electrode structure ST includes electrodes (EL, ELt) and interlayer insulating films (ILDa, ILDb) alternately stacked in a third direction D3 perpendicular to the top surface of the substrate 10. The electrode structure ST has a substantially flat top surface in the cell array region CAR and the dummy region DMY. That is, the top surface ILDbt of the uppermost interlayer insulating film ILDb of each electrode structure ST is parallel to the top surface of the substrate 10. The electrode structure ST has a stepped structure along the first direction D1 in the connection region CNR. More specifically, the length of the electrodes (EL, ELt) of the electrode structure ST in the first direction D1 decreases as it moves away from the substrate 10, and the height of the electrode structure ST decreases as it moves away from the cell array region CAR.

[0026] One sidewall of the electrodes (EL, ELt) is spaced apart at a regular interval along the first direction D1 in a plan view. The uppermost electrode ELt among the electrodes (EL, ELt) has the shortest extended length in the first direction D1 and is spaced apart from the substrate 10 by the greatest distance in the third direction D3. As an example, the thickness of each of the electrodes (EL, ELt) in the third direction D3 is substantially the same. The electrodes (EL, ELt) include at least one selected from, for example, a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a transition metal (e.g., titanium, tantalum, etc.), etc. Referring again to FIG. 1, the electrodes (EL, ELt) are used as ground selection lines (GSL0 to GSL2), word lines (WL0 to WLn, DWL), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string selection lines (SSL2-1, SSL2-2, SSL2-3).

[0027] The interlayer insulating films (ILDa, ILDb) cover the electrodes (EL, ELt), respectively, and extend from the cell array region CAR to the peripheral circuit region PCR. The top interlayer insulating film ILDb is provided on the top electrode ELt. The thickness of the top interlayer insulating film ILDb in the third direction D3 is greater than the thickness of each of the other interlayer insulating films ILDa in the third direction D3. Each of the interlayer insulating films (ILDa, ILDb) may include substantially the same insulating material, or may include different insulating materials. For example, the interlayer insulating films (ILDa, ILDb) may include high density plasma oxide (HDP oxide) or TEOS (TetraEthylOrthoSilicate).

[0028] In a plan view, common source plugs CSP surrounded by insulating spacers SP are provided between the electrode structures ST. The common source plugs CSP have a flat plate shape extending in a first direction D1 and a third direction D3. The common source plugs CSP extend in the first direction D1 from the cell array region CAR to the connection region CNR. The common source plugs CSP are spaced apart from each other in the second direction D2. The common source plugs CSP are connected to a common source region inside the substrate 10. The common source region corresponds to the common source line CSL in FIG. 1.

[0029] The source structure SC is interposed between the electrode structure ST and the substrate 10. The source structure SC extends in the first direction D1 in parallel with the electrode structure ST. The source structure SC includes a first source conductive pattern SCP1 and a second source conductive pattern SCP2 which are stacked in this order. The thickness of the first source conductive pattern SCP1 in the third direction D3 is greater than the thickness of the second source conductive pattern SCP2 in the third direction D3. The first source conductive pattern SCP1 contacts the substrate 10, and the second source conductive pattern SCP2 directly contacts the first source conductive pattern SCP1. The second source conductive pattern SCP2 is provided between the first source conductive pattern SCP1 and the lowest interlayer insulating film among the interlayer insulating films (ILDa, ILDb) of the electrode structure ST. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 include a semiconductor material doped with a dopant. For example, the concentration of the dopant is higher in the first source conductive pattern SCP1 than in the second source conductive pattern SCP2.

[0030] The planar insulating film 130 is provided on the substrate 10 to cover the electrode structure ST and the peripheral circuit insulating film 110. The top surface 130t of the planar insulating film 130 is substantially planar. The top surface 130t of the planar insulating film 130 is substantially coplanar with the top surface ILDbt of the uppermost interlayer insulating film ILDb. In the connection region CNR, the thickness of the planar insulating film 130 in the third direction D3 increases toward the first direction D1. The thickness of the planar insulating film 130 in the third direction D3 is maximum in the peripheral circuit region PCR. The planar insulating film 130 includes a different insulating material from the interlayer insulating films (ILDa, ILDb). As an example, the interlayer insulating films (ILDa, ILDb) include high density plasma oxide, and the planar insulating film 130 includes TEOS.

[0031] The first horizontal insulating film IMP1 extends in the first direction D1 along the electrodes (EL, ELt) in the uppermost interlayer insulating film ILDb. The first horizontal insulating film IMP1 extends into the planar insulating film 130. Referring to FIG. 4A and FIG. 4B, the upper surface IMP1t of the first horizontal insulating film IMP1 is located at a lower level than the upper surface of the uppermost interlayer insulating film ILDb. The lower surface of the first horizontal insulating film IMP1 is located at a higher level than the upper surface of the uppermost electrode ELt. That is, the first horizontal insulating film IMP1 extends between the upper surface of the uppermost electrode ELt and the upper surface ILDbt of the uppermost interlayer insulating film ILDb. The first horizontal insulating film IMP1 includes a material having a higher etch resistance than the uppermost interlayer insulating film ILDb and the planar insulating film 130. The etch resistance means resistance to wet etching and dry etching. For example, the first horizontal insulating film IMP1 has a higher density than the uppermost interlayer insulating film ILDb and the planar insulating film 130. Also, as an example, the first horizontal insulating film IMP1 has a higher concentration of nonmetallic elements other than oxygen than the uppermost interlayer insulating film ILDb and the flat insulating film 130. For example, the first horizontal insulating film IMP1 includes at least one nonmetallic element selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar). An ion implantation process is performed on the uppermost interlayer insulating film ILDb and the flat insulating film 130 to form the first horizontal insulating film IMP1. Also, after the ion implantation process, a heat treatment process is further performed. As an example, the heat treatment process is a rapid thermal anneal (rtp) process. The greater the amount of ions implanted in the ion implantation process, the greater the etching resistance of the first horizontal insulating film IMP1.

[0032] According to an embodiment of the present invention, a plurality of first horizontal insulating films IMP1 are provided. Referring to FIG. 4B, at least two first horizontal insulating films IMP1a extend between an upper surface of the top electrode ELt and an upper surface ILDbt of the top interlayer insulating film ILDb. The first horizontal insulating films IMP1a are spaced apart from each other in the third direction D3. As an example, the first horizontal insulating films IMP1a include different materials. At least two or more ion implantation processes are performed on the top interlayer insulating film ILDb and the planar insulating film 130 to form the first horizontal insulating film IMP1a. Different elements are used in the at least two or more ion implantation processes. Also, the at least two or more ion implantation processes are performed with different ion implantation energies or different ion implantation amounts. Also, after the ion implantation processes, a heat treatment process is further performed. The position of the first horizontal insulating film IMP1a is adjusted according to the ion implantation energy and the heat treatment method.

[0033] A plurality of first vertical structures VS1 penetrate the electrode structures ST, the source structures SC, and a portion of the substrate 10 in the cell array region CAR and the dummy region DMY. The first vertical structures VS1 penetrate the top interlayer dielectric film ILDb and the first horizontal dielectric film IMP1 inside the top interlayer dielectric film ILDb. Referring again to FIG. 1, the first vertical structures VS1 are used as channels of the erase control transistor ECT, the first and second string select transistors (SST1, SST2), the ground select transistor GST, and the memory cell transistor MCT.

[0034] Each of the first vertical structures VS1 includes a data storage pattern DSP, a first vertical semiconductor pattern VSP1, and a first conductive pad PAD1. Referring to FIG. 4A, FIG. 4B, and FIG. 5, the data storage pattern DSP includes a blocking insulating layer BLK, a charge storing layer CIL, and a tunneling insulating layer TIL, which are stacked in sequence. Each of the first vertical structures VS1 further includes a buried insulating pattern VI surrounded by the first vertical semiconductor pattern VSP1 and the first conductive pad PAD1. An upper surface IMP1t of the first horizontal insulating layer IMP1 is located at a lower level than a lower surface PAD1b of the first conductive pad PAD1. However, unlike the illustrated example, the upper surface IMP1t of the first horizontal insulating layer IMP1 may be substantially coplanar with the lower surface PAD1b of the first conductive pad PAD1.

[0035] The first vertical semiconductor pattern VSP1 is surrounded by the data storage pattern DSP. A portion of a sidewall of the first vertical semiconductor pattern VSP1 contacts the source structure SC. As an example, the first vertical semiconductor pattern VSP1 contacts the first source conductive pattern SCP1 of the source structure SC and is spaced apart from the second source conductive pattern SCP2. Each of the first vertical structures VS1 further includes a lower data storage pattern DSPr. The lower data storage pattern DSPr has a substantially U-shaped cross section. The lower data storage pattern DSPr is spaced apart from the data storage pattern DSP via the first source conductive pattern SCP1 in contact with the first vertical semiconductor pattern VSP1. The lower data storage pattern DSPr is provided below the upper surface of the substrate 10. The first conductive pad PAD1 is connected to an upper portion of the first vertical semiconductor pattern VSP1. The upper surface of the first conductive pad PAD1 is substantially coplanar with the upper surface of the data storage pattern DSP and the upper surface of the first vertical semiconductor pattern VSP1. The first conductive pad PAD1 includes a semiconductor or conductive material doped with impurities.

[0036] The data storage pattern DSP and the first vertical semiconductor pattern VSP1 are formed through a process of etching the electrode structure ST, a process of depositing an insulating material or a semiconductor material using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method, and a process of planarizing the electrode structure ST so that the top surface of the electrode structure ST is exposed.

[0037] A plurality of second vertical structures VS2 penetrate the planar insulating film 130, the electrode structure ST, the source structure SC, and a portion of the substrate 10 in the connection region CNR. The second vertical structures VS2 penetrate the staircase structure of the electrode structure ST. The second vertical structures VS2 penetrate the first horizontal insulating film IMP1 inside the planar insulating film 130. Each of the second vertical structures VS2 includes a data storage pattern DSP, a second vertical semiconductor pattern VSP2, and a second conductive pad PAD2. Each of the second vertical structures VS2 has substantially the same structure as the first vertical structure VS1, and is formed by substantially the same formation method as the formation method of the first vertical structure VS1.

[0038] The first and second vertical structures (VS1, VS2) are arranged in a zigzag shape in a plan view. In each of the first and second vertical structures (VS1, VS2), the data storage pattern DSP has a pipe shape or a macaroni shape with an open lower end. In each of the first and second vertical structures VS1, the first and second vertical semiconductor patterns (VSP1, VSP2) have a pipe shape or a macaroni shape with a closed lower end. The first and second vertical semiconductor patterns (VSP1, VSP2) include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The first and second vertical semiconductor patterns (VSP1, VSP2) include a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. For example, the top surface of the first and second vertical structures (VS1, VS2) is circular, elliptical, or bar-shaped. For example, the width of the second vertical structure VS2 is greater than the width of the first vertical structure VS1. For example, the first and second vertical structures (VS1, VS2) have substantially the same length in the third direction D3. The lower surfaces of the first and second vertical structures (VS1, VS2) are located at a lower level than the upper surface of the substrate 10. That is, the first and second vertical structures (VS1, VS2) are connected to the substrate 10. A portion of the first and second vertical structures (VS1, VS2) is a dummy vertical structure including a dummy data storage pattern DSPd.

[0039] An upper insulating film 150 is provided on the electrode structure ST and the planar insulating film 130. The upper insulating film 150 covers an upper surface ILDbt of the uppermost interlayer insulating film ILDb and an upper surface 130t of the planar insulating film 130. The thickness of the upper insulating film 150 in the third direction D3 is substantially the same in the cell array region CAR, the connection region CNR, and the peripheral circuit region PCR. For example, the upper insulating film 150 includes substantially the same insulating material as the planar insulating film 130. For example, the upper insulating film 150 includes a different insulating material from the uppermost interlayer insulating film ILDb.

[0040] The second horizontal insulating film IMP2 extends in the first direction D1 along the electrodes EL, ELt inside the upper insulating film 150. Referring to FIGS. 3A and 3B, an upper surface IMP2t of the second horizontal insulating film IMP2 is located at a lower level than an upper surface 150t of the upper insulating film 150. A lower surface of the second horizontal insulating film IMP2 is located at a higher level than an upper surface 130t of the planar insulating film 130. That is, the second horizontal insulating film IMP2 extends between an upper surface 130t of the planar insulating film 130 and an upper surface 150t of the upper insulating film 150. The second horizontal insulating film IMP2 includes a material having a higher etch resistance than the upper insulating film 150. Etch resistance means resistance to dry etching. For example, the second horizontal insulating film IMP2 has a higher density than the upper insulating film 150. For example, the second horizontal insulating film IMP2 has a higher concentration of nonmetallic elements other than oxygen than the upper insulating film 150. For example, the second horizontal insulating film IMP2 includes at least one nonmetallic element selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar). As an example, the second horizontal insulating film IMP2 has substantially the same composition as the first horizontal insulating film IMP1. However, as another example, the second horizontal insulating film IMP2 includes a nonmetallic element different from that of the first horizontal insulating film IMP1. An ion implantation process is performed on the upper insulating film 150 to form the second horizontal insulating film IMP2. In addition, after the ion implantation process, a heat treatment process is further performed. The method of forming the second horizontal insulating film IMP2 is substantially the same as the method of forming the first horizontal insulating film IMP1.

[0041] According to an embodiment of the present invention, a plurality of second horizontal insulating layers IMP2 are provided. Referring to FIG. 3B, at least two or more second horizontal insulating layers IMP2a extend between the upper surface 130t of the flat insulating layer 130 and the upper surface 150t of the upper insulating layer 150. The second horizontal insulating layers IMP2a are spaced apart from each other in the third direction D3. As an example, the second horizontal insulating layers IMP2a include different materials from each other. At least two or more ion implantation processes are performed on the upper insulating layer 150 to form the second horizontal insulating layers IMP2a. The position of the second horizontal insulating layers IMP2a is controlled according to the ion implantation energy and the thermal treatment method. The method of forming the second horizontal insulating layers IMP2a is substantially the same as the method of forming the first horizontal insulating layer IMP1a described with reference to FIG. 4B.

[0042] A plurality of bit lines BL extend in the cell array region CAR in the second direction D2 and are spaced apart from each other in the first direction D1. Referring again to FIG. 1, the bit lines BL in FIGS. 2A to 2C are used as the plurality of bit lines BL0 to BL2 in FIG. 1. The bit lines BL are provided on an upper insulating layer 150. The bit lines BL are connected to the first vertical structures VS1 through respective bit line contact plugs BPLG. The bit line contact plugs BPLG penetrate the upper insulating layer 150 and the second horizontal insulating layer IMP2. The bit lines BL and the bit line contact plugs BPLG include a conductive material.

[0043] A plurality of conductive lines CL extend in the second direction D2 in the connection region CNR and the peripheral circuit region PCR and are spaced apart from each other in the first direction D1. The conductive lines CL are provided on the upper insulating film 150. In the connection region CNR, the conductive lines CL are each connected to an electrode EL of the electrode structure ST through a cell contact plug CPLG. The cell contact plug CPLG penetrates the upper insulating film 150, the second horizontal insulating film IMP2, the planar insulating film 130, the first horizontal insulating film IMP1, and the interlayer insulating film ILDa of the electrode structure ST. In the peripheral circuit region PCR, the conductive lines CL are each connected to the first and second peripheral gate stacks PGS1, PGS2 through a peripheral contact plug PPLG. More specifically, the peripheral contact plugs PPLG each contact the gate metal pattern PMP. The peripheral contact plugs PPLG penetrate the upper insulating film 150, the second horizontal insulating film IMP2, the planar insulating film 130, the first horizontal insulating film IMP1, the peripheral circuit insulating film 110, and the peripheral hard mask pattern HMP.

[0044] 3A and 3B are enlarged views corresponding to part A of FIG. 2B.

[0045] 3A, one of the cell contact plugs CPLG penetrating the upper insulating film 150, the second horizontal insulating film IMP2, and the planar insulating film 130 is illustrated. Hereinafter, a single cell contact plug CPLG will be described, however, the following description also applies to the other cell contact plugs CPLG and the peripheral contact plugs PPLG in the peripheral circuit region PCR.

[0046] The width of the cell contact plug CPLG in the first direction D1 increases from the upper surface 150t of the upper insulating film 150 to the upper surface IMP2t of the second horizontal insulating film IMP2, and decreases from the lower surface of the second horizontal insulating film IMP2 to the substrate 10 (see FIG. 2B). More specifically, the maximum width W1m of the cell contact plug CPLG is larger than the width W1 of the upper surface CPLGt of the cell contact plug CPLG. Also, the maximum width W1m of the cell contact plug CPLG is larger than the width W1t of the upper end of the second horizontal insulating film IMP2 and the width W1b of the lower end of the second horizontal insulating film IMP2. The maximum width W1m of the cell contact plug CPLG is about 2000 Å to 3000 Å. The cell contact plug CPLG has the maximum width W1m in a region overlapping the second horizontal insulating film IMP2. A first length L1 from the upper surface CPLGt of the cell contact plug CPLG to a point having the maximum width W1m is about 1000 Å to 4000 Å.

[0047] The second horizontal insulating film IMP2 is provided inside the upper insulating film 150, so that the maximum width W1m of the cell contact plug CPLG is reduced. The reduction in the maximum width W1m of the cell contact plug CPLG is due to the fact that the etching resistance of the second horizontal insulating film IMP2 is greater than the etching resistance of the upper insulating film 150. The reduction in the maximum width W1m of the cell contact plug CPLG prevents electrical shorts between adjacent cell contact plugs CPLG. In addition, the maximum width W1m of the cell contact plug CPLG and a first length L1 from the upper surface CPLGt of the cell contact plug CPLG to a point having the maximum width W1m are controlled by controlling the ion implantation energy and the ion implantation amount of the ion implantation process.

[0048] Table 1 below shows the maximum width W1m of the cell contact plug CPLG for different ion implantation energies and different ion implantation doses.

[0049] [Table 1]

[0050] Referring to Table 1, when the second horizontal insulating film IMP2 is not provided, i.e., when the ion implantation process is not performed (Ref), the maximum width W1m of the cell contact plug CPLG is about 2580 Å. Table 1 shows that when the second horizontal insulating film IMP2 is provided by the ion implantation process, the maximum width W1m of the cell contact plug CPLG is reduced. Compared with the case where the ion implantation process is not performed (Ref), the maximum width W1m of the cell contact plug CPLG is reduced by about 5 to 6%. Therefore, electrical short-circuiting between adjacent cell contact plugs CPLG is prevented. Referring to FIG. 3B, a plurality of second horizontal insulating films IMP2a are provided inside the upper insulating film 150. For example, the thicknesses T1a of the second horizontal insulating films IMP2a in the third direction D3 are different from each other. More specifically, the thicknesses T1a of the second horizontal insulating films IMP2a in the third direction D3 are different from each other by controlling the ion implantation energy and the ion implantation amount in the ion implantation process performed at least twice. By providing the second horizontal insulating film IMP2a, the maximum width W1m of the cell contact plug CPLG is reduced compared to the case of FIG. 3A.

[0051] 4A and 4B are enlarged views corresponding to part B of FIG. 2B.

[0052] 4A, one of the first vertical structures VS1 penetrating the top interlayer insulating film ILDb, the first horizontal insulating film IMP1, and the top electrode ELt is illustrated. Hereinafter, a single first vertical structure VS1 will be described. However, the following description also applies to the other first vertical structure VS1 and the second vertical structure VS2 of the connection region CNR.

[0053] The width of the first vertical structure VS1 in the first direction D1 increases from the upper surface ILDbt of the uppermost interlayer insulating film ILDb to the upper surface IMP1t of the first horizontal insulating film IMP1, and decreases from the lower surface of the first horizontal insulating film IMP1 to the substrate 10 (see FIG. 2B). More specifically, the maximum width W2m of the first vertical structure VS1 is greater than the width W2 of the upper surface VS1t of the first vertical structure VS1. Also, the maximum width W2m of the first vertical structure VS1 is greater than the width W2t of the upper end of the first horizontal insulating film IMP1 and the width W2b of the lower end of the first horizontal insulating film IMP1. The maximum width W2m of the first vertical structure VS1 is about 2000 Å to 3000 Å. The first vertical structure VS1 has the maximum width W2m in the region overlapping the first horizontal insulating film IMP1. A second length L2 from the upper surface VS1t of the first vertical structure VS1 to the point having the maximum width W2m is about 1000 Å to 4000 Å.

[0054] The first horizontal insulating film IMP1 is provided inside the uppermost interlayer insulating film ILDb, thereby reducing the maximum width W2m of the first vertical structure VS1. The reduction in the maximum width W2m of the first vertical structure VS1 is due to the fact that the etching resistance of the first horizontal insulating film IMP1 is greater than the etching resistance of the uppermost interlayer insulating film ILDb. The reduction in the maximum width W2m of the first vertical structure VS1 prevents electrical shorting between adjacent first vertical structures VS1. In addition, the maximum width W2m of the first vertical structure VS1 and the second length L2 from the upper surface VS1t of the first vertical structure VS1 to the point having the maximum width W2m are controlled by controlling the ion implantation energy and the ion implantation amount of the ion implantation process.

[0055] Referring to FIG 4B, a plurality of first horizontal insulating layers IMP1a are provided within the uppermost interlayer insulating layer ILDb. As an example, the thicknesses T2a of the first horizontal insulating layers IMP1a in the third direction D3 are different from each other. More specifically, the thicknesses T2a of the first horizontal insulating layers IMP1a in the third direction D3 are different from each other by controlling the ion implantation energy and the ion implantation amount in the ion implantation process performed at least twice. As the first horizontal insulating layers IMP1a are provided, the maximum width W2m of the first vertical structure VS1 is reduced compared to the case of FIG 4A.

[0056] FIG. 5 is an enlarged view corresponding to part C in FIG. 2B.

[0057] 5, one of the first vertical structures VS1 including a source structure SC including first and second source conductive patterns (SCP1, SCP2), a data storage pattern DSP, a first vertical semiconductor pattern VSP1, a buried insulating pattern VI, and a lower data storage pattern DSPr is illustrated. The following description will be given for a single first vertical structure VS1. However, the following description also applies to the other first vertical structures VS1.

[0058] In the source structure SC, the first source conductive pattern SCP1 contacts the first vertical semiconductor pattern VSP1, and the second source conductive pattern SCP2 is spaced apart from the first vertical semiconductor pattern VSP1 via the data storage pattern DSP. The first source conductive pattern SCP1 is spaced apart from the buried insulating pattern VI via the first vertical semiconductor pattern VSP1.

[0059] More specifically, the first source conductive pattern SCP1 includes a protrusion SCP1bt located at a level higher than the lower surface SCP2b of the second source conductive pattern SCP2 or lower than the lower surface SCP1b of the first source conductive pattern SCP1. However, the protrusion SCP1bt is located at a level lower than the upper surface SCP2a of the second source conductive pattern SCP2. For example, the surface of the protrusion SCP1bt that contacts the data storage pattern DSP or the lower data storage pattern DSPr has a curved shape.

[0060] Figure 6A is a plan view of another example of a three-dimensional semiconductor memory device according to an embodiment of the present invention. Figures 6B and 6C are cross-sectional views of an example taken along lines I-I' and II-II' of Figure 6A, respectively. For convenience of explanation, the following description of matters that are substantially the same as those described with reference to Figures 2A to 5 will be omitted.

[0061] 6A, 6B, and 6C, a three-dimensional semiconductor memory device according to this embodiment includes a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

[0062] The peripheral circuit structure PS includes a first substrate 10, a peripheral circuit PTR integrated on the upper surface of the first substrate 10, and a peripheral insulating film 30 covering the peripheral circuit PTR. The first substrate 10 is a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The first substrate 10 has an active region defined by an element isolation film 11.

[0063] The peripheral circuits PTR include, for example, row and column decoders, page buffers, control circuits, etc. More specifically, each of the peripheral circuits PTR includes a peripheral gate electrode 21, a peripheral gate insulating film 23, a peripheral capping pattern 25, a peripheral gate spacer 27, and a peripheral source / drain region 29. The peripheral gate insulating film 23 is provided between the peripheral gate electrode 21 and the first substrate 10. The peripheral capping pattern 25 is provided on the peripheral gate electrode 21. The peripheral gate spacer 27 covers the sidewalls of the peripheral gate electrode 21, the peripheral gate insulating film 23, and the peripheral capping pattern 25. The peripheral source / drain region 29 is provided inside the first substrate 10 adjacent to both sides of the peripheral gate electrode 21. The peripheral circuit wiring 33 is electrically connected to the peripheral circuit PTR through the peripheral contact plug 31. For example, the peripheral contact plug 31 and the peripheral circuit wiring 33 are connected to a transistor on the first substrate 10. The transistor on the first substrate 10 is, for example, an NMOS transistor, a PMOS transistor, or a gate-all-around transistor. A peripheral insulating film 30 is provided on the upper surface of the first substrate 10. The peripheral insulating film 30 covers the peripheral circuit PTR, the peripheral contact plugs 31, and the peripheral circuit wiring 33 on the first substrate 10. The peripheral insulating film 30 includes insulating films stacked in multiple layers. For example, the peripheral insulating film 30 includes silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material.

[0064] A cell array structure CS including a second substrate 100, an electrode structure ST on the second substrate 100, a planar insulating film 130 covering the electrode structure ST on the second substrate 100, and an upper insulating film 150 covering the electrode structure ST and the planar insulating film 130 is provided on the peripheral insulating film 30. The cell array structure CS further includes a first horizontal insulating film IMP1 extending along the electrodes (EL, ELt) within the uppermost interlayer insulating film ILDb of the electrode structure ST and a second horizontal insulating film IMP2 extending along the electrodes (EL, ELt) within the upper insulating film 150.

[0065] A connection structure ICS is provided to connect the cell array structure CS and the peripheral circuit structure PS. The connection structure ICS includes one of the conductive lines CL on the upper insulating film 150, a cell contact plug CPLG, and a through plug TPLG. The through plug TPLG penetrates the upper insulating film 150, the planar insulating film 130, the first and second horizontal insulating films (IMP1, IMP2), the second substrate 100, and a portion of the peripheral insulating film 30. The through plug TPLG is connected to at least one of the peripheral circuit wirings 33. Unlike the illustrated example, a plurality of through plugs TPLG are provided, and each is connected to a peripheral circuit wiring 33.

[0066] Fig. 7 is a cross-sectional view of another example taken along line II' in Fig. 6A. For the sake of convenience, the following description will be omitted for the same matters as those described with reference to Figs. 2A to 6C.

[0067] Referring to FIG. 7, each of the electrode structures ST includes a first electrode structure ST1 and a second electrode structure ST2. The first electrode structure ST1 includes a first electrode EL1 and a first interlayer insulating film ILD1a between the first electrode EL1, which are stacked in sequence. The second electrode structure ST2 includes a second electrode EL2 and a second interlayer insulating film (ILD2a, ILD2b) between the second electrode EL2, which are stacked in sequence. The first electrode structure ST1 is provided on the source structure SC, and the second electrode structure ST2 is provided on the first electrode structure ST1. More specifically, the second electrode structure ST2 is provided on an upper surface of the uppermost interlayer insulating film in the first interlayer insulating film ILD1a of the first electrode structure ST1. Therefore, the lowermost interlayer insulating film in the second interlayer insulating film (ILD2a, ILD2b) of the second electrode structure ST2 and the uppermost interlayer insulating film in the first interlayer insulating film ILD1a of the first electrode structure ST1 are in contact with each other.

[0068] The first vertical channel CH1 penetrates the first electrode structure ST1 to expose a portion of the second substrate 100. The second vertical channel CH2 penetrates the second electrode structure ST2 to expose the first vertical channel CH1. The first vertical channel CH1 and the second vertical channel CH2 are connected to each other. The diameter of the lower portion of the second vertical channel CH2 is smaller than the diameter of the upper portion of the first vertical channel CH1. A first vertical structure VS1 is provided inside the first vertical channel CH1 and the second vertical channel CH2. Each of the first vertical structures VS1 includes a data storage pattern DSP, a first vertical semiconductor pattern VSP1, and a first conductive pad PAD1. At this time, the data storage pattern DSP conformally covers the sidewalls of the first vertical channel CH1 and the second vertical channel CH2.

[0069] Figures 8A and 9A are cross-sectional views of another example taken along line II' in Figure 2A. Figures 8B and 9B are cross-sectional views of another example taken along line II-II' in Figure 2A. For ease of explanation, the following description of matters that are substantially the same as those described with reference to Figures 2A to 5 will be omitted.

[0070] 8A and 8B, the 3D semiconductor memory according to this embodiment includes only a second horizontal insulating film IMP2 inside the upper insulating film 150. Also, referring to Figures 9A and 9B, the 3D semiconductor memory according to this embodiment includes only a first horizontal insulating film IMP1 inside the uppermost interlayer insulating film ILDb. The first horizontal insulating film IMP1 extends from the uppermost interlayer insulating film ILDb into the planar insulating film 130. That is, in Figures 2B and 2C, one of the first and second horizontal insulating films (IMP1, IMP2) is omitted and only the other is provided.

[0071] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0072] 10 (first) board 11. Element isolation film 13. Element isolation film 15 Gate insulating film 21 Peripheral gate electrode 23 Peripheral gate insulating film 25 Peripheral capping pattern 27 Peripheral gate spacer 29 Peripheral source / drain region 30 Peripheral insulating film 31 Peripheral contact plug 33 Peripheral circuit wiring 100 Second substrate 110 Peripheral circuit insulating film 130 Flat insulating film 130t top surface 150 Upper insulating film 150t top surface BL, BL0~BL2 bit lines BLK Blocking insulating film BPLG Bit Line Contact Plug CAR cell array area CH1, CH2 1st and 2nd vertical channels CIL Charge storage film CL Conductive Line CNR connection region CPLG Cell Contact Plug CPLGt top surface CS Cell Array Structure CSL Common Source Line CSP Common Source Plug CSTR Cell String DMC Dummy Cell Transistor DMY Dummy area DSP Data Storage Pattern DSPd Dummy data storage pattern DSPr Lower Data Storage Pattern DWL Dummy Word Line ECL Erase Control Line ECT Erase Control Transistor EL, ELt electrode EL1, EL2 First and second electrodes GSL0~GSL2 Ground selection lines GST Ground Select Transistor HMP peripheral hard mask pattern ICS concatenation structure ILD1a First interlayer insulating film ILD2a, ILD2b Second interlayer insulating film ILDa, ILDb Interlayer insulating film ILDbt top surface IMP1, IMP1a First horizontal insulating film IMP2, IMP2a Second horizontal insulating film IMP1t, IMP2t top surface MCT Memory Cell Transistor PCR peripheral circuit area PCR1, PCR2 First and second peripheral circuit areas PACT peripheral active area PAD1, PAD2 First and second conductive pads PAD1b bottom side PCP gate conductive pattern PCR peripheral circuit area PCR1, PCT2 First and second peripheral circuit areas PGS1, PGS2 First and second peripheral gate stacks PMP gate metal pattern PPLG Peripheral Contact Plug PS peripheral circuit structure PSP Gate Spacer PTR peripheral circuit SC source structure SCP1, SCP2 First and second source conductive patterns SCP1b bottom side SCP1bt protrusion SCP2a, SCP2b top, bottom SP Insulation Spacer SSL1-1~SSL1-3 1st string selection line SSL2-1~SSL2-3 Second string selection line SST1, SST2 First and second string selection transistors ST electrode structure ST1, ST2 1st, 2nd electrode structure TIL tunneling insulating film TPLG Penetration Plug VI Buried insulation pattern VS1, VS2 1st, 2nd vertical structure VS1t top surface VSP1, VSP2 1st and 2nd vertical semiconductor patterns WL0~WLn Word Lines

Claims

1. a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure including electrodes sequentially stacked on the substrate, the electrode structure extending from the cell array region to the connection region; an interlayer insulating film between the electrodes; a first horizontal insulating film provided at the uppermost portion of the interlayer insulating film; a vertical structure penetrating the first horizontal insulating film and the electrode structure; the first horizontal insulating layer extends from the cell array region toward the connection region, an upper surface of the first horizontal insulating film is located at a lower level than an upper surface of the vertical structure; 4. The three-dimensional semiconductor memory device according to claim 3, wherein the first horizontal insulating film includes a material having a higher etch resistance than the interlayer insulating film.

2. the first horizontal insulating film is a top interlayer insulating film among the interlayer insulating films, and a plurality of first horizontal insulating films are provided; 2. The three-dimensional semiconductor memory device of claim 1, wherein the first horizontal insulating layers are vertically separated from one another by a portion of an uppermost interlayer insulating layer among the interlayer insulating layers.

3. an upper insulating film on the electrode structure; a second horizontal insulating film extending along the electrode within the upper insulating film; 2. The three-dimensional semiconductor memory device of claim 1, further comprising: a first contact plug penetrating the upper insulating layer and the second horizontal insulating layer in the connection region.

4. The three-dimensional semiconductor memory device as described in claim 3, characterized in that the first contact plug penetrates the first horizontal insulating film.

5. A three-dimensional semiconductor memory device as described in claim 3, characterized in that the first horizontal insulating film and the second horizontal insulating film are arranged at a distance from each other.

6. 2. The three-dimensional semiconductor memory device of claim 1, wherein each of the vertical structures includes a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to an upper portion of the vertical semiconductor pattern.

7. 2. The three-dimensional semiconductor memory device of claim 1, wherein each of the vertical structures has a width that increases from a top surface of a top interlayer insulating film among the interlayer insulating films toward the first horizontal insulating film and a width that decreases from the first horizontal insulating film toward the substrate.

8. A peripheral circuit region including a peripheral circuit; a second contact plug penetrating the upper insulating film and the second horizontal insulating film in the peripheral circuit region, 4. The three-dimensional semiconductor memory device of claim 3, wherein the second contact plug is connected to the peripheral circuit.

9. 10. The three-dimensional semiconductor memory device of claim 8, wherein each of the first and second contact plugs has a width that increases from the top surface of the upper insulating film toward the second horizontal insulating film and a width that decreases from the second horizontal insulating film toward the substrate.

10. a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure including electrodes and an interlayer insulating film between the electrodes, the electrode structure extending from the cell array region to the connection region; an upper insulating film provided on the electrode structure; a first horizontal insulating film extending along the electrode within a top interlayer insulating film among the interlayer insulating films; a second horizontal insulating film extending along the electrode within the upper insulating film; a vertical structure penetrating the electrode structure and the first horizontal insulating film; a first contact plug penetrating the upper insulating film, the first horizontal insulating film, and the second horizontal insulating film; the first and second horizontal insulating layers are spaced apart from each other in a vertical direction; an upper surface of the first horizontal insulating film is located at a lower level than an upper surface of the vertical structure; an upper surface of the second horizontal insulating film is located at a lower level than an upper surface of the first contact plug; The second horizontal insulating film has a higher concentration of nonmetallic elements other than oxygen than the upper insulating film.

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