Stacks for 3D NAND memory cells

Abstract

A memory device and a method for fabricating the memory device are provided. As an alternative to 3D NAND cells, a plasma enhanced chemical vapor deposition (PECVD) method for forming a memory cell film stack having more than 50 layers is described. The memory stack comprises alternating layers of a first material layer and a second material layer.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0002] Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatus for fabricating electronic devices. More particularly, embodiments of the present disclosure provide 3D NAND memory cells and methods for forming 3D NAND memory cells. [Background technology]

[0002] Semiconductor technology is rapidly evolving, and device dimensions are shrinking with the evolving technology to provide faster processing and storage per unit space. In NAND devices, one of the primary objectives is to increase storage per unit space, which results in an increase in the vertical dimension or stack height of 3D NAND devices.

[0003] Existing 3D NAND memory stacks with alternating layers of oxide and nitride require a replacement metal gate (RMG) process to build the word lines. Realizing increased vertical stack heights in 3D NAND devices can be problematic. A drawback of the current process using alternating layers of oxide and nitride in the memory stack is that the memory hole etching process is difficult and results in tapering, bending, and bowing of the memory holes.

[0004] Therefore, there is a need in the art for 3D NAND devices and methods for forming 3D NAND devices with improved film stack etch process margins. Summary of the Invention

[0005] One or more embodiments of the present disclosure are directed to a method of forming a device. In one embodiment, the method of forming a device comprises treating a surface of a substrate with a plasma, the plasma comprising one or more of ammonia (NH3), nitrogen (N2), or hydrogen (H2), forming a wetting layer on the substrate, transitioning from a low deposition rate to a high deposition rate, and exposing the substrate to at least one precursor to deposit a stack of alternating layers of a first material layer and a second material layer to form a memory stack.

[0006] Additional embodiments of the present disclosure are directed to semiconductor memory devices. In one embodiment, the semiconductor memory device comprises a memory stack in a first portion of the device comprising alternating first and second material layers, and a memory stack in a second portion of the device, the memory stack comprising alternating dielectric layers and wordlines, a plurality of bitlines extending through the memory stack, and wordline insulation extending from a top surface of the wordlines.

[0007] Further embodiments of the present disclosure are directed to a method of forming a memory device. In one embodiment, the method of forming a memory device comprises forming a memory channel through a memory stack, the memory stack comprising alternating layers of a first material layer and a second material layer, removing one or more first material layers from the memory stack to form a first opening, forming a word line replacement material in the first opening, removing one or more second material layers from the memory stack to form a second opening, forming a dielectric layer in the second opening, the dielectric layer having an air gap, and forming a word line isolation.

[0008] So that the above-recited features of the present disclosure may be understood in detail, a more detailed description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are illustrated in the attached drawings. It should be noted, however, that the attached drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. The embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the attached drawings, in which like reference numerals indicate similar elements. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 depicts a flow process diagram of an embodiment of a method of forming a memory device according to embodiments described herein. [Diagram 2] FIG. 1 illustrates a cross-sectional view of a device with a memory stack according to one or more embodiments. [Diagram 3] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 4A] 1 illustrates a cross-sectional view of a substrate after formation of an opening in accordance with one or more embodiments. [Figure 4B] 4B illustrates a cross-sectional view region 103 of the substrate of FIG. 4A according to one or more embodiments. [Figure 5A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 5B] FIG. 1 illustrates an expanded view of region 103 in accordance with one or more embodiments. [Figure 6A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 6B] FIG. 1 illustrates an expanded view of region 103 in accordance with one or more embodiments. [Figure 7A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 7B]FIG. 1 illustrates an expanded view of region 103 in accordance with one or more embodiments. [Figure 8A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 8B] FIG. 1 illustrates an expanded view of region 103 in accordance with one or more embodiments. [Figure 9] 1 illustrates a cross-sectional view of a substrate after slit patterning in accordance with one or more embodiments. [Figure 10] FIG. 2 illustrates a cross-sectional view of a substrate after a sacrificial layer has been removed, in accordance with one or more embodiments. [Figure 11A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 11B] FIG. 11B illustrates an enlarged view of region 200 of FIG. 11A. [Figure 12A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 12B] FIG. 12B illustrates an enlarged view of region 200 of FIG. 12A. [Figure 13A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 13B] FIG. 13B illustrates an enlarged view of region 200 of FIG. 13A. [Figure 14A] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 14B] FIG. 14B illustrates an enlarged view of region 200 of FIG. 14A. [Figure 15] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. [Figure 16] 1 illustrates a cross-sectional view of a substrate according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Before describing several example embodiments of the present disclosure, it should be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description, as the disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

[0011] Existing 3D NAND memory stacks with alternating layers of oxide and nitride require replacement metal gate (RMG) processes to build wordlines. As stack heights get larger, high aspect ratio (HAR) memory hole etch / fill processes and stress control become more challenging.

[0012] One or more embodiments advantageously provide a PECVD (plasma enhanced chemical vapor deposition) deposition method for forming memory cell film stacks having more than 50 layers as an alternative to 3D NAND cells.

[0013] FIG. 1 illustrates a process flow diagram for an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that the method 10 can include any or all of the illustrated processes. Additionally, the order of the individual processes can be varied for some parts. The method 10 can begin with any of the listed processes without departing from the present disclosure. With reference to FIG. 1, in operation 15, a memory stack is formed. In operation 20, a hard mask is etched. In operation 25, an opening, e.g., a memory hole channel, is patterned in the memory stack. In operation 30, a transistor layer is deposited. In operation 35, an interlayer dielectric (ILD) is deposited. In operation 40, the memory stack is slit patterned. In operation 45, a sacrificial layer is optionally removed. In operation 50, a first material layer is removed. In operation 55, a metal gate material is deposited. In operation 60, a second material layer is removed. In operation 65, a silicon oxide layer is deposited, creating an air gap.

[0014] 2-14B illustrate a portion of memory device 100 following the process flow illustrated for method 10 in FIG.

[0015] Figure 2 illustrates an initial or starting metal stack of a memory device 100 according to one or more embodiments of the present disclosure. In some embodiments, the device 100 shown in Figure 2 is formed on a bare substrate 105 in layers, as shown. The device of Figure 2 consists of a substrate 105, a semiconductor layer 110, a sacrificial layer 120, a memory stack 130, an oxide layer 140, and a hard mask 142.

[0016] The substrate 105 can be any suitable material known to those of skill in the art. As used herein and in the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. Those of skill in the art will also understand that a reference to a substrate can refer to only a portion of the substrate, unless the context clearly dictates otherwise. Additionally, a reference to depositing on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0017] "Substrate" as used herein refers to a substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, silicon nitride, strained silicon (developed by IBM), silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, nitrify, anneal, and / or bake the substrate surface. In addition to film treatments performed directly on the substrate surface itself, in this disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include the underlayer as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] The semiconductor layer 110 is on the substrate 105. In one or more embodiments, the semiconductor layer 110 may be referred to as a common source line. The semiconductor layer 110 may be formed by any suitable technique known to one skilled in the art and may be made of any suitable material, including but not limited to polysilicon (poly-Si). In some embodiments, the semiconductor layer 110 is a common source line made of a conductive or semiconducting material. In some embodiments, the layer below the stack of the first material layer 132 and the second material layer 134 may be modified to form a source line contact. Any variation of the structure below the stack of the first and second layers is possible.

[0019] An optional sacrificial layer 120 may be formed on the semiconductor layer 110 and may be made of any suitable material. In some embodiments, the sacrificial layer 120 is removed or replaced in a later process. In some embodiments, the sacrificial layer 120 is not removed and remains in the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include a permanent layer, which may be referred to as a conductive layer. In the illustrated embodiment, the sacrificial layer 120 is removed during operation 45, as described further below. In one or more embodiments, the sacrificial layer 120 comprises a material that may be selectively removed relative to the adjacent semiconductor layer 110 and first material layer 132.

[0020] The memory stack 130 is formed on the sacrificial layer 120. The memory stack 130 in the illustrated embodiment comprises a plurality of alternating first material layers 132 and material layers 134. In one or more embodiments, the first material layer 132 comprises silicon (Si). In one or more embodiments, the second material layer 134 comprises silicon germanium (SiGe). Thus, in some embodiments, the memory stack 130 comprises alternating layers of silicon (Si) and silicon germanium (SiGe). In other embodiments, the first material layer 132 comprises one or more of silicon (Si) or carbon (C). In one or more embodiments, the second material layer 134 comprises one or more of silicon germanium (SiGe), silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon phosphorus (SiP), silicon oxyphosphor (SiOP, phosphosilicate glass (PSG)), silicon oxyboride (SiOB, borosilicate glass (BSG)), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon boride (SiB), boron carbon (BC), boron nitride (BN), tungsten carbide (WC), and tungsten boron carbide (WBC). In one or more embodiments, the first material layer 132 and the second material layer 134 are deposited by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or epitaxial deposition. This process can be used for multi-layer film stack deposition, e.g., Si / SiGe, on substrates including dielectrics, including but not limited to silicon oxide (SiO2), and semiconductor substrates, including but not limited to silicon (Si) or silicon germanium (SiGe). The advantages of PECVD processes over PVD or epitaxial processes are that they achieve better throughput, cost, and tunability of individual film properties.

[0021] Although the memory stack 130 illustrated in FIG. 2 has five pairs of alternating first material layers 132 and material layers 134, one of ordinary skill in the art will recognize that this is for illustrative purposes only. The memory stack 130 may have any number of alternating first material layers 132 and material layers 134. For example, in some embodiments, the memory stack 130 comprises 192 pairs of alternating first material layers 132 and material layers 134. In other embodiments, the memory stack 130 comprises more than 100 pairs of alternating first material layers 132 and material layers 134, or more than 200 pairs of alternating first material layers 132 and material layers 134, or more than 300 pairs of alternating first material layers 132 and material layers 134.

[0022] In one or more embodiments, the plasma enhanced chemical vapor deposition (PECVD) process for forming the memory stack 130 comprises a surface treatment with a plasma. In other words, the sacrificial layer 120 is treated with a plasma prior to deposition of the alternating layers of the first material layer 132 and the second material layer 134. The plasma may comprise ammonia (NH3) or nitrogen (N2) and hydrogen (H2). Without intending to be bound by theory, it is believed that the plasma treatment forms chemical bonds on the surface, for example, Si-NH chemical bonds, and therefore silane (SiH4) or disilane (Si2H6) may bond better with the surface chemical bonds.

[0023] After surface treatment with plasma, a uniform wetting layer is created prior to deposition. In some embodiments, the wetting layer comprises the same material as the first material layer 132. Thus, in one or more embodiments, the wetting layer comprises silicon (Si). In other embodiments, the wetting layer comprises carbon (C). In one or more embodiments, the silicon wetting layer creates nuclei silicon and aids in film deposition.

[0024] After the formation of the silicon wetting layer, a slow linear ramping rate is performed to transition from a low deposition rate to a high deposition rate. Deposition of the first material layer 132 and the second material layer 134 is then performed under plasma conditions. The PECVD process of some embodiments comprises exposing a substrate surface to a precursor and a co-reactant. In one or more embodiments, the co-reactant may include a mixture of one or more nuclear species. In one or more embodiments, the co-reactant gas comprises one or more of argon (Ar), oxygen (O2), hydrogen (H2), nitrogen (N2), hydrogen / nitrogen (H2 / N2), and ammonia (NH3).

[0025] In one or more embodiments, the individual alternating layers (first material layer 132 and second material layer 134) may be formed to any suitable thickness. In some embodiments, the thickness of each first material layer 132 is approximately equal. In one or more embodiments, each first material layer 132 has a first material layer thickness. In some embodiments, the thickness of each first material layer 132 is approximately equal. Approximately equal thicknesses as used in this regard are within + / - 5% of each other.

[0026] In some embodiments, the thickness of each second material layer 134 is approximately equal. In one or more embodiments, each second material layer 134 has a second material layer thickness. In some embodiments, the thickness of each second material layer 134 is approximately equal. Approximately equal thicknesses as used in this regard are within + / - 5% of each other. In one or more embodiments, the first material layer 132 has a thickness within a range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second material layer 134 has a thickness in the range of about 0.5 nm to about 40 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.

[0027] 3, in one or more embodiments, in operation 20 of method 10, hard mask 142 is etched to form gap 150 that exposes a top surface and at least one sidewall of second material layer 134. The sidewall of gap 150 is composed of oxide layer 140 and hard mask 142. Etching hard mask 142 may be performed according to any method known to one of skill in the art.

[0028] 4A and 4B, in operation 25, in one or more embodiments, an opening 152 is opened through the memory stack 130. In some embodiments, the opening 152 comprises a memory hole channel. In some embodiments, opening the opening 152 comprises etching and removing the hard mask 142, etching through the gap 150, the memory stack 130, the sacrificial layer 120 and into the semiconductor layer 110. Referring to FIG. 4B, which is a close-up of region 103, the opening 152 has sidewalls that extend through the memory stack 130 and expose a surface 138 of the first material layer 132 and a surface 139 of the second material layer 134.

[0029] In one or more embodiments, the sacrificial layer 120 has a surface 122 exposed as a sidewall of an opening 152. The opening 152 extends into the semiconductor layer 110 a distance such that a sidewall surface 112 and a bottom 114 of the opening 152 are formed in the semiconductor layer 110. The bottom 114 of the opening 152 may be formed at any point within the thickness of the semiconductor layer 110. In some embodiments, the opening 152 extends into the semiconductor layer 110 a thickness that is within the range of about 10% to about 90%, or within the range of about 20% to about 80%, or within the range of about 30% to about 70%, or within the range of about 40% to about 60% of the thickness of the semiconductor layer 110. In some embodiments, the opening 152 extends into the semiconductor layer 110 a distance that is greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80% of the thickness of the semiconductor layer 110.

[0030] 5A and 5B illustrate operation 30 in which transistor layer 165 is conformally deposited in opening 152 adjacent first material layer 132 and second material layer 134. Transistor layer 165 may be formed by any suitable technique known to those of skill in the art. In some embodiments, transistor layer 165 is formed by a conformal deposition process. In some embodiments, transistor layer 165 is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0031] In one or more embodiments, the deposition of the transistor layer 165 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer that has about the same thickness throughout (e.g., on the top, middle and bottom of the sidewalls and on the bottom of the opening 152). A substantially conformal layer varies in thickness by less than or equal to about 5%, 2%, 1%, or 0.5%.

[0032] 5B, which is an expanded view of region 103, in one or more embodiments, transistor layer 165 comprises a blocking oxide layer 170 (or first oxide layer 170), a nitride trapping layer 172 on first oxide layer 170, a second oxide layer 174 (or tunneling oxide layer 174) on nitride trapping layer 172, and a polysilicon layer 170 in opening 152 on second oxide layer 174. In one or more embodiments, blocking oxide layer 170, charge trapping nitride (SiN) layer 174, and tunneling oxide layer 174 are deposited in opening 152 on sidewalls of opening 152 or on semiconductor layer 110. In one or more embodiments, a high-k dielectric material, such as aluminum oxide or hafnium oxide, may be deposited prior to forming the blocking oxide (in other words, the blocking layer is composed of a high-k dielectric and silicon oxide).

[0033] 6A and 6B, in one or more embodiments, a polysilicon (poly-Si) layer 176 is formed in the opening 152 adjacent to the transistor layer 165. The poly-Si layer 176 may be formed directly on the transistor layer 165. The poly-Si layer 176 may be deposited by any suitable technique known to those skilled in the art, including, but not limited to, atomic layer deposition and chemical vapor deposition. In some embodiments, the poly-Si layer 176 is deposited as a conformal layer such that the poly-Si layer 176 is formed on the sidewalls and exposed surfaces 138, 139, 122, 112 of the opening 152 as well as the bottom 114 (see FIG. 4B).

[0034] The polysilicon layer 176 can have any suitable thickness depending, for example, on the dimensions of the opening 152. In some embodiments, the polysilicon layer 176 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm. In some embodiments, the polysilicon layer 176 is a continuous film. In one or more embodiments, the polysilicon layer 176 is formed in a macaroni shape using conformal deposition on the tunnel oxide layer 172, and the polysilicon layer 176 has a thickness in the range of about 1 nm to about 20 nm. The opening 152 is then filled with a dielectric material 178, such as, but not limited to, silicon oxide (SiO).

[0035] 7A and 7B show the case where a polysilicon (poly-Si) layer 176 is formed in the plug.

[0036] 8A and 8B illustrate operation 35 of method 10, in which interlayer dielectric 180 is deposited on the top surface of oxide layer 140 and bitline pad 180. Interlayer dielectric (ILD) 180 may be deposited by any suitable technique known to one of skill in the art. Interlayer dielectric 180 may comprise any suitable material known to one of skill in the art. In one or more embodiments, interlayer dielectric 180 is a low-k dielectric including materials such as, but not limited to, silicon dioxide, silicon oxide, carbon doped oxide ("CDO"), e.g., carbon doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination thereof. The term "silicon oxide" may be used to describe interlayer dielectric 180, although one of skill in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe materials having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in this disclosure, such as, for example, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, etc.

[0037] FIG. 9 illustrates act 40 of method 10 in which memory stack 130 is slit patterned to form slit pattern openings 190 that extend from the top surface of interlayer dielectric 180 down to substrate 105 .

[0038] 10 illustrates operation 45 of method 10 in which one or more of the second material layers 134, e.g., SiGe layers, are removed to form openings 210 and slit pattern openings 190. In one or more embodiments, openings 210 have a thickness (t1) in the range of about 1 nm to about 50 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, about 30 nm, about 32 nm, about 35 nm, about 37 nm, about 40 nm, about 42 nm, about 45 nm, about 47 nm, and about 50 nm. In one or more embodiments, when removing one or more of the second material layers 134, e.g., SiGe layers, a first side of the second material layer 134, e.g., SiGe layer, is exposed to the slit pattern opening 190, and the first side of the second material layer 134, e.g., SiGe layer, is exposed to an etchant through the slit pattern opening 190.

[0039] 11A-12B illustrate an operation 50 of method 10 in which semiconductor material is deposited in slit pattern openings 190 and openings 210. FIGS. 11A and 11B and 12A and 12B illustrate that an aluminum oxide layer 192 and word line replacement material 194 are deposited in openings 210. FIGS. 11B and 12B are enlarged views of a portion 200 of the device of FIGS. 11A and 12A, respectively. In one or more embodiments, word line replacement material 194 comprises a nitride liner 193 (e.g., titanium nitride, tantalum nitride, etc.) and a bulk metal 195. In one or more embodiments, the bulk metal 195 comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the bulk metal 195 comprises tungsten (W). In other embodiments, the bulk metal 195 comprises ruthenium (Ru).

[0040] 13A and 13B show operation 55 of method 10 in which one or more of the first material layers 132, e.g., Si layers, are removed to form openings 215. In one or more embodiments, openings 215 have a thickness (t2) in the range of about 1 nm to about 50 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, about 30 nm, about 32 nm, about 35 nm, about 37 nm, about 40 nm, about 42 nm, about 45 nm, about 47 nm, and about 50 nm. In one or more embodiments, when removing one or more of the first material layers 132, e.g., Si layers, a first side of the first material layer 132, e.g., Si layer, is exposed to the slit pattern opening 190, and the first side of the first material layer 132, e.g., Si layer, is exposed to an etchant through the slit pattern opening 190.

[0041] 14A and 14B show operation 60 of method 10 in which dielectric material 202 is deposited in opening 215. Dielectric material 202 may comprise any suitable dielectric material known to one of ordinary skill in the art. In one or more embodiments, the dielectric material comprises silicon oxide (SiO). In one or more embodiments, as dielectric material 202 is deposited, voids 204 are formed in opening 215.

[0042] FIG. 15 illustrates an operation 70 of method 10 in which wordline insulation 235 is formed. Dielectric material 202 forms insulation for the wordlines. Slit pattern openings 190 are filled with fill material 230. Fill material 230 can be any suitable material known to those skilled in the art. In one or more embodiments, fill material 230 comprises one or more of a dielectric material or a conductor material. As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric material comprises one or more of an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon oxide (SiO), silicon nitride (SiN), silicon oxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0043] The wordline insulation 235 extends through the memory stack 130 a sufficient distance to terminate at one of the wordlines 225. In one or more embodiments, the wordline insulation 235 can comprise any suitable material known to those skilled in the art. In one or more embodiments, the wordline insulation 235 comprises one or more of a metal, a metal silicide, polysilicon, amorphous silicon, or EPI silicon. In one or more embodiments, the wordline contacts are doped with either an N-type or P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the wordline insulation 235 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0044] 16 illustrates a semiconductor memory device according to one or more embodiments. The memory device 100 includes a memory stack 120 including alternating first material layers 132, e.g., silicon (Si) layers, and second material layers 134, e.g., silicon germanium layers, in a first portion 300 of the device 100. A memory stack 130 including alternating word lines 225 and dielectric layers 202 in a second portion 400 of the device 100.

[0045] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (particularly in the context of the claims below) should be construed to encompass both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. The recitation of ranges of values ​​herein is only intended to serve as a shorthand method of individually referring to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The use of any and all examples or illustrative language (e.g., "such as") provided herein is only intended to better illuminate the materials and methods, and does not impose limitations on the scope, unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0046] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "embodiments" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Moreover, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0047] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. It is hereby intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor memory device, the method comprising: Ammonia (NH ３ ), nitrogen (N ２ ) or hydrogen (H ２ treating a surface of a substrate with a plasma comprising one or more of the following: forming a wetting layer on the substrate; depositing a stack of alternating layers of first and second material layers by a plasma enhanced chemical vapor deposition (PECVD) process to form a memory stack, each of the first material layers comprising silicon (Si) and each of the second material layers comprising silicon germanium (SiGe); forming a memory hole channel through the memory stack; forming a slit pattern opening extending through the memory stack to the substrate; removing each of the second material layers from the memory stack to form a plurality of first openings between each of the first material layers; forming a layer of word line replacement material in the first plurality of openings; exposing a first side of each of the first material layers; exposing the first side of each of the first material layers to an etchant through the slit pattern openings to remove each of the first material layers from the memory stack to form a plurality of second openings between each of the word line replacement material layers; forming a dielectric layer in the plurality of second openings; and in that order.

2. The method of claim 1 , wherein the surface of the substrate further comprises one or more of a semiconductor layer and a sacrificial layer.

3. 2. The method of claim 1 , wherein the word line replacement material layer comprises one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), or the like.

4. 4. The method of claim 3, wherein the word line replacement material layer comprises tungsten.

5. The method of claim 3 , wherein the wordline replacement material layer further comprises a nitride liner.

6. 2. The method of claim 1 , wherein forming a dielectric layer in the plurality of second openings comprises depositing a dielectric material in the plurality of second openings such that voids are formed in the plurality of second openings.

7. 1. A method of forming a semiconductor memory device, the method comprising: A method for treating a surface of a substrate using plasma, the plasma comprising: ３ ), nitrogen (N ２ ) or hydrogen (H ２ ) treating a surface of the substrate, the surface comprising one or more of the following: forming a wetting layer on the substrate; depositing a stack of alternating layers of first and second material layers by a plasma enhanced chemical vapor deposition (PECVD) process to form a memory stack, the memory stack comprising alternating layers of the first and second material layers, each of the first material layers comprising carbon (C) and each of the second material layers comprising one or more of silicon carbide (SiC), boron carbon (BC), boron nitride (BN), tungsten carbide (WC), and tungsten boron carbide (WBC); forming a memory hole channel through the memory stack; forming a slit pattern opening extending through the memory stack to the substrate; removing each of the second material layers from the memory stack to form a plurality of first openings between each of the first material layers; forming a layer of word line replacement material in the first plurality of openings; exposing a first side of each of the first material layers; exposing a first side of each first material layer to an etchant through the slit pattern openings to remove each first material layer from the memory stack to form a plurality of second openings between each word line replacement material layer; forming a dielectric layer having gaps in the plurality of second openings; forming word line isolation; in that order.

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