Fault diagnosis circuit, method, apparatus and computer-readable storage medium

Abstract

The present disclosure discloses a fault diagnosis circuit, a method, an apparatus, and a computer-readable storage medium. The fault diagnosis circuit includes a safety protection circuit and a diagnostic module, the safety protection circuit is electrically connected to a protected circuit, performs a test operation on stored data in the protected circuit to obtain first test data, performs error injection on second test data corresponding to the stored data, and generates a first test result signal according to the first test data and the second test data after error injection, and the diagnostic module is electrically connected to the safety protection circuit and performs fault diagnosis on the safety protection circuit according to the first test result signal. In the embodiment of the present disclosure, the fault diagnosis of the safety protection circuit can be realized with a simple hardware structure. Thus, the fault can be eliminated based on the diagnosis result to ensure the normal operation of the chip.

Description

[Technical field]

[0001] This application claims priority from a Chinese patent application filed with the State Intellectual Property Office on August 20, 2021, bearing application number 202110958241.7 and entitled "Fault diagnosis circuit, method, apparatus and computer-readable storage medium", the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the technical field of fault diagnosis, and in particular to a fault diagnosis circuit, method, apparatus and computer-readable storage medium. [Background technology]

[0003] According to the requirements of functional safety grade, some circuits in a chip need corresponding safety protection circuits, however, the safety protection circuits themselves may be faulty and may affect the normal operation of the chip, so how to realize fault diagnosis of the safety protection circuits is a topic worthy of attention by those skilled in the art. Summary of the Invention [Problem to be solved by the invention]

[0004] In order to solve the above technical problems, the present disclosure is presented. The embodiments of the present disclosure provide a fault diagnosis circuit, a method, an apparatus, and a computer-readable storage medium. [Means for solving the problem]

[0005] A fault diagnosis circuit according to an aspect of an embodiment of the present disclosure includes a safety protection circuit and a diagnosis module, the safety protection circuit is electrically connected to a protected circuit, and performs a test operation on stored data in the protected circuit to obtain first test data, performs an error injection on second test data corresponding to the stored data, and generates a first test result signal based on the first test data and the second test data after the error injection; The diagnostic module is electrically connected to the safety protection circuit, and performs fault diagnosis on the safety protection circuit according to the first test result signal.

[0006] According to another aspect of the embodiment of the present disclosure, a fault diagnosis method applied to the fault diagnosis circuit includes: performing a test operation on the stored data in the protected circuit to obtain first test data; performing error injection on second test data corresponding to the stored data; generating a first test result signal based on the first test data and the second test data after the error injection; and performing fault diagnosis on a safety protection circuit in the fault diagnosis circuit based on the first inspection result signal.

[0007] According to yet another aspect of the embodiment of the present disclosure, a fault diagnosis device applied to the fault diagnosis circuit includes: a first processing module for performing a test operation on the stored data in the protected circuit to obtain first test data; a second processing module for performing error injection on second test data corresponding to the stored data; a first generating module that generates a first test result signal based on the first test data by the first processing module and the second test data after the error injection by the second processing module; and a third processing module that performs fault diagnosis on a safety protection circuit in the fault diagnosis circuit based on the first inspection result signal from the first generating module.

[0008] A computer-readable storage medium according to yet another aspect of the embodiment of the present disclosure stores a computer program for executing the fault diagnosis method.

[0009] According to yet another aspect of the present disclosure, an electronic device includes: A processor; A storage means for storing instructions executable by the processor, The processor reads the executable instructions from the storage means and executes them to implement the fault diagnosis method. Effect of the Invention

[0010] According to the fault diagnosis circuit, method, apparatus, and computer-readable storage medium according to the above embodiments of the present disclosure, the safety protection circuit can combine error injection with test data acquisition to generate a first test result signal, and provide the generated first test result signal to the diagnostic module, and the diagnostic module can perform fault diagnosis on the safety protection circuit based on the first test result signal. Therefore, the embodiments of the present disclosure can realize fault diagnosis of the safety protection circuit with a simple hardware structure, and eliminate faults based on the diagnosis results to ensure the normal operation of the chip.

[0011] The technical configuration of the present disclosure will be described in more detail below with reference to the drawings and examples. [Brief description of the drawings]

[0012] The above and other objects, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the drawings. The drawings are provided for a better understanding of the embodiments of the present disclosure, constitute a part of the specification, and are used to explain the present disclosure together with the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the drawings, the same reference numerals generally indicate the same parts or steps. [Figure 1] FIG. 1 is a schematic diagram of an embodiment to which the present disclosure is applied. [Diagram 2] FIG. 2 is a structural schematic diagram of a fault diagnosis circuit according to an exemplary embodiment of the present disclosure; [Diagram 3] FIG. 2 is a structural schematic diagram of a safety protection circuit in a fault diagnosis circuit according to an exemplary embodiment of the present disclosure; [Figure 4] FIG. 2 is a structural schematic diagram of a fault diagnosis circuit according to another exemplary embodiment of the present disclosure; [Diagram 5]FIG. 2 is a structural schematic diagram of a diagnostic module in a fault diagnosis circuit according to an exemplary embodiment of the present disclosure; [Figure 6] 4 is a schematic flow chart of an error injection in a fault diagnosis circuit according to an exemplary embodiment of the present disclosure. [Figure 7] 1 is a schematic flowchart of a fault diagnosis method according to an exemplary embodiment of the present disclosure. [Figure 8] 4 is a schematic flowchart of a fault diagnosis method according to another exemplary embodiment of the present disclosure. [Figure 9] 1 is a structural schematic diagram of a fault diagnosis device according to an exemplary embodiment of the present disclosure; [Figure 10] FIG. 2 is a structural schematic diagram of a fault diagnosis device according to another exemplary embodiment of the present disclosure; [Figure 11] FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. The described embodiments are not all embodiments of the present disclosure, but are merely a part of the embodiments of the present disclosure, and the present disclosure is not limited to the exemplary embodiments described herein.

[0014] The relative arrangement of parts and steps, formulas and numerical values ​​described in the present embodiment do not limit the scope of the present disclosure unless otherwise specified.

[0015] Those skilled in the art can understand that terms such as "first", "second", etc. in the embodiments of the present disclosure are used only to distinguish different steps, devices, or modules, etc., and do not represent any specific technical meaning or necessary logical order between them.

[0016] In the embodiments of the present disclosure, "plurality" means two or more, and "at least one" means one, two, or more than two.

[0017] Embodiments of the present disclosure may be applied to electronic devices such as terminal devices, computer systems, servers, and the like, and may operate with numerous other general purpose or special purpose computing system environments or arrangements. Examples of well-known terminal devices, computing systems, environments, and / or arrangements suitable for use with electronic devices such as terminal devices, computer systems, servers, and the like, include, but are not limited to, devices or systems with chips (e.g., automotive chips, steamship chips, airplane chips, etc.), personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, networked personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above.

[0018] Overview of the Application In the process of realizing the present disclosure, the inventors have found that according to the requirements of the grade of functional safety, some circuits in a chip (also called protected circuits) need to have corresponding safety protection circuits, and the safety protection circuits can protect the protection circuits through certain safety protection mechanisms. Optionally, the chip can be a smart car chip, and the protected circuits can be resistors.

[0019] The safety protection circuit itself may also experience a fault, which may affect the normal operation of the chip. In order to eliminate the fault in the safety protection circuit and ensure the normal operation of the chip, it is necessary to perform a fault diagnosis on the safety protection circuit.

[0020] Exemplary System 1 , a fault diagnosis circuit according to an embodiment of the present disclosure can be provided corresponding to a protected circuit 1, and the fault diagnosis circuit can include a safety protection circuit 3 electrically connected to the protected circuit 1. Fault diagnosis for the safety protection circuit 3 can be realized by the operation of the fault diagnosis circuit, and selectively, fault diagnosis for the protected circuit 1 can also be realized by the operation of the fault diagnosis circuit.

[0021] It should be noted that the embodiments of the present disclosure relate to logic gates such as NOT gates, OR gates, and AND gates, and multiplexers (MUX).

[0022] Exemplary Circuit 2 is a structural schematic diagram of a fault diagnosis circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 2, the fault diagnosis circuit includes a safety protection circuit 3 and a diagnosis module 5.

[0023] The safety protection circuit 3 is electrically connected to the protected circuit 1, performs a test operation on stored data in the protected circuit 1 to obtain first test data, performs error injection on second test data corresponding to the stored data, and generates a first test result signal based on the first test data and the second test data after error injection.

[0024] The diagnostic module 5 is electrically connected to the safety protection circuit 3 and performs fault diagnosis on the safety protection circuit 3 based on the first inspection result signal.

[0025] Here, the protected circuit 1 can be a circuit (e.g., a register) capable of storing data. Optionally, the register can be a data register or a control register. Note that the control register can control the functional arrangement of the entire chip, a subsystem in the chip, or a module in the chip. The data register can store a first-in-first-out (FIFO) queue of data and perform data caching. The register width can be, but is not limited to, 4 bits, 8 bits, 16 bits, 32 bits, etc., and can be selected according to actual needs, and the embodiment of the present disclosure does not impose any limitation on the register width.

[0026] In the embodiment of the present disclosure, the safety protection circuit 3 can obtain the stored data in the protected circuit 1 through the electrical connection between the safety protection circuit 3 and the protected circuit 1. Then, the safety protection circuit 3 can perform a test operation on the stored data according to a preset test method to obtain first test data.

[0027] Alternatively, the security protection circuit 3 can use a Cyclic Redundancy Check (CRC) algorithm to perform a CRC operation on the stored data to obtain a corresponding CRC value, and the obtained CRC value is the first check data. Or, the security protection circuit 3 can use a parity check algorithm to perform a parity check operation on the stored data to obtain a corresponding parity check value, and the obtained parity check value is the first check data.

[0028] For ease of understanding, the embodiment of the present disclosure will be described taking as an example a case where a parity check algorithm is used as a preset check method.

[0029] In addition, the safety protection circuit 3 can further acquire second inspection data corresponding to the stored data. To realize the acquisition of the second inspection data, the safety protection circuit 3 can be electrically connected to a data bus such as an AXI (Advanced eXtensible Interface) or an APB (Advanced Peripheral Bus), and the data bus transmits the data to be stored; specifically, the protected circuit 1 can acquire and store the data to be stored from the data bus, and the data stored in the protected circuit 1 can be the stored data. The safety protection circuit 3 can acquire the second inspection data corresponding to the stored data through the data bus.

[0030] Alternatively, the safety protection circuit 3 can obtain data to be stored from the data bus, and perform a test operation on the obtained data according to a preset test method, and the obtained test data can be the second test data corresponding to the stored data. Or, in addition to transmitting the data to be stored, the data bus can also transmit test data corresponding to the data to be stored, and the test data can be obtained by performing a test operation on the data transmitted by the data bus according to a preset test method, and the test data transmitted by the data bus can be the second test data corresponding to the stored data.

[0031] After obtaining the second test data, the safety protection circuit 3 can perform error injection on the second test data to introduce an error into the second test data, thereby obtaining the second test data after the error injection, and generating a first test result signal according to the first test data and the second test data after the error injection.

[0032] Alternatively, the safety protection circuit 3 can compare the first test data with the second test data after error injection, and generate a first test result signal based on the comparison result, and the first test result signal can be a signal used to determine whether the first test data and the second test data after error injection are identical.

[0033] After the safety protection circuit 3 generates the first inspection result signal, the diagnostic module 5 can obtain the first inspection result signal through the electrical connection between the diagnostic module 5 and the safety protection circuit 3, and perform fault diagnosis on the safety protection circuit 3 accordingly, such as to determine whether the safety protection circuit 3 has a fault.

[0034] In the fault diagnosis circuit of the embodiment of the present disclosure, the safety protection circuit 3 can generate a first test result signal by combining test data acquisition and error injection, and provide the generated first test result signal to the diagnostic module 5, and the diagnostic module 5 can perform fault diagnosis on the safety protection circuit 3 based on this. Therefore, the embodiment of the present disclosure can realize fault diagnosis of the safety protection circuit 3 with a simple hardware structure, and eliminate faults based on the diagnosis results to ensure the normal operation of the chip.

[0035] In one optional example, the safety protection circuit 3 can also generate a second test result signal based on the first test data and the second test data, and the diagnostic module 5 can also perform fault diagnosis on the protected circuit 1 based on the second test data.

[0036] In an embodiment of the present disclosure, the safety protection circuit 3 can compare the first test data and the second test data, and generate a second test result signal based on the comparison result, and the second test result signal can be a signal used to determine whether the first test data and the second test data are identical.

[0037] After the safety protection circuit 3 generates the second inspection result signal, the diagnostic module 5 can obtain the second inspection result signal through the electrical connection between the diagnostic module 5 and the safety protection circuit 3, and accordingly perform fault diagnosis on the protected circuit 1, such as to determine whether there is a fault in the protected circuit 1.

[0038] As can be seen from the above, in the embodiment of the present disclosure, a simple hardware structure can be used to realize not only the fault diagnosis of the safety protection circuit 3, but also the fault diagnosis of the protected circuit 1. In this way, the fault can be eliminated based on the diagnosis result, and the normal operation of the chip can be further ensured.

[0039] In one optional example, as shown in FIG. 3, the safety protection circuit 3 may include a processing module 31, a calculation module 33, and a comparison module 35.

[0040] The comparison module 35 is electrically connected to the processing module 31, the calculation module 33 and the diagnostic module 5 of FIG.

[0041] The calculation module 33 performs a test operation on the stored data to obtain first test data.

[0042] The processing module 31 performs error injection on the second test data.

[0043] The comparison module 35 is used to generate a third test result signal based on a comparison result between the first test data and the second test data after error injection, and the first test result signal is generated based on the third test result signal.

[0044] The comparison module 35 is also used to generate a fourth test result signal based on a comparison result between the first test data and the second test data, and the second test result signal is generated based on the fourth test result signal.

[0045] Here, the comparison module 35 can be a comparator.

[0046] In a specific embodiment, the processing module 31 comprises a first NOT gate 311 , a first multiplexer 313 , and a memory 315 .

[0047] The first multiplexer 313 is electrically connected to the memory 315, the memory 315 is electrically connected to the first multiplexer 313 via the first NOT gate 311, the first multiplexer 313 is also electrically connected to the data bus, and the memory 315 is also electrically connected to the comparison module 35.

[0048] When the fault diagnosis circuit is in the first operating mode, the first multiplexer 313 outputs the second test data acquired via the data bus, thereby causing the memory 315 to store the second test data and output the second test data to the comparison module 35.

[0049] When the fault diagnosis circuit is in the second operating mode, the first multiplexer 313 outputs the inverted result of the second test data stored in the memory 315 by the first NOT gate 311, so that the memory 315 outputs the inverted result of the second test data to the comparison module 35, and this inverted result of the second test data becomes the second test data after error injection.

[0050] Here, the first NOT gate 311 has a first port P1 and a second port P2, the first multiplexer 313 has a third port P3, a fourth port P4 and a fifth port P5, the memory 315 has a sixth port P6 and a seventh port P7, and the comparison module 35 can have an eighth port P8, a ninth port P9 and a tenth port P10. The first port P1 can be electrically connected to the seventh port P7, the second port P2 can be electrically connected to the third port P3, the fourth port P4 can be electrically connected to the data bus, the fifth port P5 can be electrically connected to the sixth port P6, the seventh port P7 can be electrically connected to the eighth port P8, the ninth port P9 can be electrically connected to the calculation module 33, and the tenth port P10 can be electrically connected to the diagnostic module 5.

[0051] In addition, the first port P1 functions as an input end of the first NOT gate 311, the second port P2 functions as an output end of the first NOT gate 311, the third port P3 and the fourth port P4 each function as an input end of the first multiplexer 313, the fifth port P5 functions as an output end of the first multiplexer 313, the eighth port P8 and the ninth port P9 each function as an input end of the comparison module 35, and the tenth port can function as an output end of the comparison module 35.

[0052] Here, the fault diagnosis circuit can include two operation modes, namely, a first operation mode and a second operation mode. In the first operation mode, a fault diagnosis of the protected circuit 1 is performed, and the first operation mode can also be called a normal operation mode, and in the second operation mode, a fault diagnosis of the safety protection circuit 3 is performed, and the second operation mode can also be called an error injection mode.

[0053] In an embodiment of the present disclosure, the calculation module 33 performs a test operation on the stored data to obtain the first test data, so that the comparison module 35 can obtain the first test data from the calculation module 33 via the ninth port P9 regardless of whether the fault diagnosis circuit is in the first operating mode or the second operating mode.

[0054] When the fault diagnosis circuit is in the first operation mode, the first multiplexer 313 can receive second test data (this second test data is obtained from reg update in FIG. 3, and the logic in reg update is to obtain data to be stored from the data bus, perform a test operation on the obtained data according to a preset test method, and set the obtained test data as second test data corresponding to the stored data) from the fourth port P4 and output the received second test data from the fifth port P5. The memory 315 can receive the second test data from the first multiplexer 313 from a sixth port P6, the memory 315 can store the received second test data, and the memory 315 can also output the received second test data from a seventh port P7. The comparison module 35 can receive the second test data from the memory 315 from the eighth port P8, and the comparison module 35 can compare the first test data received from the ninth port P9 with the second test data received from the eighth port P8, and generate a fourth test result signal based on the comparison result.

[0055] Here, the fourth test result signal can be used to determine whether the first test data and the second test data are the same, if the first test data and the second test data are the same, the fourth test result signal is a high level signal and can be expressed as "1", otherwise, the fourth test result signal is a low level signal and can be expressed as "0".

[0056] It should be noted that the fourth test result signal can be used to generate a subsequent second test result signal.

[0057] When the fault diagnosis circuit is in the second operation mode, the memory 315 can output the stored second test data from the seventh port P7. The first NOT gate 311 can receive the second test data from the memory 315 from the first port P1, perform an inversion process on the received second test data, and then output the inversion result of the second test data from the second port P2. Here, when the second test data is expressed as "1", the inversion result of the second test data is expressed as "0", and when the second test data is expressed as "0", the inversion result of the second test data is expressed as "1". The first multiplexer 313 can receive the inversion result of the second test data from the first NOT gate 311 from the third port P3, and output the inversion result of the received second test data from the fifth port P5. The memory 315 can receive the inversion result of the second test data from the first multiplexer 313 from the sixth port P6, and output the inversion result of the received second test data from the seventh port P7. The comparison module 35 can receive the inverted result of the second test data from the memory 315 through the eighth port P8. This corresponds to the comparison module 35 receiving the second test data after the error injection through the eighth port P8, and the comparison module 35 can then compare the first test data received through the ninth port P9 with the second test data after the error injection received through the eighth port P8, and generate a third test result signal based on the comparison result.

[0058] Here, the third test result signal can be used to determine whether the first test data and the second test data after error injection are the same, if the first test data and the second test data after error injection are the same, the third test result signal is a high level signal and can be expressed as "1", otherwise, the third test result signal is a low level signal and can be expressed as "0".

[0059] The third test result signal can be used to generate a subsequent first test result signal.

[0060] Optionally, the first multiplexer 313 may be diagnosis ) signal, and the first multiplexer 313 receives diagnosis Based on the signal, it can determine whether the fault diagnosis circuit is currently in a first operating mode or a second operating mode, and based on the determined operating mode, it can further determine whether to output the second test data or the second test data after error injection from the fifth port P5.

[0061] The first multiplexer 313 receives diagnosis The signal may be received directly from a Central Processing Unit (CPU) or may be received from a dedicated diagnosis It may be received directly from a register for storing the signal, diagnosis The signal can be written by the CPU.

[0062] Optionally, the safety protection circuit 3 further comprises a second NOT gate 37 to realize the generation of the first check result signal and the second verification result signal.

[0063] The comparison module 35 is electrically connected to the diagnostic module 5 via a second NOT gate 37, and the inversion result of the third test result signal by the second NOT gate 37 becomes the first test result signal, and the inversion result of the fourth test result by the second NOT gate 37 becomes the second test result signal.

[0064] 3, the second NOT gate 37 has an eleventh port P11 and a twelfth port P12, the eleventh port P11 is electrically connected to the tenth port P10, and the twelfth port P12 can be electrically connected to the diagnostic module 5. The eleventh port P11 can function as an input end of the second NOT gate 37, and the twelfth port P12 can function as an output end of the second NOT gate 37.

[0065] When the fault diagnosis circuit is in the first operating mode, the comparison module 35 can output a fourth inspection result signal from the tenth port P10, the second NOT gate 37 can receive the fourth inspection result signal from the comparison module 35 from the eleventh port P11, the second NOT gate 37 can perform an inversion process on the received fourth inspection result signal to obtain an inverted result of the fourth inspection result signal, and output the inverted result of the fourth inspection result signal from the twelfth port P12.

[0066] Here, when the fourth inspection result signal is expressed as "1", the inverted result of the fourth inspection result signal is expressed as "0", and when the fourth inspection result signal is expressed as "0", the inverted result of the fourth inspection result signal is expressed as "1".

[0067] In addition, the diagnostic module 5 can receive an inverted result of the fourth test result signal from the comparison module 35. This corresponds to the fact that the diagnostic module 5 has received the second test result signal, and the diagnostic module 5 can perform fault diagnosis on the protected circuit 1 accordingly.

[0068] When the fault diagnosis circuit is in the second operating mode, the comparison module 35 can output a third inspection result signal from the tenth port P10, the second NOT gate 37 can receive the third inspection result signal from the comparison module 35 from the eleventh port P11, the second NOT gate 37 can perform an inversion process on the received third inspection result signal to obtain an inverted result of the third inspection result signal, and output the inverted result of the third inspection result signal from the twelfth port P12.

[0069] Here, when the third inspection result signal is expressed as "1", the inverted result of the third inspection result signal is expressed as "0", and when the third inspection result signal is expressed as "0", the inverted result of the third inspection result signal is expressed as "1".

[0070] In addition, the diagnostic module 5 can receive the inverted result of the third test result signal from the comparison module 35. This corresponds to the diagnostic module 5 receiving the first test result signal, and the diagnostic module 5 can perform fault diagnosis on the safety protection circuit 3 accordingly.

[0071] As can be seen from the above, the inversion process of the second NOT gate 37 makes it possible to efficiently and reliably generate the second test result signal based on the fourth test result signal and the first test result signal based on the third test result.

[0072] There is no need to particularly provide the second NOT gate 37 in the safety protection circuit 3, and in this case, the tenth port P10 may be electrically connected directly to the diagnostic module 5 without being electrically connected to the diagnostic module 5 via the second NOT gate 37. In this case, the third test result signal can be used as the first test result signal as it is, and the fourth test result signal can be used as the second test result signal as it is.

[0073] In the embodiment of the present disclosure, the calculation module 33 can efficiently and reliably perform the test operation to realize the acquisition of the first test data, and the processing module 31, including the first NOT gate 311, the first multiplexer 313 and the memory 315, can efficiently and reliably realize the error injection of the second test data by utilizing the inversion process in the circuit itself, without the need to specifically calculate the error value as the second test data after the error injection, and then the comparison module 35 can efficiently and reliably realize the comparison of the corresponding test data and the generation of the corresponding test result signal, and realize the fault diagnosis for the safety protection circuit 3 and the protected circuit 1 based on the generated test result signal.

[0074] For example, the CPU can update the stored data via a data bus, and as another example, the protected circuit 1 can update the stored data via a circuit of its own hardware. When the stored data in the protected circuit 1 is updated, the second test data stored in the memory 315 must also be updated accordingly.

[0075] Optionally, as shown in FIG. 3, the memory 315 may have a thirteenth port P13, which may be electrically connected to a specific circuit, which generates a control decision logic for controlling the update conditions of the second inspection data stored in the memory 315 based on a signal transmitted by the data bus and / or some signals according to FIG. 3.

[0076] In one optional example, as shown in FIG. 4, the number of safety protection circuits 3 and the number of protected circuits 1 are both multiple, and the multiple safety protection circuits 3 and the multiple protected circuits 1 are correspondingly electrically connected, and as shown in FIG. 5, the diagnostic module 5 includes a first logic gate 51, a second logic gate 53, and a second multiplexer 55.

[0077] Both the first logic gate 51 and the second logic gate 53 are electrically connected to each safety protection circuit 3 , and both the first logic gate 51 and the second logic gate 53 are also electrically connected to a second multiplexer 55 .

[0078] When the fault diagnosis circuit is in a first operating mode, the second multiplexer 55 outputs a first operation result signal obtained by performing a first logic operation on the multiple second inspection result signals from the multiple safety protection circuits 3 in the first logic gate 51, and the first operation result signal is used to determine whether there is a faulty protected circuit 1 among the multiple protected circuits 1.

[0079] When the fault diagnosis circuit is in the second operating mode, the second multiplexer 55 outputs a second operation result signal obtained by performing a second logic operation on the multiple first inspection result signals from the multiple safety protection circuits 3 in the second logic gate 53, and the second operation result signal is used to determine whether there is a faulty safety protection circuit 3 among the multiple safety protection circuits 3.

[0080] Here, the number of safety protection circuits 3 and the number of protected circuits 1 can both be multiple (e.g., n), where n can be 2, 3, 4, 5, or an integer greater than 5, and the multiple safety protection circuits 3 and the multiple protected circuits 1 can be electrically connected in one-to-one correspondence.

[0081] Here, the first logic gate 51 can be an OR gate, the first logic operation can be an OR operation, and the second logic gate 53 can be an AND gate, and the second logic operation can be an AND operation, or the first logic gate 51 can be an AND gate, the first logic operation can be an AND operation, and the second logic gate 53 can be an OR gate, and the second logic operation can be an OR operation.

[0082] Here, the first logic gate 51 has a 14th port P14, the second logic gate 53 has a 15th port P15, and the second multiplexer 55 has a 16th port P16, a 17th port P17 and an 18th port P18, and the 16th port P16 can be electrically connected to the 14th port P14, and the 17th port P17 can be electrically connected to the 15th port P15.

[0083] The 14th port P14 can function as an output terminal of the first logic gate 51, the 15th port P15 can function as an output terminal of the second logic gate 53, the 16th port P16 and the 17th port can function as input terminals of the second multiplexer 55, and the 18th port P18 can function as an output terminal of the second multiplexer 55.

[0084] When the fault diagnosis circuit is in the first operating mode, the multiple safety protection circuits 3 output second inspection result signals generated by themselves, and the first logic gate 51 receives multiple second inspection result signals (corresponding to Parity 1 error to Parity n error in Figures 4 and 5 when in the first operating mode) via multiple input terminals, performs a first logic operation on the multiple received second inspection result signals to obtain a first operation result signal (corresponding to Parity error in Figures 4 and 5 when in the first operating mode), and outputs the first operation result signal from the 14th port P14.

[0085] Furthermore, the second multiplexer 55 receives the first operation result signal from the first logic gate 51 from the 16th port P16 and outputs the received first operation result signal from the 18th port P18, and based on the first operation result signal, relevant parties can determine whether or not there is a faulty protected circuit 1 among the multiple protected circuits 1.

[0086] In a specific example, each safety protection circuit 3 is provided with a second NOT gate 37 as shown in FIG. 3. Theoretically, if there is no failure in any of the multiple protected circuits 1, in the first operation mode, the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 are all expressed as "0", otherwise, in the first operation mode, at least a part of the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 can be expressed as "1".

[0087] Therefore, when the first logic gate 51 is an OR gate, when the parity error in the first operating mode is expressed as "0", it can be determined that there is no faulty protected circuit 1 among the multiple protected circuits 1, and when the parity error in the first operating mode is expressed as "1", it can be determined that there is a faulty protected circuit 1 among the multiple protected circuits 1.

[0088] When the fault diagnosis circuit is in the second operating mode, the multiple safety protection circuits 3 output first inspection result signals generated by themselves, and the second logic gate 53 receives multiple first inspection result signals (corresponding to Parity 1 error to Parity n error in Figures 4 and 5 when in the second operating mode) via multiple input terminals, performs a second logic operation on the multiple received first inspection result signals to obtain a second operation result signal (corresponding to Parity error in Figures 4 and 5 when in the second operating mode), and outputs the second operation result signal from the 15th port P15.

[0089] Furthermore, the second multiplexer 55 receives the second operation result signal from the second logic gate 53 from the 17th port P17 and outputs the received second operation result signal from the 18th port P18, so that relevant parties can determine whether any of the multiple safety protection circuits 3 is faulty based on the second operation result signal.

[0090] In a specific example, each safety protection circuit 3 is provided with a second NOT gate 37 as shown in FIG. 3. Theoretically, if there is no failure in any of the multiple safety protection circuits 3, in the second operation mode, the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 can all be expressed as "1", otherwise, in the second operation mode, the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 can all be expressed as "0".

[0091] Therefore, when the second logic gate 53 is an AND gate, when the parity error in the second operating mode is expressed as "1", it can be determined that there is no faulty safety protection circuit 3 among the multiple safety protection circuits 3 in the fault diagnosis circuit, and when the parity error in the second operating mode is expressed as "0", it can be determined that there is a faulty safety protection circuit 3 among the multiple safety protection circuits 3 in the fault diagnosis circuit.

[0092] Optionally, the second multiplexer 55 may be configured similarly to the first multiplexer 313 described above. diagnosis The second multiplexer 55 receives the signal. diagnosis Based on the signal, it can be determined whether the fault diagnosis circuitry is currently in a first mode of operation or a second mode of operation.

[0093] In the embodiment of the present disclosure, the arrangement of the diagnostic module 5 including the first logic gate 51, the second logic gate 53 and the second multiplexer 55 makes it possible to efficiently and reliably diagnose whether there is a faulty protected circuit 1 among the multiple protected circuits 1 based on the logical operation at the first logic gate 51, and to efficiently and reliably diagnose whether there is a faulty safety protection circuit 3 among the multiple safety protection circuits 3 based on the logical operation at the second logic gate 53. That is, in the embodiment of the present disclosure, the diagnostic module 5 can realize comprehensive fault diagnosis for the protected circuits 1 and comprehensive fault diagnosis for the safety protection circuits 3.

[0094] In one optional example, as shown in FIG. 4, the number of the safety protection circuits 3 and the number of the protected circuits 1 are both multiple, and the multiple safety protection circuits 3 and the multiple protected circuits 1 are electrically connected correspondingly, and as shown in FIG. 5, the diagnostic module 5 includes a fault location circuit 57.

[0095] The fault location circuit 57 is electrically connected to each safety protection circuit 3 .

[0096] When the fault diagnosis circuit is in the first operating mode, the fault location circuit 57 outputs a first designation signal for designating a faulty protected circuit 1 among the multiple protected circuits 1 based on a plurality of second inspection result signals from the multiple safety protection circuits 3.

[0097] When the fault diagnosis circuit is in the second operating mode, the fault location circuit 57 outputs a second designation signal for designating a faulty safety protection circuit 3 among the multiple safety protection circuits 3 based on a plurality of first inspection result signals from the multiple safety protection circuits 3.

[0098] Here, the number of safety protection circuits 3 and the number of protected circuits 1 can both be multiple (e.g., n), where n can be 2, 3, 4, 5, or an integer greater than 5, and the multiple safety protection circuits 3 and the multiple protected circuits 1 can be electrically connected in one-to-one correspondence.

[0099] Here, the fault localization circuit 57 has a 19th port P19 and a 20th port P20, and the 19th port P19 and the 20th port P20 can function as output ends of the fault localization circuit 57, respectively.

[0100] When the fault diagnosis circuit is in the first operating mode, the fault location circuit 57 scans multiple second inspection result signals (corresponding to Parity 1 error to Parity n error in Figures 4 and 5 when in the first operating mode) from the multiple safety protection circuits 3 in a set order, such as from low to high error numbers or from high to low error numbers, to determine which of the multiple protected circuits 1 has a fault, and accordingly outputs a first designation signal (corresponding to the function error number in Figures 4 and 5) from the 19th port P19.

[0101] In a specific example, each safety protection circuit 3 is provided with a second NOT gate 37 shown in FIG. 3. Theoretically, if there is no fault in any of the multiple protected circuits 1, in the first operation mode, the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 are all expressed as "0", and if not, in the first operation mode, the error corresponding to the faulty protected circuit 1 among the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 is expressed as "1".

[0102] As described above, in the first operating mode, when Parity 1 error to Parity n error in FIG. 4 or FIG. 5 are all expressed as “0,” the function error number can be the default value of “0,” and relevant parties can accordingly understand that there is no fault in any of the multiple protected circuits 1; and, in the first operating mode, when Parity 2 error in FIG. 4 or FIG. 5 is expressed as “1,” the function error number can be “2,” and relevant parties can accordingly understand that there is a fault in the protected circuit 1 corresponding to the Parity 2 error. In the first operating mode, when both the Parity 1 error and the Parity 2 error in FIG. 4 or FIG. 5 are expressed as “1”, the function error number can be “1”, and the relevant parties can accordingly know that there is a fault in the protected circuit 1 corresponding to the Parity 1 error; or the function error number can be “2”, and the relevant parties can accordingly know that there is a fault in the protected circuit 1 corresponding to the Parity 2 error; that is, when the number of faulty protected circuits 1 is at least one, the function error number can only specify the protected circuit 1 with the largest or smallest corresponding error number.

[0103] When the fault diagnosis circuit is in the second operation mode, the fault localization circuit 57 scans a plurality of first inspection result signals (corresponding to Parity 1 error to Parity n error in FIG. 4 or FIG. 5 when in the second operation mode) from a plurality of safety protection circuits 3 according to a set order, such as from low to high error numbers or from high to low error numbers, to determine which of the plurality of safety protection circuits 3 has a fault, and accordingly outputs a second designation signal (corresponding to Parity 1 error to Parity n error in FIG. 4 or FIG. 5 ). diagnosis The 20th port P20 can output a 20th error message (corresponding to the error number).

[0104] In a specific example, each safety protection circuit 3 is provided with a second NOT gate 37 as shown in FIG. 3 . Theoretically, if there is no fault in any of the multiple safety protection circuits 3, in the second operation mode, the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 are all expressed as “1”, otherwise, in the second operation mode, the error corresponding to the faulty safety protection circuit 3 among the Parity 1 error to the Parity n error in FIG. 4 or FIG. 5 is expressed as “0”.

[0105] As a result, in the second operation mode, when Parity 1 error to Parity n error in FIG. 4 and FIG. 5 are all expressed as "1", diagnosis The error number can be a default value of "0", and the relevant person can accordingly understand that there is no failure in any of the multiple safety protection circuits 3. In the second operation mode, when the Parity 1 error in FIG. 4 or FIG. 5 is expressed as "0", diagnosis The error number can be "1", and the relevant person can accordingly know that there is a failure in the safety protection circuit 3 corresponding to the Parity 1 error. In the second operation mode, when both the Parity 1 error and the Parity 2 error in FIG. 4 and FIG. 5 are expressed as "0", diagnosis The error number may be “1”, and the relevant person may accordingly know that the safety protection circuit 3 corresponding to the Parity 1 error is faulty; or diagnosis If the error number is "2", the relevant person can know accordingly that the safety protection circuit 3 corresponding to the Parity 2 error is faulty, that is, if the number of faulty safety protection circuits 3 is at least one, diagnosis The error number can only specify the safety protection circuit 3 with the highest or lowest corresponding error number.

[0106] In the embodiment of the present disclosure, the arrangement of the fault location circuit 57 enables errors in all protected circuits 1 and errors in the safety protection circuit 3 to be aggregated and located; specifically, the fault location circuit 57 outputs a first designation signal in the first operating mode to accurately designate the location of the faulty protected circuit 1, and outputs a second designation signal in the second operating mode to accurately designate the location of the faulty safety protection circuit 3.

[0107] In one optional example, as shown in FIG. 6, first, the fault diagnosis circuit is set to the normal operation mode, and after power-on and initialization, the error injection function is enabled by software to set the fault diagnosis circuit to the error injection mode, and then it is confirmed whether an error is detected in the error injection mode (corresponding to detecting whether Parity 1 error to Parity n error in FIG. 4 or FIG. 5 are all expressed as "1" in the second operation mode). If an error is detected in the error injection mode (corresponding to the case where Parity 1 error to Parity n error in FIG. 4 or FIG. 5 are all expressed as "1" in the second operation mode), it can be determined that the test is successful and there is no latent fault in each safety protection circuit 3 in FIG. 4. In this case, the error injection function can be turned off to switch to the normal operation mode.

[0108] If an error cannot be detected in the error injection mode (corresponding to a case where at least some of the errors from Parity 1 error to Parity n error in FIG. 4 or FIG. 5 are not expressed as "1" in the second operation mode), the error can be located (corresponding to determining which safety protection circuit 3 is faulty) and error processing can be performed. For example, stored data can be rewritten to each protected circuit 1 in FIG. 4, or an IP (Intellectual Property) module can be restarted, where the IP module is a module capable of realizing a certain function.

[0109] As described above, by using the fault diagnosis circuit according to the embodiment of the present disclosure, in the normal operation mode, all of the protected circuits 1 can be diagnosed collectively, and if any of the protected circuits 1 fails, the position of the failed protected circuit 1 can be accurately specified. In the error injection mode, the inversion process can be performed collectively by the above-mentioned first NOT gate 311, so there is no need to inject errors individually, which greatly improves the efficiency of error injection. All of the safety protection circuits 3 can be diagnosed collectively with just one operation by software, and if any of the safety protection circuits 3 fails, the position of the failed safety protection circuit 3 can be accurately specified.

[0110] Exemplary Methods 7 is a schematic flow chart of a fault diagnosis method according to an exemplary embodiment of the present disclosure. The method shown in FIG. 7 is applied to the above fault diagnosis circuit and includes steps 701, 702, 703 and 704.

[0111] In step 701, a test operation is performed on the stored data in the protected circuit to obtain first test data.

[0112] In step 702, error injection is performed on second test data corresponding to the stored data.

[0113] In step 703, a first test result signal is generated based on the first test data and the second test data after the error injection.

[0114] In step 704, a fault diagnosis is performed on the safety protection circuit in the fault diagnosis circuit based on the first test result signal.

[0115] In one optional example, as shown in FIG. generating a second test result signal based on the first test data and the second test data; Step 712 of performing a fault diagnosis on the protected circuit based on the second test result signal; Further includes:

[0116] Any of the fault diagnosis methods according to the embodiments of the present disclosure may be executed by any suitable device having a data processing function, including but not limited to a terminal device and a server, etc. Alternatively, any of the fault diagnosis methods according to the embodiments of the present disclosure may be executed by a processor, for example, the processor executes any of the fault diagnosis methods mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a storage means. Detailed description thereof will be omitted.

[0117] Exemplary Apparatus 9 is a structural schematic diagram of a fault diagnosis device according to an exemplary embodiment of the present disclosure. The device shown in FIG. 9 includes a first processing module 901, a second processing module 902, a first generating module 903 and a third processing module 904.

[0118] The first processing module 901 performs a test operation on the stored data in the protected circuit to obtain first test data.

[0119] A second processing module 902 performs error injection on second test data corresponding to the stored data.

[0120] The first generation module 903 generates a first test result signal based on the first test data by the first processing module 901 and the second test data after the error injection by the second processing module 902.

[0121] The third processing module 904 performs fault diagnosis on the safety protection circuit in the fault diagnosis circuit based on the first test result signal from the first generating module 903.

[0122] In one optional example, as shown in FIG. a second generating module 911 for generating a second test result signal based on the first test data and the second test data by the first processing module 901; a fourth processing module 912 that performs a fault diagnosis on the protected circuit based on the second test result signal from the second generating module 911; It further comprises:

[0123] Exemplary Electronic Devices An electronic device according to an embodiment of the present disclosure will now be described with reference to Fig. 11. The electronic device may be either or both of the first device and the second device, or a standalone device independent therefrom, which can communicate with the first device and the second device and receive collected input data therefrom.

[0124] FIG. 11 illustrates a block diagram of an electronic device according to an embodiment of the present disclosure.

[0125] As shown in FIG. 11, an electronic device 1100 includes one or more processors 1101 and a storage means 1102 .

[0126] The processor 1101 may be a CPU or other form of processing unit having data processing and / or instruction execution capabilities and is capable of controlling other components within the electronic device 1100 to perform desired functions.

[0127] The storage means 1102 may comprise one or more computer program products including various forms of computer readable storage media such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored in the computer readable storage medium, and the processor 1101 may execute the program instructions to realize the fault diagnosis method of each embodiment of the present disclosure above and / or other desired functions. The computer readable storage medium may also store various contents such as an input signal, a signal component, a noise component, etc.

[0128] In one example, the electronic device 1100 may further comprise an input device 1103 and an output device 1104 connected to each other via a bus system and / or other form of connection means (not shown).

[0129] For example, if the electronic device is a first device or a second device, the input device 1103 may be a microphone or a microphone array. If the electronic device is a stand-alone device, the input device 13 may be a communication network connector for receiving collected input signals from the first device and the second device.

[0130] The input device 1103 may also include, for example, a keyboard and a mouse.

[0131] The output device 1104 can output various information such as determined distance information, direction information, etc. The output device 1104 can include, for example, a display, a speaker, a printer, a communication network, and a remote output device connected thereto.

[0132] 11 shows only some of the components in the electronic device 1100 that are relevant to the present disclosure, and omits components such as buses, input / output interfaces, etc. Furthermore, depending on a specific application situation, the electronic device 1100 may further include any other suitable components.

[0133] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the methods and apparatus described above, embodiments of the present disclosure may be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform steps in the fault diagnosis methods according to various embodiments of the present disclosure described in the "Exemplary Method" section above of this specification.

[0134] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the advantages, merits, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting. Various embodiments of the present disclosure do not necessarily have those advantages, merits, effects. In addition, the specific details of the above disclosure are merely for illustrative and easy-to-understand functions and are not limiting, and the above details do not necessarily limit the present disclosure to be realized by the above specific details.

[0135] Each embodiment in this specification is described in a sequential manner, and the description of each embodiment focuses mainly on the differences from other embodiments, and the same or similar parts between the embodiments may be referred to each other. The system embodiments are basically corresponding to the method embodiments, so they are described relatively briefly, and the relevant parts may be referred to part of the description of the method embodiments.

[0136] Block diagrams of devices, apparatus, instruments, and systems according to the present disclosure are merely exemplary and are not intended to require or imply that the devices, apparatus, instruments, and systems be connected, arranged, or configured in the manner shown in the block diagrams, as will be understood and appreciated by those skilled in the art.

[0137] The method and apparatus of the present disclosure may be implemented in many forms. For example, the method and apparatus of the present disclosure may be implemented in software, hardware, firmware, or any combination of software, hardware, and firmware. The above-mentioned order of steps used in the method is merely illustrative, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless specifically described otherwise. In some embodiments, the present disclosure may also be implemented as a program recorded on a recording medium, and these programs include machine-readable instructions for implementing the method of the present disclosure. Thus, a recording medium storing a program for executing the method of the present disclosure is also included in the present disclosure.

[0138] It should also be noted that in the devices, apparatus, and methods of the present disclosure, each component or each step may be disassembled and / or recombined, and such disassembly and / or recombination should be considered as an equivalent form of the present disclosure.

[0139] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A safety protection circuit electrically connected to a protected circuit and a data bus, and a diagnostic module electrically connected to the safety protection circuit, the safety protection circuit comprises a processing module electrically connected to the data bus, a calculation module electrically connected to the protected circuit, and a comparison module electrically connected to the processing module, the calculation module, and the diagnostic module; the computing module performs a test operation on the stored data from the protected circuit to obtain first test data; the processing module acquires second test data corresponding to the stored data from the data bus, stores the second test data, and executes an error injection process on the second test data to introduce an error into the second test data, thereby acquiring second test data after the error injection; The comparison module generates a first test result signal based on the first test data by the calculation module and the second test data after the error injection by the processing module; The fault diagnosis circuit, wherein the diagnostic module performs a fault diagnosis on the safety protection circuit based on the first inspection result signal.

2. The comparison module generates a second inspection result signal based on the first inspection data by the calculation module and the second inspection data stored in the processing module; 2. The fault diagnosis circuit according to claim 1, wherein the diagnostic module executes a fault diagnosis on the protected circuit based on the second test result signal.

3. The comparison module generates a third test result signal based on a comparison result between the first test data by the calculation module and the second test data after the error injection by the processing module, and the first test result signal is generated based on the third test result signal; 3. The fault diagnosis circuit according to claim 2, wherein the comparison module generates a fourth inspection result signal based on a comparison result between the first inspection data by the calculation module and the second inspection data stored in the processing module, and the second inspection result signal is generated based on the fourth inspection result signal.

4. the processing module comprises a first NOT gate, a first multiplexer, and a memory; the first multiplexer is electrically connected to the memory, the memory is also electrically connected to the first multiplexer through the first NOT gate, the first multiplexer is also electrically connected to a data bus, and the memory is also electrically connected to the comparison module; When the fault diagnosis circuit is in a first operation mode, the first multiplexer outputs the second test data acquired by the data bus, thereby causing the memory to store the second test data and output the second test data to the comparison module; 4. The fault diagnosis circuit according to claim 3, characterized in that, when the fault diagnosis circuit is in a second operating mode, the first multiplexer outputs an inverted result of the second test data stored in the memory by the first NOT gate, whereby the memory outputs the inverted result of the second test data to the comparison module, and the inverted result of the second test data is set as the second test data after the error injection.

5. the safety protection circuit further comprises a second NOT gate; 5. The fault diagnosis circuit according to claim 4, wherein the comparison module is electrically connected to the diagnosis module via the second NOT gate, an inversion result of the third test result signal by the second NOT gate becomes a first test result signal, and an inversion result of the fourth test result signal by the second NOT gate becomes a second test result signal.

6. the number of the safety protection circuits and the number of the protected circuits are both plural, the plurality of the safety protection circuits and the plurality of the protected circuits are electrically connected to each other in a corresponding manner, and the diagnostic module comprises a first logic gate, a second logic gate, and a second multiplexer; the first logic gate and the second logic gate are both electrically connected to each of the safety protection circuits, and the first logic gate and the second logic gate are both also electrically connected to the second multiplexer; When the fault diagnosis circuit is in a first operation mode, the second multiplexer outputs a first operation result signal obtained by performing a first logic operation on the second test result signals by the safety protection circuits in the first logic gate, and the first operation result signal determines whether there is a faulty protected circuit among the plurality of protected circuits; 3. The fault diagnosis circuit of claim 2, wherein when the fault diagnosis circuit is in a second operation mode, the second multiplexer outputs a second operation result signal obtained by performing a second logic operation on the first test result signals by the safety protection circuits in the second logic gate, and the second operation result signal determines whether any of the safety protection circuits is faulty.

7. The number of the safety protection circuits and the number of the protected circuits are both plural, and the plurality of the safety protection circuits and the plurality of the protected circuits are electrically connected to each other in a corresponding manner, and the diagnostic module includes a fault location circuit; The fault location circuit is electrically connected to each of the safety protection circuits; When the fault diagnosis circuit is in a first operation mode, the fault localization circuit outputs a first designation signal for designating a faulty protected circuit among the plurality of protected circuits based on the plurality of second inspection result signals from the plurality of safety protection circuits; 3. The fault diagnosis circuit according to claim 2, wherein, when the fault diagnosis circuit is in a second operating mode, the fault location circuit outputs a second designation signal for designating a failed safety protection circuit among the multiple safety protection circuits based on the multiple first inspection result signals from the multiple safety protection circuits.

8. The fault diagnosis circuit according to any one of claims 1 to 7, performing a test operation on the stored data from the protected circuit to obtain first test data; performing the error injection on second test data corresponding to the stored data from the data bus to obtain second test data after error injection; generating a first test result signal based on the first test data and the second test data after the error injection; and performing a fault diagnosis on a safety protection circuit in the fault diagnosis circuit based on the first inspection result signal.

9. generating a second test result signal based on the first test data and the second test data; 9. The fault diagnosis method according to claim 8, further comprising: performing a fault diagnosis on the protected circuit based on the second inspection result signal.

10. The fault diagnosis circuit according to any one of claims 1 to 7, a first processing module for performing a test operation on the stored data from the protected circuit to obtain first test data; a second processing module that performs the error injection on second test data corresponding to the stored data from the data bus to obtain second test data after the error injection; a first generating module that generates a first test result signal based on the first test data by the first processing module and the second test data after the error injection by the second processing module; a third processing module that performs fault diagnosis on a safety protection circuit in the fault diagnosis circuit based on the first inspection result signal from the first generation module.

11. A computer-readable storage medium storing a computer program for executing the fault diagnosis method according to claim 8.

12. A processor; a storage means for storing instructions executable by said processor; 9. An electronic device, comprising: a processor configured to read and execute the executable instructions from the storage means to implement the fault diagnosis method of claim 8.

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