Semiconductor Device

Abstract

To provide a semiconductor device with high on-current and fast operation speed.SOLUTION: A semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate. The first gate and the second gate include regions which overlap each other with a semiconductor layer in between. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor includes a function for acquiring temperature information and outputting temperature information to the voltage control circuit. The voltage control circuit includes a function for converting temperature information into control voltage. The first circuit applies control voltage to the second gate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Another aspect of the present invention relates to an object, a method, or a manufacturing method. The method may be a process, machine, manufacture, or composition of matter. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to the general term. Storage devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices , and a semiconductor device. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, other materials include oxide semiconductors (OS). ) is attracting attention. Examples of oxide semiconductors include indium oxide and zinc oxide. Not only oxides of single-component metals, but also oxides of multi-component metals are known. Oxidation of multi-component metals Among these, research on In-Ga-Zn oxide (hereinafter referred to as IGZO) is particularly focused. is being actively carried out.

[0005] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous, AC (c-axis aligned crystalline) structure and nc (na A noncrystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with lower crystallinity than those in the conventional semiconductors have fine crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non-unique See patent literature 6.) LSIs and displays that utilize these properties have been reported (non- See Patent Document 7 and Non-Patent Document 8.

[0007] In addition, a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) Various semiconductor devices using a semiconductor laser (also called a "transistor") have been proposed.

[0008] In Patent Document 1, an OS transistor is used as a DRAM (Dynamic Random Access Memory) The OS transistor is used in an off-state Since the leakage current (off-state current) is very small, the refresh period is long and power consumption is low. This makes it possible to create a DRAM that does not require

[0009] Moreover, Patent Document 2 discloses a nonvolatile memory using an OS transistor. Unlike flash memory, these non-volatile memories have no limit to the number of times they can be rewritten, and This allows for fast operation and consumes little power.

[0010] In the memory using these OS transistors, the threshold voltage of the OS transistors is increased. This makes it possible to reduce the off-current and improve the data retention characteristics of the memory. In Patent Document 2, a second gate is provided in the OS transistor, An example is disclosed in which the threshold voltage of a transistor is controlled to reduce the off-current.

[0011] In order for the memory to retain data for a long period of time, It is necessary to keep applying a constant negative potential to the OS transistor. An example of a circuit configuration for driving the second gate of the transistor is disclosed. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2013-168631 A [Patent Document 2] JP 2012-069932 A [Patent Document 3] JP 2012-146965 A [Non-patent literature]

[0013] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0014] An object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of the present invention is to provide a semiconductor device that can be used in a wide temperature range. An object of one embodiment is to provide a semiconductor device capable of retaining data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0015] In addition, the description of a plurality of problems does not preclude the existence of each problem. The embodiment does not necessarily solve all of these problems. Problems other than those listed may be solved by the specification. These issues will become clear from the description, drawings, claims, etc. This may be the subject of one aspect of the invention. [Means for solving the problem]

[0016] One embodiment of the present invention is a semiconductor device including a transistor and a first circuit. The gate electrode has a first gate and a second gate, the first gate and the second gate being formed by a semiconductor layer. The first circuit includes a temperature sensor, a voltage control circuit, and The temperature sensor has the function of acquiring temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting temperature information into a control voltage, and the first circuit has a function of converting temperature information into a control voltage. A voltage is applied to the second gate.

[0017] In the above-mentioned semiconductor device, the voltage control circuit converts temperature information into the control voltage based on a conversion formula. It is preferable to replace it.

[0018] In the above-mentioned semiconductor device, it is preferable that the voltage control circuit has a microcomputer or an amplifier. .

[0019] In the above-described semiconductor device, the semiconductor layer preferably contains a metal oxide.

[0020] The semiconductor device further includes a second circuit, the second circuit applying a negative voltage to the second gate. It is preferable to apply

[0021] In the above-described semiconductor device, the second circuit can hold a negative voltage.

[0022] In the above-mentioned semiconductor device, the second circuit is a transistor including a metal oxide in a channel forming region. It is preferable to have a star.

[0023] The above-mentioned semiconductor device has a function of applying a positive or negative voltage to the first gate and a function of applying a negative voltage to the second gate. It is preferable that the second electrode has a function of applying a negative voltage. Effect of the Invention

[0024] According to one embodiment of the present invention, a semiconductor device having high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having a wide temperature range can be provided. According to one embodiment of the present invention, a semiconductor device that can be used for a long period of time can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of storing data can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. The device can be provided.

[0025] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 2] FIG. 4 is a circuit diagram showing a configuration example of a voltage generating circuit. [Diagram 3] FIG. 4 is a circuit diagram showing a configuration example of a voltage holding circuit. [Figure 4] 13A and 13B are graphs showing temperature dependence of VG-ID characteristics of an OS transistor. [Diagram 5] 13A and 13B are graphs showing temperature dependence of VG-ID characteristics of an OS transistor. [Figure 6] FIG. [Figure 7] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 8] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 9] FIG. 2 is a diagram for explaining an example of the configuration of a memory cell array. [Figure 10] FIG. 2 is a circuit diagram illustrating a configuration example of a memory cell. [Figure 11] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 12] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 13] 1A to 1C illustrate examples of the structure of a transistor. [Figure 14] 1A to 1C illustrate examples of the structure of a transistor. [Figure 15] 1A to 1C illustrate examples of the structure of a transistor. [Figure 16] 1A to 1C illustrate examples of the structure of a transistor. [Figure 17] 1A to 1C illustrate examples of the structure of a transistor. [Figure 18] FIG. 1 is a diagram illustrating an example of an electronic component. [Figure 19] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 20] FIG. 2 illustrates an example of the configuration of a storage device. [Figure 21] FIG. 4 is a diagram for explaining a method of calculating an operating frequency. [Figure 22] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 23] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 24] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 25] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 26] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 27] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 28] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 29] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 30] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 31] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 32] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 33] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 34] Schematic diagram of the assumed DOSRAM. [Diagram 35] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 36] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Figure 37] FIG. 13 shows ID-VG characteristics of a transistor. [Figure 38] FIG. 4 shows a circuit for measuring leakage current. [Figure 39] FIG. 13 is a graph showing the temperature dependence of gate leakage current. [Diagram 40] FIG. 13 is a graph showing the relationship between a back gate voltage and a threshold voltage. [Diagram 41] FIG. 13 is a graph showing the relationship between the backgate voltage and mutual conductance. [Diagram 42] FIG. 13 is a graph showing the relationship between the presence or absence of a backgate electrode and the cutoff frequency. [Diagram 43] FIG. 13 is a graph showing measurement results of cutoff frequency. [Diagram 44] FIG. 13 is a graph showing the temperature dependence of off-state current. [Diagram 45] This graph shows the temperature dependence of Hall mobility and carrier density of a CAAC-IGZO film. [Diagram 46] FIG. 4 is a graph showing the temperature dependence of the cutoff frequency. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in the following manner. The present invention is not limited to the embodiments and the description of the examples.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are referred to as the same parts. The same reference numerals are used in common among different drawings, and the repeated explanations are omitted. When referring to a function, the same hatch pattern may be used and no particular reference number may be given.

[0029] In each figure described in this specification, the size, layer thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0030] In this specification, a high power supply voltage is referred to as an H level (or VDD), and a low power supply voltage is referred to as an L level. This is sometimes called the ground (or GND).

[0031] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. For this reason, in this specification and the like, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0032] In addition, in this specification, the following embodiment modes and examples can be combined as appropriate. In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be appropriately combined. It is possible to do this.

[0033] In this specification, the term "metal oxide" refers to a metal oxide in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). For example, metal oxide is used for the semiconductor layer of a transistor. In this case, the metal oxide is sometimes called an oxide semiconductor. In the above description, a transistor having a metal oxide or an oxide semiconductor is used instead. In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Sometimes referred to collectively.

[0034] (Embodiment 1) A semiconductor device according to one embodiment of the present invention includes a temperature sensor and a voltage compensation circuit. The transistor is electrically connected to a memory device or the like, and a voltage corresponding to temperature is applied to the transistor. The function of applying the voltage to the back gate of the transistor is to maintain the cut-off voltage of the transistor regardless of temperature. By controlling the back gate voltage so that the current is roughly the same, a high operating frequency can be achieved over a wide temperature range. The storage device may be a memory device having wave numbers.

[0035] <Semiconductor device 100> FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. The device 100 includes a voltage generating circuit 11, a voltage holding circuit 12, and a correction circuit 20. The synthesis circuit 11 is electrically connected to a voltage holding circuit 12, and the voltage holding circuit 12 is connected to a correction circuit 20. The node between the correction circuit 20 and the voltage holding circuit 12 is called a node N. The voltage holding circuit 12 and the correction circuit 20 are connected to an output terminal VOU via a node ND. Electrically connected to T.

[0036] In addition, the semiconductor device 100 outputs a first output of the plurality of transistors M10 through the output terminal VOUT. The first gate ("front gate") of each transistor M10 is electrically connected to the second gate of the transistor M10. The first gate (also called the "first gate" or simply the "gate") and the second gate (also called the "back gate"). ) of the respective transistors M10. V th0 In the transistor M10, the first gate and the second gate The gates preferably have an overlapping region with a semiconductor layer interposed therebetween. 100 is electrically connected to the second gate of the transistor M10 via the output terminal VOUT. It has been done.

[0037] The transistor M10 is used in various circuits included in memory devices, pixel devices, arithmetic devices, etc. For example, the transistors in NOR and NAND type memory devices In addition, for example, a liquid crystal display device or an EL display device The transistors included in each display device are also shown. GPU (Graphic Processing Unit), GPU (Graphic Processing Unit) ng Unit), or FPGA (Field Programmable Gate Figure 1 shows three transistors in a 3-phase MOS FET. Although M10 is shown, the semiconductor device 100 may include many transistors. In the following description, the transistor M10 may be The following description will be given assuming that the transistor is an n-channel type.

[0038] A transistor that uses silicon in the semiconductor layer in which the channel is formed ("Si transistor"). Compared with the conventional transistors, the off-state current of OS transistors increases even at high temperatures. In addition, the Vth of the OS transistor shifts in the negative direction as the operating temperature rises. On the other hand, in the case of a Si transistor, the off-current decreases with increasing temperature. In addition, the Vth of a Si transistor shifts in the positive direction as the temperature rises. Therefore, an OS transistor is used as the transistor M10. This reduces the power consumption of the entire semiconductor device, including the transistor M10, even when operating at high temperatures. It can be lowered.

[0039] The semiconductor device 100 applies a voltage V BG Write and For example, the voltage V BG When a negative potential is applied as Transistor M10 is connected to V while the second gate is held at a negative potential. th0 Shift to the positive side The transistor M10 is V th0 By keeping the temperature high, normally-on This can prevent the power consumption of the entire semiconductor device including the transistor M10 from increasing. For example, when the transistor M10 is used as a select transistor of a memory cell, The charge of the capacitive element functioning as storage can be retained for a long period of time.

[0040] [Voltage generating circuit 11] Examples of the circuit configuration of the voltage generating circuit 11 are shown in FIG. 2(A) and FIG. 2(B). It is a voltage-type charge pump, with GND input to the input terminal IN and V BG0 Here, as an example, the number of stages in the basic circuit of the charge pump circuit is 4. However, the present invention is not limited to this and the charge pump circuit may be configured with any number of stages.

[0041] The voltage generating circuit 11a shown in FIG. 2A includes transistors M21 to M24, and capacitors C21 to C24. The transistor M24 will be described as an n-channel transistor.

[0042] The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT. and the gate and first electrode of each are connected to function as a diode. The gates of the transistors M21 to M24 are connected to the capacitance elements Capacitor C21 to capacitative element C24 are connected.

[0043] CLK is input to the first electrodes of the odd-numbered capacitor elements C21 and C23, and CLKB is input to the first electrodes of the capacitive elements C22 and C24. CLKB is This is an inverted clock signal with the phase of CLK inverted.

[0044] The voltage generating circuit 11a steps down the GND input to the input terminal IN and generates V BG0 Generate The voltage generating circuit 11a generates a negative potential only by supplying CLK and CLKB. It is possible.

[0045] The above-described transistors M21 to M24 may be formed of OS transistors. By using OS transistors, the diode-connected transistors M21 to This is preferable because it can reduce the reverse current of the transistor M24.

[0046] The voltage generating circuit 11b shown in FIG. 2B is a p-channel transistor. The other components are the voltage generation The description of the formation circuit 11a will be used.

[0047] [Voltage holding circuit 12] The voltage holding circuit 12 includes a transistor M11 (see FIG. 1). The semiconductor device has a first gate and a second gate. The first gate and the second gate are disposed with a semiconductor layer therebetween. In the following description, the transistor M11 will be described as an n-channel transistor.

[0048] A first terminal of the transistor M11 is electrically connected to the voltage generating circuit 11, and a second terminal of the transistor M The second terminal of the transistor M11 is electrically connected to the node ND. is electrically connected to the first gate of transistor M11 and the second gate of transistor M11. The transistor M11 functions as a diode.

[0049] The voltage holding circuit 12 holds the voltage V BG0 , the voltage V BG As, It has a function of applying and holding a voltage to the second gate of the transistor M10. The threshold voltage of M11 is V th1 Then, V BG0 =V BG -Vth1 The relationship is Stand up.

[0050] The transistor M11 has a function of writing and holding a potential to the second gate of the transistor M10. FIG. 3A shows an example in which a negative potential (− 5V) is written to the second gate of transistor M10. The negative potential is the V of transistor M10. th0 The transistor M11 shifts the By connecting the first terminal to GND, the written negative potential is maintained, and the transistor M10 can be maintained normally off.

[0051] In FIG. 3A, transistor M11 is V G becomes 0V. V G Drain at 0V If the in current (hereafter referred to as the "cut-off current" or "Icut") is small enough, The transistor M11 blocks the flow of charge, and the voltage holding circuit 12 holds the negative potential for a long period of time. It is possible.

[0052] The channel length of transistor M11 is longer than the channel length of transistor M10. For example, when the channel length of the transistor M10 is set to less than 1 μm, The channel length of the stablizer M11 is preferably 1 μm or more, more preferably 3 μm or more, and even more preferably The channel length of the transistor M11 is preferably 5 μm or more, and more preferably 10 μm or more. By making it longer, the transistor M11 is not affected by the short channel effect and the cutoff current In addition, the transistor M11 can be made to withstand a high voltage between the source and drain. If the withstand voltage between the source and drain of the transistor M11 is high, This makes it possible to easily connect the voltage generating circuit 11 that generates the voltage and the transistor M10. I wish.

[0053] The transistor M11 is an OS transistor and has a wide band gap in the channel formation region. It is preferable to use transistors using semiconductors. OS transistors and wideband Transistors using gap semiconductors have a small cutoff current and In this specification, the term "wide band gap semiconductor" refers to a semiconductor having a large band gap. Semiconductors with a peak energy of 2.2 eV or more. Examples include silicon carbide, gallium nitride, and diamond. etc.

[0054] The transistor M11 is required to have a smaller cutoff current than the transistor M10. On the other hand, the transistor M10 is required to have a larger on-current than the transistor M11. When transistors with different required properties are to be fabricated on the same substrate, different semiconductors are used. The transistor M11 is a transistor It is preferable to use a semiconductor having a larger band gap than M10 for the channel formation region. In addition, the transistor M10 uses a semiconductor with higher electron mobility than the transistor M11. It is preferably used in the channel formation region.

[0055] In some cases, the second gate of the transistor M11 may be omitted.

[0056] The voltage holding circuit 12 is composed of a plurality of transistors M11 connected in series. (See FIG. 3(B)).

[0057] [Correction circuit 20] The compensation circuit 20 measures the temperature and adjusts the second gate of the transistor M10 in response to the obtained temperature information. The compensation circuit 20 has a function of controlling the voltage applied to the port when the temperature is different. applied to the second gate so that the off-current of the transistor M10 is approximately equal regardless of Control the voltage.

[0058] Figure 4 shows the I D (Drain current)-V G (Gate voltage) Temperature dependence of characteristics FIG. D -V G The characteristics are gate voltage (V G ) change in drain voltage Flow (I D In Fig. 4, the horizontal axis shows Vg on a linear scale, and the vertical axis shows I D is shown on a log scale.

[0059] In Fig. 4, temperature A is 85°C, temperature B is 27°C, and temperature C is -40°C. I of INDIST D -V G The figure shows an example of the characteristics. Note that the back gate voltage at each temperature The threshold voltage of the OS transistor shifts to the positive side as the temperature decreases. As a result, the operating speed of the circuit decreases. The threshold voltage shifts negatively and the subthreshold slope increases. In Figure 4, the cutoff current at temperature A is IcutA, and the cutoff current at temperature B is IcutB. As shown in Fig. 4, the higher the temperature, the As a result, the cutoff current increases.

[0060] When an OS transistor is used for the transistor M10, as shown in FIG. Threshold voltage (V th0 ) fluctuates. The lower the temperature, the more V th0 shifts to positive The higher the temperature, the higher the V th0 shifts negative. This is a workable This narrows the temperature range. For example, the semiconductor device 100 has a higher back gate voltage as the temperature decreases. to the transistor M10, and the V th0 Minus This shifts the on-state current in the opposite direction, increasing the operating speed of the circuit. It can be raised.

[0061] The correction circuit 20 includes a temperature sensor 17, a voltage control circuit 18, a buffer 15, and a capacitance element 14. (See Figure 1.)

[0062] The temperature sensor 17 senses the temperature of the semiconductor device 100 and outputs temperature information V Temp Output Temperature information V Temp is analog data, and the temperature sensor 17 is Temperature information V Temp may be a voltage or a current. This is also fine.

[0063] The temperature sensor 17 may be, for example, a platinum, nickel, copper or other resistance thermometer, a thermistor, etc. , thermocouples, IC temperature sensors, etc. can be used.

[0064] The voltage control circuit 18 controls the temperature information V Temp Depending on the The voltage control circuit 18 has a function of controlling the voltage applied to the second gate of the transistor M10. The device has a microcomputer, a microprocessor, or an amplifier, and performs temperature control based on a conversion formula. degree information V Temp Converting to control voltage V CTR In this specification, etc., A microcomputer or microprocessor may be referred to as a microcomputer.

[0065] Control voltage V CTR This means that the cutoff current of transistor M10 is roughly the same regardless of temperature. The back gate voltage V BG The above conversion formula controls the temperature information V Temp from , temperature dependent control voltage V CTR The back gate voltage varies depending on the temperature. Voltage V BG By using this, the cutoff current of the transistor M10 is roughly the same, so that the output The circuit electrically connected to the VOUT terminal has a high operating frequency over a wide temperature range. can.

[0066] The backgate voltage V is set so that the cutoff current of transistor M10 is approximately the same. BG of When controlled, I D -V G The characteristics are shown in Figure 5. Figure 5 shows the characteristics at temperatures A, B and C. The back gate voltage V is set so that the cutoff current of each BG An example of adjusting For example, Icut0 is the required value for a transistor based on the specifications of the semiconductor device. Alternatively, the cut-off current value may be used.

[0067] For example, the highest cutoff current value in the specified temperature range is used as Icut0. In the examples shown in FIG. 4 and FIG. 5, Icut at temperature A where the cutoff current is the highest is A can be used as Icut0. Let the cutoff current at temperature B be Icut0. To achieve this, a control voltage V must be set higher than temperature A. CTR and outputs a back gate voltage higher than temperature A. Pressure V BG In order to set the cutoff current at temperature C to Icut0, the limit must be higher than that at temperature B. Voltage V CTR and outputs a back gate voltage V higher than temperature B. BG Let us assume that.

[0068] Temperature information V Temp to control voltage V CTR Examples of conversion to are shown in Figs. 6(A), 6(B) and 6(C). 6(C). As shown in FIG. 6(A), the temperature information V Temp and the control voltage V CTR is line As shown in FIG. 6B, the temperature information V Temp and the control voltage V CTR may have a nonlinear relationship. As shown in the figure, the temperature information V Temp and the control voltage V CTR By using the conversion formula, the temperature The difference can be finely corrected. Note that in Figures 6(A) and 6(B), the higher the temperature, the more accurate the temperature information. V Temp In addition, as shown in FIG. 6C, the temperature information V Temp and the control voltage V CTR For example, the temperature may be converted using a table. degree information V Temp1 ~V Tempn For each, the control voltage V CTR1 ~V CTR n (n is an integer of 2 or more).

[0069] From the characteristics of a transistor having the same or similar structure as the transistor M10, FIG. The conversion formula shown in FIG. 6(B) or the table shown in FIG. 6(C) is prepared in advance. The table is stored in the voltage control circuit 18. By using a table, the voltage control circuit 18 obtains the temperature information V Temp Control according to Voltage V CTR can be output.

[0070] The control voltage V output by the voltage control circuit 18 CTR is fed to the input of buffer 15. One electrode of the capacitance element 14 is electrically connected to the output of the buffer 15, and the other electrode is connected to a node The buffer 15 is electrically connected to the ND. In some cases, it may be omitted.

[0071] The voltage applied to the node ND from the voltage control circuit 18 is determined by the capacitance of the capacitive element 14 and the The capacitance of the capacitance element 14 is determined by the ratio of the parasitic capacitances generated in the It is preferable that the capacitance of the capacitance element 14 is sufficiently large. It is preferable that the correction factor is 5 times or more, and more preferably 10 times or more. A voltage according to temperature can be supplied to the node ND from the line 20. The voltage VOUT of the output terminal BG can be changed.

[0072] If the temperature change of the electrical characteristics of transistor M10 is not taken into consideration, a voltage larger than necessary will be applied to the transistor. A voltage larger than necessary is applied to the second gate of transistor M10. If a voltage is applied to the second gate of transistor M10 for a long period of time, the electrical characteristics of transistor M10 will deteriorate. According to one aspect of the present invention, the transistor M The voltage applied to the second gate of 10 can be changed. Therefore, the minimum required voltage may be applied to the second gate of transistor M10. According to one aspect of the present invention, This can improve the reliability of a semiconductor device including the transistor M11.

[0073] The temperature sensor 17 may include a voltage control circuit 18 therein. 7. In FIG. 7, the temperature sensor 19 includes a power supply control circuit (not shown) and V CTR can be output directly.

[0074] As described above, by using the semiconductor device 100 described in this embodiment, a semiconductor device with a high on-current can be obtained. It is also possible to provide a semiconductor device with a high operating speed. In addition, a semiconductor device capable of retaining data for a long period of time can be provided. It is possible to provide a semiconductor device with reduced power consumption.

[0075] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0076] (Embodiment 2) In this embodiment, a memory device using the semiconductor device 100 described in the first embodiment will be described. Reveal.

[0077] <Storage device> 8 is a block diagram showing a configuration example of a storage device. The peripheral circuit 311 includes a row decoder, a cell array 401, and a semiconductor device 100. 321, word line driver circuit 322, bit line driver circuit 330, and output circuit 340. , and a control logic circuit 360.

[0078] The word line driver circuit 322 has a function of supplying a potential to the wiring WL. The driver circuit 330 includes a column decoder 331, a precharge circuit 332, an amplifier circuit 333, and a write circuit 334. The precharge circuit 332 is connected to a wiring SL (not shown) The amplifier circuit 333 has a function of precharging the wiring BIL or the wiring RBL. The wiring WL, wiring SL, and wiring The BIL and the wiring RBL are connected to the memory cells 411 in the cell array 401. The amplified data signal is output to the output circuit 340. , and is outputted to the outside of the storage device 300 as a digital data signal RDATA.

[0079] The storage device 300 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, A high power supply voltage (VDD) for the cell array 401 and a high power supply voltage (VIL) for the cell array 401 are supplied.

[0080] The memory device 300 also includes control signals (CE, WE, RE), an address signal ADDR, The data signal WDATA is input from the outside. The address signal ADDR is input to the row decoder 32. 1 and the column decoder 331, and WDATA is input to the write circuit 334. do.

[0081] The control logic circuit 360 processes external input signals (CE, WE, RE). CE generates control signals for the row decoder 321 and the column decoder 331. WE is the write enable signal, RE is the read enable signal, The signals processed by the control logic circuit 360 are not limited to these. However, other control signals may be input as necessary.

[0082] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0083] The transistors constituting the cell array 401 can be OS transistors. In addition, OS transistors can be used as transistors constituting the peripheral circuit 311. By forming the cell array 401 and the peripheral circuit 311 using OS transistors, The cell array 401 and the peripheral circuit 311 can be manufactured in the same manufacturing process. This allows the manufacturing costs to be kept low.

[0084] [Example of cell array configuration] 9 shows the details of the cell array 401. The cell array 401 has m (m is 1 or more) cells arranged in a row. ) in each row (n is an integer greater than or equal to 1), for a total of m × n memory cells. The memory cells 411 are arranged in a matrix. The 11 addresses are also listed, [1,1], [m,1], [i,j], [1,n ], [m, n] (where i is an integer between 1 and m, and j is an integer between 1 and n, inclusive. ) is shown. The number of wirings connecting the word line driver circuit 322 to the memory cell 411 depends on the configuration of the memory cell 411, It is determined by the number of memory cells 411 included in one column. The number of wirings connecting the bit line driver circuit 330 depends on the configuration of the memory cell 411. It is determined by the number of memory cells 411 included in the row, etc.

[0085] [Example of memory cell configuration] FIG. 10 shows memory cells 411A to 411B that can be applied to the above-described memory cell 411. An example of the configuration of 1E is shown below.

[0086] [DOSRAM] FIG. 10A shows an example of a circuit configuration of a DRAM type memory cell 411A. DRAM using OS transistors is called DOSRAM (Dynamic Oxid It is called eSemiconductor Random Access Memory (ESRAM). The memory cell 411A includes a transistor M11 and a capacitor CA.

[0087] A first terminal of the transistor M11 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M11 is connected to the wiring BIL, and the gate of the transistor M11 is connected to the wiring WL. The back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the slave CA is connected to the wiring GNDL. The wiring GNDL is a low-level potential ( This is sometimes called the reference potential.

[0088] The wiring BIL functions as a bit line, and the wiring WL functions as a word line. L functions as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to BGL, the threshold voltage of transistor M11 can be increased or decreased. It is possible.

[0089] Data is written and read by applying a high-level potential to the wiring WL and 1 is brought into a conductive state, and the wiring BIL and the first terminal of the capacitance element CA are electrically connected to each other. This is carried out.

[0090] In addition, the memory cells included in the memory device 300 described above are not limited to the memory cells 411A. , the circuit configuration can be changed.

[0091] When the transistor M11 is used in a memory cell, an OS transistor is used as the transistor M11. In addition, it is preferable to use a semiconductor layer of the OS transistor containing indium, an element M, or the like. (Element M is aluminum, gallium, yttrium, or tin), or zinc In particular, an oxide semiconductor containing indium, gallium, or zinc is preferably used. It is preferable to use an oxide semiconductor having such a structure.

[0092] OS transistors using oxide semiconductors containing indium, gallium, and zinc have The transistor M11 has the characteristic of having an extremely small current. By using the above, the leakage current of the transistor M11 can be made very low. In other words, the written data can be retained for a long time by the transistor M11. Therefore, the frequency of refreshing the memory cells can be reduced. This eliminates the need for refresh operations. Also, the leakage current is very low, so the memory The register 411A, the memory cell 420, and the memory cell 430 are multi-valued data or analog data. Log data can be retained.

[0093] DOSRAM is constructed by applying an OS transistor as transistor M11. It is possible.

[0094] [NOSRAM] FIG. 10B shows a gain cell type ("2Tr 1C type). The memory cell 411B has a circuit configuration example. , a transistor M11, a transistor M3, and a capacitive element CB.

[0095] A first terminal of the transistor M11 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M11 is connected to the wiring WBL, and the gate of the transistor M11 is connected to the wiring WL. The back gate of the transistor M11 is connected to the wiring BGL. A second terminal of the transistor CB is connected to the wiring RL. A first terminal of the transistor M3 is connected to the wiring A second terminal of the transistor M3 is connected to the line SL. A second terminal of the transistor M4 is connected to the line SL. The gate of M3 is connected to the first terminal of the capacitive element CB.

[0096] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The line WL functions as a word line. The line RL is connected to the second terminal of the capacitance element CB. It functions as a wiring for applying a specific potential. In particular, it is preferable to apply a reference potential to the wiring RL.

[0097] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 is The pressure can be increased or decreased.

[0098] To write data, a high-level potential is applied to the line WL to turn on the transistor M11. This is achieved by electrically connecting the wiring WBL and the first terminal of the capacitance element CB. Specifically, when the transistor M11 is in a conductive state, A potential is applied to the first terminal of the capacitance element CB and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WL to turn off the transistor M11. By setting the capacitor CB in the ON state, the potential of the first terminal of the capacitor CB and the gate The potential of the input is maintained.

[0099] Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor M3 and the first The potential of the terminal is the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. The potential of the wiring RBL connected to the first terminal of the transistor M3 is By reading out the potential, the first terminal of the capacitance element CB (or the gate of the transistor M3) In other words, the potential held at the first terminal (or The potential held on the gate of transistor M1 or the gate of transistor M2 is used to determine the potential to be written to this memory cell. The information stored in this memory cell can be read out. You can find out whether it is available or not.

[0100] In addition, the memory cells included in the memory device 300 described above are not limited to the memory cells 411B. The circuit configuration can be changed as appropriate.

[0101] For example, the wiring WBL and the wiring RBL may be combined into one wiring BIL. An example of the circuit configuration of the memory cell is shown in FIG. The wiring WBL and the wiring RBL of the transistor M11 are connected to one wiring BIL. The second terminal and the first terminal of the transistor M3 are connected to the wiring BIL. That is, the memory cell 411C has a write bit line, a read bit line, and The configuration operates as a single wiring BIL.

[0102] In the memory cells 411B and 411C, the transistor M11 It is preferable to use an OS transistor as the transistor M11. In addition, 2Tr1C type memory cells such as memory cell 411B and memory cell 411C The memory device using this is called NOSRAM (Non-volatile Oxide Semiconductor It is called Inductor Random Access Memory.

[0103] It is preferable that the channel formation region of the transistor M3 contains silicon. The silicon may be amorphous silicon, polycrystalline silicon, low temperature polysilicon (LTPS), Low Temperature Poly-Silicon (hereafter (In these transistors, the Si transistor has a higher field strength than the OS transistor.) A Si transistor is used as the readout transistor because the effective mobility may be high. It is preferable to apply

[0104] In addition, when an OS transistor is used as the transistor M3, the memory cell is a unipolar circuit. It can be composed of:

[0105] Also, in Figure 10(D), a gain cell type with 3 transistors and 1 capacitor (called a "3Tr1C type") is shown. 4 shows an example of a circuit configuration of a memory cell 411D of the above-mentioned embodiment. The memory cell 411D is a transistor. A transistor M11, a transistor M5, a transistor M6, and a capacitance element CC. .

[0106] The first terminal of the transistor M11 is connected to the first terminal of the capacitance element CC, and the transistor M The second terminal of the transistor M11 is connected to the wiring BIL, and the gate of the transistor M11 is connected to the wiring WL. The back gate of the transistor M11 is electrically connected to the wiring BGL. The second terminal of the capacitance element CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6. The gate of the transistor M5 is connected to the first terminal of the capacitance element CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring R It is connected to L.

[0107] The wiring BIL functions as a bit line, the wiring WL functions as a write word line, and The line RL functions as a read word line.

[0108] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 is The pressure can be increased or decreased.

[0109] To write data, a high-level potential is applied to the line WL to turn on the transistor M11. The wiring BIL is connected to the first terminal of the capacitance element CC. is a potential corresponding to information to be recorded in the wiring BIL when the transistor M11 is in a conductive state. The potential is written to the first terminal of the capacitance element CC and the gate of the transistor M5. After that, a low-level potential is applied to the line WL to turn off the transistor M11. As a result, the potential of the first terminal of the capacitance element CC and the potential of the gate of the transistor M5 Hold.

[0110] To read data, a predetermined potential is precharged to the line BIL, and then the line BIL is This is done by putting the wiring RL in an electrically floating state and applying a high-level potential to the wiring RL. Since the line RL is at a high level potential, the transistor M6 is in a conductive state, and the line BIL and The second terminal of the transistor M5 is electrically connected. The potential of the wiring BIL is applied to the second terminal, but the potential of the first terminal ( or the gate of transistor M5), The potential of the second terminal and the potential of the wiring BIL change. By outputting the current, the first terminal of the capacitance element CC (or the gate of the transistor M5) In other words, the potential stored in the first terminal (or transistor) of the capacitance element CC can be read out. The potential held at the gate of transistor M5 indicates that the data written to this memory cell You can read out the information or check whether the information is written in this memory cell. You can find out.

[0111] In addition, the circuit configuration of the memory cell included in the above-described memory device 300 can be changed as appropriate. can.

[0112] In addition, in the memory cell 411D, an OS transistor is used as the transistor M11. It is preferable that the transistor M11 is a 3Tr1C type transistor using an OS transistor. Memory cell 411D is one embodiment of the NOSRAM previously described.

[0113] In addition, the channel forming regions of the transistors M5 and M6 described in this embodiment are It is preferable that the silicon has a silicon content of 10 ... , low-temperature polysilicon. Si transistors are more cost-effective than OS transistors. A Si transistor is used as the readout transistor because it may have a high field effect mobility. It is preferable to apply the stan.

[0114] In addition, when OS transistors are used as the transistors M5 and M6, the memory cell It can be constructed with a unipolar circuit.

[0115] [oxSRAM] FIG. 10(E) shows a static random access memory (SRAM) using OS transistors. 4 shows an example of a circuit configuration of a memory cell 411E of the access memory type. In this paper, the SRAM using OS transistors is called oxSRAM. ) is a backup capable SRAM type memory cell.

[0116] The memory cell 411E includes transistors M7 to M10 and a transistor MS 1 to 4, a transistor MS1 to a transistor MS2, a capacitor CD1, and a capacitor CD2. The transistor M7 and the transistor M8 correspond to the transistor M11. Transistors M7 to M10 are transistors having a back gate. The transistors MS1 and MS2 are p-channel transistors. The transistor MS3 and the transistor MS4 are n-channel transistors. do.

[0117] A first terminal of the transistor M7 is connected to the wiring BIL, and a second terminal of the transistor M7 is , a first terminal of the transistor MS1, a first terminal of the transistor MS3, and a transistor M a gate of transistor S2, a gate of transistor MS4, and a first terminal of transistor M10; The gate of the transistor M7 is connected to the wiring WL. The back gate of the transistor is connected to the wiring BGL1.

[0118] A first terminal of the transistor M8 is connected to the line BILB, and a second terminal of the transistor M8 is connected to the line BILB. a first terminal of the transistor MS2, a first terminal of the transistor MS4, and a second terminal of the transistor a gate of transistor MS1, a gate of transistor MS3, and a first terminal of transistor M9; The gate of the transistor M8 is connected to the wiring WL. The back gate of is connected to the wiring BGL2.

[0119] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. The second terminal of the transistor MS2 is electrically connected to the wiring VDL. The second terminal of the transistor MS4 is electrically connected to the wiring GNDL. It is connected to the line GNDL.

[0120] The second terminal of the transistor M9 is connected to the first terminal of the capacitance element CD1. The gate of the transistor M9 is connected to the wiring BGL. 3. The second terminal of the transistor M10 is connected to the first terminal of the capacitive element CD2. The gate of the transistor M10 is connected to the wiring BRL. The back gate is connected to a wiring BGL4.

[0121] The second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is It is connected to the wiring GNDL.

[0122] The wirings BIL and BILB function as bit lines, and the wiring WL functions as a word line. The wiring BRL controls the conductive state and non-conductive state of the transistor M9 and the transistor M10. This is the wiring that controls the on state.

[0123] The wirings BGL1 to BGL4 are the transistors M7 to M10, respectively. It functions as a wiring for applying a potential to the back gate.

[0124] The wirings BGL1 to BGL4 are electrically connected to the output terminal VOUT of the semiconductor device 100. In addition, a plurality of semiconductor devices 100 are provided in the storage device 300, and wirings BGL1 to BGL3 are provided in the storage device 300. The wirings BGL1 and BGL4 may be electrically connected to different semiconductor devices 100. By applying an arbitrary potential to the wiring BGL4, the transistors M7 to The threshold voltage of transistor M10 can be increased or decreased.

[0125] The wiring VDL is a wiring that provides a high-level potential, and the wiring GNDL is a wiring that provides a low-level potential. This is the wiring.

[0126] To write data, a high-level potential is applied to the line WL and a high-level potential is applied to the line BRL. Specifically, when transistor M10 is in a conducting state, A potential corresponding to the information to be recorded is applied to the wiring BIL, and the second terminal side of the transistor M10 The potential is written to

[0127] By the way, the memory cell 411E is configured by transistors MS1 to MS4. Since an inverter loop is formed, a potential corresponding to the potential is applied to the second terminal side of the transistor M8. The inverted signal of the data signal is input. Since the transistor M8 is in a conductive state, The BILB is a potential applied to the wiring BIL, i.e., a potential input to the wiring BIL. The inverted signal of the signal is output. Also, transistors M9 and M10 are Since the transistor M7 is in the on state, the potential of the second terminal of the transistor M8 The potentials of the terminals are the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, Thereafter, a low level potential is applied to the wiring WL, and a low level potential is applied to the wiring BRL. , turning off transistors M7 through M10, The first terminal of the capacitive element CD1 and the first terminal of the capacitive element CD2 are held.

[0128] To read data, the lines BIL and BILB are precharged to a predetermined potential. After the write operation, a high-level potential is applied to the wiring WL and a high-level potential is applied to the wiring BRL. As a result, the potential of the first terminal of the capacitance element CD1 becomes equal to the potential of the inverter of the memory cell 411E. The first input of the capacitance element CD2 is refreshed by the loop and output to the wiring BILB. The potential of the first terminal is refreshed by the inverter loop of the memory cell 411E, and the The signal is output to the line BIL. The signal is precharged on the lines BIL and BILB. The potential at the first terminal of the capacitance element CD2 and the potential at the first terminal of the capacitance element CD1 are Since the potential of the wiring BIL or BILB varies, the potential held in the memory cell can be read out.

[0129] Note that OS transistors may be used as the transistors M7 to M10. It is preferable to use OS transistors for the transistors M7 to M10. Therefore, data written in the memory cell 411E can be retained for a long time. This reduces the frequency of refreshing the memory cell 411E. This eliminates the need for a refresh operation in 11E. Also, the leakage current is very low, Therefore, multi-level data or analog data can be held in memory cell 411E.

[0130] Note that silicon is used for the channel formation regions of the transistors MS1 to MS4. In particular, the silicon may be amorphous silicon, polycrystalline silicon, low-temperature polysilicon, etc. Silicon transistors can be made of silicon. Si transistors have a higher field effect than OS transistors. In some cases, the mobility of the Si transistors in the inverters is high. It is preferable to use a transistor.

[0131] In addition, by using OS transistors in memory cells, the power supply to the memory cells can be stopped. Therefore, the information written in the memory cell can be retained for a long time even if the memory cell is When writing is not required, power supply to a part or all of the peripheral circuit 311 is stopped. This can be done.

[0132] One semiconductor device 100 may be electrically connected to all memory cells. A plurality of semiconductor devices 100 are provided in the memory cell array 300, and a plurality of memory cells are arranged in each column or in each plurality of columns. A single semiconductor device 100 may be electrically connected. The memory cells may be electrically connected to one semiconductor device 100. The included memory cells are divided into multiple blocks, and each block or multiple blocks are Alternatively, one semiconductor device 100 may be provided for each block.

[0133] The memory cells described in this embodiment are included in registers and It can be used in memory elements such as caches.

[0134] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0135] (Embodiment 3) In this embodiment, a cross-sectional configuration example of a memory device will be described with reference to the drawings.

[0136] <Example of memory device structure> 11 shows a cross section of a portion of a memory device 300. The memory device 300 shown in FIG. 11, a single crystal substrate 231 is used as the substrate 231. 1 shows a case where a crystalline semiconductor substrate (for example, a single crystal silicon substrate) is used.

[0137] [Layer 310] In FIG. 11, layer 310 includes transistors 233a, 233b, and 233c on substrate 231. 11, the transistor 233a, the transistor 3b, and the transistor 233c. 1 shows cross sections of a transistor 233b and a transistor 233c in the channel length direction.

[0138] The channels of the transistors 233a, 233b, and 233c is formed on a part of the substrate 231. When high speed operation is required for the integrated circuit, It is preferable to use a single crystal semiconductor substrate as the substrate 1.

[0139] The transistor 233a, the transistor 233b, and the transistor 233c are element components. The transistors are electrically isolated from each other by the separation layer 232. The LOCOS (Local Oxidation of Silicon) method and S The TI (Shallow Trench Isolation) method can be used. do.

[0140] An insulating layer 234 is provided on the substrate 231, and a transistor 233a and a transistor 2 An insulating layer 235 and an insulating layer 237 are provided on the transistor 33b and the transistor 233c. An electrode 238 is buried in the layer 237. The electrode 238 is connected to the layer 237 through a contact plug 236. The transistor 233a is electrically connected to one of the source and the drain of the transistor 233a.

[0141] In addition, on the electrode 238 and the insulating layer 237, an insulating layer 239, an insulating layer 240, and an insulating A layer 241 is provided, and an electrode 24 is disposed in the insulating layer 239, the insulating layer 240, and the insulating layer 241. 2 is embedded in the electrode 242. The electrode 242 is electrically connected to the electrode 238.

[0142] Moreover, an insulating layer 243 and an insulating layer 244 are provided on the electrode 242 and the insulating layer 241. An electrode 245 is embedded in the insulating layer 243 and the insulating layer 244. 5 is electrically connected to the electrode 242.

[0143] Moreover, an insulating layer 246 and an insulating layer 247 are provided on the electrode 245 and the insulating layer 244. An electrode 249 is embedded in the insulating layer 246 and the insulating layer 247. , and is electrically connected to electrode 245.

[0144] Moreover, an insulating layer 248 and an insulating layer 250 are provided on the electrode 249 and the insulating layer 247. An electrode 251 is embedded in the insulating layer 248 and the insulating layer 250. , and is electrically connected to electrode 249.

[0145] [Layer 320] Layer 320 is disposed on layer 310. Layer 320 includes transistor 368a, transistor In FIG. 11, the transistor 368b has a capacitance element 369a, and the capacitance element 369b has a capacitance element 369b. 13 shows a cross section of the transistor 368a and the transistor 368b in the channel length direction. , transistor 368a, and transistor 368b are transistors having a back gate. It's Jista.

[0146] The transistor 368a and the transistor 368b are the same as those in the above embodiment. Therefore, the transistor 368a and the transistor 368b correspond to the transistor M11. It is preferable to use an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer. , the transistor 368a, and the transistor 368b are OS transistors. is preferred.

[0147] The transistor 368a and the transistor 368b are formed by insulating layers 361 and 36 2. In addition, insulating layer 363 and insulating layer 364 are provided on insulating layer 362. The back gates of the transistors 368a and 368b are insulated. The insulating layer 361 is embedded in the edge layer 363 and the insulating layer 364. An electrode 367 is embedded in the insulating layer 361. The electrode 367 is electrically connected to the electrode 251. On the insulating layer 364, an insulating layer 365, an insulating layer 366, an insulating layer 371, an insulating layer 372, An insulating layer 373, an insulating layer 375, and an insulating layer 376 are provided.

[0148] The insulating layer 375 and the insulating layer 376 are formed on the transistor 368a and the transistor 368b. An electrode 374 is provided on the insulating layer 365, the insulating layer 366, and the insulating layer 371. , are embedded in insulating layers 372, 373, 375, and 376. 374 functions as a contact plug.

[0149] An electrode 377 is provided on the insulating layer 376, and the electrode 377 is connected to the electrode 367 via the electrode 374. are electrically connected.

[0150] In addition, an insulating layer 378 and an insulating layer 379 are provided over the electrode 377. The insulating layer 378 and the capacitor element 369b are formed through an opening in the insulating layer 379. an electrode 391 disposed in the insulating layer 379; and an insulating layer 392 disposed on the electrode 391 and the insulating layer 379. and an electrode 393 on the layer 392. An opening formed in the insulating layer 378 and the insulating layer 379. In the mouth, at least a portion of the electrode 391, at least a portion of the insulating layer 392, and the electrode 3 At least a portion of 93 will be deployed.

[0151] The electrode 391 functions as a lower electrode of the capacitor element, and the electrode 393 functions as an upper electrode of the capacitor element. The capacitor is connected to the insulating layer 378 and the insulating layer 392 functions as a dielectric for the capacitor. In addition, in the opening of the insulating layer 379, the upper electrode and the lower electrode are connected not only to the bottom surface but also to the side surface. The electrodes face each other with a dielectric between them, which increases the capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element. By increasing the capacitance per unit area of ​​the capacitance element in this way, This makes it possible to promote miniaturization or high integration of semiconductor devices.

[0152] The shape of the openings formed in the insulating layers 378 and 379 when viewed from above is a rectangle. Alternatively, the shape may be a polygon other than a square, or the corners of the polygon may be curved. It may be in a circular shape including an ellipse.

[0153] Further, an insulating layer 381 and an insulating layer 382 are provided over the insulating layer 392 and the electrode 393 . In addition, the insulating layer 378, the insulating layer 379, the insulating layer 392, the insulating layer 381, and the insulating layer 382 An electrode 383 is embedded in the electrode 377. The electrode 383 is electrically connected to the electrode 377. The electrode 383 can function as a contact plug. The electrode 384 is electrically connected to the electrode 383. An insulating layer 385 is provided.

[0154] <Modification> FIG. 12 shows a cross section of a portion of the memory device 300A. In the example shown, the storage device 300A has a layer 310A and a layer 320. In A, an insulating substrate (for example, a glass substrate) is used as the substrate 231.

[0155] Layer 310A includes transistor 268a, transistor 268b, capacitive element 369a, and The layer 310A includes a thin film transistor (TFT). (For example, OS transistors are used.) All the transistors included in layer 310A are OS By making it a transistor, layer 310A can be made into a unipolar integrated circuit. By using OS transistors for all the transistors included in the memory device 300A, 0A can be made into a unipolar storage device.

[0156] <About the constituent materials> 〔substrate〕 There is no particular restriction on the material used for the substrate, but it should be strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, silicon or silicon carbide is used as the substrate. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, silicon germanium substrates, etc. In addition, a compound semiconductor substrate with a strained surface on an SOI substrate or a semiconductor substrate can be used. Use of transistors, FIN type transistors, and other semiconductor elements. Alternatively, a high electron mobility transistor (HEMT) can be used. Gallium arsenide and aluminum arsenide applicable to the 1000 n Mobility Transistor Nitride, Indium Gallium Arsenide, Gallium Nitride, Indium Phosphide, Silicon In other words, the substrate is not limited to a simple support substrate, but may be any other type of substrate. It may also be a substrate on which devices such as transistors are formed.

[0157] In addition, glass such as barium borosilicate glass and aluminoborosilicate glass can be used as a substrate. A substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may also be used. A flexible substrate may be used as the plate. When a flexible substrate is used, A transistor, a capacitor, or the like may be directly manufactured on a flexible substrate, or may be manufactured on another substrate. A transistor, a capacitor, or the like may be fabricated on the substrate, and then the transistor, the capacitor, or the like may be peeled off and transferred to the flexible substrate. In order to peel and transfer the transistors and capacitors from the manufacturing substrate to the flexible substrate, It is advisable to provide a release layer between the substrate and the resin.

[0158] The flexible substrate may be, for example, a metal, an alloy, a resin, a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate used, the less the deformation caused by the environment. The flexible substrate used for the substrate has a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 If a material with a temperature of 0.1 to 1.5 K or less is used, Examples of resins include polyester, polyolefin, polyamide (nylon, a Aramid, polyimide, polycarbonate, acrylic, etc. In particular, aramid Since the linear expansion coefficient is low, it is suitable as a flexible substrate.

[0159] [Insulating layer] The insulating layer is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxynitride. Minium, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, oxynitride silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate Materials selected from the above are used in a single layer or in a laminated form. In addition, oxide materials, nitride materials, etc. A mixture of a plurality of materials selected from the group consisting of oxynitride materials and nitride oxide materials may also be used.

[0160] In this specification and the like, the term "nitride oxide" refers to a compound that contains more nitrogen than oxygen. In addition, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of is, for example, measured by Rutherford Backscattering (RBS) spectroscopy. Measurements can be made using techniques such as kScattering Spectrometry. .

[0161] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, In order to prevent an increase in the hydrogen concentration in the insulating layer, it is preferable to reduce the hydrogen concentration in the insulating layer. The hydrogen concentration in the insulating layer was measured using secondary ion mass spectrometry (SIMS). Ion Mass Spectrometry) is 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18atoms / cm 3 The following In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0162] In order to prevent an increase in the nitrogen concentration in the semiconductor layer, the nitrogen concentration in the insulating layer can be reduced. Specifically, the nitrogen concentration in the insulating layer is preferably 5×10 19 atom s / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1× 10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 Below Below.

[0163] In addition, it is preferable that at least the region of the insulating layer that contacts the semiconductor layer has few defects. Specifically, the electron spin resonance (ESR) method For example, the above-mentioned signal is preferably observed at a g value of The E' center is observed at 2.001. The E' center is silicon For example, a silicon oxide layer or a nitriding layer is used as an insulating layer. When a silicon oxide layer is used, the spin density due to the E' center is 3×10 17 spins / cm 3 Less than or equal to 5×10 16 spins / cm 3 A silicon oxide layer Alternatively, a silicon oxynitride layer may be used.

[0164] In addition, if signals due to nitrogen dioxide (NO2) are observed in addition to the above signals, The signal is split into three signals due to the nuclear spin of N, g value is 2.037 or more and 2.039 or less (first signal), g value is 2.001 or less 2.003 or less (second signal), and g value is 1.964 or more and 1.966 or less. It is observed below (referred to as the third signal).

[0165] For example, the spin density of the signal caused by nitrogen dioxide (NO2) as an insulating layer is 1× 10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Using an insulating layer that is less than It is preferable to have

[0166] In addition, nitrogen oxides (NO x ) forms a level in the insulating layer The level is located within the energy gap of the oxide semiconductor layer. Things (NO x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, the level is As a result, the trapped electrons are transported between the insulating layer and the oxide. Since it remains near the interface of the semiconductor layer, it shifts the threshold voltage of the transistor in the positive direction. Therefore, it is recommended to use an insulating layer and a film with a low content of nitrogen oxide as the insulating layer. When used, the shift in the threshold voltage of a transistor can be reduced.

[0167] Nitrogen oxides (NO x As an insulating layer with a low emission of ., for example, a silicon oxynitride layer is used. The silicon oxynitride layer can be analyzed by thermal desorption spectroscopy (TDS). In real time desorption spectroscopy, nitrogen oxides ( NO x ) is a membrane that releases more ammonia than water. The amount is 1×10 18 molecules / cm 3 5×10 or more 19 molecules / cm 3 The following is the case. The amount of ammonia released is higher when the heat treatment temperature in TDS is between 50°C and 650°C, and is the total amount in the range of 50°C to 550°C.

[0168] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating layer with a high monia emission rate, nitrogen oxides (NO x ) is reduced.

[0169] At least one of the insulating layers in contact with the oxide semiconductor layer is a layer that releases oxygen by heating. Specifically, the insulating layer is preferably formed so that the surface temperature of the insulating layer is 100° C. The TDS is performed at a temperature of 100°C to 500°C or lower. The amount of oxygen released, calculated as oxygen atoms, is 1.0 × 10 18 atoms / cm 3 That's it, part 1. 0×10 19 atoms / cm 3 or more, or 1.0×10 20 atoms / cm 3 End It is preferable to use an insulating layer in which the The oxygen that is released is called "excess oxygen."

[0170] The insulating layer containing excess oxygen can also be formed by performing a process of adding oxygen to the insulating layer. The treatment to add oxygen is carried out by heat treatment in an oxidizing atmosphere or plasma treatment. Alternatively, ion implantation, ion doping, plasma immersion Oxygen may be added by using an on-implantation method or the like. teeth, 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas, or ozone gas In this specification, the process of adding oxygen is referred to as "oxygen doping." The oxygen doping process may be performed by heating the substrate.

[0171] The insulating layer may be made of polyimide, acrylic resin, benzocyclobutene resin, polyamide resin, or the like. Organic materials having heat resistance, such as amides and epoxy resins, can be used. In addition to the above materials, low-k materials, siloxane resins, and PSG (lingala The material can be shaped by using these materials. The insulating layer may be formed by stacking a plurality of insulating layers formed of the insulating material.

[0172] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0173] The method for forming the insulating layer is not particularly limited. Depending on the material used for the insulating layer, a firing process may be used. In this case, the insulating layer firing process can be combined with other heat treatment processes to efficiently This makes it possible to fabricate transistors efficiently.

[0174] 〔electrode〕 Conductive materials for forming electrodes include aluminum, chromium, copper, silver, gold, platinum, Tantalum, Nickel, Titanium, Molybdenum, Tungsten, Hafnium, Vanadium, Ni Selected from obium, manganese, magnesium, zirconium, beryllium, indium, etc. Materials containing one or more metal elements such as phosphorus can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon, nickel silicide, etc. Alternatively, a silicide such as the above may be used.

[0175] In addition, a conductive material containing the above metal element and oxygen may be used. Conductive materials containing silicon and nitrogen may also be used, such as titanium nitride and tantalum nitride. A conductive material containing nitrogen may be used. um Tin Oxide), Indium Oxide with Tungsten Oxide, Tungsten Oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, indium gallium zinc oxide, silicon Indium tin oxide doped with nitrogen may also be used. Zinc oxide may also be used.

[0176] In addition, a plurality of conductive layers made of the above materials may be laminated. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining the above-mentioned material containing a metal element and a conductive material containing nitrogen is also available. The above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure may be formed by combining the conductive material containing nitrogen. Alternatively, the conductive material may have a laminated structure in which a conductive material containing oxygen is combined with the conductive material containing oxygen.

[0177] In addition, an oxide semiconductor is used for the semiconductor layer, and the above-mentioned material containing a metal element is used for the gate electrode. When a laminated structure combining a conductive material containing oxygen is used, By providing a conductive material containing oxygen on the semiconductor layer side, Therefore, oxygen released from the conductive material is easily supplied to the semiconductor layer.

[0178] The electrodes are made of highly conductive materials with high embedding properties, such as tungsten and polysilicon. In addition, a highly conductive material with high embedding properties and a titanium layer, a titanium nitride layer, A barrier layer (diffusion prevention layer) such as a tantalum nitride layer may be used in combination. is sometimes called a "contact plug."

[0179] In particular, it is preferable to use a conductive material that is difficult for impurities to permeate into the electrode in contact with the gate insulating layer. An example of a conductive material that is difficult for impurities to permeate is tantalum nitride.

[0180] The insulating layer is made of insulating material that is difficult for impurities to penetrate, and the electrodes are made of conductive material that is difficult for impurities to penetrate. By using such a material, the diffusion of impurities into the transistor can be further suppressed. This can further increase the reliability of the transistor. It can be further increased.

[0181] [Semiconductor Layer] The semiconductor layer may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like. The semiconductor materials may be, for example, silicon. Silicon, germanium, etc. can be used. Silicon germanium, silicon carbide, etc. Compound semiconductors such as silicon, gallium arsenide, oxide semiconductors, and nitride semiconductors, as well as organic semiconductors etc. can be used.

[0182] In addition, when using an organic semiconductor as the semiconductor layer, low molecular weight organic materials with aromatic rings or π electrons are used. Conjugated conductive polymers can be used. For example, rubrene, tetracene, penta Cene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene , polyparaphenylene vinylene, etc. can be used.

[0183] In addition, the semiconductor layers may be stacked. When the semiconductor layers are stacked, each layer may have a different crystal state. Alternatively, different semiconductor materials may be used.

[0184] In addition, the band gap of oxide semiconductors, a type of metal oxide, is 2 eV or more. By using an oxide semiconductor for the conductor layer, it is possible to realize a transistor with extremely low off-state current. Specifically, the voltage between the source and drain is 3.5 V and the device is at room temperature (typically 25°C). ) and the off-current per 1 μm of channel width is 1×10 -20 Less than A, 1×10 - 22 Less than A or 1×10 -24 A. That is, the on-off ratio In addition, a transistor using an oxide semiconductor for a semiconductor layer can be used. (OS transistor) has high dielectric strength between source and drain. Therefore, it has good reliability. In addition, a transistor having a large output voltage and a high withstand voltage can be provided. In addition, a highly reliable memory device can be provided. A storage device may be provided.

[0185] In the present specification and the like, the semiconductor layer in which the channel is formed is made of crystalline silicon. The transistor used is also called a "crystalline silicon transistor."

[0186] Crystalline silicon transistors tend to have higher mobility than OS transistors. Crystalline silicon transistors can achieve extremely low off-state current like OS transistors. Therefore, the semiconductor material used in the semiconductor layer should be appropriately selected according to the purpose and application. For example, depending on the purpose and application, it is necessary to select OS transistors and crystalline Si transistors. A transistor or the like may also be used in combination.

[0187] When an oxide semiconductor layer is used as the semiconductor layer, the oxide semiconductor layer is formed by a sputtering method. When the oxide semiconductor layer is formed by a sputtering method, This is preferable because the density of the oxide semiconductor layer can be increased. In this case, the sputtering gas is a rare gas (typically argon), oxygen, or a rare gas. A mixed gas of niobium and oxygen can be used. In addition, the sputtering gas must be highly purified. For example, oxygen gas and rare gases used as sputtering gases have a dew point of -60°C or lower. The gas used is preferably purified to a temperature of -100°C or lower. By forming the oxide semiconductor layer using ring gas, moisture and other substances can be taken into the oxide semiconductor layer. It can be prevented as much as possible.

[0188] In addition, in the case where the oxide semiconductor layer is formed by a sputtering method, It is preferable to remove as much moisture as possible from the deposition chamber. For example, using a cryopump or similar device. A suction-type vacuum pump was used to create a high vacuum (5×10 -7 Pa to 1×10 - 4 It is preferable to evacuate the gas to a pressure of about 10 Pa, especially when the sputtering device is in standby mode. The partial pressure of gas molecules equivalent to HO (gas molecules equivalent to m / z = 18) in the deposition chamber is 1×10 -4 Pa or less, preferably 5×10 -5 It is preferable to set the pressure to 0.1 Pa or less.

[0189] [Metal oxides] Oxide semiconductors, which are a type of metal oxide, often contain at least indium or zinc. It is preferable that the alloy contains indium and zinc. It is preferable that the material contains aluminum, gallium, yttrium, or tin. Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium The metal may contain one or more elements selected from the group consisting of ruthenium, cadmium, and the like.

[0190] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M are boron, silicon, titanium, iron, nickel, and germanium. , Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum, Tungsten, magnesium, etc. However, the element M can be a combination of multiple of the above elements. There are cases where it is okay to match them.

[0191] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met de). It may also be called tetrahydrofuran (tetrahydrofuran) oxynitride.

[0192] [Metal oxide composition] The following describes a CAC (Cl This paper explains the configuration of the 3G-OS (3G-Aligned Composite).

[0193] In this specification, CAAC (c-axis aligned crystal ), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Shows an example.

[0194] CAC-OS or CAC-metal oxide is a material that has the function of electrical conductivity. A part of the material has an insulating function, and the whole material has a semiconductor function. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a material, the function of conductivity is to allow electrons (or holes) to flow as carriers, The insulating function is the function of not allowing the electrons that act as carriers to flow. The function and the function work complementary to each other to provide a switching function (On / Off The function of providing a CAC-OS or CAC-metal oxide with a The functions of CAC-OS and CAC-metal oxide can be By separating them, the functions of both can be maximized.

[0195] In addition, CAC-OS or CAC-metal oxide is used in conductive areas and insulating areas. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0196] In addition, in the CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be present in the material:

[0197] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxi de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, the narrow gap is In the component with a narrow gap, carriers mainly flow. It acts complementarily to the component with a wide gap and acts in conjunction with the component with a narrow gap. Carriers also flow into the components with gaps. When C-metal oxide is used for the channel formation region of a transistor, The on-state current of the transistor is high, i.e., the on-current is large, and the field-effect transition is high. You can get mobility.

[0198] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a composite matrix.

[0199] [Metal oxide structures] Oxide semiconductors, a type of metal oxide, are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (c-axis aligned crystalline oxide semico inductor, polycrystalline oxide semiconductor, nc-OS (nanocrystalline A-like amorphous oxide semiconductor OS:amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

[0200] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is caused by the area where multiple nanocrystals are connected. In the region, between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement, Indicates the point where the direction is changing.

[0201] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may be non-regular hexagons. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In addition, in the CAAC-OS, clear grain boundaries (grain boundaries) are not observed even in the vicinity of the strain. It is difficult to confirm the presence of the lattice distortion. This is because the CAAC-OS is aligned in the ab-plane direction. In the case of the ferroelectric material, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0202] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as the (M, Zn) layer) are stacked. Indium and element M tend to have a layered structure. If the element M in the (M, Zn) layer is replaced with indium, then (In, M, Zn) Also, when the indium in the In layer is replaced with element M, (In,M ) layer.

[0203] CAAC-OS is a metal oxide with high crystallinity. On the other hand, CAAC-OS has no clear crystallinity. Since it is difficult to confirm grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides decreases due to the inclusion of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having the CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat resistant and highly reliable.

[0204] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The atomic arrangement has periodicity in the region below 1 nm. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0205] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has voids or low density areas. e-OS has a lower crystallinity than nc-OS and CAAC-OS.

[0206] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductors are amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc- The compound may have two or more of the above-mentioned OS and CAAC-OS.

[0207] [Transistors with metal oxide] Next, a case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0208] By using the above metal oxide for the channel formation region of a transistor, a high field effect It is possible to realize a highly reliable transistor. It is possible.

[0209] In addition, it is preferable to use a metal oxide having a low carrier density for the transistor. In order to reduce the carrier density of the oxide film, the impurity concentration in the metal oxide film is reduced. In the present specification and the like, the impurity concentration is low and the defect level density is low. A low density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides are Carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, more Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than that is fine. .

[0210] In addition, high-purity intrinsic or substantially high-purity intrinsic metal oxide films have a low density of defect states. Therefore, the trap level density may also be low.

[0211] In addition, the charges trapped in the trap levels of the metal oxide take a long time to disappear. Therefore, gold, which has a high density of trap states, A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. do.

[0212] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide In order to reduce the impurity concentration in the metal oxide, it is effective to reduce the It is also preferable to reduce the impurity concentration in the adjacent film. These include potassium metal, alkaline earth metals, iron, nickel, silicon, etc.

[0213] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0214] When metal oxides contain silicon or carbon, which are group 14 elements, the metal oxide This leads to the formation of defect levels in the metal oxide. The concentration of silicon and carbon near the interface with the metal oxide was measured using secondary ion mass spectrometry (SIMS) : Secondary Ion Mass Spectrometry Concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0215] In addition, when alkali metals or alkaline earth metals are included in the metal oxide, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using a metal oxide containing fluorine in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide is Specifically, it is preferable to reduce the amount of alkali metal in the metal oxide obtained by SIMS. The concentration of alkali metals or alkaline earth metals is 1×10 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 To the following:

[0216] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carrier density increases. As a result, the metal oxide containing nitrogen is used to form a channel. The transistor used in the region tends to be normally on. In the case of the nitride, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxide is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 a toms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0217] In addition, the hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, hydrogen-containing metal oxides can generate electrons that are The transistors used in the channel forming region tend to be normally-on. It is preferable that the hydrogen content in the metal oxide is reduced as much as possible. The hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, Preferably 1 x 10 19 atoms / cm 3 less than 5×10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0218] By using a metal oxide with a sufficiently reduced impurity concentration for the channel formation region of a transistor, This makes it possible to impart stable electrical characteristics.

[0219] <Film formation method> Insulating materials for forming insulating layers, conductive materials for forming electrodes, or semiconducting layers The semiconductor material for forming the semiconductor layer is prepared by sputtering, spin coating, or CVD (Chemical Vapor Deposition). ical vapor deposition) method (thermal CVD method, MOCVD (Meta l Organic Chemical Vapor Deposition) method, PE CVD (Plasma Enhanced CVD) method, High density plasma CVD (Hig h density plasma CVD) method, LPCVD (low pressur e CVD) method, APCVD (atmospheric pressure CVD) method etc.), ALD (Atomic Layer Deposition) method, or MBE (Molecular Beam Epitaxy) method or PLD (Pul sed Laser Deposition method, dip method, spray coating method, droplet ejection Printing methods (such as inkjet printing) and printing methods (such as screen printing and offset printing) are used. It can be formed by:

[0220] The plasma CVD method can produce high-quality films at relatively low temperatures. When a deposition method that does not use plasma, such as a thermal CVD method, is used, the deposition surface is damaged. For example, the wiring, electrodes, and elements (transistors, capacitors, etc.) contained in memory devices Some elements (such as quantum elements) may become charged up by receiving electric charge from the plasma. At this time, the accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the memory device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage may occur. Since no defects occur, the yield of the memory device can be increased. Since no damage occurs, a film with few defects can be obtained.

[0221] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0222] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the storage device may be improved.

[0223] When forming a film by the ALD method, gases that do not contain chlorine should be used as the material gas. is preferred.

[0224] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0225] (Embodiment 4) In this embodiment mode, a transistor that can be used for the semiconductor device shown in the above embodiment mode and the like is An example of the structure of the resistor will now be described.

[0226] <Transistor structure example 1> An example of the structure of a transistor 500A will be described with reference to FIGS. FIG. 13A is a top view of a transistor 500A. FIG. 13B is a top view of the transistor 500A shown in FIG. FIG 13(C) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG 13(A). 13A is a cross-sectional view of a portion indicated by a line W1-W2. For convenience, some elements are omitted in the figure.

[0227] 13A, 13B, and 13C, a transistor 500A and a semiconductor device that functions as an interlayer film are shown. Insulating layer 511, insulating layer 512, insulating layer 514, insulating layer 516, insulating layer 580, insulating layer 5 82, and insulating layer 584. , the conductive layer 546 (conductive layer 546a and conductive layer 546 5B) and a conductive layer 503 functioning as wiring.

[0228] The transistor 500A includes a conductive layer 560 (conductive layer 560) that functions as a first gate electrode. a, and conductive layer 560b), and conductive layer 505 (conductive layer 505a, and conductive layer 505b) and an insulating layer 550 which serves as a first gate insulating layer. and an insulating layer 521, an insulating layer 522, and an insulating layer 52 4, and an oxide 530 having a region in which a channel is to be formed (oxide 530a, oxide 530 b, and oxide 530c), and a conductive layer 54 acting as either a source or a drain. 0a, a conductive layer 540b serving as the other of the source and drain, and an insulating layer 574. has.

[0229] In addition, in the transistor 500A shown in FIG. 13, the oxide 530c, the insulating layer 550, and The conductive layer 560 is disposed in an opening provided in the insulating layer 580 via the insulating layer 574. In addition, the oxide 530c, the insulating layer 550, and the conductive layer 560 are formed on the conductive layer 540a and and conductive layer 540b.

[0230] The insulating layers 511 and 512 function as interlayer films.

[0231] The interlayer film may be silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. , hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT ), strontium titanate (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulators such as the above can be used in a single layer or in a laminated form. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added. Alternatively, these insulators may be nitrided. Alternatively, silicon oxide or silicon nitride may be laminated.

[0232] For example, the insulating layer 511 prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. It is preferable that the insulating layer functions as a barrier film to prevent the inclusion of the metal oxide in the insulating layer. 511 has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use an insulating material that is impermeable to the above-mentioned impurities. (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use an insulating material that is difficult for oxygen to permeate. Aluminum oxide, silicon nitride, or the like may be used as the material 11. Impurities such as water diffuse from the substrate side to the transistor 500A side through the insulating layer 511. can be suppressed.

[0233] For example, it is preferable that the insulating layer 512 has a lower dielectric constant than the insulating layer 511. By using a thin material for the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0234] The conductive layer 503 is formed so as to be embedded in the insulating layer 512. The height of the upper surface of the conductive layer 503 can be made to be approximately the same as the height of the upper surface of the insulating layer 512. However, the present invention is not limited to this. The conductive layer 503 may have a multilayer structure of two or more layers. It is preferable to use a conductive material having high conductivity, which is mainly composed of copper or aluminum. stomach.

[0235] In the transistor 500A, the conductive layer 560 is a first gate (also called a top gate). In the transistor 500A, the conductive layer 560 may function as an insulating The conductive layer 56 is formed in a self-aligned manner to fill the opening formed in the layer 580, etc. By forming the conductive layer 540a and the conductive layer 540b in this manner, The conductive layer 560 can be reliably placed without alignment.

[0236] In addition, the conductive layer 505 functions as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductive layer 505 is linked to the potential applied to the conductive layer 560. By changing the threshold voltage of the transistor 500A independently, the threshold voltage of the transistor 500A can be controlled. In particular, applying a negative potential to the conductive layer 505 can turn on the transistor 500A. It is therefore possible to increase the threshold voltage of the MOSFET to above 0 V and reduce the off-state current. Applying a negative potential to the conductive layer 505 is more effective than applying no potential to the conductive layer 560. This can reduce the drain current when the applied potential is 0V.

[0237] In addition, for example, the conductive layer 505 and the conductive layer 560 are provided so as to overlap each other. When a potential is applied to the conductive layer 505, the electric field generated by the conductive layer 560 and the conductive layer 5 5 and the electric field generated by the oxide 530 are connected to each other, and the channel forming region is formed in the oxide 530. It is possible.

[0238] That is, the electric field of the conductive layer 560 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductive layer 505, which functions as an electrode, electrically connects the channel forming region. In this specification, the electric potential of the first gate electrode and the electric potential of the second gate electrode The structure of a transistor in which the channel formation region is electrically surrounded by a field is called a surrou This is called the ned channel (S-channel) structure.

[0239] The insulating layer 514 and the insulating layer 516 are interlayer insulating layers similar to the insulating layer 511 and the insulating layer 512. For example, the insulating layer 514 functions as a barrier against impurities such as water or hydrogen from the substrate side. It is preferable that the film functions as a barrier film to prevent contamination of the transistor 500A. With this configuration, impurities such as hydrogen and water can pass through the insulating layer 514 from the substrate side to the transistor 5 In addition, for example, the insulating layer 516 can be formed by It is preferable that the dielectric constant of the interlayer is lower than that of 514. By using a material with a low dielectric constant as the interlayer, The parasitic capacitance occurring between lines can be reduced.

[0240] The conductive layer 505, which functions as a second gate, is disposed in the opening of the insulating layer 514 and the insulating layer 516. A conductive layer 505a is formed in contact with the inner wall, and a conductive layer 505b is further formed on the inside. Here, the height of the upper surfaces of the conductive layers 505a and 505b and the upper surface of the insulating layer 516 are In the transistor 500A, the conductive layer 505a and the conductive layer Although a configuration in which 505b is stacked is shown, the present invention is not limited to this. For example, the conductive layer 505 may be provided as a single layer or a stacked structure of three or more layers. stomach.

[0241] Here, the conductive layer 505a prevents the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has a function of suppressing the impurities (i.e., the impurities are unlikely to permeate). Or, the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material having the above-mentioned oxygen permeability. In the specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0242] For example, the conductive layer 505a has a function of suppressing oxygen diffusion, so that the conductive layer 505b This can prevent the conductivity from decreasing due to oxidation.

[0243] When the conductive layer 505 also functions as a wiring, the conductive layer 505b is made of tungsten, copper, Alternatively, it is preferable to use a highly conductive material containing aluminum as a main component. In that case, the conductive layer 503 is not necessarily provided. Although shown in the figure, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. It may also be a laminate.

[0244] The insulating layer 521, the insulating layer 522, and the insulating layer 524 function as a second gate insulating layer. has.

[0245] In addition, the insulating layer 522 preferably has a barrier property. This prevents impurities such as hydrogen from entering the transistor 500A from the periphery of the transistor 500A. It functions as a layer that prevents contamination.

[0246] The insulating layer 522 may be, for example, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide. Hafnium-containing oxides (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba Insulators including so-called high-k materials such as Sr, TiO3 (BST) and As transistors become smaller and more highly integrated, Thinning of the gate insulating layer may cause problems such as leakage current. By using a high-k material as an insulator that functions as a gate insulator, the thickness of the transistor can be increased while maintaining the physical thickness. This makes it possible to reduce the gate potential during transistor operation.

[0247] For example, the insulating layer 521 is preferably thermally stable. Silicon oxide nitride and silicon oxynitride are preferred because they are thermally stable. By combining the insulator with silicon oxide or silicon oxynitride, Moreover, insulating layer 521 having a laminated structure with a high relative dielectric constant can be obtained.

[0248] Although FIG. 13 shows a three-layer laminated structure as the second gate insulating layer, a single layer or The laminated structure may be two or more layers. In that case, the laminated structure is not limited to the same material. Alternatively, it may have a laminated structure made of different materials.

[0249] The oxide 530 having a region that functions as a channel formation region is made up of an oxide 530a and an oxide The oxide 530b is on the oxide 530a, and the oxide 530c is on the oxide 530b. By having the oxide 530a under the oxide 530b, the The diffusion of impurities from the structure to the oxide 530b can be suppressed. By having oxide 530c on 530b, the structure formed above oxide 530c The diffusion of impurities from the structure to the oxide 530b can be suppressed. For this purpose, an oxide semiconductor, which is one of the metal oxides described in the above embodiment, can be used. .

[0250] In a transistor in which an oxide semiconductor is used as an oxide for forming a channel, Therefore, the leakage current (off-state current) is extremely small. In addition, since the oxide semiconductor can be formed by a sputtering method or the like, This makes it easier to realize an integrated semiconductor device.

[0251] For example, the oxide 530 may be an In-M-Zn oxide (wherein the element M is gallium, yttrium, Aluminum, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tantalum The metal oxides are selected from one or more of the following: tin, tin oxide, magnesium oxide, etc. In particular, the element M may be gallium, yttrium, or tin. The semiconductor layer 530 is made of In-M oxide, In-Zn oxide, or M-Zn oxide. It's fine.

[0252] The oxide 530c is formed in the opening in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, the insulating layer 580 is preferably provided. The diffusion of impurities into the oxide 530 can be suppressed.

[0253] One of the conductive layers 540 functions as a source electrode, and the other functions as a drain electrode.

[0254] The conductive layer 540a and the conductive layer 540b are made of aluminum, titanium, chromium, nickel, copper, or the like. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten. Metals or alloys containing metals as the main component can be used. In particular, tantalum nitride, etc. Metal nitride films have barrier properties against hydrogen and oxygen, and also have high oxidation resistance. preferable.

[0255] Although a single-layer structure is shown in FIG. 13, a laminated structure of two or more layers may be used. For example, a nitride It is preferable to stack a tantalum film and a tungsten film. It is also preferable to stack a titanium film and an aluminum film. Also, a two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium film, etc. A two-layer structure in which a copper film is laminated on a sodium-aluminum alloy film, and a copper film is laminated on a titanium film A two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0256] In addition, a titanium film or a titanium nitride film and an aluminum film over the titanium film or the titanium nitride film are A titanium film or a copper film is laminated, and a titanium film or a titanium nitride film is further formed on the aluminum film or a copper film. Three-layer structure, a molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the tantalum film, and a molybdenum film or The molybdenum nitride film is a three-layer structure. A transparent conductive material containing zinc oxide may also be used.

[0257] A barrier layer may be provided on the conductive layer 540. The barrier layer has a property of being resistant to oxygen or hydrogen. It is preferable to use a material having a barrier property as the insulating layer 574. During the deposition, the conductive layer 540 can be prevented from being oxidized.

[0258] The barrier layer can be made of, for example, a metal oxide. In particular, aluminum oxide, oxide Uses insulating films with barrier properties against oxygen and hydrogen, such as hafnium oxide and gallium oxide. It is also preferable to use silicon nitride formed by a CVD method.

[0259] The inclusion of the barrier layer can broaden the range of material options for the conductive layer 540. For example, The conductive layer 540 is made of a material having low oxidation resistance but high conductivity, such as tungsten or aluminum. In addition, for example, a conductive material that is easy to form a film or process can be used. It is possible.

[0260] The insulating layer 550 functions as a first gate insulating layer. In the opening, an oxide layer 530c and an insulating layer 574 are provided. preferable.

[0261] As transistors become smaller and more highly integrated, the gate insulating layer becomes thinner, causing leakage currents to increase. In that case, the insulating layer 550 may become a second gate insulating layer. Similarly, a laminated structure may be used. The insulator functioning as the gate insulating layer is a high-k material. By using a laminated structure of a material that is thermally stable and a material that is not thermally stable, the thickness of the material is maintained while the It is possible to reduce the gate potential during transistor operation. In addition, it is thermally stable and has a high relative dielectric constant. It may be a laminated structure.

[0262] The conductive layer 560 functioning as the first gate electrode includes a conductive layer 560a and a conductive layer 560b. The conductive layer 560a is a conductive layer 560b on the conductive layer 505a. The conductive material has the function of suppressing the diffusion of impurities such as hydrogen molecules, water molecules, and copper atoms. Alternatively, oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, etc.) It is preferable to use a conductive material that has a function of suppressing the diffusion of the metal.

[0263] Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, the material selection of the conductive layer 560b is In other words, the conductive layer 560a can improve the selectivity. Therefore, the oxidation of the electrode is suppressed, and the decrease in electrical conductivity can be prevented.

[0264] Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and tantalum nitride. It is preferable to use ruthenium, ruthenium oxide, or the like. As a, an oxide semiconductor which can be used as the oxide 530 can be used. In this case, the conductive layer 560b is formed by a sputtering method, so that the electric It is possible to lower the resistance and make it a conductor. This is called OC (Oxide Conductor). The tor electrode can be called a

[0265] The conductive layer 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductive layer 560 functions as a wiring, it is preferable to use a conductive material having high conductivity. It is preferable to use a conductor, for example a material mainly composed of tungsten, copper, or aluminum. The conductive layer 560b may have a layered structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0266] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 500A. The present invention provides an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, other materials such as magnesium oxide, gallium oxide, germanium oxide, and oxide yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide Any metal oxide, silicon oxide nitride or silicon nitride may be used.

[0267] By providing the insulating layer 574, impurities such as water and hydrogen contained in the insulating layer 580 are oxidized. The oxide 530b is prevented from diffusing through the insulating layer 550. In addition, the conductive layer 560 can be prevented from being oxidized due to excess oxygen contained in the insulating layer 580. It is possible.

[0268] The insulating layers 580, 582, and 584 function as interlayer films.

[0269] The insulating layer 582, like the insulating layer 514, prevents impurities such as water or hydrogen from entering the transistor from the outside. It is preferable that the insulating film functions as a barrier insulating film that prevents the inclusion of the oxide in the transistor 500A.

[0270] In addition, the insulating layer 580 and the insulating layer 584 are, like the insulating layer 516, thicker than the insulating layer 582. By using a material with a low dielectric constant as the interlayer film, the This can reduce the parasitic capacitance.

[0271] The transistor 500A is also embedded in an insulating layer 580, an insulating layer 582, and an insulating layer 584. Electrical connections may be made to other structures through plugs or wiring, such as recessed conductive layer 546. stomach.

[0272] As the material of the conductive layer 546, similar to the conductive layer 505, a metal material, an alloy material, a metal Conductive materials such as nitride materials or metal oxide materials can be used in a single layer or in a laminated form. For example, tungsten and molybdenum, which have high melting points and are both heat resistant and conductive, can be used. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. It is preferable to use a low-resistance conductive material to reduce the wiring resistance. .

[0273] For example, the conductive layer 546 may be a conductive material having a barrier property against hydrogen and oxygen. By using a layered structure of tantalum nitride, which is an electric conductor, and tungsten, which has high electrical conductivity, The diffusion of impurities from the outside can be suppressed while maintaining the electrical conductivity of the wiring.

[0274] By using the above structure, a transistor including an oxide semiconductor with large on-state current can be provided. A semiconductor device having an oxide semiconductor with a low off-state current can be provided. It is possible to provide a semiconductor device having a transistor. As a result, it is possible to provide a semiconductor device having stable electrical characteristics and improved reliability. can.

[0275] <Transistor structure example 2> An example of the structure of the transistor 500B will be described with reference to FIGS. FIG. 14A is a top view of a transistor 500B. FIG. 14B is a top view of the transistor 500B shown in FIG. 14(C) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG. 14A is a cross-sectional view of a portion indicated by a line W1-W2. For convenience, some elements are omitted in the figure.

[0276] Transistor 500B is a modification of transistor 500A. To avoid this, differences from transistor 500A will be mainly described.

[0277] The transistor 500B includes a conductive layer 540 (conductive layer 540a and conductive layer 540b) and The oxide 530c, the insulating layer 550, and the conductive layer 560 overlap each other. By adopting this structure, a transistor with high on-state current can be provided. It is possible to provide a transistor with high

[0278] The conductive layer 560 functioning as the first gate electrode includes a conductive layer 560a and a conductive layer 560b. The conductive layer 560a is a conductive layer 560b on the conductive layer 505a. The conductive material has the function of suppressing the diffusion of impurities such as hydrogen molecules, water molecules, and copper atoms. Alternatively, oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, etc.) It is preferable to use a conductive material that has a function of suppressing the diffusion of the metal.

[0279] Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, the material selection of the conductive layer 560b is In other words, the conductive layer 560a can improve the selectivity. Therefore, the oxidation of the electrode is suppressed, and the decrease in electrical conductivity can be prevented.

[0280] In addition, the upper surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide layer 530c It is preferable to provide an insulating layer 574 so as to cover the surface. It is recommended to use an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Other examples include magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, etc. Metal oxides such as tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide Silicon oxide, silicon nitride, silicon oxide or silicon nitride can be used.

[0281] By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. By providing the insulating layer 574, impurities such as water and hydrogen contained in the insulating layer 580 can be prevented from Therefore, diffusion to the star 500B can be suppressed.

[0282] In addition, an insulating layer 576 (insulating layer 580) having a barrier property is provided between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, the insulating layer 576 can be provided. The oxygen in the edge layer 580 reacts with the conductive layer 546, and the conductive layer 546 is prevented from being oxidized. can be done.

[0283] In addition, by providing the insulating layer 576 having a barrier property, the conductor used for the plug or wiring For example, the conductive layer 546 may be provided with a material that absorbs oxygen. By using metal materials with high electrical conductivity, a semiconductor device with low power consumption can be provided. Specifically, tungsten and aluminum have low oxidation resistance, while A material having high electrical conductivity can be used. In addition, for example, a conductive material that is easy to form a film or process can be used. An electric body can be used.

[0284] <Transistor structure example 3> A structural example of a transistor 500C will be described with reference to FIGS. 15(A), 15(B), and 15(C). FIG. 15A is a top view of a transistor 500C. FIG. 15(A) is a cross-sectional view of the transistor 500C in the channel length direction, and is shown by the dashed line L1-L2 in FIG. 15C is a cross-sectional view of the transistor 500C in the channel width direction. 15(A) is a cross-sectional view of a portion indicated by a dashed line W1-W2 in FIG. In the top view of (A), some elements are omitted for clarity. 5, the transistor 500C shown in FIG. 13 has the same function as the transistor 500A shown in FIG. The structures having the same components are denoted by the same reference numerals, and the details are the same as those of the transistor 500A shown in FIG. The relevant descriptions may be taken into consideration.

[0285] Transistor 500C shown in FIG. 15 includes conductive layer 540a between oxide 530b. 47a is disposed, and conductive layer 547b is disposed between conductive layer 540b and oxide 530b. 13. Here, the conductive layer 540a ( The conductive layer 540b) is disposed on the upper surface of the conductive layer 547a (conductive layer 547b) and on the side of the conductive layer 560. The conductive layer 547 is provided in contact with the upper surface of the oxide 530b. The conductive layer 547 may be made of a conductive material that can be used for the conductive layer 540. It is preferable that the thickness of the conductive layer is at least as thick as that of the conductive layer 540 .

[0286] In addition, in the transistor 500C shown in FIG. 15, the distance between the conductive layer 540a and the conductive layer 540b is , the channel length direction of the openings formed in the insulating layer 580, the insulating layer 574, and the insulating layer 545. 13 in that the length of the transistor 500A shown in FIG.

[0287] The transistor 500C shown in FIG. 15 has the above-described structure. The electric field of the conductive layer 560 also contributes to the regions near the conductive layers 540a and 540b of FIG. This allows the effective channel length of the transistor 500C to be increased. This can shorten the length and improve the on-state current and frequency characteristics.

[0288] In addition, the conductive layer 547a (conductive layer 547b) overlaps with the conductive layer 546a (conductive layer 546b). With such a configuration, the conductive layer 546a (conductive layer In the etching to form an opening in which the conductive layer 54 is embedded, the conductive layer 54 is formed at the bottom of the opening. 7a (conductive layer 547b) is provided, so that oxide 530b is over-etched. This can prevent the following:

[0289] 15, the transistor 500C has an insulating layer 545 in contact with the insulating layer 574. The insulating layer 574 may be formed by removing impurities such as water or hydrogen, or by removing excess A barrier insulating layer 580 prevents oxygen from entering the transistor 500C from the insulating layer 580 side. It is preferable that the insulating layer 574 functions as a film. The insulating layer 574 may be made of, for example, aluminum nitride. titanium, aluminum titanium nitride, titanium nitride, silicon nitride or silicon oxide nitride Any nitride insulator may be used.

[0290] 15 is different from the transistor 500A shown in FIG. In this case, the conductive layer 505 may be formed in a single layer structure. 5, an insulating film that will become the insulating layer 516 is formed, and the upper part of the insulating film is placed on the upper surface of the conductive layer 505. The conductive layer 505 may be removed by a CMP method or the like until the flat surface of the conductive layer 505 is exposed. It is preferable to improve the flatness. For example, the average surface roughness (Ra) of the upper surface of the conductive layer 505 is 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. This improves the flatness of the insulating layer 524 formed on the conductive layer 505, and the oxide 5 This can improve the crystallinity of the oxide 530b and the oxide 530c.

[0291] The conductive layer 546a, the conductive layer 546b, the conductive layer 548a, and the conductive layer 548b form a capacitance element. The conductive layer 546a functions as a plug or wiring that connects to a transistor. The material of the layer 546b, the conductive layer 548a, and the conductive layer 548b may be a metal material, an alloy material, or the like. A conductive material such as a metal nitride material or a metal oxide material is used as a single layer or a laminate. High-melting-point materials such as tungsten and molybdenum that are both heat-resistant and conductive are used. It is preferable to use tungsten. Alternatively, aluminum It is preferable to form the conductive layer from a low-resistance conductive material such as copper. This allows the wiring resistance to be reduced.

[0292] <Transistor structure example 4> A structural example of a transistor 500D will be described with reference to FIGS. 16(A), (B), and (C). FIG. 16A is a top view of a transistor 500D. FIG. 16B is a top view of the transistor 500D. FIG. 16(C) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG. It is to be noted that in the top view of FIG. For clarity, some elements are omitted in the illustration.

[0293] Transistor 500D is a variation of the transistor described above. In order to prevent this, differences from the above transistor will be mainly described.

[0294] In FIG. 16A to FIG. 16C, the conductive layer 540 and the conductive layer 547 are not provided, and the exposed oxide is The oxide 530b has a region 531a and a region 531b on a part of its surface. One of the regions 531b functions as a source region, and the other functions as a drain region. In addition, an insulating layer 573 is provided between the oxide 530b and the insulating layer 574. As the insulating layer 574, a material that can be used for the insulating layer 574 can be used.

[0295] The region 531 (region 531a and region 531b) shown in FIG. The region 531 is a region where the above-mentioned elements are added to the semiconductor substrate 520. For example, a dummy gate is used for the region 531. It can be formed by:

[0296] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask to It is preferable to add an element that reduces the resistance of the oxide 530b. The element is added to the region not overlapping with the dummy gate, forming a region 531. The element is added by mass-separating the ionized source gas. ion implantation, which adds ionized source gas without mass separation; and ion doping, which adds ionized source gas without mass separation. method, plasma immersion ion implantation method, etc. can be used.

[0297] Representative elements that reduce the resistance of the oxide 530 include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. are used. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon. The concentration of the elements is measured by secondary ion mass spectrometry (SIMS). It is better to use standard ion mass spectrometry (MMS) or other methods. stomach.

[0298] In particular, boron and phosphorus are used in the manufacturing process of amorphous silicon or low-temperature polysilicon. This is preferable because existing equipment can be used. Existing facilities can be repurposed. Capital investment can be reduced.

[0299] Next, an insulating film that will become an insulating layer 573 is formed on the oxide 530b and the dummy gate. An insulating film to be the insulating layer 573 and an insulating film to be the insulating layer 574 may be formed. Layer 574 is stacked to form region 531, oxide 530c, and insulating layer 550. There may be an overlapping region.

[0300] Specifically, after forming an insulating film that will become the insulating layer 580 on the insulating film that will become the insulating layer 574, The insulating film that will become the edge layer 580 is CMP (Chemical Mechanical Polishing). By performing a dummy gate insulating film (580) etching process, a part of the insulating film that will become the insulating layer 580 is removed. When the dummy gate is subsequently removed, the insulating layer 57 in contact with the dummy gate is exposed. Therefore, the insulating layer 580 has an opening on its side. The layer 574 and the insulating layer 573 are exposed, and the bottom surface of the opening is provided with an oxide 530b. A part of the region 531 is exposed. Next, an oxide film that becomes oxide 530c is formed in the opening. After forming an insulating film that will become the insulating layer 550 and a conductive film that will become the conductive layer 560 in this order, The oxide film that becomes the oxide 530c and the insulating layer 55 are removed by CMP or the like until the insulating layer 580 is exposed. 16. By removing a part of the insulating film to be the conductive layer 560 and a part of the conductive film to be the conductive layer 560, A transistor can be formed by using the same.

[0301] Note that the insulating layer 573 and the insulating layer 574 are not essential components. Appropriate design may be required depending on the characteristics.

[0302] The transistor shown in FIG. 16 can be made from an existing device, and further includes conductive layer 54. Since the conductive layer 547 and the insulating layer 548 are not provided, costs can be reduced.

[0303] <Transistor structure example 5> An example of the structure of the transistor 500E will be described with reference to FIGS. FIG. 17A is a top view of a transistor 500E. FIG 17(C) is a cross-sectional view of the L1-L2 region indicated by the dashed line in FIG 17(A). 17(A) is a cross-sectional view of the portion W1-W2 shown by the line. For convenience, some elements are omitted in the figure.

[0304] Transistor 500E is a modified version of transistor 500A. To avoid this, differences from transistor 500A will be mainly described.

[0305] In the transistor 500A, a portion of the insulating layer 574 is formed in an opening in the insulating layer 580. The conductive layer 560 is provided so as to cover the side surface of the conductive layer 560. At 0E, portions of insulating layer 580 and insulating layer 574 have been removed to form openings.

[0306] In addition, an insulating layer 576 (insulating layer 580) having a barrier property is provided between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, the insulating layer 576 can be provided. The oxygen in the edge layer 580 reacts with the conductive layer 546, and the conductive layer 546 is prevented from being oxidized. can be done.

[0307] When an oxide semiconductor is used as the oxide 530, the atomic ratio of each metal atom is different. It is preferable that the oxide has a laminated structure. In the metal oxide, the atomic ratio of element M in the constituent elements is It is preferable that the atomic ratio of element M in the constituent elements of the oxide is larger than that of element M in the constituent elements of the oxide. In the metal oxide used in 530a, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In in the metal oxide used for b is larger than that of element M to In. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is is greater than the atomic ratio of In to element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c is preferably larger than the oxide 530a or the oxide 530b. Any metal oxide can be used.

[0308] The oxide 530a, the oxide 530b, and the oxide 530c preferably have crystallinity. It is preferable to use CAAC-OS, and particularly, CAAC-OS is preferable. The oxides used have few impurities and defects (oxygen vacancies, etc.), high crystallinity, and a dense structure. Therefore, the source electrode or the drain electrode draws oxygen from the oxide 530b. This can prevent the oxide 530b from being oxidized by heat treatment. Since the transistor 500E can reduce the pull-out of the It is stable with respect to temperature (so-called thermal budget).

[0309] One or both of the oxide 530a and the oxide 530c may be omitted. Alternatively, oxide 530 may be a single layer of oxide 530b. In the case of stacking the oxide 530a and oxide 530b, and the oxide 530c, The energy of the conduction band minimum of oxide 530c becomes higher than the energy of the conduction band minimum of oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably It is preferable that the electron affinity of the oxide 530b is smaller than the electron affinity of the oxide 530. It is preferable that c is a metal oxide that can be used for the oxide 530a. In the metal oxide used for the oxide 530c, the atomic ratio of element M among the constituent elements is The ratio of the number of atoms of element M in the constituent elements of the metal oxide used for the oxide 530b is larger than that of the element M in the constituent elements. In addition, in the metal oxide used for the oxide 530c, the element for In is preferably The atomic ratio of element M to In in the metal oxide used for oxide 530b is It is preferable that the atomic ratio is larger than that of the metal oxide used for the oxide 530b. The atomic ratio of In to the element M in the metal oxide used for the oxide 530c is It is preferable that the atomic ratio of In to M is larger than that of In.

[0310] Here, at the junctions of oxide 530a, oxide 530b, and oxide 530c, The energy level of the lower band edge changes gradually. The energy level of the conduction band minimum at the junction of 530b and oxide 530c is continuous. In order to achieve this, the oxide 5 At the interface between oxide 30a and oxide 530b, and at the interface between oxide 530b and oxide 530c, In this case, the defect level density of the mixed layer formed by the above process is preferably reduced.

[0311] Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c are oxides. By having a common element other than the element (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 5 30a and oxide 530c, In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used. The oxide 530c may have a laminated structure. For example, I A laminated structure of n-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide or In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide. In other words, a laminated structure of In-Ga-Zn oxide and a layer containing no In can be used. A stacked structure with an oxide that is not a barrier layer may be used as the oxide 530c.

[0312] Specifically, the oxide 530a is In:Ga:Zn=1:3:4 [atomic ratio], The oxide 530b may be a metal oxide having an atomic ratio of 1:1:0.5. In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] metal The oxide 530c may be In:Ga:Zn=1:3:4[ Atomic ratio], In:Ga:Zn=4:2:3 [Atomic ratio], Ga:Zn=2:1 [Atomic ratio] The metal oxide with Ga:Zn=2:5 [atomic ratio] or Ga:Zn=2:5 [atomic ratio] may be used. A specific example of the laminated structure of the object 530c is In:Ga:Zn=4:2:3 [prime A stacked structure with In:Ga:Zn=4:2 [atomic ratio] and Ga:Zn=2:1 [atomic ratio] :3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio] stacked structure, In:Ga:Zn = 4:2:3 [atomic ratio] and a layered structure with gallium oxide.

[0313] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500E has high In addition, the oxide 530c is formed in a laminated structure. In this structure, the defect state density at the interface between the oxide 530b and the oxide 530c is In addition to the effect of lowering the temperature, the constituent elements of the oxide 530c diffuse to the insulating layer 550 side. More specifically, the oxide 530c has a laminated structure, and the laminated In order to position an oxide that does not contain In at the top of the structure, In that can diffuse to the insulating layer 550 side is Since the insulating layer 550 functions as a gate insulating layer, it is possible to suppress the diffusion of In. If the oxide 530c is dispersed, the transistor characteristics will be deteriorated. This makes it possible to provide a highly reliable display device.

[0314] The oxide 530 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that will be the channel formation region of the oxide 530 has a band gap of 2e It is preferable to use a band of 5 V or more, preferably 2.5 eV or more. By using metal oxide with a wide gap, it is possible to reduce the off-state current of a transistor. By using such a transistor, a semiconductor device with low power consumption can be provided. .

[0315] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0316] (Embodiment 5) This embodiment mode will be described with reference to an electronic component and an electronic An example of the device is shown.

[0317] <Electronic components> First, an example of an electronic component incorporating the storage device 300 will be described with reference to FIGS. 18(A) and 18(B). Make a statement.

[0318] FIG. 18A shows an electronic component 700 and a substrate on which the electronic component 700 is mounted (a substrate 704 on which the electronic component 700 is mounted). The electronic component 700 shown in FIG. 18(A) is an IC chip, and has leads and The electronic component 700 is mounted on, for example, a printed circuit board 702. A number of such IC chips are combined and each is electrically connected on the printed circuit board 702. This completes the mounting board 704.

[0319] The electronic component 700 includes the memory device 300 shown in the above embodiment as a circuit unit. In FIG. 18A, the package of the electronic component 700 is a QFP (Quad Flat Pack). However, the form of the package is not limited to this.

[0320] 18B shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) MCM (Multi Chip Module) The electronic component 730 is an interposer on a package substrate 732 (printed circuit board). A semiconductor device 735 and a plurality of memory devices are provided on the interposer 731. A station 300 is provided.

[0321] In the electronic component 730, the storage device 300 is a high bandwidth memory (HBM). dth Memory). Integrated circuits (semiconductor devices) such as PUs, GPUs, and FPGAs can be used.

[0322] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be a silicon interposer, a resin interposer, or the like. A resin interposer or the like can be used.

[0323] The interposer 731 has a plurality of wirings and electrically connects a plurality of integrated circuits having different terminal pitches. The wiring has a function of effectively connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 to the package substrate 73. 2. The interposer is sometimes called a "rewiring substrate" or an "intermediate substrate." A through electrode is provided in the package substrate 732, and the through electrode is used to electrically connect the integrated circuit and the package substrate 732. In addition, in silicon interposers, TSV (Transistor Via) is used as a through electrode. Through Silicon Via can also be used.

[0324] It is preferable to use a silicon interposer as the interposer 731. Silicon Since there is no need to provide active elements in an interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring that is difficult to achieve with resin interposers.

[0325] In HBM, many wires must be connected to achieve a wide memory bandwidth. Therefore, the interposer that mounts HBM requires fine and high-density wiring. Therefore, the interposer for mounting HBM should be a silicon interposer. is preferred.

[0326] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to the difference in the expansion coefficient between the silicon interposer. The silicon interposer has a high surface flatness, so the integrated circuit and silicon interposer can be mounted on the silicon interposer without any problems. In particular, it is difficult to cause connection failure between interposers. In 2.5D packaging (2.5-dimensional assembly), silicon interposers are used to place It is preferable to use:

[0327] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the memory device 300 and the semiconductor device 735 It is preferable to make the heights of the electrodes uniform.

[0328] In order to mount the electronic component 730 on another substrate, electrodes 733 are provided on the bottom of the package substrate 732. 18B shows an example in which the electrode 733 is formed using a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, a BGA (Ba In addition, the electrodes 733 can be formed with conductive pins. The bottom of the package substrate 732 may be provided with conductive pins arranged in a matrix. This allows for PGA (Pin Grid Array) implementation.

[0329] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ay), LGA (Land Grid Array), QFP (Quad Flat P ackage), QFJ(Quad Flat J-leaded package), Or QFN (Quad Flat Non-leaded package) A mounting method can be used.

[0330] <Electronic equipment> Next, an example of an electronic device including the above electronic components will be described with reference to FIG.

[0331] The robot 7100 is equipped with a light sensor, a microphone, a camera, a speaker, a display, Various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The electronic component 730 includes a processor, etc. For example, the electronic component 700 may have a function of controlling the peripheral devices. The memory has a function of storing the data.

[0332] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has a function of emitting audio signals such as voice and warning sounds. The 7100 analyzes the audio signal input through the microphone and outputs the necessary audio. The robot 7100 can emit audio signals from the speaker. It is possible to communicate with the user using a microphone and speaker. be.

[0333] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has a function of moving using a moving mechanism. It is possible to capture images and analyze them to detect the presence or absence of obstacles when moving around.

[0334] The flying object 7120 has a propeller, a camera, a battery, etc., and is an autonomous flying object. The electronic component 730 has a function of controlling these peripheral devices.

[0335] For example, image data captured by a camera is stored in the electronic component 700. It can analyze image data and detect the presence or absence of obstacles when moving. The remaining battery charge is estimated from the change in the storage capacity of the battery by the electronic component 730. can be done.

[0336] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. The robot has a brush, a control button, various sensors, etc. The 7300 is equipped with tires, a suction port, etc. The cleaning robot 7300 is self-propelled. It can detect dust and suck it up through a suction port provided on the bottom surface.

[0337] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. It can determine whether there is an obstacle. Also, by analyzing images, it can detect wires and other objects that are entangled in the brush. If such an object is detected, the brush can stop rotating.

[0338] The automobile 7160 has an engine, tires, brakes, a steering system, a camera, etc. For example, the electronic components 730 may include navigation information, speed, engine status, gear selection status, To optimize the driving condition of the car 7160 based on data such as the frequency of brake use, For example, image data captured by a camera is stored in the electronic component 700.

[0339] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (a television receiver device), smartphone 7210, PC (personal computer) 7220, 7230 , can be incorporated into game console 7240, game console 7260, etc.

[0340] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic components 730 can perform functions such as noise reduction, resolution up-conversion, etc. Which image processing is performed?

[0341] The smartphone 7210 is an example of a portable information terminal. The electronic component 730 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by

[0342] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The keyboard 7232 and the monitor device 7233 are connected to the 7230 by wireless or wired connection. The game machine 7240 is an example of a portable game machine. The game machine 7260 is a stationary game machine. The game machine 7260 is an example of a stationary game machine. 262 is connected to the controller 7262. Component 730 may also be included.

[0343] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0344] (Embodiment 6) In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is applicable to, for example, various electronic devices (e.g., terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment may be used in a memory card (e.g., Various removable media such as cards, USB memory, and SSDs (Solid State Drives) FIG. 20 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. and used in various storage devices and removable memory.

[0345] FIG. 20A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, The cap 1102, the USB connector 1103, and the board 1104 are included. For example, the substrate 1104 includes a memory chip 1105. , and a controller chip 1106 are attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 05 or the like.

[0346] FIG. 20(B) is a schematic diagram of the external appearance of an SD card, and FIG. 20(C) shows the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate. The substrate 1113 is housed in a housing 1111. For example, the substrate 111 3 is equipped with a memory chip 1114 and a controller chip 1115. By providing a memory chip 1114 on the back side of the board 1113, the capacity of the SD card 1110 In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the memory to be wirelessly transmitted between the host device and the SD card 1110. This allows data to be read from and written to the memory chip 1114 on the substrate 1113. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0347] FIG. 20(D) is a schematic diagram of the external appearance of an SSD, and FIG. 20(E) is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 may include a memory The chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing the memory 4, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0348] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0349] In this specification, unless otherwise specified, the on-state current is the current that flows when a transistor is in the on-state. The drain current when the device is in the on state (sometimes abbreviated as on) is Without this, an n-channel transistor would have a gate-to-source voltage (V G ) is the threshold Value Voltage (V th ) above, for p-channel transistors, V G V th The following state For example, the on-current of an n-channel transistor is V G V th When the above The drain current of a transistor is the voltage between the drain and source. (V D ) may be dependent on

[0350] In this specification, unless otherwise specified, the off-state current refers to the current flowing when a transistor is in an off state. The drain current when the device is in the off state (sometimes abbreviated as "off") is In this case, for an n-channel transistor, V G V th lower than that of p-channel transistors. In Jista, V G V th For example, an n-channel transistor The off-state current of V G V th The drain current of a transistor is lower than the The current is V G Therefore, the off-state current of the transistor may depend on -21 A The off-state current of the transistor is less than 10 -21 V less than A G If a value of exists, It is sometimes said that...

[0351] The off-state current of the transistor is V D In this specification, off Currents are V unless otherwise stated. D The absolute value of is 0.1V, 0.8V, 1V, 1.2V, 1 .8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V Alternatively, it may represent a current flowing through a semiconductor device that includes the transistor. Used V D In some cases, it represents the off-state current at

[0352] In the present specification, when it is explicitly stated that X and Y are connected, X In the present invention, the case where X and Y are electrically connected and the case where X and Y are directly connected are It is assumed that such disclosure is made in the detailed instructions, etc.

[0353] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0354] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When X and Y are connected without any intermediate devices (electrodes, display elements, light-emitting elements, loads, etc.) It is.

[0355] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch can be in a conductive state (ON state) or a non-conductive state (OFF state). ) and has the function of controlling whether or not current flows. It has the function of selecting and switching the path through which current flows. X and Y are electrically connected. When X and Y are connected to each other, this includes the case where X and Y are directly connected to each other. EXAMPLES

[0356] In this example, the operating frequency was estimated for the DOSRAM shown in the second embodiment. OSRAM is a transistor with a channel length (L) of 60 nm and a channel width (W) of 60 nm. A configuration having a capacitor and a storage capacitance of 3.5 fF was assumed.

[0357] "Allowable voltage fluctuation," one of the specifications required for DOSRAM, is the capacity of the DOSRAM. This is the allowable amount of change in the voltage applied to the element after data is written. The "data retention time" of M is the time when the voltage fluctuation applied to the capacitance element of the DOSRAM changes. This can be said to be the time required for the voltage to reach the permissible fluctuation voltage. In this embodiment, the "permissible fluctuation voltage" is set to 0. 2V, and the "data retention time" is the voltage applied to the capacitance element (retention capacity 3.5fF) The time required for the voltage to drop by 0.2 V from the state after writing is set as the time. If the data retention time of OSRAM is one hour, the voltage applied to the capacitance element of the DOSRAM is This means that it takes 1 hour for the voltage to drop by 0.2V after data is written. .

[0358] The data retention time of DOSRAM is determined by the cutoff current of the transistors in the DOSRAM. As mentioned above, the cutoff current (Icut) of a transistor is Transistor V G I at 0 V D For example, the data retention characteristics of DOSRAM are If the Icut value depends only on the size of the transistor in the DOSRAM, The data retention time of RAM is proportional to the size of the Icut of the transistor in DOSRAM. Proportional.

[0359] When the Icut of the transistors in the DOSRAM is known, the data of the DOSRAM The retention time is the amount of charge lost from the capacitance element during data retention (the retention capacitance of the capacitance element (3.5 fF) and the voltage drop across the capacitance element (0.2V), which is 0.7fC It can be calculated by dividing by cut. By setting the time and dividing the charge amount 0.7fC by the retention time, the DOSRAM Estimate the value of Icut required for a transistor having If the target retention time is 1 hour, the required Icut for the transistor is approximately 200zA(200×10 -21 A). Icut0 shown in Figure 5 is 200zA. By adjusting the back gate voltage to achieve a high operating frequency over a wide temperature range, In this embodiment, the back gate voltage and operation of the DOSRAM are The relationship to frequency was evaluated.

[0360] In estimating the operating frequency of the DOSRAM, a transistor 500A shown in FIG. In this example, the parameters required for the estimation were extracted from the electrical characteristics. Assuming that the transistor M11 shown in (A) is the transistor 500A, The AM operating frequency was estimated.

[0361] The size of the prototype transistor 500A is L (channel length) 0.38 μm, W (channel The width of the channel was set to 0.23 μm. Three types of samples were prepared: Sample A, Sample B, and Sample C. .

[0362] In the prototype transistor 500A, the oxide 530a is an In-GaAs layer having a thickness of 5 nm. The oxide 530a is made of In:Ga:Zn oxide having an atomic ratio of 1:3: The deposition was performed by DC sputtering using a target of In-Ga-Zn oxide No. 4. The sputtering method was performed at a substrate temperature of 200° C. using a mixed gas of argon and oxygen.

[0363] In the prototype transistor 500A, the oxide 530b is an In-GaAs layer having a thickness of 20 nm. The oxide 530b is made of a-Zn oxide. The atomic ratio of the oxide 530b is In:Ga:Zn=4:2. The deposition was performed by DC sputtering using an In-Ga-Zn oxide target of 4.1. The sputtering method was performed with a substrate temperature of 200°C and a mixed gas of argon and oxygen. .

[0364] In the prototype transistor 500A, the oxide 530c is an In-GaAs layer having a thickness of 5 nm. The oxide 530c is made of In:Ga:Zn oxide with an atomic ratio of In:Ga:Zn=4:2: The deposition was performed by DC sputtering using the In-Ga-Zn oxide target of 4.1. The sputtering method was performed at a substrate temperature of 130° C. using a mixed gas of argon and oxygen.

[0365] After the fabrication of the transistor 500A, the samples A and B were heated at 400° C. for 4 hours in a nitrogen gas atmosphere. Sample C was heat-treated at 400°C for 8 hours in a nitrogen gas atmosphere. .

[0366] Next, in Sample A, Sample B, and Sample C, the I D -V G Take a measurement I D -V G The measurement is the drain voltage V of the transistor. D +1.08V, source voltage Pressure V S to 0V, and the gate voltage V G was swept from -1.0V to +3.3V. Back gate voltage V BG The measurement was performed at four levels: -2V, -3V, -4V, and -5V. The temperature was set at three levels: -40℃, 27℃, and 85℃. The 5-inch square substrate on which the resistor was formed was fixed on a thermo chuck set to each of the above temperatures. In the state, the I D -V G The measurements were also carried out. BG Measurements were performed on three elements for each measurement temperature.

[0367] Obtained I D -V G From the curve, the transistor shift voltage (Vsh) and subthreshold The shift voltage (Vsh) is the voltage swing of the transistor. Ta's I D -V G The tangent at the point on the curve where the slope is maximum is I D = V crosses the 1pA line G It is defined as:

[0368] The transistor 500A is a transistor having a structure similar to that described in the <Method for manufacturing a semiconductor device> of Embodiment 1. A metal oxide is used for the channel formation region. For example, compared to a transistor that uses Si for the channel formation region, Therefore, the leakage current is extremely small in the channel formation region. It may be difficult to detect Icut by actual measurement for transistors with Since it was difficult to measure Icut even with the 500A converter, the above-mentioned I D -V G From the curve From the obtained Vsh and Svalue, Icut is estimated by extrapolation using equation (1). As shown in equation (1), the off-state current of the transistor is V G = Until 0V is reached , According to Svalue I D is assumed to be monotonically decreasing.

[0369]

number

[0370] Here, we will explain how to estimate the DOSRAM operating frequency. The number is the inverse number of data write cycles for DOSRAM. The write cycle is determined by the charging time of the capacitance element of the DOSRAM. In this embodiment, the data write cycle of the DOSRAM ( The time equivalent to 40% of the reciprocal of the operating frequency (the reciprocal of the operating frequency) is used to charge the capacitance element of the DOSRAM. The setting was made to be between 0 and 100 seconds.

[0371] The operating frequency of DOSRAM depends on the charging time of the capacitance element of DOSRAM. Therefore, when estimating the operating frequency of DOSRAM, the first thing to consider is the capacitance of the DOSRAM. In this embodiment, the charge duration of the DOSRAM is known in advance. The state in which a potential of 0.55 V or more is applied to a capacitance element (3.5 fF) is called a "charged" state. Therefore, in this embodiment, the data write operation of the DOSRAM is The time from when the DOS is started until the potential applied to the capacitance element reaches 0.55V is This corresponds to the charging time of the capacitance element of the RAM.

[0372] The charging time of the capacitance element of DOSRAM is The I of the transistor in DOSRAM D Therefore, in this embodiment, D It is assumed that the transistors in the DOSRAM will be affected when writing data to the OSRAM. The potential (see FIG. 21A) of the transistor according to one embodiment of the present invention (L / W=0.3 4 / 0.22μm) to reproduce the DOSRAM data write operation. At this time, the I D FIG. 21(A) shows a capacitance element Cs with a transistor. It is assumed that data is written through the transistor Tr1. D is the drain and G is the gate. The potential of the source of the transistor Tr1 (applied to the capacitance element Cs) is The voltage applied to the S By turning on the transistor Tr1, the current I D Flow Specifically, the gate voltage V G to +2.97 V, drain voltage V D to +1.08V, and source voltage Vs from 0V to +0.55V By sweeping the I D Measurements were performed. Backgate voltage V BG is -2V, - The measurements were performed at four levels: 3V, -4V, and -5V. The measurements were performed at three temperatures: -40°C, 27°C, and 85°C. I went in semi-final.

[0373] The I obtained from a 500A transistor (L / W=0.34 / 0.22μm) D Value of The size of the transistor (L / W=60 / 60nm) assumed for DOSRAM is was corrected with.

[0374] DOSRAM starts charging and V S is the write decision voltage V CS When it reaches this level, charging is complete. This time is called charging time t W (See FIG. 21(B)). The charge stored in the capacitance element of the storage capacitance Cs [F] is Q [C], and the charging time is t W [sec] The potential applied to the capacitance element by charging is Vcs (=VS )[V], DOSRAM's Let the drain current of the transistor be I D If [A], the following formula ( The relationship 2) holds.

[0375]

number

[0376] By modifying equation (2), the charging time t W The following formula ( 3) (see FIG. 21(C)).

[0377]

number

[0378] In this embodiment, Cs in formula (3) is 3.5 fF, Vcs is +0.55 V, and the above-mentioned I D -V S The measured I D Substituting the above, the charging time of the capacitance element of the DOSRAM is t W was calculated. .

[0379] DOSRAM operating frequency f and charging time t w The relationship can be expressed by equation (4).

[0380]

number

[0381] In equation (4), A is a coefficient. In DOSRAM, the write time is Since the time required for loading is estimated to be 40%, in this embodiment, coefficient A is set to 0.4. The frequency f was calculated.

[0382] In sample A, the operating frequency of the DOSRAM at a power supply voltage of 2.5 V is shown in Fig. 22(A), 22(B) and 23. FIG. 22(A) is at −40° C., FIG. 22(B) is at 27° C., and FIG. are the results estimated at 85°C. Figures 22(A), 22(B) and 23 show, respectively, Backgate voltage V BG are estimated at -2.5V, -3V, -4V, and -5.5V respectively. In Fig. 22(A), Fig. 22(B) and Fig. 23, the horizontal axis indicates the D The vertical axis shows the data retention time of the OSRAM, and the vertical axis shows the operating frequency of the DOSRAM. As shown in FIG. 22(B) and FIG. 23, the back gate voltage V BG The higher the We confirmed that the operating frequency tends to increase. In addition, at a power supply voltage of 2.5V, the operating frequency It was confirmed that the expected speed is over 100MHz and the data retention time is over 1 hour. Using the semiconductor device 100, the back gate voltage V BG By correcting the temperature, it can be used in a wide range of temperatures. It was confirmed that the device could operate at a high operating frequency.

[0383] In sample A, the operating frequency of the DOSRAM at a power supply voltage of 3.3 V is shown in Fig. 24(A), 24(B) and 25. Fig. 24(A) is at -40°C, Fig. 24(B) is at 27°C, and Fig. 25 are the results estimated at 85°C. Figures 24(A), 24(B) and 25 show, respectively, Backgate voltage V BG are estimated at -2.5V, -3V, -4V, and -5.5V respectively. In Fig. 24(A), Fig. 24(B) and Fig. 25, the horizontal axis indicates the D The vertical axis shows the data retention time of the OSRAM, and the vertical axis shows the operating frequency of the DOSRAM. As shown in FIG. 24(B) and FIG. 25, the back gate voltage V BGThe higher the We were able to confirm that the operating frequency tends to increase. In addition, at a power supply voltage of 3.3 V, the operating frequency It was confirmed that the expected speed is 150MHz or higher and the data retention time is more than one hour. Using the semiconductor device 100, the back gate voltage V BG By correcting the temperature, it can be used in a wide range of temperatures. It was confirmed that the device could operate at a high operating frequency.

[0384] For comparison, the back gate voltage V BG The data without adjustment is shown below. For sample A, The power supply voltage is 3.3V and the back gate voltage is V BG DOSRAM when -5.5V The operating frequency is shown in Fig. 26. In Fig. 26, the horizontal axis indicates the data retention time of DOSRAM. The vertical axis indicates the operating frequency of the DOSRAM. The lower the temperature, the lower the operating frequency. We were able to confirm this.

[0385] In sample B, the operating frequency of the DOSRAM at a power supply voltage of 2.5 V is shown in Fig. 27(A) and Fig. 27(B) and 28. Fig. 27(A) is at -40°C, Fig. 27(B) is at 27°C, and Fig. 28 are the results estimated at 85°C. Figures 27(A), 27(B) and 28 show, respectively, Backgate voltage V BG -1.5V, -2V, -2.5V, -3V, -4V, -4.8 The operating frequencies estimated for each V are shown in Figs. 27(A), 27(B) and 2 In FIG. 8, the horizontal axis indicates the data retention time of the DOSRAM, and the vertical axis indicates the operating frequency of the DOSRAM. As with sample A, sample B also showed a wide temperature range at a power supply voltage of 2.5 V. The operating frequency is expected to be 100 MHz or more, and the data retention time is expected to be 1 hour or more. We were able to confirm this.

[0386] In sample B, the operating frequency of the DOSRAM at a power supply voltage of 3.3 V is shown in Fig. 29(A) and Fig. 29(B) and 30. FIG. 29(A) shows the temperature at -40°C, FIG. 29(B) shows the temperature at 27°C, and FIG. are the results estimated at 85°C. Figures 29(A), 29(B) and 30 show, respectively, Backgate voltage V BG -1.5V, -2V, -2.5V, -3V, -4V, -4.8 The operating frequencies estimated for each V are shown in Figs. 29(A), 29(B) and 3 At 0, the horizontal axis indicates the data retention time of the DOSRAM, and the vertical axis indicates the operating frequency of the DOSRAM. As with sample A, sample B also showed a wide temperature range at a power supply voltage of 3.3 V. The operating frequency is expected to be 150 MHz or more, and the data retention time is expected to be 1 hour or more. We were able to confirm this.

[0387] For comparison, the back gate voltage V BG The data without adjustment is shown below. For sample B, The power supply voltage is 3.3V and the back gate voltage is V BG DOSRAM when -4.8V The operating frequency is shown in Fig. 31. In Fig. 31, the horizontal axis indicates the data retention time of DOSRAM. The vertical axis indicates the operating frequency of the DOSRAM. I see, it has been confirmed that the operating frequency is lower.

[0388] Operating frequency of DOSRAM in sample C at power supply voltage of 2.5V and temperature of -40℃ is shown in Figure 32. Figure 32 shows the back gate voltage V BG -2V, -3V, -4V, -5V The horizontal axis in Fig. 32 shows the estimated operating frequency for each. The vertical axis indicates the operating frequency of the DOSRAM. In the case of sample C, the operating frequency was 100 MHz at a power supply voltage of 2.5 V and -40°C. From the above, we have confirmed that data retention time is expected to be more than one hour.

[0389] For comparison, the back gate voltage V BG The data without adjustment is shown below. For sample C, The power supply voltage is 3.3V and the back gate voltage is V BG DOSRAM operation when -5V The frequency is shown in Figure 33(A). The power supply voltage is 2.5V and the back gate voltage V BG to -5V The operating frequency of the DOSRAM in this case is shown in FIG. In the graphs of Fig. 1B, the horizontal axis indicates the temperature and the vertical axis indicates the operating frequency of the DOSRAM. As with sample B, it was confirmed that the operating frequency of sample C decreased as the temperature decreased. .

[0390] The configurations, methods, etc. shown in this embodiment may be at least partially implemented in other embodiments described in this specification. The present invention can be implemented in combination with the above embodiment. EXAMPLES

[0391] In this embodiment, the DOSRAM (see FIG. 10A) shown in the second embodiment is Gate voltage V BG Data retention time under different operating temperatures and operating frequencies with constant was estimated.

[0392] In estimating the operating frequency of the DOSRAM, the transistor 500E shown in Figure 17 was tested. In this example, the parameters required for the estimation were extracted from the electrical characteristics. Assuming the transistor M11 in (A) is the transistor 500E, The operating frequency was estimated.

[0393] In this embodiment, the size of the prototype transistor 500E is 80 mm in channel length (L). nm, and the channel width (W) was 55 nm.

[0394] In the transistor 500E fabricated in this example, the oxide 530a has a thickness of 5 nm. The oxide 530a is made of In-Ga-Zn oxide. The oxide 530a is formed in a film having an atomic ratio of In:Ga:Zn The target was an In-Ga-Zn oxide with a ratio of 1:3:4. The sputtering was performed at a substrate temperature of 200°C using a mixed gas of argon and oxygen. Ta.

[0395] In addition, the oxide 530b of the transistor 500E fabricated in this embodiment has a thickness of 15 nm. The oxide 530b is made of In-Ga-Zn oxide. The oxide 530b is formed in an atomic ratio of In:Ga:Zn DC sputtering using a target of In-Ga-Zn oxide with a ratio of 4:2:4.1 The sputtering method was performed with a substrate temperature of 200°C and a mixed gas of argon and oxygen. So I went.

[0396] In addition, the oxide 530c of the transistor 500E fabricated in this example is an I The oxide 530c is made of n-Ga-Zn oxide. The atomic ratio of the oxide 530c is In:Ga:Zn= DC sputtering method using a target of In-Ga-Zn oxide with a ratio of 4:2:4.1 The sputtering method was performed with a substrate temperature of 130°C and a mixed gas of argon and oxygen. went.

[0397] After fabrication of the transistor 500E, a heat treatment was performed at 400°C for 8 hours in a nitrogen gas atmosphere. .

[0398] Next, the I D -V G Measurements were carried out. D -V G The measurement is Drain voltage V of the 500E D to +1.08V, source voltage V S With the gate voltage set to 0V, Pressure V G The back gate voltage V was swept from -1.0 V to +3.3 V. BG The measurements were performed at two levels: -5.7V and -10.5V. The temperatures were 125℃, 85℃, and 27℃. The test was performed at four temperatures: 40° C., 40° C., and −40° C. Specifically, The inch square substrate was fixed on a thermo chuck set to each of the above temperatures, and the transistor 500E I D -V G Measurements were carried out. In addition, measurements were carried out on three elements at each measurement temperature ( n=3).

[0399] Next, in the same manner as in Example 1, the obtained I D -V G From the curve, the Vsh and S Based on the calculated data, we assume a DOSRAM with a memory capacity of 1Mb. The data retention time and DOSRAM operating frequency were estimated.

[0400] Table 1 shows the specifications of the assumed DOSRAM. Figure 34 shows the assumed DOSRAM. A schematic diagram of the above is shown.

[0401] [Table 1]

[0402] 35A to 35D, the voltage applied to the gate of transistor 500E is applied to the gate of transistor 50 Voltage V that makes 0E the on-state GON With the voltage at 2.25V and the transistor 500E in the off state, Voltage V GOFF -0.72V, the back gate voltage V of the 500E transistor BG of- The following shows the estimated data retention time and operating frequency when the voltage is set to 5.7V.

[0403] FIG. 35(A) shows the estimated data retention time and operating frequency when the measurement temperature is 125°C. Figure 35(B) shows the estimated data retention time and operating frequency when the measurement temperature is 85°C. FIG. 35(C) shows the estimated data retention time and operating frequency when the measurement temperature is 27°C. FIG. 35(D) shows the estimated data retention time and operating frequency when the measurement temperature is -40°C. It is a forest.

[0404] From Figures 35(A) to (D), the operating frequency is 100 MHz or more at all measurement temperatures. In addition, the holding time for all the measurement temperatures was approximately 1 hour or more. It can also be seen that the lower the measurement temperature, the longer the retention time.

[0405] 36(A) to (D) show data retention under different operating conditions from those in FIG. 35(A) to (D). The estimated operating frequency and the time required for the voltage V GON to 1.65V, voltage V G OFF -1.32V, voltage V BG The measurement temperature was set to -3.0 V. The data retention time and operating frequency are estimated at 25°C. The data retention time and operating frequency are estimated when the temperature is 85°C. The data retention time and operating frequency are estimated at 27°C. It is an estimate of the data retention time and operating frequency at a temperature of -40°C. Also, for each measurement temperature the measurement was performed one element at a time (n = 1).

[0406] From FIGS. 36(A) to (D), an operating frequency of 100 MHz or higher is estimated at all measurement temperatures. Also, similar to FIGS. 35(A) to (D), it can be seen that the lower the measurement temperature, the longer the retention time. When the measurement temperature is 125°C, the retention time is about 1 year, but when the measurement temperature is 85°C or lower, a data retention time of 10 years or more is obtained.

[0407] From this example, it was found that by adjusting the gate voltage V G and the back gate voltage V BG the operating frequency and data retention time of the DOS RAM can be adjusted.

Example

[0408] An electric field effect transistor using IGZO containing a CAAC structure in the semiconductor layer (also referred to as a "CAAC- IGZO FET") was fabricated, and the off-current and cut-off frequency f T etc. were investigated under a high-temperature environment of 150°C.

[0409] <Structure and Characteristics of CAAC-IGZO FET> The transistor has a self-aligned transistor structure similar to the transistor 500E shown in FIG. 17, and the thickness of the gate insulating layer on the top gate (front gate) side is 6 nm in terms of EOT (Equivalent Oxide Thickness). Also, the thickness of the gate insulating layer on the back gate side is 31 n m in terms of EOT.

[0410] The study was conducted on a CAAC-I with a channel length (L) of 25 nm and a channel width (W) of 21 nm. GZO FET and C This was carried out using AAC-IGZO FETs and other devices.

[0411] Figure 37 shows the I D -V G characteristics I D -V G The characteristics are measured at drain voltage V D 1.2V, source voltage V S to 0V , back gate voltage V BG is set to -10V, and the gate voltage V G Vary from 0V to 2.5V This was done.

[0412] I D -V G The characteristic measurement results showed that the Svalue was 79mV / dec and the field effect mobility was 1 0.2cm 2 / Vs, on-current is 2.8μA(V G =2.5V), and the threshold voltage Vth is A voltage of 1.44V was obtained.

[0413] In addition, the lower limit of the measuring instrument for current measurement is usually 1×10 -12 ~1×10 -13 At about A Therefore, the CAAC-IGZO FET has the characteristic of having an extremely low off-state current. It is impossible to accurately measure the off-state current of a single transistor. For example, - 24 In order to measure the current value of A, multiple transistors are connected in parallel. However, in this case, the number of transistors connected in parallel is 10. 11 Pieces are needed Therefore, it is not realistic.

[0414] In this example, the current was measured using the circuit shown in FIG. Specifically, 20,000 CAAC-IGZO FETs are connected in parallel to form a DUT (Device Under Test). ce Under Test), the time dependence of the node FN potential change was measured, and the leakage current By using the circuit shown in FIG. 38(A), the gate leakage current Ig (gate The sum of the gate-source current, gate-drain current, and gate-backgate current The value of the off-current can be known by using the circuit shown in FIG. It is possible.

[0415] Figure 39 shows the gate resistance measured under the temperatures of 85℃, 125℃, and 150℃. The measurement results of the peak current Ig are shown in Fig. 1. The DUT is 20,000 L / W = 60 nm / 60 The horizontal axis of Fig. 39 is the inverse of temperature, with 100 The vertical axis shows the logarithmic Ig per CAAC-IGZO FET. The measurement is performed with a source voltage of V S 2.4V, drain voltage V D 2.4V, gate voltage V G This was done with a source voltage of V S is 0V, drain voltage Vd is 0V , gate voltage V G The same as the CAAC- This means that the IGZO FET is in the off state. Note that the back gate voltage V BG was set to -10V.

[0416] As shown in Figure 39, even in a temperature environment of 150°C, Ig is 3.3 x 10 -20 A, and the gate leakage current Ig was found to be sufficiently low. .

[0417] The CAAC-IGZO FET fabricated in this example has a back gate electrode BGE (Back As shown in FIG. 40, a back gate electrode BG Back gate voltage V supplied to E BG By changing It was confirmed that the threshold voltage change was dVth / dV BG is -0.15V / V. Also, as shown in FIG. 41, the back gate voltage V BG Mutual cost for changes in Inductance g m It was confirmed that the change in the back gate voltage V BG of Change in transconductance g m It was confirmed that the maximum value of shifts in the same way as Vth. Done.

[0418] By providing the back gate electrode BGE, dynamic Vth control becomes possible. There is no need to change the manufacturing process of the transistor depending on the circuit application. There are also disadvantages to providing a back gate electrode. Parasitic capacitance may occur between the source and drain, which may increase the gate delay time. In order to verify the function, the transistors with and without back gate electrodes BGE were Cutoff frequency f T The cutoff frequency f T is derived by equation (5).

[0419]

number

[0420] In formula (5), C tg is the gate capacitance on the top gate (front gate) side, and C bg is the gate capacitance on the back gate side. C g is C tg and C. bg is the total capacity. From equation (5), the cutoff frequency f T Same Then, g normalized by the gate capacitance m It can be seen that the are similar.

[0421] In CAAC-IGZO FET with L / W=25nm / 21nm, the back gate electrode The cutoff frequency f T was measured. The test was performed at room temperature (27°C). The back gate voltage V BG The measurements were taken at 0V, -3V, and -6V. The measurements were also performed with 672 CAAC-IGZO FETs connected in parallel (M = 672).

[0422] The measurement results are shown in Figure 42. The element with the back gate electrode BGE has a 30 GHz and the back gate electrode BGE has a 30 GHz. The cutoff frequency f of the element without the gate electrode BGE is 27 GHz. T Also, Gate voltage V BG Cutoff frequency f when is -6V T The frequency is 27.7GHz, and the back Gate voltage V BG The cutoff frequency f is the same as when T From these results, Cutoff frequency f with and without back gate electrode BGE TIt was found that the change was small. Thus, it was found that even if the back gate electrode BGE was added, the delay time did not increase. Also, it was found that by adding the back gate electrode BGE, it was possible to suppress the Vth shift caused by temperature changes.

[0423] Also, the cut-off frequency f T was measured using an element different from that in FIG. 42. Specifically, a CAAC-IGZO FET without a back gate electrode BGE with L / W = 39 nm / 28 nm was used to measure the cut-off frequency f T . The measurement was performed at room temperature (27 °C) . Also, the measurement was performed by connecting 672 CAAC-IGZO FETs in parallel (M = 672).

[0424] FIG. 43 shows the measurement results. Also in this measurement, a cut-off frequency f T of 30 GHz was obtained.

[0425] <High-temperature characteristics of CAAC-IGZO FET> CAAC-IGZO FET can be fabricated in the BEOL (Back End Of Line) process of semiconductor manufacturing processes such as CMOS. Thus, it is possible to form a stacked layer with a Si transistor (among Si transistors, a field-effect Si transistor is also referred to as a "Si FET"). For example, applications such as fabricating a circuit that requires high-speed operation in a CMOS process and fabricating a circuit that requires a low leakage current in a CAAC-IGZO process are possible. Also, while the off-current of a Si FET increases as the temperature rises, CAAC-IGZO

[0426] ​​In FET, the off-current is always at the lower limit of measurement. Off-current of Si FET and CAAC-IGZO FET with L / W=60nm / 60nm The temperature characteristics of the off-current of both were compared. The off-current of both was measured using the circuit shown in Figure 38(B). This was carried out using

[0427] The off-state current of a Si FET is G =-1.0V, source voltage V S =0V, Dre Input voltage V D =1.2V, body voltage V B = 0V. CAAC-IGZO F The off-state current of ET is G =-2.0V, source voltage V S =0V, drain voltage V D = 2.0V, back gate voltage V BG Measured at -3.0V.

[0428] The measurement results are shown in Figure 44. At a measurement temperature of 150°C, the off-current of the Si FET was approximately 2. 2×10 -6 A, and the off-current of the CAAC-IGZO FET is approximately 3.9×10 -20 A. CAAC-IGZO FETs can maintain low off-state current even in high-temperature environments. In addition, the off-current can be further reduced by adjusting the back gate voltage. .

[0429] Next, Figure 45 shows the temperature dependence of Hall mobility and carrier density of CAAC-IGZO film. As shown in Figure 45, the Hall mobility of the CAAC-IGZO film changes with temperature. It can be seen that there is almost no change. The Hall mobility of the CAAC-IGZO film is Since it is assumed that Coulomb scattering is dominant over the lattice constant, it does not decrease even at high temperatures.

[0430] Next, the cutoff frequencies of CAAC-IGZO FETs and Si FETs at 25℃ and 150℃ were number f T The measurement DUT was a Si FET with L / W=60nm / 480nm and L / The experiment was carried out using a CAAC-IGZO FET with W=25nm / 21nm. The FET measurements were performed by connecting 21 Si FETs in parallel (M=21). -IGZO FET measurements were performed using 672 CAAC-IGZO FETs connected in parallel. (M=672).

[0431] The measurement results are shown in Figure 46. The maximum cutoff frequency f T The change rate of CAA is 36%. Maximum cutoff frequency f of C-IGZO FET T The change rate of the Si FET was 13%. In comparison, the CAAC-IGZO FET has a cutoff frequency of f T and 150℃ cutoff wave number f T The CAAC-IGZO FET measured this time had small differences in characteristics. So, the measurement temperature is 150℃, V D Maximum cutoff frequency f = 2.5V T was 33GHz .

[0432] These results suggest that CAAC-IGZO FETs have a lower cutoff frequency f T The temperature dependence of the CAAC-IGZO FET was also found to be small. It was found that the provision of a gate electrode can suppress the fluctuation of Vth due to temperature changes. , the cutoff frequency f T The change in SiF In addition, the CAAC-IGZO FET was found to have a lower The off-state current is 10 -20 A was found to be extremely rare. By using FETs, it is possible to realize circuits and memories that consume less power in a wide range of operating temperatures. It can be achieved.

[0433] The configurations, methods, etc. shown in the above embodiments may be at least partially described in other embodiments in this specification. The present invention can be implemented in appropriate combination with the embodiments. [Explanation of symbols]

[0434] 11 voltage generating circuit, 11a voltage generating circuit, 11b voltage generating circuit, 12 voltage holding circuit, 14 Capacitor element, 15 Buffer, 17 Temperature sensor, 18 Voltage control circuit, 20 Correction circuit , 100 Semiconductor device

Claims

[Claim 1] The power supply circuit includes a transistor, a capacitance element, a correction circuit, a voltage generating circuit, and a voltage holding circuit, one of a source and a drain of the transistor is electrically connected to the capacitance element; an output of the correction circuit is electrically connected to a gate of the transistor; an output of the voltage generating circuit is electrically connected to an input of the voltage holding circuit; an output of the voltage holding circuit is electrically connected to a gate of the transistor; the voltage holding circuit has a function of applying the voltage generated by the voltage generating circuit to a gate of the transistor and holding the voltage; the correction circuit has a function of acquiring temperature information and a function of converting the temperature information into a control voltage; The control voltage is a voltage that controls the voltage generated by the voltage generating circuit.

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