Task execution method, apparatus, storage medium and electronic device

Abstract

The present invention discloses a task execution method, apparatus, storage medium and electronic device, which predetermines all combinations of operators that can be executed in parallel, and when executing a task in response to a task request issued by a user, determines whether there is a matching combination of operators that can be executed in parallel between each executable operator corresponding to the task that needs to be executed and the operator of a second task being executed by a chip executing the second task, and if there is, the first task can be executed in parallel by the chip executing the second task, thereby improving the utilization rate of the chip's computing resources.

Description

[Technical field]

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a task execution method, apparatus, storage medium and electronic device. [Background technology]

[0002] Currently, various artificial intelligence models are widely applied in fields such as autonomous driving and augmented reality. When a business platform executes a task using an artificial intelligence model, the business platform usually determines operators required to execute the task from among the operators included in the artificial intelligence model, and executes these operators using a chip to execute the task.

[0003] In the process of executing these operators by the chip, only a part of the computing resources of the chip is occupied, so that the computing resources of the chip are wasted and the utilization rate of the computing resources of the chip is reduced. Therefore, how to improve the utilization rate of the computing resources of the chip has become an urgent issue. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT DISCLOSURE In order to partially solve the above problems existing in the prior art, the present invention provides a task execution method, an apparatus, a storage medium and an electronic device. [Means for solving the problem]

[0005] The task execution method provided in the present invention includes: obtaining a first task request; determining a combination of operators required to execute a first task corresponding to the first task request; and determining at least one executable operator in the combination of operators as a first target operator, where the executable operator can be directly executed because it does not need to depend on the execution results of other operators; for a chip executing a second task, determining whether the remaining computing resources of the chip satisfy a predetermined condition; if the judgment result is positive, determining at least one executable operator corresponding to the second task currently executed by the chip as a second target operator; and allocating at least a portion of the remaining computing resources of the chip to each of the first target operators, on the premise that the chip does not affect the computing resources allocated to each of the second target operators, so that the chip executes the first task by executing each of the first target operators in parallel in executing each of the second target operators.

[0006] Optionally, allocating at least a portion of the remaining computing resources of the chip to each of the first target operators, provided that the computing resources allocated by the chip to each of the second target operators are not affected, includes: selecting candidate operator combinations including the second target operator from a predetermined plurality of parallelizable operator combinations; for each of the candidate operator combinations, if the number of the first target operators included in the candidate operator combination exceeds a predetermined first threshold, determining the candidate operator combination as a target operator combination; and executing each of the first target operators and each of the second target operators in the target operator combination in parallel by the chip to perform the first task.

[0007] Optionally, determining a combination of operators that can be parallelized includes obtaining a plurality of target models; determining, for each of the target models, data transmission dependencies between the operators included in the target model; and determining, based on the data transmission dependencies of each of the plurality of target models, a combination of operators that have no data transmission dependencies among all the operators included in the plurality of target models as the combination of operators that can be parallelized.

[0008] Optionally, determining a combination of operators that have no data transmission dependency among all the operators included in the multiple target models as the combination of parallelizable operators based on the data transmission dependency of each of the multiple target models includes: determining a data flow graph corresponding to the target model based on the data transmission dependency determined for each of the target models, wherein in the data flow graph, each node is used to represent an operator included in the target model and an edge between two nodes is used to represent the existence of a data transmission dependency between the two nodes; and determining the combination of parallelizable operators based on a plurality of the data flow graphs corresponding to the multiple target models.

[0009] Optionally, determining the combination of parallelizable operators based on a plurality of the data flow graphs corresponding to the plurality of target models includes determining, for each node included in the plurality of data flow graphs, a combination of parallelizable operators corresponding to the node through a plurality of iterations, wherein for each iteration, a combination of target nodes in the corresponding iteration is determined, the combination of target nodes including one target node or a plurality of target nodes having no mutual dependency, and for each other node other than each target node in the combination of target nodes included in the plurality of data flow graphs, if the other node does not depend on any of the target nodes in the combination of target nodes, a combination of parallelizable operators is determined based on the other node and the combination of target nodes, and the determined combination of parallelizable operators is set as a combination of target nodes in a next iteration, or a target node in the next iteration is sequentially selected from nodes included in the plurality of data flow graphs until a preset termination condition is satisfied.

[0010] Optionally, determining a combination of parallelizable operators based on the combination of the other node and the target node includes merging the combination of the other node and the target node as a candidate operator combination, and determining the candidate operator combination as a parallelizable operator combination if the execution time of the candidate operator combination within the chip does not exceed a predetermined second threshold.

[0011] Optionally, sequentially selecting a target node for a next iteration from nodes included in the plurality of data flow graphs includes sequentially selecting a node from a candidate node set as a target node for a next iteration, where the candidate node set includes all nodes included in the plurality of data flow graphs for which the execution time of a corresponding operator in the chip does not exceed a second preset threshold.

[0012] Optionally, determining the execution time of the combination of candidate operators within the chip includes obtaining relevant features of the combination of candidate operators, the relevant features including at least one of the past chip computing amount, past data bandwidth, past execution time, and average, maximum, minimum, and variance of data transmission size of operators included in the combination of candidate operators; inputting the relevant features into a pre-configured prediction model, and predicting and outputting the execution time of the combination of candidate operators within the chip using the prediction model.

[0013] Optionally, the combination of parallelizable operators is determined when the chip is in an offline state.

[0014] The task execution device provided in the present invention includes an acquisition module for acquiring a first task request; a first determination module for determining a combination of operators required to execute a first task corresponding to the first task request and determining at least one executable operator in the combination of operators as a first target operator, where the executable operator can be directly executed because it does not need to depend on the execution results of other operators; a detection module for determining whether the remaining computing resources of a chip executing a second task satisfy a preset condition; and a second determination module for determining at least one executable operator corresponding to the second task currently being executed by the chip as a second target operator if the judgment result of the detection module is positive; and an execution module for assigning at least a portion of the remaining computing resources of the chip to each of the first target operators, on the condition that the computing resources assigned by the chip to each of the second target operators are not affected, so that the chip executes the first task by executing each of the first target operators in parallel in executing each of the second target operators.

[0015] Optionally, the execution module is specifically used to select candidate operator combinations including the second target operator from a predetermined plurality of parallelizable operator combinations, and for each of the candidate operator combinations, if the number of the first target operators included in the candidate operator combination exceeds a predetermined first threshold, determine the candidate operator combination as a target operator combination, and execute each of the first target operators and each of the second target operators in the target operator combination in parallel by the chip to perform the first task.

[0016] Optionally, the apparatus further includes a third determination module for obtaining a plurality of target models, determining for each of the target models data transmission dependencies between operators included in the target model, and determining, based on the data transmission dependencies of each of the plurality of target models, a combination of operators among all operators included in the plurality of target models that have no data transmission dependencies between each other as the combination of parallelizable operators.

[0017] Optionally, the third determination module specifically determines a data flow graph corresponding to the target model based on the data transmission dependency determined for each of the target models, in which each node in the data flow graph is used to represent an operator included in the target model and an edge between two nodes is used to represent the existence of a data transmission dependency between the two nodes, and is used to determine a combination of operators that can be parallelized based on a plurality of the data flow graphs corresponding to the plurality of target models.

[0018] Optionally, the third determination module is specifically used for determining, for each node included in the plurality of data flow graphs, a combination of parallelizable operators corresponding to the node through a plurality of iterations, in which, for each iteration, a combination of target nodes in the corresponding iteration is determined, the combination of target nodes including one target node or a plurality of target nodes having no mutual dependency, and for each other node other than each target node in the combination of target nodes included in the plurality of data flow graphs, if the other node does not depend on any of the target nodes in the combination of target nodes, a combination of parallelizable operators is determined based on the other node and the combination of target nodes, and the determined combination of parallelizable operators is a combination of target nodes in the next iteration, or a target node in the next iteration is sequentially selected from nodes included in the plurality of data flow graphs until a preset termination condition is met.

[0019] Optionally, the third determination module is specifically used for merging the combination of the other node and the target node as a candidate operator combination, and determining the candidate operator combination as a parallelizable operator combination if the execution time of the candidate operator combination in the chip does not exceed a predetermined second threshold.

[0020] Optionally, the third determining module is specifically used for sequentially selecting one node from a candidate node set as a target node in a next iteration, where the candidate node set includes all nodes included in the multiple data flow graphs, whose corresponding operator execution times in the chip do not exceed a preset second threshold.

[0021] Optionally, the third determination module is specifically used to obtain related features of the candidate operator combination, including at least one of the past chip computing amount, past data bandwidth, past execution time, and average, maximum, minimum, and variance of data transmission size of operators included in the candidate operator combination, input the related features into a pre-configured prediction model, and predict and output the execution time of the candidate operator combination in the chip through the prediction model.

[0022] Optionally, the combination of parallelizable operators is determined when the chip is in an offline state.

[0023] The present invention provides a computer-readable storage medium storing a computer program, the computer program causing a processor to execute the task execution method described above.

[0024] The present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable by the processor, the processor executing the program to perform the task execution method described above. Effect of the Invention

[0025] According to the task execution method provided in an embodiment of the present invention, an executable operator that does not need to depend on the execution results of other operators in a combination of operators required to execute a first task corresponding to a current task request is determined as a first target operator, and when the remaining computing resources of the chip executing the second task satisfy a predetermined condition, at least a portion of the remaining computing resources of the chip is allocated to each first target operator, on the premise that the computing resources allocated by the chip to each executable operator (hereinafter referred to as second target operators) corresponding to the second task are not affected. In this way, the chip can execute the first task by executing each first target operator in parallel while executing each second target operator, thereby effectively improving the utilization rate of the computing resources of the chip. [Brief description of the drawings]

[0026] The drawings are used to provide a further understanding of the present invention and constitute a part of the present invention, and the schematic embodiments of the present invention and their explanations are used to interpret the present invention and do not constitute undue limitations on the present invention. [Figure 1] 2 is a schematic diagram of a task execution method provided by an embodiment of the present invention; [Diagram 2] FIG. 2 is a schematic diagram of a data flow diagram provided by an embodiment of the present invention. [Diagram 3] FIG. 4 is a schematic diagram of a process for determining a combination of parallelizable operators provided by an embodiment of the present invention; [Figure 4] 2 is a schematic diagram of functional modules of a task execution device provided by an embodiment of the present invention; [Diagram 5] 1 is a schematic diagram of the structure of an electronic device for performing tasks provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described clearly and completely below in conjunction with specific embodiments of the present invention and corresponding drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments that can be obtained by those skilled in the art without creative efforts are all within the protection scope of the present invention.

[0028] The technical solutions provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] As shown in FIG. 1, the task execution method provided in the present invention includes the following steps S101 to S105.

[0030] In step S101, a first task request is obtained.

[0031] In the present invention, a user can execute a corresponding task in an artificial intelligence model arranged in a business platform. Specifically, a user can send a task request to the business platform through a device used by the user, so that the business platform can obtain the task request and then schedule the computing resources of the chip in response to the received task request to execute a task corresponding to the task request. For example, a user can send a product recommendation request to the business platform through a device used by the user, and after receiving the product recommendation request, the business platform can call the chip to execute an operator in the product recommendation model to execute a product recommendation task.

[0032] In the present invention, the execution subject for realizing the task execution method may be a designated device installed on a business platform, such as a server, or may be a terminal device, such as a desktop computer, a laptop computer, etc. For ease of explanation, the task execution method provided by the present invention will be described below by taking the server as an example of the execution subject.

[0033] In step S102, a combination of operators required for executing a first task corresponding to the first task request is determined, and at least one executable operator included in the combination of operators is determined as a first target operator, where the executable operator does not need to depend on the execution results of other operators and can be directly executed by, for example, a chip.

[0034] For example, the server may determine a combination of operators required to execute a task corresponding to the task request, and determine at least one executable operator included in the combination of operators as a first target operator, where the executable operator can be executed directly because it does not need to depend on the execution results of other operators.

[0035] Specifically, when a server needs to execute a certain task, it determines a model for executing the task, and operators included in the model for executing the task constitute a combination of operators required for executing the task, and the chip executes the operators included in the combination of operators to realize the execution of the task. Here, the model for executing the task determined by the server may be multiple, and for example, to execute task A, it is necessary to execute operators a and b of model 1, and operators c and d of model 2.

[0036] In practical use scenarios, the server may execute each executable operator by multiple chips, and thus the server may determine at least one executable operator in the combination of operators as the first target operator. For example, if the executable operators include an operator a, an operator b, an operator c, and an operator d, the server may execute the operator a on chip 1, the operator b on chip 2, and the operators c and d on chip 3.

[0037] In addition, there may be certain data transmission dependencies between operators. For example, when an operator is executed, it needs to use the data processing result of another operator as a parameter for the execution of the operator. Therefore, if the operator on which the operator depends is not executed, the parameters required for the execution of the operator are not determined, and therefore the operator cannot be executed directly. Therefore, after the server determines a combination of operators that need to be executed in response to a task request issued by a user, it may determine an operator that can be directly executed by the chip from the combination of operators as a first target operator. By executing the first target operator by the chip, other operators in the combination of operators that depend on the execution result of the first target operator can be continuously executed by the chip.

[0038] In addition, after the server finishes executing the first target operator by the chip, the operators in the combination of operators corresponding to the first task that depend on the first target operator become operators that can be directly executed by the chip after obtaining the execution result of the first target operator. At this time, the server may newly determine at least one new operator that can be directly executed by the chip from the combination of operators as the first target operator.

[0039] In step S103, for the chip executing the second task, determine whether the remaining computing resources of the chip satisfy a preset condition.

[0040] In step S104, if the determination result in step S103 is positive, obtain an executable operator corresponding to a second task currently being executed by the chip as a second target operator.

[0041] After determining the first target operator that needs to be executed by the chip currently, the server may determine, for the chip executing the second task, whether the remaining computing resources of the chip satisfy a preset condition, and if the determination result is positive, may execute the first target operator corresponding to the first task in parallel when the chip executes the second task. If the determination result is negative, may assign an idle chip to the first task to execute the first target operator corresponding to the first task, or may put the first task into a waiting state when there is no chip currently in an idle state. Here, the preset condition may be set according to actual requirements, such as determining whether the remaining computing resources of the chip reach a specified condition threshold.

[0042] In step S105, the chip allocates at least a portion of the remaining computing resources of the chip to each of the first target operators, provided that the computing resources allocated to each of the second target operators are not affected, and the chip executes the first task by executing each of the first target operators in parallel while executing each of the second target operators.

[0043] For example, the server may assign at least a portion of the remaining computing resources of the chip to each first target operator, and execute each first target operator in parallel to perform the corresponding first task, without affecting the computing resources assigned by the chip to each second target operator.

[0044] Specifically, the server may select combinations of parallelizable operators including a second target operator as candidate operator combinations from predetermined combinations of parallelizable operators, and for each candidate operator combination, if the number of first target operators included in the candidate operator combination exceeds a predetermined first threshold, determine the candidate operator combination as a target operator combination, and execute each first target operator and each second target operator in the target operator combination in parallel by the chip.

[0045] In practical use scenarios, when a server needs to execute a first task in parallel by a chip executing a second task, it needs to predict whether a first target operator that needs to be executed to execute the first task can be executed in parallel with a second target operator of a currently executing second task, and the above prediction process may result in an extended response delay of a task request. Based on this, the server may predetermine all combinations of operators that can be executed in parallel as combinations of parallelizable operators in an offline state, so that in practical applications, it can directly select combinations of target operators that match the second target operator and the first target operator from each combination of parallelizable operators and have the chip execute them in parallel.

[0046] Here, the method by which the server determines each combination of parallelizable operators may include the steps of acquiring a plurality of target models; for each target model, determining data transmission dependencies between the operators included in the target model; and determining, based on the data transmission dependencies corresponding to each of the target models, a combination of operators that do not have data transmission dependencies between all the operators included in the plurality of target models as the combination of parallelizable operators.

[0047] Fig. 2 is a schematic diagram of a data flow diagram provided by an embodiment of the present invention. As can be seen from Fig. 2, the server can determine a data flow diagram corresponding to each target model based on the determined data transmission dependency. In the data flow diagram, each node is used to represent an operator included in the target model, and an edge between two nodes is used to represent the existence of a data transmission dependency between the two nodes. Here, if there is an edge pointing from node A to node B between node A and node B, it is indicated that node B depends on node A.

[0048] Furthermore, for each node included in the data flow graph, the server may determine a combination of parallelizable operators corresponding to the node through multiple iterations.

[0049] Here, for each iteration, the server may determine a combination of goal nodes in that iteration that includes one goal node or multiple goal nodes that have no dependency relationship with each other, and for each other node included in the data flow diagram other than each goal node in the combination of goal nodes, determine whether the other node depends on any of the goal nodes in the combination of goal nodes.

[0050] If the other node does not depend on any of the target nodes in the combination of target nodes, the server may determine a combination of parallelizable operators based on the other node and the combination of target nodes, and set the determined combination of parallelizable operators as the combination of target nodes in the next iteration, or may sequentially select target nodes in the next iteration from the nodes included in the data flow diagram.

[0051] For each other node, the server may sequentially determine whether the target node in the combination of target nodes is a parent node or ancestor node of the other node according to the data flow graph, and if there is one target node in the combination of target nodes that is a parent node or ancestor node of the other node, the other node may be determined to depend on the target node in the combination of target nodes. Here, if there is an edge pointing from a first node to a second node in the data flow graph, the first node is a parent node and the second node is a child node. And the parent node and ancestor node of the first node are ancestor nodes of the second node.

[0052] Furthermore, when the server determines that a preset termination condition is satisfied, the server may determine the combination of each obtained goal node as a combination of operators that can be parallelized. Here, the preset termination condition may be that all nodes included in the data flow diagram participate in the iterative process as goal nodes. Of course, the preset termination condition may be that the number of iterations reaches a designated number.

[0053] Here, the server's determination of a combination of operators that can be parallelized based on the combination of the other node and the target node may specifically mean that the server merges the combination of the other node and the target node as a candidate operator combination, determines the execution time of the candidate operator combination within the chip, and if the execution time of the candidate operator combination within the chip does not exceed a predetermined second threshold, determines the candidate operator combination as the parallelizable operator combination.

[0054] As can be seen from the above, the server may predict the execution time of each candidate operator combination within the chip, and further select each candidate operator combination based on the predicted execution time of each candidate operator combination within the chip.

[0055] In actual usage scenarios, some operators may not be suitable for combination with other operators as a parallelizable operator combination due to their long execution time in the chip. Therefore, before determining the combination of parallelizable operators, the server may determine, for each node included in the data flow diagram, the execution time of the operator corresponding to the node in the chip, and add the node to a preset candidate node set if the execution time of the operator corresponding to the node in the chip does not exceed a preset second threshold. In this way, in multiple iterations of determining the combination of parallelizable operators, one node from the candidate node set can be sequentially selected as a target node in the next iteration.

[0056] Specifically, the server determining the execution time of the candidate operator combination in the chip may be such that the server obtains relevant features of the candidate operator combination, inputs the relevant features into a pre-defined prediction model, and predicts and outputs the execution time of the candidate operator combination in the chip through the prediction model. Here, the relevant features include at least one of the following: the amount of computing power of the chip used in the past, the past data bandwidth, the past execution time of each operator included in the candidate operator combination, and the average, maximum, minimum, and variance of the data transmission size of the operators included in the candidate operator combination. Note that, when the candidate operator combination includes only one operator, the execution time of the operator in the chip is obtained by the above method.

[0057] Here, the method for training the prediction model may include inputting a combination of sample operators including at least one sample operator into the prediction model, predicting and outputting an execution time of the combination of sample operators in a chip using the prediction model, and training the prediction model by minimizing a difference between the execution time of the combination of sample operators in the chip output by the prediction model and an actual execution time of the combination of sample operators obtained by offline simulation.

[0058] FIG. 3 is a schematic diagram of a process for determining a combination of parallelizable operators provided by an embodiment of the present invention.

[0059] As can be seen in conjunction with Figure 3, the server can code an operator corresponding to each node in the data flow diagram, where the coding method may be to code each node in the data flow diagram sequentially in ascending order from 0 to N, where N represents the number of all nodes in the data flow diagram.

[0060] Furthermore, the server determines that the execution time of an operator corresponding to node i in the chip (hereinafter referred to as the i-th operator or operator i) is t i and the execution time of operator i can be predicted as t i is less than a second preset threshold, add the operator i to the set 1 and the set 2, respectively, and add it to the result set R, where i is an integer greater than or equal to 0 and less than N, and represents the code of the node and the operator corresponding to the node.

[0061] In the process of each iteration, the server may determine whether set 1 is empty. If set 1 is not empty, the server may select an operator x in set 1, remove the operator x from set 1, and combine each operator in set 2 with operator x to obtain an operator combination x′. Furthermore, if there is no data dependency between the operators in the operator combination x′ and the execution time of the operator combination x′ in a single chip does not exceed a second threshold, add the operator combination x′ to set 1 and the result set R; otherwise, discard the operator combination x′. The above process is repeated until set 1 is empty, and at this time, each operator combination in the result set R is a parallelizable operator combination.

[0062] As can be seen from the above, by determining in advance all combinations of operators that can be executed in parallel, and combining the combinations of operators that can be executed in parallel between executable operators corresponding to a first task to be executed in response to a task request issued by a user and executable operators of a second task being executed by the chip, the first task can be executed in parallel in executing the second task by the chip, thereby effectively improving the utilization rate of the chip's computing resources.

[0063] Above is the task execution method provided in one or more embodiments of the present invention. Based on the same idea, the present invention also provides a corresponding task execution device. As shown in Figure 4, the device includes: an acquisition module 401, a first determination module 402, a detection module 403, a second determination module 404, and an execution module 405.

[0064] The obtaining module 401 is used to obtain a first task request.

[0065] The first determination module 402 is used to determine a combination of operators required to execute a first task corresponding to the first task request, and to determine at least one executable operator in the combination of operators as a first target operator, where the executable operator can be directly executed because it does not need to depend on the execution results of other operators.

[0066] The detection module 403 is used for determining, for a chip executing a second task, whether the remaining computing resources of the chip meet a preset condition.

[0067] A second determination module 404 is used to determine at least one executable operator corresponding to a second task currently being executed by the chip as each second target operator when the judgment result of the detection module 403 is positive.

[0068] The execution module 405 is used to allocate at least a portion of the remaining computing resources of the chip to each of the first target operators so as to execute each of the first target operators in parallel upon execution of each of the second target operators by the chip, without affecting the computing resources allocated by the chip to each of the second target operators.

[0069] Optionally, the execution module 405 specifically selects candidate operator combinations including the second target operator from a predetermined plurality of parallelizable operator combinations, and for each candidate operator combination, if the number of the first target operators included in the candidate operator combination exceeds a predetermined first threshold, determines the candidate operator combination as a target operator combination, and uses the chip to execute each first target operator and each second target operator in the target operator combination in parallel.

[0070] Optionally, the apparatus further includes a third determination module 406. The third determination module 406 is specifically used for obtaining a plurality of target models, determining, for each target model, data transmission dependencies between operators included in the target model, and determining, based on the data transmission dependencies corresponding to each of the plurality of target models, a combination of operators among all the operators included in the plurality of target models that do not have data transmission dependencies with each other as a combination of operators that can be parallelized.

[0071] Optionally, the third determination module 406 specifically determines a data flow graph corresponding to each of the target models based on the determined data transmission dependency, in which each node in the data flow graph is used to represent an operator included in the target model, and an edge between two nodes is used to represent the existence of a data transmission dependency between the two nodes, and is used to determine a combination of operators that can be parallelized based on the data flow graph.

[0072] Optionally, the third determination module 406 is specifically used for determining a combination of parallelizable operators corresponding to each node included in the data flow graph through multiple iterations, where for each iteration, the third determination module 406 is specifically used to determine a combination of target nodes in the current iteration, which includes one target node or a combination of target nodes that do not have a mutual dependency relationship, and for each other node other than each target node in the combination of target nodes included in the data flow graph, if the other node does not depend on any of the target nodes in the combination of target nodes, determine a combination of parallelizable operators based on the other node and the combination of the target node, and set the determined combination of parallelizable operators as the combination of target nodes in the next iteration, or sequentially select target nodes in the next iteration from the nodes included in the multiple data flow graphs, and obtain a combination of parallelizable operators after determining that a preset termination condition is satisfied.

[0073] Optionally, the third determination module 406 is specifically used to merge the combination of the other node and the target node as a candidate operator combination, determine the execution time of the candidate operator combination in the chip, and determine the candidate operator combination as a parallelizable operator combination if the execution time of the candidate operator combination in the chip does not exceed a predetermined second threshold.

[0074] Optionally, the third determination module 406 is specifically used to determine, for each node included in the data flow diagram, the execution time of the operator corresponding to the node in the chip, and if the execution time of the operator corresponding to the node in the chip does not exceed a predetermined threshold, add the node to a predetermined candidate node set, and sequentially select one node from the candidate node set as a target node in the next iteration.

[0075] Optionally, the third determination module 406 is specifically used to obtain related features of the candidate operator combination, including at least one of the past chip computing amount, past data bandwidth, past execution time, and average, maximum, minimum, and variance of data transmission size of the operators included in the candidate operator combination, and input the related features into a pre-configured prediction model, so as to predict and output the execution time of the candidate operator combination in the chip through the prediction model.

[0076] Optionally, the combination of parallelizable operators is determined when the chip is in an offline state.

[0077] The present invention further provides a computer readable storage medium, the storage medium storing a computer program for executing the method for performing the above tasks.

[0078] The present invention further provides a schematic structural diagram of an electronic device for performing a task, as shown in Figure 5. As shown in Figure 5, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, an internal memory, and a non-volatile memory, and may of course include other hardware required for operation. The processor loads the corresponding computer program from the non-volatile memory into the internal memory and executes it to realize the method for performing the above task.

[0079] Of course, in addition to realization by software, the present invention does not exclude other realization methods, such as logical devices or a combination of hardware and software. In other words, the entity that executes the following processing steps is not limited to each logical unit, but may be hardware or a logical device.

[0080] In the 1990s, improvements in a technology could be clearly divided into hardware improvements (such as improvements in circuit structures such as diodes, transistors, and switches) and software improvements (improvements in method flows). However, with the development of technology, many of the current method flow improvements can be considered as direct improvements to hardware circuit structures. Designers can mostly obtain the corresponding hardware circuit structures by programming the improved method flows into the hardware circuits. Therefore, it cannot be said that method flow improvements cannot be realized by hardware physical modules. For example, Programmable Logic Devices (PLDs) (e.g. Field Programmable Gate Arrays (FPGAs)) are such integrated circuits, whose logical functions are determined by the user's programming of the device. Instead of chip manufacturers designing and manufacturing dedicated integrated circuit chips, designers program and "integrate" digital systems onto a single PLD.Nowadays, instead of handcrafting integrated circuit chips, this programming is mostly realized using software called a "logic compiler", which is similar to a software compiler used to write a program, and in order to compile the original code, it needs to be written in a specific programming language, which is called a Hardware Description Language (HDL). There is not just one type of HDL, but many types such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., and the most commonly used at present are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. It will be clear to those skilled in the art that a hardware circuit that realizes a logical method flow can be easily obtained by simply programming a method flow logically in some of the above hardware description languages ​​and programming it into an integrated circuit.

[0081] The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor, a computer readable storage medium storing computer readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers, examples of which include, but are not limited to, microcontrollers such as ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, Silicone Labs C8051F320, etc., and the memory controller may also be implemented as part of the control logic of the memory. It will be clear to those skilled in the art that in addition to implementing the controller purely with computer readable program code, it is entirely possible to logically program method steps to cause the controller to perform the same functions in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers, etc. Thus, such controllers may be considered as hardware components, and the devices included therein for implementing various functions may also be considered as structures within the hardware components. Alternatively, the apparatus for implementing various functions may be considered to be software modules implementing a method, or structures within hardware components.

[0082] The system, device, module or unit described in the above embodiments may be specifically implemented by a computer chip, an entity, or a product having some function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a mobile phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet, a wearable device, or any combination of these devices.

[0083] For the sake of convenience, the above-mentioned device will be described by dividing it into various units according to their functions. Of course, when implementing the present invention, the functions of each unit can be realized by the same or multiple pieces of software and / or hardware.

[0084] As will be appreciated by those skilled in the art, embodiments of the present invention may be provided as a method, a system, or a computer program product. Thus, the present invention may employ an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware. Furthermore, the present invention may take the form of a computer program product embodied in one or more computer usable storage media (including, but not limited to, magnetic disk memory, CD-ROM, optical memory, etc.) that contains computer usable program code.

[0085] The present invention will be described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, may be realized by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, whereby the instructions executed by the processor of the computer or other programmable data processing device generate an apparatus for implementing the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0086] These computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture that includes an instruction apparatus that implements the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0087] These computer program instructions may be loaded into a computer or other programmable data processing device such that a series of operational steps are executed on the computer or other programmable device to generate a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0088] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0089] The memory may include volatile, random access memory (RAM) and / or non-volatile memory forms of computer readable storage media, such as read only memory (ROM) or flash memory (flash RAM). The memory is one example of a computer readable storage medium.

[0090] Computer readable storage media include non-volatile and volatile media, removable and non-removable media, and may implement information storage by any method or technology. Information may be computer readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, Phase Change Memory (PRAM), Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, magnetic cassette tape, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that may be used to store information accessible by a computing device. As defined herein, computer readable storage media does not include transitory computer readable storage media, such as modulated data signals and carriers.

[0091] Additionally, the terms "comprise," "contain," or any other variations thereof are intended to include a non-exclusive inclusion, whereby a process, method, article, or device that comprises a set of elements not only includes those elements, but also includes other elements not expressly listed, or includes the inherent elements of such process, method, article, or device. Absent more limitations, an element qualified by the phrase "comprises a..." does not exclude the presence of further identical elements in a process, method, article, or device that includes said element.

[0092] As will be appreciated by those skilled in the art, embodiments of the present invention may be provided as a method, a system, or a computer program product. Thus, the present invention may employ an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware. Furthermore, the present invention may take the form of a computer program product embodied in one or more computer usable storage media (including, but not limited to, magnetic disk memory, CD-ROM, optical memory, etc.) that contains computer usable program code.

[0093] The invention may be described in the general context of computer-executable instructions being executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media, including storage devices.

[0094] Each embodiment of the present invention will be described in a stepwise manner, and the same or similar parts between each embodiment may be referred to each other, and the emphasis of each embodiment is on the differences from other embodiments. In particular, the system embodiment is basically similar to the method embodiment, so it will be briefly described, and the relevant parts may be referred to the description of part of the method embodiment.

Claims

1. A task execution method for chip computing power scheduling, comprising: Obtaining a first task request; determining a plurality of models for executing the first task request; determining a combination of operators required for executing a first task corresponding to the first task request based on operators included in the plurality of models; and determining at least one executable operator in the combination of operators as a first target operator, wherein the executable operator does not need to depend on execution results of other operators and can be directly executed; For a chip that is executing a second task, determining whether the remaining computing resources of the chip satisfy a preset condition; If the result of the determination is positive, determining at least one executable operator corresponding to the second task currently being executed by the chip as a second target operator; and allocating at least a portion of the remaining computing resources of the chip to each of the first target operators, such that the chip performs the first task by executing each of the first target operators in parallel upon executing each of the second target operators, without affecting the computing resources allocated to each of the second target operators by the chip; Allocating at least a portion of the remaining computing resources of the chip to each of the first target operators without affecting the computing resources allocated by the chip to each of the second target operators includes: selecting a combination of candidate operators including the second target operator from a combination of a plurality of parallelizable operators that is predetermined when the chip is in an idle state, the combination of parallelizable operators being a combination of operators that can be executed in parallel, and an execution time of each operator in the combination of the plurality of parallelizable operators that is predetermined within the chip does not exceed a second threshold that is preset; For each of the combinations of the candidate operators, if the number of the first target operators included in the combination of the candidate operators exceeds a first threshold value set in advance, determining the combination of the candidate operators as a combination of the target operators.

23. A task execution method comprising:

2. Determining combinations of operators that can be parallelized is Obtaining a plurality of target models; determining, for each said target model, data transmission dependencies between operators contained in said target model; determining, based on the data transmission dependency relationships of each of the plurality of target models, a combination of operators that have no data transmission dependency relationships among all the operators included in the plurality of target models as the combination of operators that can be parallelized; 2. The method of claim 1 .

3. determining, based on the data transmission dependency relationship of each of the plurality of target models, a combination of operators that do not have a data transmission dependency relationship among all the operators included in the plurality of target models as the combination of operators that can be parallelized; determining a data flow graph corresponding to the target model based on the data transmission dependency determined for each of the target models, in which each node in the data flow graph is used to represent an operator included in the target model, and an edge between two nodes is used to represent the existence of a data transmission dependency between the two nodes; determining a combination of the parallelizable operators based on a plurality of the data flow graphs corresponding to the plurality of target models; 3. The method of claim 2 .

4. Determining a combination of the parallelizable operators based on a plurality of the data flow graphs corresponding to the plurality of target models includes: determining, for each node included in the plurality of data flow graphs, a combination of parallelizable operators corresponding to the node through a plurality of iterations, wherein: For each iteration, determining a combination of goal nodes in the current iteration, the combination including one goal node or multiple goal nodes that have no dependencies on each other; For each other node other than each goal node in the combination of goal nodes included in the plurality of data flow graphs, if the other node does not depend on any goal node in the combination of goal nodes, determining a combination of operators that can be parallelized based on the other node and the combination of the goal node; set the determined combination of parallelizable operators as a combination of target nodes in the next iteration, or sequentially select target nodes in the next iteration from among nodes included in the plurality of data flow graphs until a preset termination condition is satisfied; 4. The method according to claim 3 .

5. Determining a combination of operators that can be parallelized based on a combination of the other nodes and the goal node includes: determining a combination of operators corresponding to the combination of the other node and the goal node as a candidate combination of operators; determining the combination of candidate operators as a combination of operators that can be parallelized if the execution time of the combination of candidate operators within the chip does not exceed a second threshold value set in advance; 5. The method of claim 4.

6. Sequentially selecting a target node in a next iteration from the nodes included in the plurality of data flow graphs includes: sequentially selecting a node from the set of candidate nodes as a goal node in a next iteration; wherein the candidate node set includes all nodes included in the plurality of data flow graphs, the execution time of a corresponding operator in the chip not exceeding a second preset threshold value; 5. The method of claim 4.

7. Determining execution times of the combinations of candidate operators within the chip includes: obtaining relevant characteristics of the candidate operator combination, the relevant characteristics including at least one of the following: a past chip computing amount, a past data bandwidth, a past execution time, and an average, a maximum, a minimum, and a variance of data transmission size of operators included in the candidate operator combination; inputting the related features into a preset prediction model, and predicting and outputting an execution time of the combination of the candidate operators in the chip using the prediction model; 6. The method of claim 5 .

8. A task execution device for chip computing power scheduling, comprising: an acquisition module for acquiring a first task request; a first determination module for determining a plurality of models for executing the first task request, determining a combination of operators required for executing a first task corresponding to the first task request based on operators included in the plurality of models, and determining at least one executable operator in the combination of operators as a first target operator, wherein the executable operator does not need to depend on the execution results of other operators and can be directly executed; For a chip that is executing a second task, a detection module is configured to determine whether the remaining computing resources of the chip satisfy a preset condition; a second determination module for determining, when the determination result of the detection module is positive, at least one executable operator corresponding to the second task currently being executed by the chip as a second target operator; an execution module for allocating at least a portion of the remaining computing resources of the chip to each of the first target operators, without affecting the computing resources allocated by the chip to each of the second target operators, such that the chip performs the first task by executing each of the first target operators in parallel upon executing each of the second target operators; Allocating at least a portion of the remaining computing resources of the chip to each of the first target operators without affecting the computing resources allocated by the chip to each of the second target operators includes: selecting a combination of candidate operators including the second target operator from a combination of a plurality of parallelizable operators that is predetermined when the chip is in an idle state, the combination of parallelizable operators being a combination of operators that can be executed in parallel, and an execution time of each operator in the combination of the plurality of parallelizable operators that is predetermined within the chip does not exceed a second threshold that is preset; For each of the combinations of the candidate operators, if the number of the first target operators included in the combination of the candidate operators exceeds a first threshold value set in advance, determining the combination of the candidate operators as a combination of the target operators.

2. A task execution device comprising:

9. A computer-readable storage medium storing a computer program, the computer program being executed by a processor to perform the method according to any one of claims 1 to 7. A computer-readable storage medium comprising:

10. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable by the processor, the processor executing the program to perform the method according to any one of claims 1 to 7.

1. An electronic device comprising:

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