Semiconductor Device

Abstract

To require no identification number specific to each chip while mitigating area overhead in a laminate-type semiconductor device.SOLUTION: In a semiconductor device, an arithmetic circuit 20 of a chip at a first stage performs predetermined arithmetic operation on an inputted N-bit (N=4) selection signal MF. Similarly, the arithmetic circuit 20 of each of chips at a second stage and succeeding stages included in chip CHIPs at the total of M stages (M>N≥2 and M=16) executes predetermined common arithmetic operation on a calculation result of the arithmetic circuit 20 of a chip at the previous stage. A determination circuit 21 provided at each chip executes predetermined common logic operation on a bit string of a N-bit signal as the operation result of the corresponding arithmetic circuit 20 to thereby determine whether or not the chip is the one selected by the selection signal MF.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and is suitably used, for example, in a semiconductor device having a stacked structure in which a plurality of semiconductor chips are stacked. [Background technology]

[0002] In recent years, stacked semiconductor devices have been developed in which multiple stacked semiconductor chips are housed in a single package and the semiconductor chips are connected via silicon through electrodes (Through Silicon Via: TSV). In this type of semiconductor device, it is necessary to select the semiconductor chip to be accessed from among the multiple semiconductor chips.

[0003] Specifically, in JP 2018-055740 A (Patent Document 1), n ​​through electrodes formed in each memory chip are used to transmit a chip select signal to n memory chips. Through internal wiring of each memory chip, lower pads corresponding to the 1st to (n-1)th through electrodes are connected to upper pads corresponding to the 2nd to nth through electrodes. Furthermore, the lower pad corresponding to the nth through electrode is connected to the upper pad corresponding to the 1st through electrode. Due to such a shift circulation connection, the chip select signal passes through all of the 1st to nth through electrodes while transmitting through the n memory chips. Only the specific through electrode is connected to the internal circuit of each memory chip.

[0004] The semiconductor device disclosed in JP 2012-150565 A (Patent Document 2) includes multiple core chips, each having a unique chip address, and an interface chip that controls them. The interface chip generates a chip selection address from an address signal and a chip selection signal in response to a mode signal. Each core chip includes a comparison circuit that compares the chip selection address with the unique chip address and passes a command if the two match. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-055740 A [Patent Document 2] JP 2012-150565 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the chip selection method disclosed in the above-mentioned JP 2018-055740 A (Patent Document 1), when the number of stacked semiconductor chips is doubled, the number of through electrodes used to transmit chip selection signals is also doubled. Accordingly, the power supply capacity for supplying the chip selection signals also increases, which causes a problem of increased area overhead.

[0007] In the chip selection method disclosed in the above-mentioned JP 2012-150565 A (Patent Document 2), it is necessary to store a unique chip address for each semiconductor chip in advance in a memory or a register, etc. Therefore, it is troublesome to manage the chip addresses, and it cannot be said to be practical.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] In a semiconductor device according to one embodiment, an arithmetic circuit in a first stage chip performs a predetermined arithmetic operation on an input N-bit selection signal. An arithmetic circuit in a second stage chip performs the same arithmetic operation on the result of this operation. In this way, among a total of M stages (M>N≧2) of chips, the arithmetic circuits in the second stage chips and thereafter perform a predetermined common arithmetic operation on the result of the operation of the arithmetic circuit in the previous stage chip. A determination circuit provided in each chip performs a predetermined common logical operation on the bit string of the N-bit signal that is the result of the operation of the corresponding arithmetic circuit, thereby determining whether or not the chip is the one selected by the selection signal. Effect of the Invention

[0010] According to the semiconductor device of the above embodiment, the area overhead is alleviated, and there is no need to previously store a unique chip address for each chip in a memory or the like. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device 100 according to a first embodiment. [Diagram 2] FIG. 13 is a diagram for explaining a module selection method. [Diagram 3] 3 is a diagram for explaining a modification of the module selection method of FIG. 2. FIG. [Figure 4] 3 is a diagram showing a specific example of an arithmetic circuit 20 and a decision circuit 21 in FIG. 2. [Diagram 5] 5 is a diagram for explaining a specific operation of the arithmetic circuit of FIG. 4. [Figure 6] 5 is a diagram showing, in a table format, selection signals MF to be input from the base die 11 in order to select each chip in FIG. 4. [Figure 7] 4 is a diagram showing a specific example of an arithmetic circuit 20 and a decision circuit 21 in FIG. 3. [Figure 8] 8 is a diagram showing, in a table format, selection signals MF to be input from the base die 11 in order to select each chip in FIG. 7. [Figure 9] 5 is a diagram for explaining a specific operation of the arithmetic circuit when the number of chips in FIG. 4 is expanded to 32. FIG. [Figure 10] 5 is a diagram showing, in a table format, selection signals MF to be input from the base die 11 in order to select each chip when the number of chips in FIG. 4 is expanded to 32. FIG. [Figure 11] 11A and 11B are diagrams for explaining the area reduction effect in the semiconductor device of the present embodiment. [Figure 12] FIG. 13 is a diagram showing a specific example of a circuit for chip selection in the stacked semiconductor device according to the second embodiment. [Figure 13] 13 is a diagram for explaining a specific operation of the arithmetic circuit of FIG. 12. [Figure 14] 13 is a diagram showing, in a table format, selection signals MF to be input from the base die 11 in order to select each chip in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, each embodiment will be described in detail with reference to the drawings. In addition, the same or corresponding parts are designated by the same reference characters and description thereof will not be repeated.

[0013] <First embodiment> [Schematic configuration of semiconductor device] Fig. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 in Fig. 1 is a semiconductor package called a high bandwidth memory (HBM). The semiconductor device 100 includes a plurality of memory chips 10, a base die 11, an interposer 12, a system on chip (SoC) 102, and a package substrate 13. Hereinafter, the memory chip 10 will also be simply referred to as a chip 10.

[0014] 1, in a semiconductor device 100, a stacked structure 101 of a memory chip 10 and a base die 11 stacked using TSVs is connected to an SoC 102 via an interposer 12. Specifically, the base die 11 and the SoC 102 are connected to signal lines 17 and bumps 14 formed on the interposer 12.

[0015] Semiconductor integrated circuits are fabricated on the surfaces of the memory chip 10 and the base die 11 using normal semiconductor processes. For example, a dynamic random access memory (DRAM) core circuit is formed on the memory chip 10. An interface (I / F) circuit such as a memory controller, and a physical layer (PHY) circuit for connecting to the SoC 102 are formed on the base die 11. The memory circuits such as the DRAM core circuit mounted on the memory chip 10 are controlled by a processor (PROCESSOR) 103 mounted on the SoC 102.

[0016] The interposer 12 is formed using a Si semiconductor. A large number of fine signal lines 17 are formed in the interposer 12 using semiconductor processing technology. Furthermore, contact plugs (not shown) and through electrodes (not shown) that penetrate the interlayer insulating layer are formed between the bumps 14 on the front surface of the interposer 12 and the back surface bumps 15.

[0017] The package substrate 13 is formed of a printed circuit board (PCB). A plurality of solder balls 16 called a BGA (Ball Grid Array) are formed on the lower surface of the package substrate 13 as external connection terminals.

[0018] [Principle of chip selection method] Next, the principle of the chip selection method in the semiconductor device of this embodiment will be described with reference to Figures 2 and 3. In the following, a more general method of selecting a module will be described when the semiconductor device 200 includes M modules MOD_0 to MOD_M-1 connected in cascade. In this case, the M modules are not limited to a stacked structure, and are not limited to memory chips.

[0019] Fig. 2 is a diagram for explaining a module selection method. Referring to Fig. 2, the semiconductor device 200 includes cascaded modules MOD_0 to MOD_M-1 of M stages each having a common circuit configuration. Hereinafter, any one of the modules MOD_0 to MOD_M-1 of the M stages will be referred to as a module MOD.

[0020] Each module MOD includes an arithmetic circuit (ARITHMETIC CIRCUIT) 20 and a determination circuit (DETERMINATION CIRCUIT) 21. These circuits are used for module selection and are common to each module MOD.

[0021] As shown in FIG. 2, an N-bit selection signal MF[0:N-1] is input from an interface circuit (I / F) 23 to the arithmetic circuit 20 of the first-stage module MOD_0. M and N have a relationship of M>N≧2. Usually, M=2 N The selection signal MF is a signal for selecting one of the modules MOD_0 to MOD_M-1 in the M stages.

[0022] The arithmetic circuit 20 of the first-stage module MOD_0 performs an N-bit arithmetic operation on the input N-bit selection signal MF. The N-bit signal generated as a result of this arithmetic operation is input to the decision circuit 21 of the first-stage module MOD_0 as a decision signal MB[0:N-1].

[0023] An N-bit signal which is the result of the operation of the operation circuit 20 of the first-stage module MOD_0 is input to the operation circuit 20 of the second-stage module MOD_1. The operation circuit 20 of the second-stage module MOD_1 performs the same arithmetic operation on the input N-bit signal as the operation circuit 20 of the first-stage module MOD_0. The N-bit signal generated as a result of this arithmetic operation is input to the decision circuit 21 of the second-stage module MOD_1 as a decision signal MB[0:N-1].

[0024] The same is true for the arithmetic circuit 20 of each module MOD from the third stage to the Mth stage. That is, each arithmetic circuit 20 performs the same arithmetic operation as the arithmetic circuit 20 of the first stage module MOD_0 on the N-bit signal that is the operation result of the arithmetic circuit 20 of the previous stage module MOD. That is, the arithmetic operation performed by each arithmetic circuit 20 is the same arithmetic operation commonly defined for the M stage modules MOD_0 to MOD_M-1. In each module MOD, the N-bit signal that is the operation result of the arithmetic circuit 20 is input to the judgment circuit 21 as a judgment signal MB[0:N-1].

[0025] Here, an N-bit arithmetic operation can be determined so that the operation results of each of the arithmetic circuits 20 of the M-stage modules MOD_0 to MOD_M-1 are different. For example, an arithmetic operation of adding "1" to an input N-bit signal generates a different operation result for each module MOD, regardless of the selection signal MF that is input first. That is, each arithmetic circuit 20 may be an N-bit adder that adds "1". By expanding on this, it can be easily understood that each arithmetic circuit 20 may be an N-bit adder that adds a predetermined odd number, such as "11" or "101".

[0026] Similarly, an arithmetic operation of subtracting "1" from an input N-bit signal generates a different operation result for each module MOD, regardless of the selection signal MF that is input initially. That is, each arithmetic circuit 20 may be an N-bit subtractor that subtracts "1". By expanding on this, it can be easily understood that each arithmetic circuit 20 may be an N-bit subtractor that subtracts a predetermined odd number.

[0027] Next, each decision circuit 21 decides whether or not the bit sequence of the input decision signal MB[0:N-1] matches a specific bit sequence. The specific bit sequence is commonly defined for the M-stage modules MOD_0 to MOD_M-1. More specifically, each decision circuit 21 generates an enable signal (EN SIGNAL) 22 by performing a logical operation using the value of each bit of the input decision signal MB[0:N-1]. This logical operation is commonly defined for the M-stage modules MOD_0 to MOD_M-1. When the bit sequence of the input decision signal MB[0:N-1] matches the specific bit sequence, the enable signal 22 is asserted.

[0028] The internal circuitry of each module MOD becomes operable upon receiving the asserted enable signal 22. For example, a case will be described in which a controller (not shown, corresponding to the processor 103 in FIG. 1) provided in the semiconductor device 200 operates the internal circuitry of a selected module MOD. In this case, the controller determines the selection signal MF so that the enable signal 22 generated by the determination circuit 21 of the selected module MOD is asserted. Then, the controller causes the interface circuit 23 to input the determined selection signal MF to the first-stage module MOD_0.

[0029] 3 is a diagram for explaining a modification of the module selection method of FIG. 2. In the case of FIG. 3, an N-bit selection signal MF is input from an interface circuit 23 to a decision circuit 21 of a first-stage module MOD_0, instead of the operation result of the arithmetic circuit 20 of the first-stage module MOD_0. Similarly, an N-bit signal, which is the operation result of the arithmetic circuit 20 of the module MOD of the previous stage, is input to a decision circuit 21 of each of the modules MOD from the second stage to the Mth stage. In this way, the semiconductor device 200 of FIG. 3 differs from the semiconductor device 200 of FIG. 2 in the decision signal MB[0:N-1] input to each decision circuit 21. Furthermore, in the case of FIG. 3, the arithmetic circuit 20 may not be provided in the module MOD_M-1, which is the final stage.

[0030] Other points in Fig. 3 are the same as those in Fig. 2, so the same or corresponding parts are given the same reference characters and description will not be repeated. In the case of Fig. 3, by changing the selection signal MF output from the interface circuit 23, the enable signal 22 generated by the desired chip 10 can be asserted.

[0031] [Specific example of an arithmetic circuit and an enable signal generation circuit (part 1)] Next, a description will be given of a specific example of the arithmetic circuit 20 and the decision circuit 21 in Fig. 2 and Fig. 3. Fig. 4 is a diagram showing a specific example of the arithmetic circuit 20 and the decision circuit 21 in Fig. 2.

[0032] 4 shows an example in which 16 memory chips 10 are provided as a stacked structure 101 of a semiconductor device 100. In Fig. 4, the 16 memory chips 10 are described as CHIP_0 to CHIP_15. The memory chips CHIP_0 to CHIP_15 correspond to the modules MOD_0 to MOD_15 (where M=16) in Fig. 2, respectively.

[0033] A 4-bit selection signal MF[0:3] is used to select one of these memory chips CHIP_0 to CHIP_15. The least significant bit (first bit) of the selection signal MF[0:3] is described as MF0. The second bit is described as MF1. The third bit is described as selection signal MF2. The most significant bit (fourth bit) is described as selection signal MF3. The same applies to the determination signal MB[0:3].

[0034] As shown in Fig. 4, the arithmetic circuits 20 provided in adjacent memory chips CHIP are connected to each other by four signal lines, which is equal to the number of bits N of the selection signal MF. Therefore, in the example of Fig. 4, an N-bit signal is transmitted in parallel for each bit. Each signal line includes a TSV.

[0035] Each arithmetic circuit 20 is configured as a 4-bit adder that adds "1" to an input N-bit signal. Specifically, the arithmetic circuit 20 includes a NOT circuit 30, exclusive OR circuits 31 to 33, and AND circuits 34 and 35. To obtain a first bit output, the NOT circuit 30 inverts the first bit input. To obtain a second bit output, the exclusive OR circuit 31 calculates the exclusive OR of the first bit input and the second bit input. To obtain a third bit output, the AND circuit 34 first calculates the AND of the first bit input and the second bit input. Next, the exclusive OR circuit 32 calculates the exclusive OR of the output of the AND circuit 34 and the third bit input, thereby generating a third bit output. To obtain a fourth bit output, the AND circuit 35 first calculates the AND of the first bit input, the second bit input, and the third bit input. Next, the exclusive OR circuit 33 calculates the exclusive OR of the output of the AND circuit 35 and the fourth bit input, thereby generating the fourth bit output.

[0036] Each decision circuit 21 includes a logical AND circuit 36 ​​that calculates the logical AND of each bit of the decision signal MB[0:3] output from the corresponding arithmetic circuit 20. Therefore, when "1111" is output as the decision signal MB from the corresponding arithmetic circuit 20, the enable signal 22 output from the decision circuit 21 is asserted to "1." When a decision signal MB of any other value is output from the corresponding arithmetic circuit 20, the enable signal 22 output from the decision circuit 21 is negated to "0."

[0037] Fig. 5 is a diagram for explaining the specific operation of the arithmetic circuit of Fig. 4. Fig. 5 shows in table form the judgment signal MB input to the judgment circuit 21 of each chip CHIP when "1111" is input as the selection signal MF[0:3] from the base die (BASE DIE) 11. To facilitate illustration, the bit "1" is hatched.

[0038] 5, the determination signal MB input to the determination circuit 21 of the 16th stage chip CHIP_15 becomes "1111." Therefore, the enable signal 22 output from the determination circuit 21 of the 16th stage chip CHIP_15 is asserted to "1." In other words, when "1111" is input as the selection signal MF[0:3] from the base die 11, the 16th stage chip CHIP_15 is selected.

[0039] 6 is a diagram showing, in a table format, the selection signal MF to be input from the base die 11 to select each chip in FIG. 4. As shown in FIG. 6, by changing the selection signal MF[0:3] input from the base die 11, each chip 10 can be uniquely selected. The correspondence between the selection signal MF[0:3] and the selected chip 10 is determined by the stacking order of the chip 10. Therefore, in the case of this embodiment, a register or memory for storing a unique identification number for each chip 10 is not required.

[0040] [Specific example of arithmetic circuit and enable signal generation circuit (part 2)] FIG. 7 is a diagram showing a specific example of the arithmetic circuit 20 and the judgment circuit 21 in FIG. 3. In the case of the stacked structure 101 in FIG. 7, the judgment signal MB input to the judgment circuit 21 is not the arithmetic result of the corresponding arithmetic circuit 20 of the same memory chip 10. The selection signal MF is input from the interface circuit 23 of the base die 11 as the judgment signal MB to the judgment circuit 21 of the first memory chip CHIP_0. The arithmetic result of the arithmetic circuit 20 of the preceding memory chip CHIP is input as the judgment signal MB to the judgment circuit 21 of the second or subsequent memory chip CHIP. In this respect, the stacked structure 101 in FIG. 7 differs from the stacked structure 101 in FIG. 4. Since the other points in FIG. 7 are the same as those in FIG. 4, the same or corresponding parts are given the same reference symbols and description will not be repeated.

[0041] Fig. 8 is a diagram showing, in a table format, the selection signal MF to be input from the base die 11 in order to select each chip in Fig. 7. As shown in Fig. 8, by changing the selection signal MF input from the base die 11, each chip 10 can be uniquely selected.

[0042] [Specific example of arithmetic circuit and enable signal generation circuit (part 3)] Next, a case will be described in which the number of memory chips 10 is expanded from 16 to 32 in the specific example (part 1) described in Figures 4 to 6. In this case, the selection signal MF and the determination signal MB are changed to 5-bit signals. Each arithmetic circuit 20 is configured as a 5-bit adder that adds "1" to the input 5-bit signal.

[0043] FIG. 9 is a diagram for explaining the specific operation of the arithmetic circuit when the number of chips in FIG. 4 is expanded to 32. In FIG. 9, the judgment signal MB input to the judgment circuit 21 of each chip 10 is shown in a table format when "11111" is input as the selection signal MF[0:4] from the base die (BASE DIE) 11. As in the case of FIG. 5, the bit "1" is hatched to facilitate illustration. Also, the first to fourth bits of the selection signal MF[0:4] are written as MF0 to MF3, and the most significant bit (fifth bit) is written as MF4. The same applies to the judgment signal MB[0:4].

[0044] 9, the calculation result of the calculation circuit 20 of the 32nd stage chip CHIP_31 (CHIP 31) is "11111." Therefore, the output of the decision circuit 21 of the 32nd stage chip CHIP_31 is asserted to "1." In other words, when "11111" is input from the base die 11 as the selection signal MF[0:4], the 31st stage chip CHIP_31 is selected.

[0045] 10 is a diagram showing, in a table format, the selection signal MF to be input from the base die 11 to select each chip when the number of chips in FIG. 4 is expanded to 32. As shown in FIG. 10, by changing the selection signal MF[0:4] input from the base die 11, each chip 10 can be uniquely selected. Therefore, compared to the case of FIG. 6, even if the number of chips is doubled, the number of bits of the selection signal MF increases by only one bit. This makes it possible to suppress an increase in the area of ​​the circuit for chip selection.

[0046] [Advantages of the first embodiment] As described above, according to the semiconductor device 100 of the first embodiment, in order to select a stacked memory chip 10, an arithmetic circuit 20 and a judgment circuit 21 are provided in each chip 10. The circuit configurations of the arithmetic circuit 20 and the judgment circuit 21 are the same regardless of the chip 10. The arithmetic circuit 20 performs an N-bit arithmetic operation on an input N-bit signal. For example, the arithmetic circuit 20 is configured as an N-bit adder that adds an odd number to an input N-bit signal. An N-bit selection signal MF is input to the arithmetic circuit 20 of the first-stage memory chip 10. The arithmetic circuit 20 of the second-stage or later memory chip 10 receives the operation result of the arithmetic circuit 20 of the previous-stage memory chip 10. The arithmetic circuit 20 of the corresponding memory chip 10 is input to the judgment circuit 21 as a judgment signal MB. The judgment circuit 21 executes a logical operation using the value of each bit of the judgment signal MB, and asserts an enable signal 22 when the bit string of the judgment signal MB is equal to a specific bit string.

[0047] With this configuration, there is no need to define a unique identification number for each memory chip 10. Any one of the memory chips 10 can be uniquely selected by inputting a selection signal MF based on the stacking order of the memory chips 10. Furthermore, M signal lines are not required to select one of the M stages of memory chips 10. Since an N-bit selection signal MF (M>N≧2) is used, the circuit area required for chip selection can be reduced.

[0048] 11 is a diagram for explaining the area reduction effect in the semiconductor device of this embodiment. Specifically, the graph in FIG. 11 shows the area reduction effect of the circuit portion necessary for chip selection in comparison with the method disclosed in JP 2018-055740 A (Patent Document 1) described in the background art. The horizontal axis of FIG. 11 is chip size (CHIP SIZE) [mm 2 ], and the vertical axis shows the area reduction ratio (AREA REDUCTION RATIO) [%].

[0049] Referring to FIG. 11, the number of stacked chips is set to 16, and the chip size is set to 100 mm 2 In this case, there will be an area reduction effect of about 3% compared to conventional technology. In the future, if the minimum line width of the semiconductor process is reduced and the chip size is reduced to 70%, an area reduction effect of about 4% can be expected. Furthermore, the area reduction effect will increase further if the number of stacked chips is increased from 16 to 32.

[0050] <Second embodiment> In the second embodiment, a case will be described in which the arithmetic circuit 20 provided in each chip 10 is configured with a subtraction circuit instead of an addition circuit.

[0051] Fig. 12 is a diagram showing a specific example of a circuit for chip selection in the stacked semiconductor device of the second embodiment. In the stacked structure 101 of Fig. 12, each arithmetic circuit 20 is configured as an N-bit subtractor that subtracts "1" from an input N-bit (N=4) signal. In this respect, the stacked structure 101 of Fig. 12 differs from the stacked structure 101 of Fig. 4. Since the other points in Fig. 12 are the same as those in Fig. 4, the same reference characters are used to designate the same or corresponding parts and description will not be repeated.

[0052] Fig. 13 is a diagram for explaining the specific operation of the arithmetic circuit of Fig. 12. Fig. 13 shows in table form the judgment signal MB input to the judgment circuit 21 of each chip CHIP when "1111" is input as the selection signal MF[0:3] from the base die (BASE DIE) 11. To facilitate illustration, the bit "1" is hatched.

[0053] 13, "1111", which is the calculation result of the calculation circuit 20 of the 16th stage chip CHIP_15, is input to the judgment circuit 21 as the judgment signal MB. Therefore, the enable signal 22 output from the judgment circuit 21 of the 16th stage chip CHIP_15 is asserted to "1." In other words, when "1111" is input from the base die 11 as the selection signal MF[0:3], the 16th stage chip CHIP_15 is selected.

[0054] 14 is a diagram showing, in table form, the selection signal MF to be input from the base die 11 to select each chip in FIG. 12. As shown in FIG. 14, by changing the selection signal MF[0:3] input from the base die 11, each chip CHIP can be uniquely selected. The correspondence between the selection signal MF[0:3] and the chip CHIP is determined by the stacking order of the chip CHIP. Therefore, there is no need for a register or memory for storing a unique identification number for each chip CHIP.

[0055] [Effects of the second embodiment] As described above, in the semiconductor device 100 of the second embodiment, similarly to the first embodiment, there is no need to define a unique identification number for each memory chip 10. Any one of the memory chips 10 can be uniquely selected by inputting a selection signal MF based on the stacking order of the memory chips 10. In addition, since an N-bit selection signal MF (M>N≧2) is used to select one of the M stages of memory chips 10, the circuit area required for chip selection can be reduced.

[0056] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0057] 10,CHIP memory chip, 11 base die, 12 interposer, 13 package substrate, 14 bump, 15 back bump, 16 solder ball, 17 signal line, 20 arithmetic circuit, 21 judgment circuit, 22 enable signal, 23 interface circuit, 30 NOT circuit, 31-33 exclusive OR circuit, 34-36 logical AND circuit, 100,200 semiconductor device, 101 stacked structure, MF selection signal, MB judgment signal, MOD module.

Claims

1. M stages of modules connected in series, each including an arithmetic circuit and a decision circuit; an interface circuit for inputting an N-bit selection signal (M>N≧2) for selecting one of the M-stage modules to the arithmetic circuit of the first-stage module; the arithmetic circuit of the first stage module performs an N-bit arithmetic operation on the N-bit selection signal; the arithmetic circuit of each of the modules from the second stage to the Mth stage performs an arithmetic operation of N bits identical to that performed by the arithmetic circuit of the module in the first stage on an N-bit signal that is a result of the operation of the arithmetic circuit of the module in the previous stage, and the results of the operation of each of the arithmetic circuits of the modules in the Mth stage are different from one another; In each of the M stage modules, the judgment circuit receives an input of an N-bit signal which is the result of the calculation of the arithmetic circuit, and determines whether or not the bit sequence of the input N-bit signal matches a specific bit sequence commonly determined in the M stage modules.

2. A semiconductor device comprising: The system includes M stages of modules connected in cascade, Each of the modules from the first stage to the (M-1)th stage includes an arithmetic circuit, Each of the M stages of modules includes a decision circuit; The semiconductor device further comprises: an interface circuit for inputting an N-bit selection signal (M>N≧2) for selecting one of the M-stage modules to the arithmetic circuit and the decision circuit of a first-stage module; the arithmetic circuit of the first stage module performs an N-bit arithmetic operation on the input N-bit selection signal; the arithmetic circuit of each module from the second stage to the (M-1)th stage performs an N-bit arithmetic operation identical to that performed by the arithmetic circuit of the first stage module on an N-bit signal that is a result of the operation of the arithmetic circuit of the module in the previous stage, and the results of the operation of the arithmetic circuit of each module are different from one another; The determination circuit of the first stage module determines whether or not a bit string of the input N-bit selection signal matches a specific bit string; The judgment circuit of each module from the second stage to the Mth stage receives an input of an N-bit signal which is the result of the calculation by the arithmetic circuit of the module of the previous stage, and judges whether the bit string of the input N-bit signal matches the specific bit string.

3. 3. The semiconductor device according to claim 1, wherein each of the arithmetic circuits is an N-bit adder that adds a predetermined odd number to an input N-bit signal, or an N-bit subtractor that subtracts a predetermined odd number from an input N-bit signal.

4. 4. The semiconductor device according to claim 3, wherein the predetermined odd number is one.

5. The M is 2 Ｎ 3. The semiconductor device according to claim 1, wherein

6. 3. The semiconductor device according to claim 1, wherein the arithmetic circuits of two adjacent modules are connected to each other via N signal lines.

7. 3. The semiconductor device according to claim 1, wherein in each of the M stage modules, the determination circuit generates an enable signal by performing a common logical operation in the M stage modules using the values ​​of each bit of an input N-bit signal, and when a bit sequence of the N-bit signal input to the determination circuit matches the specific bit sequence, the enable signal is asserted.

8. 8. The semiconductor device according to claim 7, wherein an internal circuit of each of said M stages of modules is made operable by receiving said enable signal asserted.

9. The semiconductor device is a stacked type semiconductor device including M stacked chips, 8. The semiconductor device according to claim 7, wherein said M stages of modules correspond to said M chips, respectively.

10. 10. The semiconductor device according to claim 9, wherein each of the M chips includes a memory circuit, and the chips are connected to each other via a plurality of TSVs (Through Silicon Vias).

11. A chip having a processor that accesses the memory circuit mounted on each of the M chips is further provided, 11. The semiconductor device according to claim 10, wherein when accessing the memory circuit of a selected chip among the M chips, the processor determines the selection signal so that the enable signal generated by the judgment circuit of the selected chip is asserted, and causes the determined selection signal to be input to the arithmetic circuit of a first stage module by the interface circuit.

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