Method and apparatus for precise data conditioning for analog neural memories in artificial neural networks - Patents.com

Abstract

To provide a precision programming algorithm, device, and method for precisely and rapidly depositing a precise amount of charges on floating gates of non-volatile memory cells in vector matrix multiplication (VMM) arrays in an artificial neural network.SOLUTION: An adjustment and compensation method that may be performed by an algorithmic controller within a VMM system includes: generating an adaptive target based on a final error resulting from a cell output and an original target of the cell; determining an initial current target for the selected cell or group of selected cells by using a predictive target model by, for example, using a function or lookup table, and setting a variable DeltaError to be 0; and executing soft erasing of each cell to an intermediate weak erase level and performing a soft erasing on all unused cells to reach a <pA current level for all cells in the VMM.SELECTED DRAWING: Figure 34

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 957,013, entitled "Precise Data Tuning Method And Apparatus For Analog Neuromorphic Memory In An Artificial Neural Network," filed on January 3, 2020, and U.S. Patent Application No. 16 / 829,757, entitled "Precise Data Tuning Method And Apparatus For Analog Neural Memory In An Artificial Neural Network," filed on March 25, 2020.

[0002] FIELD OF THEINVENTION Numerous embodiments are disclosed for a precision-tuned method and apparatus for precisely and rapidly depositing precise amounts of charge onto the floating gates of non-volatile memory cells in vector matrix multiplication (VMM) arrays in artificial neural networks. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain), and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the artificial neural network to adapt to the inputs and learn. Typically, an artificial neural network contains multiple layers of inputs. There is typically one or more intermediate layers of neurons, and an output layer of neurons that provides the output of the neural network. At each level, the neurons make decisions, either individually or together, based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical artificial neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Serial No. 15 / 594,439, published as U.S. Patent Publication 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. As used herein, the term neuromorphic refers to a circuit that implements a model of a neural system. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells are configured to multiply a first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs. An array of memory cells arranged in this manner may be referred to as a vector matrix multiplication (VMM) array.

[0007] Each non-volatile memory cell used in a VMM array must hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate in response to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256. One challenge is the ability to program selected cells with the precision and granularity required for the different values ​​of N. For example, if a selected cell can contain one of 64 different values, then extremely high precision is required in the program operation.

[0008] What is needed is an improved programming system and method suitable for use with VMM arrays in analog neuromorphic memories. Summary of the Invention

[0009] Numerous embodiments are disclosed of precision-tuned algorithms and apparatus for precisely and rapidly depositing precise amounts of charge onto the floating gates of non-volatile memory cells in a VMM array in an analog neuromorphic memory system, such that selected cells can be programmed with extreme precision to hold one of N different values.

[0010] In one embodiment, a method for tuning a selected non-volatile memory cell in a vector matrix multiplication array of non-volatile memory cells is provided, the method comprising: (i) setting an initial current target for the selected non-volatile memory cell; (ii) performing a soft erase on all non-volatile memory cells in the vector matrix multiplication array; (iii) performing a coarse programming operation on the selected memory cell; (iv) performing a fine programming operation on the selected memory cell; (v) performing a read operation on the selected memory cell and determining a current drawn by the selected memory cell during the read operation; (vi) calculating an output error based on a difference between the determined current and the initial current target; and repeating steps (i), (ii), (iii), (iv), (v), and (vi) until the output error is less than a predetermined threshold.

[0011] In another embodiment, a method for tuning a selected non-volatile memory cell in a vector matrix multiplication array of non-volatile memory cells is provided, the method comprising the steps of: (i) setting an initial target for the selected non-volatile memory cell; (ii) performing a programming operation on the selected memory cell; (iii) performing a read operation on the selected memory cell and determining a cell output drawn by the selected memory cell during the read operation; (iv) calculating an output error based on a difference between the determined output and the initial target; and (v) repeating steps (i), (ii), (iii), and (iv) until the output error is less than a predetermined threshold.

[0012] In another embodiment, a neuron output circuit is provided for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit including a first adjustable current source for generating a scaled current in response to neuron currents implementing positive weights and a second adjustable current source for generating the scaled current in response to neuron currents implementing negative weights.

[0013] In another embodiment, a neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array includes an adjustable capacitor having a first terminal and a second terminal, the second terminal providing an output voltage to the neuron output circuit, a control transistor having a first terminal and a second terminal, a first switch selectively coupled between the first terminal and the second terminal of the adjustable capacitor, a second switch selectively coupled between the second terminal of the adjustable capacitor and the first terminal of the control transistor, and an adjustable current source coupled to the second terminal of the control transistor.

[0014] In another embodiment, a neuron output circuit is provided for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit including: an adjustable capacitor having a first terminal and a second terminal, the second terminal providing an output voltage to the neuron output circuit; a control transistor having a first terminal and a second terminal; a switch selectively coupled between the second terminal of the adjustable capacitor and the first terminal of the control transistor; and an adjustable current source coupled to the second terminal of the control transistor.

[0015] In another embodiment, a neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array includes an adjustable capacitor having a first terminal and a second terminal, the first terminal providing an output voltage to the neuron output circuit, a control transistor having a first terminal and a second terminal, a first switch selectively coupled between the first terminal of the adjustable capacitor and the first terminal of the control transistor, and an adjustable current source coupled to the second terminal of the control transistor.

[0016] In another embodiment, a neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit includes a first operational amplifier having an inverting input, a non-inverting input, and an output, a second operational amplifier having an inverting input, a non-inverting input, and an output, a first adjustable current source coupled to the inverting input of the first operational amplifier, a second adjustable current source coupled to the inverting input of the second operational amplifier, a first adjustable resistor coupled to the inverting input of the first operational amplifier, a second adjustable resistor coupled to the inverting input of the second operational amplifier, and a third adjustable resistor coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier.

[0017] In another embodiment, a neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit includes a first operational amplifier having an inverting input, a non-inverting input, and an output; a second operational amplifier having an inverting input, a non-inverting input, and an output; a first adjustable current source coupled to the inverting input of the first operational amplifier; a second adjustable current source coupled to the inverting input of the second operational amplifier; a first switch coupled between the inverting input and the output of the first operational amplifier; a second switch coupled between the inverting input and the output of the second operational amplifier; a first adjustable capacitor coupled between the inverting input and the output of the first operational amplifier; a second adjustable capacitor coupled between the inverting input and the output of the second operational amplifier; and a third adjustable capacitor coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier.

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[0071] [Brief description of the drawings]

[0072] [Figure 1] FIG. 1 illustrates a prior art artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8]FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more VMM arrays. [Figure 9] FIG. 1 is a block diagram showing a VMM system including a VMM array and other circuits. [Figure 10] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 11] 1 illustrates another embodiment of a VMM array. [Figure 12] 1 illustrates another embodiment of a VMM array. [Figure 13] 1 illustrates another embodiment of a VMM array. [Figure 14] 1 illustrates another embodiment of a VMM array. [Figure 15] 1 illustrates another embodiment of a VMM array. [Figure 16] 1 illustrates another embodiment of a VMM array. [Figure 17] 1 illustrates another embodiment of a VMM array. [Figure 18] 1 illustrates another embodiment of a VMM array. [Figure 19] 1 illustrates another embodiment of a VMM array. [Figure 20] 1 illustrates another embodiment of a VMM array. [Figure 21] 1 illustrates another embodiment of a VMM array. [Figure 22] 1 illustrates another embodiment of a VMM array. [Figure 23] 1 illustrates another embodiment of a VMM array. [Figure 24] 1 illustrates another embodiment of a VMM array. [Diagram 25] 1 shows a prior art long-term and short-term memory system. [Figure 26] An exemplary cell for use in a long- and short-term memory system is shown. [Figure 27] 27 illustrates an embodiment of the exemplary cell of FIG. 26. [Figure 28] 27 illustrates another embodiment of the exemplary cell of FIG. 26. [Figure 29]1 shows a prior art gated recurrent unit system. [Diagram 30] 1 shows an exemplary cell for use in a gated recurrent unit system. [Diagram 31] 31 illustrates an embodiment of the exemplary cell of FIG. 30. [Diagram 32] 31 illustrates another embodiment of the exemplary cell of FIG. 30. [Diagram 33] 1 shows a VMM system. [Diagram 34] The adjustment and correction method is shown. [Figure 35A] The adjustment and correction method is shown. [Figure 35B] A sector adjustment correction method is shown. [Figure 36A] 4 illustrates the effect of temperature on the value stored in the cell. [Figure 36B] This paper describes a problem caused by data drift during the operation of a VMM system. [Figure 36C] 4 shows a block for compensating for data drift. [Figure 36D] 1 shows a data drift monitor. [Figure 37] 2 shows a bit line compensation circuit. [Figure 38] 4 illustrates another bit line compensation circuit. [Figure 39] 4 illustrates another bit line compensation circuit. [Diagram 40] 4 illustrates another bit line compensation circuit. [Diagram 41] 4 illustrates another bit line compensation circuit. [Diagram 42] 4 illustrates another bit line compensation circuit. [Diagram 43] Shows neuronal circuits. [Diagram 44] 1 shows another neuron circuit. [Diagram 45] 1 shows another neuron circuit. [Diagram 46] 1 shows another neuron circuit. [Figure 47] 1 shows another neuron circuit. [Figure 48] 1 shows another neuron circuit. [Figure 49A] A block diagram of an output circuit is shown. [Figure 49B] 4 shows a block diagram of another output circuit. [Figure 49C] 4 shows a block diagram of another output circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0073] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. [Non-volatile memory cell]

[0074] Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18) and a second portion extending upwardly over the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline terminal 24 is coupled to the drain region 16.

[0075] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0076] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electron current flows from the source region 14 (source line terminal) towards the drain region 16. The electrons accelerate and are heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0077] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0078] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0079] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2 with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0v / -8V) during erasure, and a low or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are biased similarly to those of Figure 2.

[0080] FIG. 4 shows a four-gate memory cell 410 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0081] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 2: Operation of Flash Memory Cell 410 of FIG. [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0082] Figure 5 shows a memory cell 510 similar to memory cell 410 of Figure 4, except that memory cell 510 does not include an erase gate (EG) terminal. Erasing is accomplished by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar to those of Figure 4.

[0083] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (where erasure occurs through the use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0084] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. 6 [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0085] Figure 7 shows another type of flash memory cell, a stacked gate memory cell 710. Memory cell 710 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a wordline) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner as previously described for memory cell 210.

[0086] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 710 of FIG. [Table 4]

[0087] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output at the source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0088] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0089] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), making every cell in the memory array very precisely and individually adjustable, and making the memory array ideal for storing and fine-tuning the synaptic weights of a neural network.

[0090] The methods and means described herein can be applied to other non-volatile memory technologies, such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive RAM), PCM (phase change RAM), MRAM (magnetoresistive RAM), FeRAM (ferroelectric RAM), OTP (bi-level or multi-level one-time programmable) and CeRAM (strongly correlated electron RAM). The methods and means described herein can be applied to, but not limited to, volatile memory technologies used in neural networks, such as SRAM, DRAM, and other volatile synapse cells. [Neural network using non-volatile memory cell array]

[0091] 8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using the non-volatile memory array-based neural network.

[0092] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel being 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., called filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0093] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0094] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g. to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e. 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from consecutive non-overlapping 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0095] Each layer of synapses is implemented using an array or part of an array of non-volatile memory cells.

[0096] FIG. 9 is a block diagram of a system that can be used for that purpose. The VMM system 32 includes non-volatile memory cells and is used as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM system 32 includes a VMM array 33 including non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37 that decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0097] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient with in-place memory computation.

[0098] The outputs of the VMM array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive and negative weight inputs to output a single value.

[0099] The summed output values ​​of the differential summer 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other non-linear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the VMM array 33 constitutes a number of synapses (which receive input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and the activation function circuit 39 constitute a number of neurons.

[0100] The inputs to the VMM system 32 of FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0101] FIG. 10 is a block diagram illustrating the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s) to the input VMM system 32a.

[0102] The output generated by the input VMM system 32a is then provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as an input to the input VMM system (hidden level 2) 32c, and so on. The various layers of the VMM systems 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can be a standalone physical system that includes a corresponding non-volatile memory array, or the multiple VMM systems can utilize different portions of the same physical non-volatile memory array, or the multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can also be time multiplexed to various portions of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. [VMM Array]

[0103] 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array could be located at the bottom.

[0104] In the VMM array 1100, control gate lines such as control gate line 1103 run vertically (so that row-wise reference array 1102 is orthogonal to control gate line 1103) and erase gate lines such as erase gate line 1104 run horizontally. Here, inputs to the VMM array 1100 are provided to the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0105] As described herein for neural networks, the non-volatile memory cells of VMM array 1100, ie, the flash memory of VMM array 1100, are preferably configured to operate in the sub-threshold region.

[0106] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * T / q, k is the Boltzmann constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is equal to (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0107] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0108] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io]

[0109] where wp is the w of the reference or periphery memory cell.

[0110] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=w for each memory cell in the memory array.

[0111] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0112] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=β * (Vgs-Vth) * Vds; β=u * Cox * Wt / L W α (Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0113] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0114] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0115] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * β * (Vgs-Vth) 2 ; β=u * Cox * Wt / L W α (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0116] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0117] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation).

[0118] Other embodiments for the VMM array 33 of Figure 9 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0119] FIG. 12 shows a neuron VMM array 1200 that is particularly suitable for the memory cells 210 shown in FIG. 2 and used as synapses between an input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 arranged in the columns of the array serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (only some of which are shown) with current inputs flowing into them. The reference cells are adjusted (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0120] Memory array 1203 serves two purposes. First, it stores the weights used by VMM array 1200 in each memory cell. Second, memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1201 and 1202 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory cell array 1203, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which are the inputs to the next layer or the last layer. Having memory array 1203 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on bit lines BL0-BLN, respectively, during a read (inference) operation. The current placed on each bit line BL0-BLN performs a function of the sum of the currents from all non-volatile memory cells connected to that particular bit line.

[0121] Table 5 shows the operating voltages for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations. Table 5: Operation of VMM Array 1200 in FIG. 12 [Table 5]

[0122] FIG. 13 illustrates a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of synapses and neurons between an input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 run in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1300. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0123] Table 6 shows the operating voltages for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in FIG. 13 [Table 6]

[0124] 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 to voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexers 1412 each include a respective multiplexer 1405 and cascoding transistor 1404 to ensure a constant voltage on the bit line (e.g., BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are adjusted to a target reference level.

[0125] Memory array 1403 serves two purposes. First, it stores the weights used by VMM array 1400. Second, memory array 1403 stores the weights that are provided to the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3) and reference arrays 1401 and 1402 convert these current inputs into input voltages that are provided to the control gates (CG0, CG1, CG2, and CG3). ) is multiplied by weights stored in the memory cell array and then all the results (cell currents) are added together to produce an output that appears on BL0-BLN and serves as the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions removes the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current applied to each bit line performs a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0126] The VMM array 1400 performs one-way adjustment of the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (such as an incorrect value being stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached. Table 7 shows the operating voltages for the VMM array 1400. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1400 in FIG. 14 [Table 7]

[0127] 15 shows a neuron VMM array 1500 that is particularly suited for memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between an input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells; The first non-volatile reference memory cell Reference Array 150 1 and, and a second reference array 1502 of non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 run vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 run horizontally. VMM array 1500 is similar to VMM array 1400, except that VMM array 1500 implements bidirectional tuning, whereby each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1501 and 1502 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1514), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums up all the currents from the non-volatile memory cells connected to that particular bit line.

[0128] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in FIG. 15 [Table 8]

[0129] 16 shows a neuron VMM array 1600 that is particularly suited for memory cells 210 shown in FIG. 2 and is used as part of synapses and neurons between an input layer and the next layer. In the VMM array 1600, inputs INPUT0, ..., INPUT Nare bit lines BL0, ..., BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0130] 17 illustrates a neuron VMM array 1700 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0131] 18 illustrates a neuron VMM array 1800 that is particularly suited for memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M are received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0132] 19 shows a neuron VMM array 1900 that is particularly suited for memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M are received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0133] 20 shows a neuron VMM array 2000 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0、 ..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0134] 21 shows a neuron VMM array 2100 that is particularly suited for memory cells 410 shown in FIG. 4 and is used as part of synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are bit lines BL0, ..., BL N , 2901-(N-1) and 2901-N, which are coupled to the source lines SL0 and SL1, respectively. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0135] 22 shows a neuron VMM array 2200 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N are generated respectively.

[0136] 23 shows a neuron VMM array 2300 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT Mare the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0137] 24 shows a neuron VMM array 2400 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. [Long and short-term memory]

[0138] Prior art includes a concept known as long short-term memory (LSTM). LSTMs are often used in artificial neural networks. LSTMs allow artificial neural networks to remember information for any given period of time and use that information in subsequent operations. A traditional LSTM includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTMs.

[0139] FIG. 25 illustrates an exemplary LSTM 2500. The LSTM 2500 in this example includes cells 2501, 2502, 2503, and 2504. Cell 2501 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 2502 receives an input vector x1, an output vector (hidden state) h0 from cell 2501, and a cell state c0 from cell 2501, and generates an output vector h1 and a cell state vector c1. Cell 2503 receives an input vector x2, an output vector (hidden state) h1 from cell 2502, and a cell state c1 from cell 2502, and generates an output vector h2 and a cell state vector c2. Cell 2504 receives an input vector x3, an output vector (hidden state) h2 from cell 2503, and a cell state c2 from cell 2503, and generates an output vector h3. Additional cells can be used, the LSTM with four cells is just an example.

[0140] Figure 26 shows an example implementation of an LSTM cell 2600 that can be used for cells 2501, 2502, 2503, and 2504 in Figure 25. LSTM cell 2600 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0141] LSTM cell 2600 includes sigmoid function devices 2601, 2602, and 2603, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 2600 also includes tanh devices 2604 and 2605 for applying a hyperbolic tangent function to the input vector, multiplier devices 2606, 2607, and 2608 for multiplying two vectors, and adder device 2609 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0142] 27 shows an example of an implementation of LSTM cell 2600, LSTM cell 2700. For the convenience of the reader, the same numbering scheme from LSTM cell 2600 is used in LSTM cell 2700. Sigmoid function devices 2601, 2602, and 2603, and tanh device 2604 each include multiple VMM arrays 2701 and activation circuit blocks 2702. It can therefore be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems.

[0143] An alternative example of LSTM cell 2700 (and another example of one implementation of LSTM cell 2600) is shown in Figure 28. In Figure 28, sigmoid function devices 2601, 2602, and 2603, and tanh device 2604 may share the same physical hardware (VMM array 2801 and activation function block 2802) in a time-multiplexed manner. LSTM cell 2800 also includes a multiplier device 2803 for multiplying two vectors, an adder device 2808 for adding two vectors, a tanh device 2605 (including activation circuit block 2802), a register 2807 for storing the value i(t) output from sigmoid function block 2802, and a value f(t) output from multiplier device 2803 via multiplexer 2810. * A register 2804 stores c(t-1), and a value i(t) output from the multiplier device 2803 via a multiplexer 2810. * A register 2805 stores u(t) and the value o(t) output from the multiplier device 2803 via a multiplexer 2810. * It includes a register 2806 that stores {tilde over (c)}(t) and a multiplexer 2809.

[0144] Whereas LSTM cell 2700 includes multiple sets of VMM arrays 2701 and respective activation function blocks 2702, LSTM cell 2800 includes only one set of VMM arrays 2801 and activation function blocks 2802 that are used to represent multiple layers in embodiments of LSTM cell 2800. LSTM cell 2800 requires less space than LSTM cell 2700 because it requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 2700.

[0145] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as an adder and activation circuit block and a high voltage generation block. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself. [Gated Recurrent Unit]

[0146] An analog VMM implementation can be used for gated recurrent units (GRUs), which are gating mechanisms in recurrent artificial neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0147] 29 illustrates an exemplary GRU 2900. The GRU 2900 in this example includes cells 2901, 2902, 2903, and 2904. Cell 2901 receives input vector x0 and generates output vector h0. Cell 2902 receives input vector x1 and output vector h0 from cell 2901 and generates output vector h1. Cell 2903 receives input vector x2 and output vector (hidden state) h1 from cell 2902 and generates output vector h2. Cell 2904 receives input vector x3 and output vector (hidden state) h2 from cell 2903 and generates output vector h3. Additional cells are possible, and a GRU with four cells is merely an example.

[0148] FIG. 30 illustrates an exemplary implementation of a GRU cell 3000 that can be used for cells 2901, 2902, 2903, and 2904 of FIG. 29. The GRU cell 3000 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). The GRU cell 3000 includes sigmoid function devices 3001 and 3002, each of which applies a number between 0 and 1 to the output vector h(t-1) and the components from the input vector x(t). The GRU cell 3000 also includes a tanh device 3003 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 3004, 3005, and 3006 for multiplying two vectors, an adder device 3007 for adding the two vectors, and a complementary device 3008 for subtracting the input from 1 to generate an output.

[0149] Figure 31 shows a GRU cell 3100, which is an example of one implementation of GRU cell 3000. For the convenience of the reader, the same numbering scheme from GRU cell 3000 is used in GRU cell 3100. As can be seen from Figure 31, sigmoid function devices 3001 and 3002 and tanh device 3003 each include multiple VMM arrays 3101 and activation function blocks 3102. It can therefore be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems.

[0150] An alternative example of GRU cell 3100 (and another example of one implementation of GRU cell 3000) is shown in Figure 32. In Figure 32, GRU cell 3200 uses a VMM array 3201 and activation function block 3202, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In Figure 32, sigmoid function devices 3001 and 3002 and tanh device 3003 share the same physical hardware (VMM array 3201 and activation function block 3202) in a time-multiplexed manner. The GRU cell 3200 also includes a multiplier device 3203 for multiplying two vectors together, an adder device 3205 for adding the two vectors together, a complementary device 3209 for subtracting an input from one to generate an output, a multiplexer 3204, and a value h(t-1) output from the multiplier device 3203 via the multiplexer 3204. * A register 3206 holds r(t) and a value h(t-1) output from the multiplier device 3203 via a multiplexer 3204. * A register 3207 holds z(t), and a value h^(t) output from the multiplier device 3203 via a multiplexer 3204. * and a register 3208 that holds (1-z((t)).

[0151] Whereas GRU cell 3100 includes multiple sets of VMM arrays 3101 and activation function blocks 3102, GRU cell 3200 includes only one set of VMM arrays 3201 and activation function blocks 3202 that are used to represent multiple tiers in embodiments of GRU cell 3200. GRU cell 3200 requires less space than GRU cell 3100 because it requires ⅓ the space for the VMM and activation function blocks compared to GRU cell 3100.

[0152] It can be further appreciated that a system utilizing a GRU typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as an adder and activation circuit block and a high voltage generation block. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0153] The input to the VMM array can be analog levels, binary levels, timing pulses, or digital bits, and the output can be analog levels, binary levels, timing pulses, or digital bits (in this case an output ADC is required to convert the output analog level current or voltage to digital bits).

[0154] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell, by a differential cell, or by two blended memory cells (an average of two or more cells). In the case of a differential cell, two memory cells are required to implement weight w as a differential weight (w=w+-w-). In the case of two blended memory cells, two memory cells are required to implement weight w as an average of two cells. [Embodiments for precision adjustment of cells in a VMM]

[0155] 33 shows a block diagram of a VMM system 3300. The VMM system 3300 includes a VMM array 3301, a row decoder 3302, a high voltage decoder 3303, a column decoder 3304, a bit line driver 3305, an input circuit 3306, an output circuit 3307, a control logic 3308, and a bias generator 3309. The VMM system 3300 further includes a high voltage generation block 3310 including a charge pump 3311, a charge pump regulator 3312, and a high voltage level generator 3313. The VMM system 3300 further includes an algorithm controller 3314, an analog circuit 3315, a control logic 3316, and a test control logic 3317. The systems and methods described below may be implemented in the VMM system 3300.

[0156] The input circuit 3306 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter such as a current-to-voltage converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3306 may implement a normalization, scaling function, or arithmetic function. The input circuit 3306 may implement a temperature compensation function for the input. The input circuit 3306 may implement an activation function such as a ReLU or a sigmoid function.

[0157] The output circuit 3307 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog outputs to digital bits), an AAC (analog-to-analog converter such as a current-to-voltage converter), an APC (analog-to-pulse converter), or any other type of converter. The output circuit 3307 may implement an activation function such as a ReLU or a sigmoid function. The output circuit 3307 may implement a normalization, scaling function, or arithmetic function for the neuron output. The output circuit 3307 may implement a temperature compensation function for the neuron output or the array output (such as the bit line output), as described below.

[0158] FIG. 34 shows an adjustment and correction method 3400 that can be executed by an algorithm controller 3314 in a VMM system 3300. The adjustment and correction method 3400 generates an adaptive target based on the final error resulting from the cell output and the original target of the cell. This method is typically initiated in response to a received adjustment command (step 3401). The initial current target (used in the program / verification algorithm) for the selected cell or group of selected cells, Itargetv(i), is determined using a prediction target model, such as by using a function or look-up table, and the variable DeltaError is set to 0 (step 3402). The target function, if used, is based on the I-V program curve of one selected memory cell or cell group. The target function also depends on various variations caused by characteristics of the array, such as the degree of program disturb exhibited by the cell (depending on the cell address and cell level within the sector, cells that exhibit a relatively large disturb are exposed to more program time in the inhibited state, and cells with higher currents typically have more disturb), cell-to-cell coupling, and various types of array noise. These variations can be characterized by the silicon PVT (process, voltage, temperature). The look-up table, if used, can be characterized in the same way to emulate the I-V curve and various variations.

[0159] Next, soft erase is performed on all cells in the VMM such that each cell draws a current of, for example, about 3 - 5 μA during the read operation, erasing each cell to an intermediate weak erase level (step 3403). Soft erase is performed, for example, by applying an incremental erase pulse voltage to the cell until an intermediate cell current is reached. Next, a deep programming operation is performed on all unused cells, for example, to reach a <pA current level (step 3404). Then, target adjustment (correction) based on the error result is performed. If DeltaError > 0, which means the cell has overshot during programming, Itargetv(i + 1) is then Itarget+theta *DeltaError is set, and theta is, for example, a number equal to or close to 1 (step 3405A).

[0160] Itarget(i+1) may also be adjusted based on the previous Itarget(i) with appropriate error target adjustment / correction. If DeltaError<0, meaning the cell has experienced undershoot in programming, meaning the cell current has not yet reached the target, then Itargetv(i+1) is set to the previous target Itargetv(i) (step 3405B).

[0161] Next, coarse and / or fine program and verify operations are performed (step 3406). Multiple adaptive coarse programming methods may be used to accelerate programming, such as by targeting multiple progressively smaller coarse targets before performing a fine (fine) programming step. Adaptive fine programming is performed, for example, with fine (precise) incremental program voltage pulses or constant program timing pulses. Examples of systems and methods for performing coarse and fine programming are described in U.S. Provisional Patent Application No. 62 / 933,809, entitled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on November 11, 2019 by the same assignee as this application, which is incorporated herein by reference.

[0162] Icell is measured at the selected cell (step 3407). The cell current can be measured, for example, by an ammeter circuit. The cell current can be measured, for example, by an ADC (analog-to-digital converter) circuit, in which case the output is represented by digital bits. The cell current can be measured, for example, by an I-V (current-voltage converter) circuit, in which case the output is represented by an analog voltage. DeltaError is calculated, which is Icell - Itarget and represents the difference between the actual current in the measured cell (Icell) and the target current (Itarget). If |DeltaError| < DeltaMargin, the cell has achieved the target current within a specific tolerance (DeltaMargin) and the method ends (step 3410). |Deltaerror| = abs(DeltaError) = the absolute value of DeltaError. Otherwise, the method returns to step 3403 and sequentially re-executes the steps (step 3410).

[0163] Figures 35A and 35B illustrate an adjustment correction method 3500 that can be executed by an algorithm controller 3314 within the VMM system 3300. Referring to FIG. 35A, the method typically starts in response to an adjustment command that is received (step 3501). The entire VMM array is erased, such as by a soft erase method (step 3502). Deep programming operations are performed on all unused cells to obtain a cell current <pA level (step 3503). All cells within the VMM array are programmed to an intermediate value, such as 0.5 to 1.0 μA, using coarse and / or fine programming cycles (step 3504). Examples of systems and methods for performing coarse programming and fine programming are described in U.S. Provisional Patent Application No. 62 / 933,809, entitled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on November 11, 2019, by the same assignee as this application and incorporated herein by reference. As described above, a prediction target for the cells to be used is set using a function or a look-up table (step 3505). Next, a sector adjustment method 3507 is executed for each sector within the VMM (step 3506). A sector typically consists of two or more adjacent rows within the array.

[0164] Figure 35B shows the adaptive target sector adjustment method 3507. All cells within the sector are ultimately programmed to the desired value (e.g., 1 nA to 50 nA) (step 3508A) using individual or combined program / verify (P / V) methods such as (1) coarse / fine / constant P / V cycles, (2) CG+(only CG increment) or EG+(only EG increment) or complementary CG+ / EG-(CG increment and EG decrement), (3) the deepest cell programmed first (such as progressive grouping which means grouping cells together, and the group with the cell having the lowest current is programmed first). Next, a determination is made as to whether Icell < Itarget. (Step 3508B) . If yes, the method proceeds to step 3509. If no, the method repeats step 3508A. In step 3509, DeltaError is measured, which is equal to the measured Icell - Itarget(i + 1) (step 3509). A determination is made as to whether |DeltaError| < DeltaMargin (step 3510). If yes, the method is complete (step 3511). If no, target adjustment is performed. If DeltaError > 0, which means the cell has received an overshoot during programming, the target is adjusted by setting the new target to Itarget + theta * DeltaError, where theta is typically = 1 (step 3512A). Itarget(i + 1) can also be adjusted based on the previous Itarget(i) with appropriate error target adjustment / correction. If DeltaError < 0, which means the cell has received an undershoot during programming, it means the cell has not yet reached the target, and the target is adjusted by holding the previous target which means Itarget(i + 1) = Itargetv(i) (step 3512B). The sector is softly erased (step 3513). All cells of the sector are programmed to an intermediate value (step 3514), and the method returns to step 3509.

[0165] A typical neural network may have positive weights w+ and negative weights w-, where the composite weight=w+-w-. w+ and w- are implemented by memory cells (Iw+ and Iw-, respectively), and the composite weight (Iw=Iw+-Iw-, current subtraction) may be performed at the peripheral circuit level (such as the array bit line output circuit). Thus, weight adjustment embodiments for the composite weight may include adjusting both w+ and w- cells simultaneously, adjusting only w+ cells, or adjusting only w- cells, as in the example shown in Table 8. The adjustments are performed using the program / verify and error target adjustment methods described above with respect to Figures 34 / 35A / 35B. Verification may be performed on the composite weight only (e.g., measuring / reading the composite weight current, rather than the individual positive w+ or w- cell currents, only w+ cell currents, or only w- cell currents).

[0166] For example, for a composite Iw of 3na, Iw+ can be 3na and Iw- can be 0na, or Iw+ can be 13na and Iw- can be 10na, meaning that both the positive weight Iw+ and the negative weight Iw- are not zero (e.g., zero represents a deeply programmed cell). This may be preferable in certain operating conditions, as both Iw+ and Iw- will be less susceptible to noise. table 9 :Weight adjustment method [Table 9]

[0167] FIG. 36A shows data behavior (IV curve) versus temperature (for example in the subthreshold region), FIG. 36B shows problems caused by data drift during operation of a VMM system, and FIGS. 36C and 36D show blocks for compensating for data drift, with respect to FIG. 36C showing blocks for compensating for temperature changes.

[0168] FIG. 36A illustrates a known characteristic of a VMM system in which as the operating temperature increases, the current sensed within any given selected non-volatile memory cell within the VMM array increases in the subthreshold region, decreases in the saturation region, or generally decreases in the linear region.

[0169] Figure 36B shows the array current distribution (data drift) over time, which shows that the aggregate output from the VMM array (the sum of the currents from all bitlines in the VMM array) shifts to the right (or left, depending on the technology used) over time of operation, meaning that the total aggregate output drifts over the life of the VMM system. This phenomenon is known as data drift, and data drifts due to degradation due to usage conditions and environmental factors.

[0170] FIG. 36C shows a compensation current i COMP 36 shows a bitline compensation circuit 3600 that may include injecting a . The bitline compensation circuit 3600 may include scaling the output up or down with a scaler circuit based on a resistor or capacitor network. The bitline compensation circuit 3600 may include shifting or offsetting the output with a shifter circuit based on the resistor or capacitor network.

[0171] FIG. 36D shows a data drift monitor 3620 that detects the amount of data drift. That information is then used as an input to the bit line compensation circuit 3600, which results in an appropriate level of i COMP can be selected.

[0172] Figure 37 shows a bit line compensation circuit 3700, which is one embodiment of the bit line compensation circuit 3600 of Figure 36. The bit line compensation circuit 3700 includes an adjustable current source 3701 and an adjustable current source 3702, which together correspond to i COMP Generate i COMPis equal to the current generated by the adjustable current source 3701 minus the current generated by the adjustable current source 3701.

[0173] Figure 38 illustrates a bitline compensation circuit 3700, which is one embodiment of the bitline compensation circuit 3600 of Figure 36. Bitline compensation circuit 3800 includes an operational amplifier 3801, an adjustable resistor 3802, and an adjustable resistor 3803. Operational amplifier 3801 receives a reference voltage VREF at its non-inverting terminal and VREF at its inverting terminal. INPUT Received, V INPUT is the voltage received from the bit line output circuit 3610 of FIG. 36C, and V OUTPUT Generates an output of V OUTPUT is a voltage for compensating for data drift based on the ratio of resistors 3803 and 3802. INPUT By configuring the values ​​of resistors 3803 and / or 3802, V OUTPUT can be scaled up or down.

[0174] FIG. 39 shows a bitline compensation circuit 3900, which is one embodiment of the bitline compensation circuit 3600 of FIG. 36. The bitline compensation circuit 3900 includes an operational amplifier 3901, a current source 3902, a switch 3904, and an adjustable integrating output capacitor 3903, where the current source 3902 is actually the output current of a single bitline or a collection of bitlines (such as one for summing positive weights (w+) and one for summing negative weights (w−)) in the VMM array. The operational amplifier 3901 receives a reference voltage VREF at its non-inverting terminal and a reference voltage VREF at its inverting terminal. INPUT Received, V INPUT is the voltage received from the bit line output circuit 3610 of FIG. 36C. The bit line compensation circuit 3900 integrates the current Ineu through the capacitor 3903 over an adjustable integration time to produce an output voltage V OUTPUT It acts as an integrator to generate V OUTPUT =Inue * Integral time / C 3903 and C 3903is the value of the capacitor 3903. Therefore, the output voltage V OUTPUT is proportional to the (bit line) output current Ineu, proportional to the integration time, and inversely proportional to the capacitance of the capacitor 3903. The bit line compensation circuit 3900 OUTPUT Generates an output of V OUTPUT The value of is scaled based on the configuration value of capacitor 3903 and / or the integration time to compensate for data drift.

[0175] FIG. 40 illustrates a bitline compensation circuit 4000, which is one embodiment of the bitline compensation circuit 3600 of FIG. 36. The bitline compensation circuit 4000 includes an M:N ratio current mirror 4010, which is COMP =(M / N) * i input The current mirror 4010 is INPUT , mirrors that current, and optionally scales that current to i COMP Therefore, by configuring the M and / or N parameters, i COMP can be scaled up or down.

[0176] Figure 41 shows a bitline compensation circuit 4100, which is one embodiment of the bitline compensation circuit 3600 of Figure 36. The bitline compensation circuit 4100 includes an operational amplifier 4101, an adjustable scaling resistor 4102, an adjustable shifting resistor 4103, and an adjustable resistor 4104. The operational amplifier 4101 couples a reference voltage V REF Receives V at its inverting terminal. IN Receive. V IN V INPUT and Vshft, and V INPUT is the voltage received from the bit line output circuit 3610 of FIG. 36C, and Vshft is V INPUT and V OUTPUT is the voltage intended to implement a shift between In this way, V OUTPUT is the amount of data drift compensation, V INPUTis a scaled and shifted version of

[0177] FIG. 42 shows a bitline compensation circuit 4200, which is one embodiment of the bitline compensation circuit 3600 of FIG. 36. The bitline compensation circuit 4200 includes an operational amplifier 4201, an input current source Ineu 4202, a current shifter 4203, switches 4205 and 4206, and an adjustable integrating output capacitor 4204, where the current source 4202 is actually the output current Ineu at a single bitline or multiple bitlines in a VMM array. The operational amplifier 4201 receives a reference voltage VREF at its non-inverting terminal and I IN Received, I IN is the sum of Inue and the current output by the current shifter 4203, and V OUTPUT Generates an output of V OUTPUT is scaled (based on Capacitor 4204) and shifted (based on Ishifter 4203) to compensate for data drift.

[0178] 43-48 show various circuits that may be used to provide a W value to be programmed or read into each selected cell during a programming or read operation.

[0179] FIG. 43 shows a neuron output circuit 4300 that includes an adjustable current source 4301 and an adjustable current source 4302, which together provide I OUT Generate I OUT is the current I generated by the adjustable current source 4301. W+ , the current I generated by the adjustable current source 4302 W- The adjustable current Iw+ 4301 is a scaled current of the cell or neuron current (e.g., bit line current) to implement positive weights. The adjustable current Iw- 4302 is a scaled current of the cell or neuron current (e.g., bit line current) to implement negative weights. Current scaling is achieved by using a current mirror circuit with an M:N ratio, Iout=(M / N) *This is done by Iin et al.

[0180] FIG. 44 shows a neuron output circuit 4400 including an adjustable capacitor 4401, a control transistor 4405, a switch 4402, a switch 4403, and an adjustable current source 4404Iw+, where Iw+ is a scaled output current of the cell current or the (bit line) neuron current, such as by an M:N current mirror circuit. The transistor 4405 is used, for example, to impose a fixed bias voltage on the current source 4404. The circuit 4404 is connected to V OUT Generate V OUT is inversely proportional to the capacitor 4401 and proportional to the adjustable integration time (the time switch 4403 was closed and switch 4402 was open), and is connected to an adjustable current source 4404, I W+ is proportional to the current generated by V OUT is V+ -((Iw+ * integration time) / C 4401 ), C 4401 is the value of the capacitor 4401. The positive terminal V+ of the capacitor 4401 is connected to the positive supply voltage, and the negative terminal V- of the capacitor 4401 is connected to the output voltage V OUT is connected.

[0181] FIG. 45 shows a neuron circuit 4500 including a capacitor 4401 and an adjustable current source 4502, which is a scaled version of the cell current or (bit line) neuron current, such as by an M:N current mirror. OUT Generate V OUT is inversely proportional to the capacitor 4401, proportional to the adjustable integration time (the time that the switch 4501 is open), and is connected to an adjustable current source 4502, I Wi The capacitor 4401 is reused from the neuron output circuit 44 after completing its operation of integrating the current Iw+. The positive and negative terminals (V+ and V−) are then swapped in the neuron output circuit 45, and the positive terminal is supplied with the output voltage V OUTThe negative terminal is held at its previous voltage value by a clamp circuit (not shown). In effect, output circuit 44 is used to implement the positive weights and circuit 45 is used to implement the negative weights, so that the final charge on capacitor 4401 effectively represents the composite weight (Qw=Qw+-Qw-). vinegar.

[0182] FIG. 46 shows a neuron circuit 4600 that includes an adjustable capacitor 4601, a switch 4602, a control transistor 4604, and an adjustable current source 4603. The circuit 4600 is OUT Generate V OUT is inversely proportional to the capacitor 4601, proportional to the adjustable integration time (the time that the switch 4602 is open), and is connected to an adjustable current source 4603, I W- The negative terminal V− of the capacitor 4601 is, for example, equal to ground. The positive terminal V+ of the capacitor 4601 is, for example, first precharged to a positive voltage before integrating the current Iw−. The neuron circuit 4600 can be used in place of the neuron circuit 4500 together with the neuron circuit 4400 to implement a composite weight (Qw=Qw+−Qw−).

[0183] FIG. 47 shows a neuron circuit 4700 including operational amplifiers 4703 and 4706, adjustable current sources Iw+ 4701 and Iw− 4702, and adjustable resistors 4704, 4705, and 4707. The neuron circuit 4700 includes R4707. * V equal to (Iw+ - Iw-) OUT The adjustable resistor 4707 implements the scaling of the output. The adjustable current sources Iw+ 4701 and Iw- 4702 also form a current mirror circuit with an M:N ratio (Iout=(M / N) * Implement output scaling by Iin etc.

[0184] 48 shows a neuron circuit 4800 that includes operational amplifiers 4803 and 4806, switches 4808 and 4809, adjustable current sources Iw− 4802 and Iw+ 4801, and adjustable capacitors 4804, 4805, and 4807. The neuron circuit 4800 generates a V OUT The adjustable capacitor 4807 implements the scaling of the output. The adjustable current sources Iw+ 4801 and Iw- 4802 also form a current mirror circuit with an M:N ratio (Iout=(M / N) * Iin), etc. The integral time may also adjust the output scaling.

[0185] 49A, 49B, and 49C show block diagrams of an output circuit, such as output circuit 3307 of FIG.

[0186] In FIG. 49A, output circuit 4901 includes ADC circuit 4911, which is used to directly digitize analog neuron outputs 4910 to provide digital output bits 4912.

[0187] In Figure 49B, the output circuit 4902 includes a neuron output circuit 4921 and an ADC 4911. The neuron output circuit 4921 receives the neuron output 4920 and shapes it before it is digitized by the ADC circuit 4911 to generate the output 4912. The neuron output circuit 4921 may be used for normalization, scaling, shifting, mapping, arithmetic operations, activation, and / or temperature compensation as previously described. The ADC circuit may be a serial (slope or ramp or count) ADC, a SAR ADC, a pipeline ADC, a sigma delta ADC, or any type of ADC.

[0188] In FIG. 49C, the output circuit includes a neuron output circuit 4921 that receives a neuron output 4930, and a converter circuit 4931 for converting the output from the neuron output circuit 4921 to an output 4932. The converter 4931 may include an ADC, an AAC (analog-to-analog converter such as a current-to-voltage converter), an APC (analog-to-pulse converter), or any other type of converter. The ADC 4911 or the converter 4931 may be used to implement an activation function, for example, by bit mapping (e.g., quantization) or clipping (e.g., clipped ReLU). The ADC 4911 and the converter 4931 may be configurable for lower or higher precision (e.g., smaller or larger number of bits), lower or higher performance (e.g., slower or faster speed), etc.

[0189] Another embodiment of scaling and shifting is by configuring an ADC (analog-to-digital) conversion circuit (e.g., serial ADC, SAR ADC, pipeline ADC, slope ADC, etc.) that is used to convert the output of the array (bit lines) into digital bits with lower or higher bit precision and then manipulate the digital output bits via normalization (e.g., 12 bits to 8 bits), shifting, or remapping, etc. according to a particular function (e.g., linear or nonlinear, compression, nonlinear activation, etc.). An example of an ADC conversion circuit is described in U.S. Provisional Patent Application No. 62 / 933,809, entitled "Precise Programming Method and Apparatus for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on November 11, 2019 by the same assignee as this application, which is incorporated herein by reference.

[0190] table 10 shows an alternative approach for performing read, erase and program operations. table 10 : Operation of flash memory cells [Table 10] The read and erase operations are similar to the previous table, however the two methods for programming are implemented by the Fowler-Nordheim (FN) tunneling mechanism.

[0191] An embodiment for scaling the inputs may be done by validating a certain number of rows of the VMM at a time and then combining the results together, etc.

[0192] Another embodiment scales the input voltage and appropriately rescales the output for normalization.

[0193] Another embodiment for scaling a pulse width modulated input is by adjusting the timing of the pulse width. An example of this technique is described in U.S. patent application Ser. No. 16 / 449,201, entitled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in Deep Learning Artificial Neural Network," filed Jun. 21, 2019 by the same assignee as this application, which is incorporated herein by reference.

[0194] Another embodiment for scaling the input is by enabling the input binary bits one at a time, e.g., for an 8-bit input IN7:0, successively evaluating IN0, IN1, ..., IN7, respectively, and then combining the output result with the appropriate binary bit weighting. An example of this technique is described in U.S. patent application Ser. No. 16 / 449,201, entitled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in Deep Learning Artificial Neural Network," filed on Jun. 21, 2019 by the same assignee as this application, which is incorporated herein by reference.

[0195] Optionally, in the above embodiments, measuring the cell current for purposes of verifying or reading the current may be an average or taking multiple measurements, e.g., 8-32 measurements, to reduce the effects of noise (such as RTN or any random noise) and / or to detect any outlier bits that are defective and need to be replaced by redundant bits.

[0196] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly on" (with no intermediate material, element, or gap disposed between them) and "indirectly on" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached to" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled to" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above the substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. A neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit comprising: an adjustable capacitor including a first terminal and a second terminal, the second terminal providing an output voltage to the neuron output circuit; a control transistor having a first terminal and a second terminal; a first switch selectively coupled between the first and second terminals of the adjustable capacitor; a second switch selectively coupled between the second terminal of the adjustable capacitor and the first terminal of the control transistor; an adjustable current source coupled to the second terminal of the control transistor.

2. 1. A neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit comprising: an adjustable capacitor including a first terminal and a second terminal, the second terminal providing an output voltage to the neuron output circuit; a control transistor having a first terminal and a second terminal; a switch selectively coupled between the second terminal of the adjustable capacitor and the first terminal of the control transistor; an adjustable current source coupled to the second terminal of the control transistor.

3. 1. A neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit comprising: an adjustable capacitor including a first terminal and a second terminal, the first terminal providing an output voltage to the neuron output circuit; a control transistor having a first terminal and a second terminal; a first switch selectively coupled between the first terminal of the adjustable capacitor and the first terminal of the control transistor; an adjustable current source coupled to the second terminal of the control transistor.

4. 1. A neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit comprising: a first operational amplifier including an inverting input, a non-inverting input, and an output; a second operational amplifier having an inverting input, a non-inverting input, and an output; a first adjustable current source coupled to the inverting input of the first operational amplifier; a second adjustable current source coupled to the inverting input of the second operational amplifier; a first adjustable resistor coupled to the inverting input of the first operational amplifier; a second adjustable resistor coupled to the inverting input of the second operational amplifier; a third adjustable resistor coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier.

5. 1. A neuron output circuit for providing currents to program as weight values ​​in selected memory cells in a vector matrix multiplication array, the neuron output circuit comprising: a first operational amplifier including an inverting input, a non-inverting input, and an output; a second operational amplifier having an inverting input, a non-inverting input, and an output; a first adjustable current source coupled to the inverting input of the first operational amplifier; a second adjustable current source coupled to the inverting input of the second operational amplifier; a first switch coupled between the inverting input and the output of the first operational amplifier; a second switch coupled between the inverting input and the output of the second operational amplifier; a first adjustable capacitor coupled between the inverting input and the output of the first operational amplifier; a second adjustable capacitor coupled between the inverting input and the output of the second operational amplifier; a third adjustable capacitor coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier.

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