Cell Multi-Inverter

Abstract

In a cell-multiplexed inverter in which multiple cells are multiplexed and connected to each phase of an AC system using star wiring, the AC output voltages of the cells are made equal even when an unbalanced AC voltage occurs or when an unbalanced AC voltage is intentionally output. [Solution] A corrected voltage command value generating unit superimposes a sine wave of opposite phase to the certain phase as a zero-phase voltage on the voltage command value if the amplitude of the voltage command value of a certain phase is larger than the amplitude of the voltage command value of the other phase, and superimposes a sine wave of the same phase as the certain phase as a zero-phase voltage on the voltage command value if the amplitude of the voltage command value of a certain phase is smaller than the amplitude of the voltage command value of the other phase.

Description

[Technical field]

[0001] The present invention relates to a multiple cell inverter in which a plurality of cells are multiplexed and connected in a star connection to each phase of an AC system. [Background technology]

[0002] As an example of a cell multiplexing inverter, a modular multilevel cascade converter (MMCC) with a single star bridge cell (SSBC) connected to a three-phase AC system is known. In addition, a configuration in which a separate power supply or DC / DC converter is connected to the DC side of the full bridge cell of the MMCC-SSBC is also known.

[0003] A typical example of this configuration is the solid-state transformer (SST) described in Patent Document 1. Figure 1 shows an SST consisting of three cells per phase that combines an MMCC-SSBC and a bidirectional isolated DC / DC converter using the dual active bridge (DAB) method.

[0004] High-voltage AC power is converted to DC power by serially connected cells, the DC power is converted to high-frequency AC power, and the power is converted back to DC power by isolating and rectifying it with a transformer. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0005] Another application is the high-voltage multiple inverter described in Patent Document 2.

[0006] When an SST is connected to an unbalanced three-phase AC system, or when a high-voltage multiple inverter intentionally outputs an unbalanced three-phase AC voltage, the phase voltage amplitude of a certain phase increases and the AC voltage that the cell connected to that phase should output also increases.

[0007] To meet this demand, it is necessary to increase the DC voltage of the cells, but this also requires the components to have a higher withstand voltage, which leads to increased costs and size. Using switching devices with a high withstand voltage for the cells can also lead to increased losses.

[0008] In addition, some equipment may be required to continue operating even if some cells fail.

[0009] Patent Document 1 discloses the main circuit configuration of an SST, and Patent Document 2 discloses the configuration of a high-voltage multiple inverter.

[0010] Patent documents 3 and 4 disclose methods for continuing operation when a cell fails. In both documents, the failed cell is first short-circuited. However, this alone reduces the AC voltage amplitude that can be output from the phase with the failed cell. Therefore, Patent document 3 inserts a spare cell prepared in advance into the corresponding phase. Patent document 4 increases the DC voltage of the non-failed cells in the corresponding phase.

[0011] Patent Documents 5 and 6 disclose a technique for dealing with voltage imbalance by using a zero-sequence voltage in an MMCC-SSBC. The purpose of this technique is to balance the capacitor voltages of each cell.

[0012] Patent Document 7 describes a technology that reduces the peak of the voltage command value by superimposing a zero-phase voltage on the voltage command value of a single three-phase inverter that does not perform cell multiplexing. It can also be used to output unbalanced three-phase AC voltages, and can equalize the peak voltage command value of each phase. The technology in Patent Document 7 can be applied to MMCC-SSBC and high-voltage multiple inverters. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 10-75580 [Patent Document 2] Japanese Patent Application Publication No. 11-122943 [Patent Document 3] JP 2012-147613 A [Patent Document 4] WO2017 / 094379 A1 [Patent Document 5] JP 2013-5694 A [Patent Document 6] Patent Publication No. 2021-19481 [Patent Document 7] Japanese Patent Application Publication No. 3-107373 Summary of the Invention [Problem to be solved by the invention]

[0014] However, Patent Documents 1 and 2 do not particularly mention connection to an unbalanced system, output of an unbalanced voltage, or how to deal with a cell failure.

[0015] In the technology of Patent Document 3, it is necessary to incorporate a spare cell into the device, and a switch for turning on the spare cell is also required, which increases costs and size. If no failure occurs, the spare cell will not be used and may be wasted.

[0016] In Patent Document 4, the DC voltage of other cells in the corresponding phase is increased, so the cells must be designed based on this, which causes problems with cost, size, and increased losses. Furthermore, neither Patent Document 3 nor Patent Document 4 describes a method for dealing with voltage imbalance.

[0017] In Patent Documents 5 and 6, only a capacitor is connected to the DC side of each cell, and applications that do not handle active power, such as reactive power compensation devices, are assumed. However, high-voltage multiple inverters and SSTs have separate paths through which active power passes, and this path can be used to exchange power between cells and balance the capacitor voltages. This reduces the importance of the technologies in Patent Documents 5 and 6. Furthermore, neither Patent Document 5 nor 6 describes a method for dealing with cell failures.

[0018] In Patent Document 7, harmonics of an odd multiple of three are superimposed as the zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the larger the common mode current flows through the floating capacitance of the circuit. This may cause many problems, such as increased heat generation in components, reduced efficiency, malfunction of the earth fault detector, insulation breakdown of the high-frequency transformer, and electromagnetic interference with other equipment. Therefore, it is necessary to lower the frequency of the superimposed zero-phase voltage. Patent Document 7 also does not describe a method for dealing with cell failure.

[0019] As described above, in a cell-multiplexed inverter in which multiple cells are multiplexed and connected in a star connection to each phase of an AC system, the challenge is to equalize the AC output voltages of the cells even when an unbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output. [Means for solving the problem]

[0020] The present invention has been devised in view of the above-mentioned problems in the related art. One aspect of the present invention is a multi-cell inverter including: a plurality of cells connected in a star connection to each phase of an AC system in multiplex; the cells having a full-bridge circuit on the AC system side; a correction voltage command value generation unit that generates a correction voltage command value by superimposing a zero-sequence voltage having the same frequency as a fundamental wave on a voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein the correction voltage command value generation unit superimposes a sine wave of an opposite phase to the certain phase as the zero-sequence voltage on the voltage command value if the amplitude of the voltage command value of a certain phase is larger than the amplitude of the voltage command value of the other phase, and superimposes a sine wave of the same phase as the certain phase as the zero-sequence voltage on the voltage command value if the amplitude of the voltage command value of a certain phase is smaller than the amplitude of the voltage command value of the other phase.

[0021] In one aspect, the correction voltage command value generating unit includes a first adder that adds the zero-phase voltage to the voltage command value and outputs the correction voltage command value, an amplitude detector that outputs an amplitude of the correction voltage command value for each phase, a first subtractor that calculates a deviation between a three-phase average value of the amplitude of the correction voltage command value and the amplitude of the correction voltage command value, an amplifier that amplifies the deviation between the three-phase average value and the amplitude, a third multiplier that multiplies an output of the amplifier by a sine wave having the same phase as the voltage command value, and a fourth adder that adds up outputs of the third multiplier for three phases and outputs the result as the zero-phase voltage.

[0022] In one aspect, the amplitude used in the first subtractor is a value obtained by multiplying the amplitude of the voltage command value by a coefficient based on the number of failed cells, and the three-phase average value is a three-phase average value of the amplitude after multiplication by the coefficient.

[0023] In one aspect of the present invention, the amplitude of the voltage command value is set to an effective value of the voltage command value.

[0024] In another aspect, the amplitude of the voltage command value is a value obtained by extracting the amplitude of a fundamental wave component of the voltage command value.

[0025] In another aspect, the amplitude of the voltage command value is a peak value per one period of the voltage command value.

[0026] In one aspect, the sine wave having the same phase as the voltage command value has three phases, one of which has a phase obtained by a PLL, a rotary encoder, or a resolver, or a phase estimated by an observer, and the other phase has a phase obtained by adding a fixed value to the phase of the one of the three phases.

[0027] In another aspect, the correction voltage command value generation unit includes a phase output unit that outputs a phase ωt synchronized with an AC voltage of a grid, a fourth multiplier that multiplies the correction voltage command value by cosωt, a fifth multiplier that doubles the output of the fourth multiplier, a second low-pass filter that extracts a DC component from the output of the fifth multiplier and outputs an in-phase component synchronized with cosωt of the correction voltage command value, a sixth multiplier that multiplies the correction voltage command value by sinωt, a seventh multiplier that doubles the output of the sixth multiplier, a third low-pass filter that extracts a DC component from the output of the seventh multiplier and outputs a quadrature component synchronized with sinωt of the correction voltage command value, an eighth multiplier that multiplies the in-phase component by cosωt, a ninth multiplier that multiplies the quadrature component by sinωt, and a fifth adder that adds the output of the eighth multiplier and the output of the ninth multiplier. an output of the fifth adder being a sine wave having the same phase as the voltage command value.

[0028] In one aspect, the corrected voltage command value generating unit includes a phase output unit that outputs a phase ωt synchronized with an AC voltage of a system, a first dq converter that converts a phase voltage detection signal or the voltage command value into a value on a rotating coordinate system synchronized with a system frequency, a second dq converter that converts the phase voltage detection signal or the voltage command value into a value on a rotating coordinate system that rotates in a direction opposite to the system frequency, and a positive-phase d-axis component and a positive-phase q-axis component that are DC components extracted from an output of the first dq converter, and a negative-phase d-axis component and a negative-phase q-axis component that are DC components extracted from an output of the second dq converter. the voltage command value added by the eighth adder, wherein the first adder uses the voltage command value to which the output of the seventh adder has been added by the eighth adder.

[0029] In one aspect, the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (1).

[0030]

number

[0031] V 0d :D-axis component of zero-phase voltage V 0q :Zero-phase voltage q-axis component V 1d : Positive sequence voltage d-axis component V 1q : Positive sequence voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative sequence voltage q-axis component.

[0032] In another aspect, the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (2).

[0033]

number

[0034] V 0d :D-axis component of zero-phase voltage V 0q :Zero-phase voltage q-axis component V 1d : Positive sequence voltage d-axis component V 1q : Positive sequence voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative sequence voltage q-axis component.

[0035] In another aspect, the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3).

[0036]

number

[0037] V 0d :D-axis component of zero-phase voltage V 0q :Zero-phase voltage q-axis component V 2d : Negative-phase voltage d-axis component V 2q : Negative-phase voltage q-axis component V1: Voltage positive sequence component.

[0038] In one aspect, the phase voltage detection signal or the voltage command value used in the first dq converter and the second dq converter is a value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure. Effect of the Invention

[0039] According to the present invention, in a multi-cell inverter in which a number of cells are multiplexed and connected in a star connection to each phase of an AC system, it is possible to equalize the AC output voltages of the cells even when an unbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output. [Brief description of the drawings]

[0040] [Figure 1] FIG. 1 is a circuit diagram showing a main circuit configuration according to first to fourth embodiments. [Diagram 2] FIG. 11 is a circuit diagram showing another example of a cell. [Diagram 3] FIG. 2 is a block diagram showing a correction voltage command value generating unit according to the first embodiment. [Figure 4] FIG. 11 is a block diagram showing a correction voltage command value generating unit according to the second embodiment. [Diagram 5] FIG. 11 is a block diagram showing a correction voltage command value generating unit according to a third embodiment. [Figure 6] FIG. 13 is a block diagram showing a correction voltage command value generating unit according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Hereinafter, first to fourth embodiments of the multi-cell inverter of the present invention will be described in detail with reference to FIGS.

[0042] [Embodiment 1] First, as an example of a multiple-cell inverter, the main circuit configuration of an MMCC-SSBC shown in FIG. 1 will be described.

[0043] As shown in FIG. 1(a), cells cellu1, cellu2, and cellu3 are connected in series to the U phase of the AC system AC via a reactor Lu. Similarly, cells cellv1, cellv2, and cellv3 are connected in series to the V phase of the AC system AC via a reactor Lv, and cells cellw1, cellw2, and cellw3 are connected in series to the W phase of the AC system AC via a reactor Lw. Here, the AC phase voltage (phase voltage detection signal) is V U ,v V ,v W Let us assume that.

[0044] The DC terminals of cells cellu1, cellu2, cellu3, cellv1, cellv2, cellv3, cellw1, cellw2, and cellw3 are connected in parallel. The DC voltages of cells cellu1 to cellw3 are V DC Let us assume that.

[0045] Figure 1(b) shows the configuration of one cell. One end of switching devices S1, S3 is connected to one AC terminal of the cell. One end of switching devices S2, S4 is connected to the other AC terminal of the cell. The other ends of switching devices S1, S2 are connected to one end of first capacitor C1. The other ends of switching devices S3, S4 are connected to the other end of first capacitor C1. The above switching devices S1, S2, S3, S4 form a full bridge circuit provided on the AC side of the AC system.

[0046] Switching devices S5 and S6 are connected in series between one end and the other end of the first capacitor C1, and switching devices S7 and S8 are connected in series between one end and the other end of the first capacitor C1.

[0047] One end of a reactor L1 is connected to the connection point of the switching devices S5 and S6. One end of a reactor L2 is connected to the connection point of the switching devices S7 and S8. A primary winding of a transformer Tr is connected between the other end of the reactor L1 and the other end of the reactor L2.

[0048] A second capacitor C2 is connected between one DC terminal and the other DC terminal of the cell. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. Switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

[0049] One end of a reactor L3 is connected to the connection point of the switching devices S9 and S11. One end of a reactor L4 is connected to the connection point of the switching devices S10 and S12. A secondary winding of a transformer Tr is connected between the other end of the reactor L3 and the other end of the reactor L4. Note that the reactors L1 to L4 in FIG. 1(b) may be omitted.

[0050] The cell in Fig. 1(b) adjusts the phase difference between the output voltages of the inverters on both sides of the transformer Tr to adjust the active power to be accommodated. Gate signals for the switching devices S5 to S12 are generated so that the phase difference between the output voltages of the inverters on both sides of the transformer Tr becomes the desired phase difference (i.e., so that the desired active power is accommodated). The gate signals for the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, so a detailed description thereof will be omitted here, and a conventionally known method will be used.

[0051] The gate signal "gate" of the switching devices S1 to S4 of the full bridge circuit provided on the AC system AC side receives a gate signal generated according to the first embodiment, which will be described later.

[0052] Another example of a circuit diagram for one cell is shown in Figure 2. In this example, an LLC resonant converter is used as the bidirectional isolated DC / DC converter.

[0053] 2, a third capacitor C3 is connected between the connection point of the switching devices S5 and S6 and the reactor L1. A fourth capacitor C4 is connected between the connection point of the switching devices S7 and S8 and the reactor L2. A fifth capacitor C5 is connected between the connection point of the switching devices S9 and S11 and the reactor L3. A sixth capacitor C6 is connected between the connection point of the switching devices S10 and S12 and the reactor L4.

[0054] The NOT circuit 37 inverts the 50% duty ratio signal. The dead time unit 38 inserts dead time into the 50% duty ratio signal and the inverted signal of the 50% duty ratio signal, and outputs the result as gate signals to the switching devices S5 to S12 of the inverters on both sides of the transformer Tr. The other circuit configurations are the same as those in FIG. 1(b).

[0055] In FIG. 2, third to sixth capacitors C3 to C6 are connected in series to a transformer (high frequency transformer) Tr. This causes resonance between the leakage inductance of the transformer Tr and reactors L1 to L4 connected in series. The inverters on both sides of the transformer Tr output AC voltages of this resonance frequency. The duty ratio of the gate signals driving the inverters on both sides of the transformer Tr is fixed at 50%. This allows active power according to the difference in DC voltages on both sides of the transformer Tr to be accommodated through the transformer Tr. The gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to the present invention, so a detailed description thereof will be omitted here.

[0056] The gate signal "gate" of the switching devices S1 to S4 of the full bridge circuit provided on the AC system AC side receives a gate signal generated according to the first embodiment, which will be described later.

[0057] 3 shows a block diagram of the corrected voltage command value generating unit of the present embodiment 1. In the present embodiment 1, the voltage responsibilities of each cell are equalized in an application in which it is not necessary to equalize the power responsibilities of each cell.

[0058] The first adders 1u, 1v, and 1w calculate the voltage command value v U *,v V *,v W * is superimposed with the zero-phase voltage obtained in the previous calculation cycle, and the corrected voltage command value v U *',v V *',v W *' is output. Voltage command value v U *,v V *,v W * may be given as a sine wave of a fixed amplitude and frequency, or may be obtained by feedback control of voltage or current.

[0059] Corrected voltage command value v U *',v V *',v W *' generates a gate signal (on / off command signal) by comparing carrier triangular waves in the subsequent stage (gate signal generating section) and inputs it to the switching devices S1 to S4 of the full bridge circuit provided on the AC side of the AC system of each cell in Figures 1(b) and 2. The above gate signal generating method is disclosed in Patent Document 6.

[0060] The amplitude detectors 2u, 2v, and 2w detect the corrected voltage command value v U *',v V *',v W In the first embodiment, the amplitude detectors 2u, 2v, and 2w detect the amplitude of the correction voltage command value v U *',v V *',v W As an example of calculating the effective value of *', the following is configured. In addition, as shown in the third embodiment described later, U *',vV *',v W The amplitude of the fundamental wave of *' may be obtained, or the corrected voltage command value v U *',v V *',v W The peak value per period of *' may be stored and output.

[0061] The first multipliers 3u, 3v, and 3w calculate the correction voltage command value v U *',v V *',v W The first low-pass filters 4u, 4v, and 4w extract the DC components per period from the outputs of the first multipliers 3u, 3v, and 3w. The square root calculators 5u, 5v, and 5w calculate the square roots of the outputs of the first low-pass filters 4u, 4v, and 4w. The outputs of the square root calculators 5u, 5v, and 5w are used as the compensation voltage command value v U *',v V *',v W *' is the amplitude.

[0062] The square root calculators 5u, 5v, and 5w may be omitted because of their high calculation load. In this case, attention should be paid to the fact that the gain is likely to be excessive because the target to be amplified by the amplifiers 9u, 9v, and 9w described below is the square of the effective value.

[0063] The second adder 6 calculates the correction voltage command value v U *',v V *',v W The second multiplier 7 calculates the sum of the amplitudes of the corrected voltage command value v U *',v V *',v W The sum of the amplitudes of *' (output of the second adder 6) is multiplied by 1 / 3 to obtain the three-phase average value. The first subtractors 8u, 8v, and 8w multiply the three-phase average value by the correction voltage command value v U *',v V *',v W *' and find the deviation of .

[0064] The amplifiers 9u, 9v, and 9w amplify the outputs (deviations between the three-phase average value and the amplitude) of the first subtractors 8u, 8v, and 8w. Here, a proportional integrator is used as an example.

[0065] A phase output unit (e.g., PLL: Phase-Locked Loop) 10 outputs a phase voltage detection signal v U ,v V ,v W The phase ωt synchronized with the AC voltage of the system is output from the

[0066] Phase voltage detection signal v U ,v V ,v W The line voltage may be detected and converted to a phase voltage by calculation. Also, the phase voltage detection signal v U ,v V ,v W Instead of the voltage command value v U *,v V *,v W * may be input. The system AC voltage input to the phase output unit 10 may be only one representative phase. In motor drive applications, the phase ωt may be detected from a rotary encoder or resolver, or a phase estimated by an observer may be used. Hereinafter, the phase output unit 10 will be referred to as PLL 10.

[0067] The oscillator 11u outputs a voltage command value v U The second subtractor 12v subtracts 2π / 3 from the phase ωt. The oscillator 11v subtracts the voltage command value v from the phase ωt-2π / 3. V The third adder 12w adds 2π / 3 to the phase ωt. The oscillator 11w converts the phase ωt+2π / 3 into the voltage command value v W * Outputs a sine wave with the same phase and amplitude as *.

[0068] The third multipliers 13u, 13v, and 13w multiply the outputs of the amplifiers 9u, 9v, and 9w of each phase by the voltage command values ​​v U *,v V *,v W *Multiply by a sine wave (output of oscillators 11u, 11v, and 11w) synchronized with.

[0069] The fourth adder 14 multiplies the sum of the three third multipliers 13u, 13v, and 13w by the voltage command value vU *,v V *,v W The output of the fourth adder 14 is temporarily stored in the buffer 15, and is used as the voltage command value v U *,v V *,v W * is added to the corrected voltage command value v U *',v V *',v W *' is obtained.

[0070] In the first embodiment, the three-phase voltage command value v U *,v V *,v W The purpose is to make the amplitude of the voltage command value of each phase equal by superimposing a zero-phase voltage on *.

[0071] In the first embodiment, the correction voltage command value v U *',v V *',v W The amplitude of *' is detected and the deviation from the three-phase average value is calculated. U If the amplitude of *' is smaller than the three-phase average value, the corrected voltage command value v U *' is added as a zero-phase voltage, and the corrected voltage command value v U Increase the amplitude of the corrected voltage command value v U If the amplitude of *' is greater than the three-phase average value, the corrected voltage command value v U *' is added as a zero-phase voltage, and the compensation voltage command value v U *' to decrease the amplitude.

[0072] This is done for three phases, and the zero-sequence voltage to be superimposed is the sum of the three phases. In the next calculation cycle, the correction voltage command value v U *',v V *',v W *' amplitude is detected, and if there is an integral element in the amplifier, the deviation becomes zero and the compensation voltage command value v U *',v V *',v W Repeat until the amplitudes of *' become equal. If there is no integral element, repeat until the deviation becomes small enough to correspond to the gain.

[0073] By the above operation, when there is an unbalance in the AC voltage or when an unbalanced AC voltage is intentionally output, the correction voltage command value v U *',v V *',v W *' can be made equal in amplitude.

[0074] In the first embodiment, one of the three phases of the sine wave having the same phase as the voltage command value is a phase obtained by a PLL, a rotary encoder, or a resolver, or a phase estimated by an observer, and the other phases are a phase obtained by adding a fixed value to the phase of the one of the three phases. That is, the corrected voltage command value v U *',v V *',v W It is assumed that *' are synchronized with cosωt, cos(ωt-2π / 3), and cos(ωt+2π / 3), respectively.

[0075] This holds true as long as the PLL 10 is operating normally. If the phase of the AC voltage changes suddenly due to a fault or a sudden load change, the synchronization may temporarily be lost.

[0076] The larger the phase difference, the greater the correction voltage command value v U *',v V *',v W It takes time for the amplitudes of *' to become equal, and especially when the phase difference exceeds π / 2, the compensation voltage command value v U *',v V *',v W This results in the superposition of a zero-sequence voltage which increases the amplitude of *'.

[0077] However, for example, the failure-recovery (FRT) requirement requires that operation be continued for a phase jump of 41° or less, and under this condition, even if the first embodiment is applied, instability will not occur.

[0078] As described above, according to the first embodiment, in a star-connected cell multiplexed inverter including an MMCC-SSBC, the AC output voltages of the cells can be made uniform even when an unbalanced AC voltage occurs or when an unbalanced AC voltage is intentionally output. This eliminates the need to insert a cell into a certain phase or to raise the cell DC voltage of only that phase even if the voltage amplitude of that phase increases.

[0079] Furthermore, since the superimposed zero-phase voltage is only the fundamental wave component, the common mode current can be suppressed.

[0080] In the first embodiment, the DC voltage of all cells needs to be increased or raised in advance, but the increase in the DC voltage can be significantly suppressed compared to the conventional technology, and the increase in the voltage resistance of the cells can be minimized, thereby reducing costs and size.

[0081] Furthermore, since the zero-phase sequence voltage to be superimposed is determined by feedback, the first embodiment can equalize the AC output voltages of the cells even if there is a disturbance, such as an error in detecting the AC voltage.

[0082] [Embodiment 2] 4 shows a block diagram of a correction voltage command value generating unit of the present embodiment 2. The present embodiment 2 differs from the embodiment 1 in the following points.

[0083] The coefficient multipliers 16u, 16v, and 16w calculate the correction voltage command value v U *',v V *',v W *'s amplitude (output of amplitude detectors 2u, 2v, 2w) is multiplied by a factor of N / n U ,N / n V ,N / n W The numerator N of the coefficient is the number of cells in each phase. The denominator n U ,n V ,n W is the number of cells in each phase that are functioning without failure.

[0084] The amplitudes used in the first subtractors 8u, 8v, and 8w are values ​​obtained by multiplying the amplitudes by coefficients, and the three-phase average values ​​are the three-phase average values ​​of the amplitudes after multiplication by the coefficients.

[0085] In the second embodiment, a function to reduce the voltage duty of a phase in which a faulty cell exists is added to the first embodiment. U *',v V *',v W The amplitude of *' is multiplied by a coefficient, and the AC voltage of the phase containing the faulty cell is made to appear larger according to the number of faulty cells, to obtain the average value and deviation.

[0086] By amplifying this deviation and superimposing the resulting zero-phase sequence voltage, the amplitude of the voltage command value for a phase in which a faulty cell exists can be reduced.

[0087] Note that the gate signal is generated based on Fig. 4 for healthy cells that are not faulty. For a faulty cell, the AC system turns on the switching devices S1 and S3, or turns on the switching devices S2 and S4 to output zero voltage, or performs short-circuit treatment with an external switch. Switching devices S5 to S12 are turned off.

[0088] As described above, according to the second embodiment, in addition to the effects of the first embodiment, even if some of the cells fail and short-circuit measures are taken, the AC output voltages of the cells can be made uniform. Even if more cells fail than in the prior art, operation can be continued.

[0089] [Embodiment 3] 5 shows a block diagram of a correction voltage command value generating unit of the present embodiment 3. The present embodiment 3 differs from the embodiment 2 in the following points.

[0090] The oscillator 17 receives the phase ωt output from the PLL 10 and outputs a sine wave sinωt. The oscillator 18 receives the phase ωt output from the PLL 10 and outputs a cosine wave cosωt.

[0091] In the first embodiment, the voltage command value v U* is synchronized with cosωt, and the voltage command value v V * is synchronized with cos(ωt-2π / 3), v W In the above, it is assumed that * is synchronized with cos(ωt+2π / 3), but in the third embodiment, a sine wave synchronized with (in phase with) the voltage command value of each phase is prepared by the following blocks.

[0092] The fourth multiplier 19u is the correction voltage command value v U The fifth multiplier 20u multiplies the output of the fourth multiplier 19u by two. The second low-pass filter 4u multiplies the output of 2v U The DC component is extracted from the second low-pass filter 4u. The output of the second low-pass filter 4u is the corrected voltage command value v U *', the component synchronized with the cosine wave cosωt (v U *In-phase components

[0093] The sixth multiplier 21u calculates the correction voltage command value v U The seventh multiplier 22u multiplies the output of the sixth multiplier 21u by two. The third low-pass filter 4u multiplies the output of 2v U The DC component is extracted from *'sinωt. The output of the third low-pass filter 4u is the corrected voltage command value v U *', the component synchronized with the sine wave sinωt (v U *orthogonal components).

[0094] The eighth multiplier 23u is U *The in-phase component is multiplied by the cosine wave cosωt. The ninth multiplier 24u multiplies v U *The product of the orthogonal component and the sine wave sinωt is calculated. The fifth adder 25u adds the outputs of the eighth and ninth multipliers 23u and 24u. The output of the fifth adder 25u is the voltage command value v U The third multiplier 13u multiplies this sine wave by the output of the U-phase amplifier 9u instead of cosωt. The same applies to the V-phase and W-phase.

[0095] Accordingly, the corrected voltage command value v U *',v V *',v WThe amplitude detectors 2u, 2v, and 2w of the amplifier *' are modified to the following configuration, which uses the values ​​of the above blocks to determine the amplitude of the fundamental wave. As in the second embodiment, the effective value may be used, or the peak value per period may be stored and output.

[0096] The tenth multiplier 26u is U *In-phase components and v U *The square of each of the quadrature components is calculated. The sixth adder 27u adds the outputs of the two tenth multipliers 26. The square root calculator 28u calculates the square root of the output of the sixth adder 27u. The square root calculator 28u may be omitted because of its high calculation load. The precautions in this case are the same as those in the first embodiment. The same applies to the V phase and the W phase.

[0097] In the third embodiment, the correction voltage command value v U *',v V *',v W The difference from the first embodiment is that a sine wave synchronized with the phase jump is accurately obtained. As a result, when the phase jump in the system occurs frequently, or when operation is required to continue with a phase jump exceeding the FRT requirement, the corrected voltage command value v U *',v V *',v W This has the effect of shortening the time until the amplitudes of *' become equal and preventing the feedback control from becoming unstable.

[0098] In addition, in synchronous motor drive applications, a rotary encoder or the like is used to detect the phase ωt, but the phase of the rotary encoder does not necessarily match the voltage phase. In the first and second embodiments, correction is required when the difference is large, but the third embodiment can be applied without correction even if the difference is large.

[0099] According to the third embodiment, when the system is unstable and phase jumps occur frequently, and when operation continuation is required even for a large phase jump, the convergence time can be shortened and instability can be prevented more than in the first and second embodiments. Also, the third embodiment can be easily applied to motor drive applications. However, the calculation load is smaller in the first and second embodiments.

[0100] [Embodiment 4] 6 shows a block diagram of a correction voltage command value generating unit of the embodiment 4. The embodiment 4 is a combination of the embodiment 3 with feedforward control.

[0101] The input for feedforward control is the voltage command value v U *,v V *,v W *, but it is necessary to use the value before adding the zero-phase voltage. Phase voltage detection signal v U ,v V ,v W The input of the feedback control needs to be the sum of the zero-phase sequence voltage by the feedforward control in addition to the zero-phase sequence voltage by the feedback control in the previous calculation cycle.

[0102] In the second coefficient multipliers 29u, 29v, and 29w, the voltage command value v U *,v V *,v W *(or phase voltage detection signal v U ,v V ,v W ) with the coefficient N / n U ,N / n V ,N / n W The numerator of the coefficient, N, is the number of cells in each phase. In the example in Figure 1, N=3. The denominator of the coefficient, n U ,n V ,n W is the number of cells in each phase that are operating without failure. The voltage command value v U *,v V *,v W *(or phase voltage detection signal v U ,v V ,v W ) is multiplied by this coefficient.

[0103] The first dq converter 30 has a coefficient N / n U ,N / n V ,N / n W The voltage command value v U *,v V*,v W * is converted to a value on a rotating coordinate system synchronized with the system frequency based on the phase ωt.

[0104] When only the DC component is extracted from the output of the first dq converter 30, the d-axis component is the voltage command value v U *,v V *,v W *Positive-phase d-axis component of V 1d , the q-axis component is the positive-phase q-axis component V 1q If the PLL 10 is operating normally, the positive phase q-axis component V 1q is zero and therefore not used.

[0105] The second dq converter 31 has a coefficient N / n U ,N / n V ,N / n W The voltage command value v U *,v V *,v W * is converted to a value on a rotating coordinate system that rotates in the opposite direction to the system frequency based on the phase -ωt.

[0106] When only the DC component is extracted from the output of the second dq converter 31, the voltage command value v U *,v V *,v W *The negative-phase d-axis component of V 2d , reverse phase q-axis component V 2q It becomes.

[0107] The calculator 32 calculates the positive-phase d-axis component V 1d , Positive phase q-axis component V 1q , out-of-phase d-axis component V 2d , reverse phase q-axis component V 2q Using equation (1) described later, the zero-phase voltage d-axis component V 0d , zero-phase voltage q-axis component V 0q Using equations (2) and (3) instead of equation (1), we obtain the zero-phase voltage d-axis component V 0d and the zero-phase voltage q-axis component V 0q In this calculator 32, when the amplitudes of the positive and negative phase components of the AC voltage are substantially equal, V 0d =V 0q =Output 0.

[0108] The eleventh multiplier 33 multiplies the zero-phase voltage d-axis component V 0d The twelfth multiplier 34 calculates the product of the zero-phase voltage q-axis component V 0q and the sine wave sinωt.

[0109] The seventh adder 35 multiplies the V 0d cosωt and V output by the 12th multiplier 34 0q Find the sum of sinωt.

[0110] The eighth adders 36u, 36v, and 36w calculate the voltage command value v U *,v V *,v W *Each of the V calculated by the seventh adder 35 0d cosωt+V 0q In the fourth embodiment, the outputs of the eighth adders 36u, 36v, and 36w are output to the first adders 1u, 1v, and 1w. The first adders 1u, 1v, and 1w superimpose the zero-phase voltage obtained in the previous calculation cycle on the outputs of the eighth adders 36u, 36v, and 36w to obtain the correction voltage command value v U *',v V *',v W *' is output.

[0111] Equations (1) to (3) are shown below.

[0112]

number

[0113] Positive phase q-axis component V 1q If is close to zero, equation (1) can be approximated by equation (2).

[0114]

number

[0115] Positive phase q-axis component V 1qIf is equal to zero, then equation (1) can be simplified to equation (3). In equation (3), V1 represents the positive-sequence component of the AC voltage.

[0116]

number

[0117] In the fourth embodiment, in comparison with the third embodiment, the correction voltage command value v U *',v V *',v W *' are made equal, and deviations due to detection errors are corrected by feedback. Therefore, even if the feedback gain is reduced, the correction voltage command value v U *',v V *',v W The time it takes for the amplitudes of *' to become equal can be shortened, and stability is improved. In addition to the effect of feedback, which can reduce deviation (it can be reduced to zero by using an integrating amplifier), the effect of feedforward can also be obtained.

[0118] As described above, according to the fourth embodiment, the zero-phase voltage to be superimposed is determined by using both feedforward and feedback. Even if the feedback gain is reduced, the response to the voltage fluctuation is high speed, and the AC output voltage of the cells can be made uniform even if there is a disturbance while improving stability.

[0119] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims. [Explanation of symbols]

[0120] AC…Alternating current system 1u, 1v, 1w...First adder 2u, 2v, 2w...Amplitude detector 3u,3v,3w…1st multiplier 4u, 4v, 4w...1st low pass filter 5u,5v,5w…Square root calculator 6...Second adder 7...Second multiplier 8u, 8v, 8w...First subtractor 9u, 9v, 9w...Amplifier 10…Phase output section (PLL) 11u, 11v, 11w...Oscillators 12v…Second subtractor 12w…3rd adder 13u, 13v, 13w...Second multiplier 14...4th adder 15…Buffer

Claims

1. A multiple-cell inverter including: a plurality of cells connected in multiplex to each phase of an AC system by star connection, the cells having a full-bridge circuit on the AC system side; a correction voltage command value generating unit that generates a correction voltage command value by superimposing a zero-phase sequence voltage having the same frequency as a fundamental wave on a voltage command value; and a gate signal generating unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, The correction voltage command value generating unit a multi-cell inverter, characterized in that if the amplitude of the voltage command value for a certain phase is larger than the amplitude of the voltage command value for another phase, a sine wave of an opposite phase to the certain phase is superimposed on the voltage command value as the zero-sequence voltage, and if the amplitude of the voltage command value for a certain phase is smaller than the amplitude of the voltage command value for the other phase, a sine wave of the same phase as the certain phase is superimposed on the voltage command value as the zero-sequence voltage.

2. The correction voltage command value generating unit a first adder that adds the zero-phase voltage to the voltage command value and outputs the corrected voltage command value; an amplitude detector that outputs the amplitude of the correction voltage command value for each phase; a first subtractor that calculates a deviation between a three-phase average value of the amplitude of the correction voltage command value and the amplitude of the correction voltage command value; an amplifier that amplifies the deviation between the three-phase average value and the amplitude; a third multiplier that multiplies the output of the amplifier by a sine wave having the same phase as the voltage command value; a fourth adder that adds up the outputs of the third multipliers for three phases and outputs the sum as the zero-phase voltage; 2. The cell multiple inverter according to claim 1, further comprising:

3. 3. The cell-multiplexing inverter according to claim 2, wherein the amplitude used in the first subtractor is a value obtained by multiplying the amplitude of the voltage command value by a coefficient based on the number of failed cells, and the three-phase average value is a three-phase average value of the amplitude after multiplication by the coefficient.

4. 2. The multi-cell inverter according to claim 1, wherein the amplitude of the voltage command value is an effective value of the voltage command value.

5. 2. The multi-cell inverter according to claim 1, wherein the amplitude of the voltage command value is a value obtained by extracting the amplitude of a fundamental wave component of the voltage command value.

6. 2. The multi-cell inverter according to claim 1, wherein the amplitude of the voltage command value is a peak value per one period of the voltage command value.

7. 3. The cell multi-inverter according to claim 2, wherein one of the three phases of the sine wave having the same phase as the voltage command value is a phase obtained by a PLL, a rotary encoder, or a resolver, or a phase estimated by an observer, and the other phase is a phase obtained by adding a fixed value to the phase of the one of the three phases.

8. The correction voltage command value generating unit A phase output unit that outputs a phase ωt synchronized with the AC voltage of the system; a fourth multiplier that multiplies the correction voltage command value by cosωt; a fifth multiplier that doubles the output of the fourth multiplier; a second low-pass filter that extracts a DC component from the output of the fifth multiplier and outputs an in-phase component of the correction voltage command value that is synchronized with cosωt; a sixth multiplier that multiplies the correction voltage command value by sinωt; a seventh multiplier that doubles the output of the sixth multiplier; a third low-pass filter that extracts a DC component from the output of the seventh multiplier and outputs an orthogonal component of the correction voltage command value that is synchronized with sinωt; an eighth multiplier that multiplies the in-phase component by cosωt; a ninth multiplier for multiplying the quadrature component by sinωt; a fifth adder that adds the output of the eighth multiplier and the output of the ninth multiplier; 3. The multi-cell inverter according to claim 2, further comprising: a fifth adder for outputting an output of the fifth adder that is a sine wave having the same phase as the voltage command value.

9. The correction voltage command value generating unit A phase output unit that outputs a phase ωt synchronized with the AC voltage of the system; a first dq converter that converts the phase voltage detection signal or the voltage command value into a value on a rotating coordinate system synchronized with a system frequency; a second dq converter that converts the phase voltage detection signal or the voltage command value into a value on a rotating coordinate system that rotates in a direction opposite to the system frequency; a calculator that calculates a zero-phase d-axis component and a zero-phase q-axis component that make the AC side output voltages of the cells uniform, based on a positive-phase d-axis component and a positive-phase q-axis component that are DC components extracted from the output of the first dq converter, and a negative-phase d-axis component and a negative-phase q-axis component that are DC components extracted from the output of the second dq converter; a tenth multiplier that multiplies the zero-phase voltage d-axis component by cosωt; an eleventh multiplier that multiplies the zero-phase voltage q-axis component by sinωt; a seventh adder that adds an output of the tenth multiplier and an output of the eleventh multiplier; an eighth adder that adds an output of the seventh adder to the voltage command value; Equipped with 3. The multi-cell inverter according to claim 2, wherein the first adder uses the voltage command value to which the output of the seventh adder is added in the eighth adder.

10. 10. The multi-cell inverter according to claim 9, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (1). [0010] V ０ｄ : d-axis component of zero-phase voltage V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ : Negative-phase voltage d-axis component V ２ｑ : negative sequence voltage q-axis component

11. 10. The multi-cell inverter according to claim 9, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (2). [0025] V ０ｄ : d-axis component of zero-phase voltage V ０ｑ : Zero-phase voltage q-axis component V １ｄ : Positive sequence voltage d-axis component V １ｑ : Positive sequence voltage q-axis component V ２ｄ : Negative-phase voltage d-axis component V ２ｑ : negative sequence voltage q-axis component

12. 10. The multi-cell inverter according to claim 9, wherein the calculator calculates the d-axis component of the zero-phase-sequence voltage and the q-axis component of the zero-phase-sequence voltage based on equation (3). [0030] V ０ｄ : d-axis component of zero-phase voltage V ０ｑ : Zero-phase voltage q-axis component V ２ｄ : Negative-phase voltage d-axis component V ２ｑ : negative sequence voltage q-axis component V １ : Positive-sequence voltage component

13. The phase voltage detection signal or the voltage command value used in the first dq converter and the second dq converter is 10. The multi-cell inverter according to claim 9, wherein the phase voltage detection signal or the voltage command value is multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure.

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