Low-Voltage, Low-Power MEMS Transducers with Direct Interconnect Capability

Abstract

To provide a low voltage, low power MEMS transducer with a direct interconnect capability.SOLUTION: A transceiver (210) includes an array of pMUT elements (302), where each pMUT element (302) includes: a substrate (1030); a membrane (1034) suspending from the substrate (1030); a bottom electrode (1002) disposed on the membrane (1034); a piezoelectric layer (1010) disposed on the bottom electrode (1002); and a first electrode (1008) disposed on the piezoelectric layer (1010). Each pMUT element exhibits one or more modes of vibration.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 62,429,832, filed December 4, 2016, entitled "A Configurable Ultrasonic Line Imager," U.S. Provisional Application No. 62,429,833, filed December 4, 2016, entitled "Low Voltage, Low Power MEMS Transducer with Direct Interconnect," and U.S. Provisional Application No. 62,433,782, filed December 13, 2016, entitled "Micromachined Transceiver Array," the contents of which are incorporated herein by reference in their entireties.

[0002] A. Technical Field The present invention relates to imaging devices, and more particularly to imaging devices having a configurable ultrasound line imager. [Background technology]

[0003] B. Background of the Invention Non-invasive imaging systems for imaging internal tissues, bones, blood flow or organs of a human or animal body and displaying the images require transmitting a signal into the body and receiving a reflected signal from the body part being imaged. Typically, the transducers used in imaging systems are called transceivers, some of which are based on the photoacoustic or ultrasonic effect. Generally, transceivers are used for imaging, but are not necessarily limited to imaging. For example, transceivers can be used in medical imaging, flow measurement in tubes, speaker and microphone arrays, lithotripsy, localized tissue heating for therapy or high intensity focused ultrasound (HIFU) for surgery.

[0004] Conventional transducers constructed from bulk piezoelectric (PZT) materials typically require very high voltages to generate a transmit signal, typically pulses of 100V or more. This high voltage translates to high power dissipation, since the power consumption / dissipation in the transducer is proportional to the square of the driving voltage. There is also a limit to how hot the surface of the probe can get, and since power consumption is proportional to the heat generated by the probe, this limits how much power can be dissipated in the probe. In conventional systems, the heat generation requires cooling devices for some probes, increasing the manufacturing cost and weight of the probe. In general, the weight of conventional probes is also an issue, since many ultrasound technicians using these probes are known to suffer from muscle injuries.

[0005] Conventional ultrasound probes used in medical imaging typically use PZT material or other piezoelectric ceramic and polymer composites. The probe typically houses the transducer and some other electronic circuitry with a means for displaying the image on a display unit. To manufacture conventional bulk PZT elements for a transducer, one simply cuts a thick slab of piezoelectric material into large rectangular PZT elements. These rectangular PZT elements are very expensive to manufacture because the manufacturing process involves precisely cutting rectangular pieces of thick PZT or ceramic material and mounting them on a substrate at precise intervals. Furthermore, the impedance of the transducer is much higher than the impedance of the transmitting and receiving electronics for the transducer.

[0006] In conventional systems, the transmit and receive electronics for the transducer are often located far away from the probe, requiring a small coaxial cable between the transducer and the electronics. Typically, the cable needs to have a precise length for delay and impedance matching, and quite often an additional impedance matching network is required for efficient connection of the transducer to the electronics via the cable.

[0007] Advances in micromachining technology allow sensors and actuators such as capacitive micromachined ultrasonic transducers (cMUTs) and piezoelectric micromachined ultrasonic transducers (pMUTs) to be efficiently formed on substrates. Compared to conventional transducers with bulk piezoelectric material, pMUTs have simpler and more powerful interconnects between electronic circuits and the transducer, offer greater flexibility in operating frequencies, and offer the potential to produce higher quality images while being less bulky and less expensive. Summary of the Invention [Problem to be solved by the invention]

[0008] Although the basic concepts of these transducers were disclosed in the early 1990s, commercial implementation of these concepts faces many challenges. For example, traditional cMUT sensors are prone to failure or performance drift due to charge accumulation during high voltage operation, have difficulty generating sufficiently high acoustic pressure at low frequencies, and are inherently nonlinear. Traditional pMUTs have been a promising alternative, but suffer from issues with transmit and receive inefficiencies, still require relatively high operating voltages, and have limited bandwidth. Thus, there is a need for pMUTs that have improved efficiency, can operate at lower voltages, and exhibit high bandwidth. [Means for solving the problem]

[0009] In an embodiment, the transceiver includes: a substrate; a membrane suspended from the substrate; a bottom electrode disposed on the membrane; a piezoelectric layer disposed on the bottom electrode; and first and second top electrodes disposed on the piezoelectric layer, the first top electrode being electrically isolated from the second top electrode; the piezoelectric layer including a first portion located under the first top electrode and poled in a first orientation, and a second portion located under the second top electrode and poled in a second orientation opposite the first orientation.

[0010] In an embodiment, the transceiver includes: a transceiver substrate and an ASIC chip. The transceiver substrate includes: a substrate; at least one membrane disposed on the substrate; and a plurality of piezoelectric elements disposed on the at least one membrane, each of the plurality of piezoelectric elements including a bottom electrode, a piezoelectric layer disposed on the bottom electrode, and first and second top electrodes disposed on the piezoelectric layer, the first top electrode being electrically and spatially separated from the second top electrode; the piezoelectric layer including a first portion located under the first top electrode and poled in a first orientation, and a second portion located under the second top electrode and poled in a second orientation opposite to the first orientation. The ASIC chip includes at least one circuit electrically coupled to the transceiver substrate by a three-dimensional interconnect mechanism for controlling one or more of the plurality of piezoelectric elements; and a control unit electrically coupled to the at least one circuit for controlling the at least one circuit.

[0011] In an embodiment, an imaging system includes a first and a second imaging device, each of the first and second imaging devices including: a substrate; at least one membrane disposed on the substrate; and a plurality of piezoelectric elements disposed on the at least one membrane, each of the plurality of piezoelectric elements including: a lower electrode, a piezoelectric layer disposed on the lower electrode, and first and second upper electrodes disposed on the piezoelectric layer, the first upper electrode being electrically and spatially separated from the second upper electrode; the piezoelectric layer including a first portion located under the first upper electrode and poled in a first orientation, and a second portion located under the second upper electrode and poled in a second orientation opposite the first orientation. The first imaging device transmits pressure waves toward a target to be imaged, and the second imaging device is located at a different location than the first imaging device and receives pressure waves reflected from the target. [Brief description of the drawings]

[0012] Reference will now be made to embodiments of the present invention, examples of which may be illustrated in the accompanying drawings, which are intended to be illustrative, not limiting, and in which: While the invention will generally be described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.

[0013] [Figure 1] 1 shows a schematic diagram of an imaging system according to an embodiment of the present disclosure.

[0014] [Diagram 2] 1 shows a schematic diagram of an ultrasound imager according to an embodiment of the present disclosure.

[0015] [Figure 3A] 1 illustrates a side view of an exemplary transceiver array in accordance with an embodiment of the present disclosure.

[0016] [Figure 3B] 1 illustrates a top view of a transceiver tile according to an embodiment of the present disclosure.

[0017] [Figure 4] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Diagram 5] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 6] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 7] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 8] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure.

[0018] [Figure 9] 1 shows a schematic diagram of a piezoelectric element according to an embodiment of the present disclosure.

[0019] [Figure 10A]1 shows a schematic diagram of a piezoelectric element according to an embodiment of the present disclosure.

[0020] [Figure 10B] 10B shows a symbolic representation of the piezoelectric element in FIG. 10A.

[0021] [Figure 10C] 1 shows a schematic cross-sectional view of an exemplary piezoelectric element according to an embodiment of the present disclosure.

[0022] [Figure 10D] 1 shows a schematic diagram of a piezoelectric element according to an embodiment of the present disclosure.

[0023] [Figure 10E] 1 shows a schematic diagram of a piezoelectric element according to an embodiment of the present disclosure.

[0024] [Figure 10F] 1 shows a schematic diagram of a piezoelectric element according to an embodiment of the present disclosure.

[0025] [Figure 10G] FIG. 10F illustrates a bottom view of the piezoelectric element of FIG. 10F according to an embodiment of the present disclosure.

[0026] [Figure 10H] 10F shows a cross-sectional view of the piezoelectric element of FIG. 10F according to an embodiment of the present disclosure.

[0027] [Figure 11] 1 shows a schematic diagram of a piezoelectric element according to an embodiment of the present disclosure.

[0028] [Figure 12] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 13] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 14] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 15]4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. [Figure 16] 4 illustrates steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure.

[0029] [Figure 17A] 1 illustrates the dipole orientation of a piezoelectric material before, during, and after a poling process, according to an embodiment of the present disclosure.

[0030] [Figure 17B] 1 illustrates a flowchart of an exemplary process for poling a piezoelectric layer, according to an embodiment of the present disclosure.

[0031] [Figure 18A] 1 shows a schematic diagram of an imaging assembly according to an embodiment of the present disclosure.

[0032] [Figure 18B] 1 shows a schematic diagram of an imaging assembly according to an embodiment of the present disclosure.

[0033] [Figure 19A-1] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0034] [Figure 19A-2] 1 illustrates a side view of an imaging assembly according to an embodiment of the present disclosure.

[0035] [Figure 19B-1] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0036] [Figure 19B-2] 1 illustrates a side view of an imaging assembly according to an embodiment of the present disclosure.

[0037] [Figure 19C] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0038] [Figure 19D] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0039] [Figure 19E] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0040] [Figure 19F] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0041] [Figure 19G] 1 illustrates a top view of a transceiver substrate and an ASIC chip according to an embodiment of the present disclosure.

[0042] [Figure 20] 1 shows a schematic diagram of an array of piezoelectric elements capable of performing two-dimensional and three-dimensional imaging according to an embodiment of the present disclosure.

[0043] [Figure 21] FIG. 2 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0044] [Figure 22] FIG. 2 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0045] [Figure 23] 1 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0046] [Figure 24] 1 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0047] [Diagram 25] FIG. 2 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0048] [Figure 26] FIG. 2 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0049] [Figure 27] FIG. 2 shows a schematic diagram of an array of piezoelectric elements according to an embodiment of the present disclosure.

[0050] [Figure 28] 1 shows a schematic diagram of an imaging system according to an embodiment of the present disclosure.

[0051] [Figure 29] 1 shows a schematic diagram of an imaging system according to an embodiment of the present disclosure.

[0052] [Diagram 30] 1 illustrates an embodiment of a piezoelectric element coupled to a circuit element according to an embodiment of the present disclosure.

[0053] [Diagram 31] 1 illustrates a circuit for controlling multiple piezoelectric elements according to an embodiment of the present disclosure.

[0054] [Diagram 32] 1 illustrates a circuit for controlling multiple piezoelectric elements according to an embodiment of the present disclosure.

[0055] [Diagram 33] 4 illustrates a transmit drive signal waveform according to an embodiment of the present disclosure.

[0056] [Diagram 34] 4 illustrates a transmit drive signal waveform according to an embodiment of the present disclosure.

[0057] [Diagram 35] 4 illustrates a transmit drive signal waveform according to an embodiment of the present disclosure.

[0058] [Diagram 36] 1 illustrates input / output signals of various circuits in an imaging assembly according to an embodiment of the present disclosure.

[0059] [Figure 37A] 13 shows a plot of transmitted pressure wave amplitude as a function of angle in accordance with an embodiment of the present disclosure.

[0060] [Figure 37B] 1 illustrates a window for an apodization process, according to an embodiment of the present disclosure.

[0061] [Figure 38] 1 shows a schematic diagram of an imaging assembly according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0062] In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without these details. Furthermore, one skilled in the art will recognize that the embodiments of the present disclosure described below can be implemented in a variety of ways, such as a process, an apparatus, a system, a device, or a method on a tangible computer-readable medium.

[0063] Those skilled in the art will recognize that: (1) certain manufacturing steps may be performed optionally; (2) steps may not be limited to the particular order described herein; and (3) certain steps may be performed in differing orders, including simultaneously.

[0064] The elements / components depicted in the figures depict exemplary embodiments of the disclosure and are intended to avoid obscuring the disclosure. Reference in the specification to "one embodiment," "preferred embodiment," "an embodiment," or "embodiment" means that a particular feature, structure, characteristic, or function described in connection with that embodiment is included in at least one embodiment of the disclosure and may be included in multiple embodiments. The appearance of the phrases "in one embodiment," "in an embodiment," or "in an embodiment" in various places in the specification do not necessarily all refer to the same embodiment or embodiments. The terms "including," "including," "having," and "having" are to be understood as open terms, and the accompanying listings are examples and are not intended to be limited to the listed items. Any headings used herein are merely for organizational purposes and are not to be used to limit the scope of the specification or claims. Additionally, the use of certain terms in various places in the specification is for illustrative purposes and should not be construed as limiting.

[0065] In embodiments, pMUT transducers and transducer assemblies may be used to generate images of internal organs of the human / animal body, as well as for other therapeutic applications using ultrasound beams to heat tissue for therapy or to focus high power ultrasound beams for microsurgery. In embodiments, piezoelectric elements may be used for tomography applications.

[0066] In embodiments, the manufacturing costs of pMUTs may be reduced by applying modern semiconductor and wafer processing techniques. In embodiments, thin film piezoelectric layers may be spun or sputtered onto a semiconductor wafer and later patterned to form piezoelectric sensors each having two or more electrodes. In embodiments, each piezoelectric element may be designed with the ability to emit or receive signals at one frequency, known as the center frequency, as well as at second and / or additional frequencies. Hereinafter, the terms piezoelectric element, pMUT, transceiver, and pixel are used interchangeably.

[0067] FIG. 1 shows a schematic diagram of an imaging system 100 according to an embodiment of the present disclosure. As shown, the system 100 may include an imager 120 that generates and transmits pressure waves 122 toward an internal organ 112, such as a heart, in a transmission mode / process; and a device 102 that transmits and receives signals to the imager through a communication channel 130. In an embodiment, the internal organ 112 may reflect a portion of the pressure waves 122 toward the imager 120, which may capture the reflected pressure waves and generate an electrical signal in a reception mode / process. The imager 120 may communicate the electrical signal to the device 102, which may use the electrical signal to display an image of the organ or target on a display / screen 104.

[0068] In an embodiment, the imager 120 may be used to perform one-dimensional imaging, also known as A-scan, two-dimensional imaging, also known as B-scan, three-dimensional imaging, also known as C-scan, and Doppler imaging, and the imager may be switched under program control into various imaging modes.

[0069] In an embodiment, the imager 120 may be used to obtain images of the internal organs of the animal. The imager 120 may also be used to determine the direction and velocity of blood flow in arteries and veins, as in Doppler mode imaging, and to measure tissue stiffness. In an embodiment, the pressure waves 122 may be acoustic, ultrasonic or photoacoustic waves that can pass through the human / animal body and be reflected by the internal organs, tissues, or arteries and veins.

[0070] In an embodiment, imager 120 may be a portable device and may communicate signals wirelessly (using a protocol such as the 802.11 protocol) or via cable (such as USB2, USB 3, USB 3.1 and USB-C) with device 102 over a communication channel 130. In an embodiment, device 102 may be a mobile device such as a cell phone or iPad®, or a stationary computing device capable of displaying images to a user.

[0071] In embodiments, the imager may be configured to simultaneously transmit and receive ultrasound waveforms. Certain piezoelectric elements may be configured to transmit pressure waves towards the target organ being imaged, while other piezoelectric elements may receive pressure waves reflected from the target organ and generate an electric charge in response to the received waves.

[0072] FIG. 2 shows a schematic diagram of an imager 120 according to an embodiment of the present disclosure. In an embodiment, the imager 120 may be an ultrasound imager. As depicted in FIG. 2, the imager 120 includes: a transceiver tile(s) 210 for transmitting and receiving pressure waves; a coating layer 212 that acts as a lens to control the propagation direction of the pressure waves and / or focus the pressure waves, and also serves as an impedance interface between the transceiver tile and the human body 110; a control unit 202, such as an ASIC chip (or simply ASIC), coupled to the transducer tile 210 by bumps, for controlling the transceiver tile 210; a field programmable gate array (FPGA) 214 for controlling the components of the imager 120; and an analogue front end (AFE) for processing / conditioning the signals. an acoustic absorbing layer 203 for absorbing waves generated by the transducer tile and propagating towards the circuitry 215; a communication unit 208 for communicating data with an external device, such as the device 102, through one or more ports 216; a memory 218 for storing data; a battery 206 for providing power to the imager components; and optionally a display 217 for displaying an image of the target organ.

[0073] In an embodiment, the device 102 may have a display / screen. In such a case, the imager 120 may not include a display. In an embodiment, the imager 120 may receive power from the device 102 through one of the ports 230. In such a case, the imager 120 may not include a battery 206. It is noted that one or more of the components of the imager 120 may be combined into a single integrated electrical device. Similarly, each component of the imager 120 may be implemented in one or more electrical devices.

[0074] In an embodiment, the user may apply gel onto the skin of the human body 110 before the body 110 comes into direct contact with the coating layer 212. This may improve impedance matching at the interface between the coating layer 212 and the human body 110, i.e., reducing losses of the pressure wave 122 at the interface and also reducing losses of the reflected wave towards the imager 120. In an embodiment, the transceiver tile 210 may be mounted on a substrate and attached to an acoustic absorber layer. This layer absorbs any ultrasound signals radiated in the opposite direction that would otherwise be reflected and may interfere with the quality of the image.

[0075] As discussed below, the coating layer 212 may simply be a flat matching layer to maximize the transmission of the acoustic signal from the transducer to the body and vice versa. In an embodiment, the thickness of the coating layer 212 may be a quarter wavelength of the pressure waves generated by the transducer tiles 202. Beam focusing in the elevation direction along the length of the array is not required in this case, as it can be implemented electronically in the control unit 202. Nevertheless, a focusing lens may be designed in some cases. The imager 120 uses the reflected signal to generate an image of the organ 112, and the results may be displayed on the screen in various formats, such as graphs, plots, and statistics shown with or without the image of the organ 112.

[0076] In embodiments, the control unit 202, such as an ASIC, may be assembled with the transceiver tile as a unit. In other embodiments, the control unit 202 may be located external to the imager 120 and electrically coupled to the transceiver tile 210 via a cable. In embodiments, the imager 120 may include a housing that encloses the components 202-215 and a heat dissipation mechanism for dissipating thermal energy generated by those components.

[0077] FIG. 3A illustrates a schematic diagram of an exemplary transceiver array having three transceiver tiles 210, according to an embodiment of the disclosure. The tiles may be on a planar or curved surface. FIG. 3B illustrates a top view of a transceiver tile 210 including one or more piezoelectric elements 302, according to an embodiment of the disclosure. As shown, the transceiver tile 210 may include a transceiver substrate 304 and one or more piezoelectric elements 302 disposed on the transceiver substrate 304.

[0078] Unlike conventional systems that use bulk piezoelectric elements, in embodiments, the pMUT array 302 may be formed on a wafer, which may be diced to form multiple transceiver tiles 210. This process may reduce manufacturing costs since the transceiver tiles 210 may be manufactured in large quantities at low cost. In embodiments, the diameter of the wafer may range from 6 to 12 inches, and many pMUT arrays may be batch manufactured. Furthermore, in the embodiments discussed in connection with FIGS. 18 and 19, the integrated circuit for controlling the pMUT array 302 may be formed in an ASIC chip, such that the pMUT array 302 may be connected to a matching integrated circuit in close proximity, preferably within 25 μm to 100 μm. For example, a transceiver tile 210 may have 1024 pMUT elements 302 and be connected to a matching ASIC chip having an appropriate number of circuits for driving the 1024 pMUT elements 302.

[0079] In embodiments, each piezoelectric element 302 may have any suitable shape, such as a square, a rectangle, and a circle. In embodiments, two or more piezoelectric elements may be connected to form a larger pixel element. In constructing an imager, it is desirable to have a two-dimensional array of piezoelectric elements 302 arranged in orthogonal directions, as shown in FIG. 3B. In embodiments, a row of N piezoelectric elements 302 may be electrically connected in parallel to create a line element. This line element can then provide similar transmission and reception of ultrasonic signals as that achieved by a continuous piezoelectric element of approximately N times the length of each element. This line element may be referred to interchangeably as a column or line or line element. It is understood that the tiles may be arranged in other shapes, such as a circle or other shape. In embodiments, one or more temperature sensors 320 may be located within the transducer tile 210 to measure the temperature of the tile 210. It is noted that the imager 120 may include one or more temperature sensors for measuring the temperature at various locations of the imager 120.

[0080] To mimic a line element of a conventional design, the shape of the piezoelectric element for a given width must be very tall. For example, a line element of a conventional design may be 280 μm wide and 8000 μm tall, with a thickness of 100 μm. However, on a transceiver tile 210, it may be advantageous to design a line element using multiple identical piezoelectric elements 302, each element having its characteristic center frequency. In an embodiment, when multiple piezoelectric elements 302 are connected together, the composite structure (i.e., the line element) may act as one line element with a center frequency consisting of the center frequencies of all the element pixels. In modern semiconductor processes, these center frequencies are well matched to each other, with very little deviation from the center frequency of the line element. It is also possible to mix several pixels with somewhat different center frequencies to create a line with a wider bandwidth compared to a line using only one center frequency.

[0081] In an embodiment, the piezoelectric element 302 is associated with a suspended membrane that vibrates at its center frequency when exposed to a stimulus at that center frequency and behaves like a resonator. These resonators have a selectivity known as the Q factor. In an embodiment, for an ultrasound imager, the Q may typically be designed to be low (close to or around unity) and may be achieved in practical use by a combination of pixel design and loading applied to the pixel. In an embodiment, the loading may be provided by applying a layer of RTV or other material on top of the piezoelectric element, which may facilitate a closer impedance match between the transducer surface emitting and receiving pressure waves and the body part being imaged. In an embodiment, the low Q and well-matched center frequency may allow the line element to essentially act like a line imaging element with substantially one center frequency. In an embodiment, the loading may also include a matching layer underlying the transducer, where the emitted waveform is absorbed by an acoustic absorber.

[0082] In an embodiment, for example, each piezoelectric element 302 may be spaced 250 μm apart on center. For further simplification, assume they are square shaped. Here, the piezoelectric elements 302 in a row may be connected to each other, so as to mimic a conventional line element. For example, 24 piezoelectric elements 302 in a row may form a line element about 6 mm high, with each element being 0.25 mm wide. In an embodiment, this connection may be achieved at wafer level using a metal interconnect layer.

[0083] It is noted that the transceiver tile 210 may include one or more membranes suspended from a substrate, and the piezoelectric elements 302 may be disposed on the membranes. In embodiments, a membrane may be disposed beneath each of the piezoelectric elements 302, as described below in connection with FIGS. 4-8. In embodiments, multiple piezoelectric elements may be disposed on a single membrane 309. In embodiments, two or more membranes may be disposed beneath one of the piezoelectric elements 302. Further information regarding the arrangement of piezoelectric elements on a membrane may be found in co-pending U.S. patent application Ser. No. 15 / 820,319, filed Nov. 21, 2017, entitled “IMAGING DEVICE HAVING A PIEZOELECTRIC TRANSDUCER,” which is incorporated herein by reference in its entirety.

[0084] In a conventional bulk piezoelectric element, the voltage potential between the top and bottom electrodes ranges from 100V to 200V. In a conventional pMUT, the voltage potential between the top and bottom electrodes is about 30V. In an embodiment, to further reduce this voltage, the piezoelectric element 302 may include a scaled down thin piezoelectric layer, which may have a thickness on the order of 2 μm or less. FIGS. 4-8 illustrate steps for fabricating an exemplary piezoelectric element according to an embodiment of the present disclosure. FIG. 4 illustrates a top view of a membrane 406 disposed on a substrate 402, and FIG. 5 illustrates a cross-sectional view of the membrane and substrate taken along line 4-4, according to an embodiment of the present disclosure. (In an embodiment, the substrate 402 may correspond to the transceiver substrate 304 of FIG. 3B.) As illustrated, in an embodiment, a membrane layer 404 may be deposited on the substrate 402, and a cavity 408 may be formed to remove a portion of the substrate 402, thereby forming a membrane 406 that may vibrate in a direction perpendicular to the substrate 402. In an embodiment, the cavity 408 may be formed by conventional wafer processing techniques such as etching. In an embodiment, the substrate 402 may be formed from the same material as the membrane layer 404. In an alternative embodiment, the substrate 402 may be formed from a different material than the membrane layer 404. Note that the cavity 408 may be formed after other components, such as the top conductor of the piezoelectric element (812 in FIG. 8), have been formed.

[0085] In an embodiment, membrane 406 has a circular projected area, however, it should be apparent to one skilled in the art that membrane 406 can have other suitable geometric shapes.

[0086] Figure 6 shows a top view of a bottom electrode 602 disposed on the membrane layer 404 and above the membrane 406, according to an embodiment of the present disclosure. Figure 7 shows a top view of a piezoelectric layer 706 disposed on the bottom electrode 602, according to an embodiment of the present disclosure. In an embodiment, the piezoelectric layer 706 may have a similar projected area as the bottom electrode 602, such that the piezoelectric layer 706 may cover an entire portion of the bottom electrode 602.

[0087] 8 illustrates a top view of a piezoelectric element according to an embodiment of the present disclosure. As shown, a top electrode 808 may be disposed on the piezoelectric layer 706 and disposed above the membrane 406. In an embodiment, a conductor 812 may be disposed on the top electrode 808 and electrically coupled to the top electrode 808, while conductors 810 and 811 may reach the bottom electrode 602 through one or more vias 814. In an embodiment, the top electrode 808, the piezoelectric layer 706, and the bottom electrode 602 may form a two-terminal piezoelectric element, and the membrane 406 may vibrate when a voltage is applied between the top and bottom electrodes. In an embodiment, charges may be formed at the top and bottom electrodes when the membrane is deformed by pressure waves during a receive mode / process.

[0088] 9 shows a schematic diagram of a piezoelectric element 900 according to an embodiment of the present disclosure. As shown, a piezoelectric layer 910 may be disposed between a first electrode (X) 906 and a second electrode (O) 904. In an embodiment, the first electrode (X) 906 may be connected to ground or a DC bias via a conductor (X) 908, and the second electrode (O) 904 may be connected to an electrical circuit (not shown in FIG. 9) through a signal conductor (O) 902. In an embodiment, the piezoelectric element 800 of FIG. 8 is an exemplary implementation of the piezoelectric element 900, and the piezoelectric element 900 may be disposed on a membrane layer (such as 404 of FIG. 5).

[0089] In conventional piezoelectric elements, the piezoelectric layer is thick, approaching approximately 100 μm, and an AC voltage of +100 to −100 V across the piezoelectric layer is typically required to generate ultrasonic pressure waves strong enough to enable medical imaging. The frequency of this AC drive signal is typically near the resonant frequency of the piezoelectric structure, typically exceeding 1 MHz for medical imaging applications. In conventional systems, the power dissipated in driving the piezoelectric element is approximately equal to C*V 2 where C is the capacitance of the piezoelectric element and V is the maximum voltage across the piezoelectric layer. Typically, when transmitting a pressure wave, multiple piezoelectric lines are driven together with somewhat different phase delays to focus the pressure wave or steer its propagation direction. The simultaneous driving of multiple piezoelectric lines increases the temperature of the surface of the piezoelectric element. In general, it is highly desirable not to exceed a certain threshold temperature so as not to damage the subject being imaged. This limits the number of lines that can be driven and the time period for which they can be driven.

[0090] In an embodiment, the piezoelectric layer 910 is much thinner, approximately 1-2 μm thick, compared to conventional bulk piezoelectric elements. In an embodiment, this significant reduction in thickness allows for the use of a lower voltage drive signal for the piezoelectric element 900. Here, to maintain a similar electric field strength, the voltage is reduced approximately by an amount that reduces the thickness of the piezoelectric layer 910. For example, in an embodiment, the voltage potential across the two electrodes 904 and 906 may range from approximately 1.8 V to 12.6 V peak-to-peak. The capacitance of the piezoelectric element 900 may be increased by a reduction in the thickness of the piezoelectric layer 910 for a similar piezoelectric material. For example, if the drive voltage is reduced by 10 times and the thickness of the piezoelectric layer 910 is also reduced by 10 times, the capacitance increases by 10 times and the power dissipation is reduced by 10 times. This reduction in power dissipation also reduces the heat generation and temperature rise in the piezoelectric element. Thus, in an embodiment, a lower drive voltage and a thinner piezoelectric layer may be used to reduce the temperature at the pMUT surface compared to conventional piezoelectric elements. Alternatively, in embodiments, for a given temperature, more pMUT elements may be driven simultaneously to illuminate a larger target area compared to conventional piezoelectric elements. This may allow faster scanning of the target, especially when multiple emissions are required to scan all portions of the target to form an image. In embodiments, the target area may be scanned with multiple emissions using different steering angles, and the resulting image data may be combined to obtain a higher quality image.

[0091] In embodiments, the ability to simultaneously drive more piezoelectric elements allows for greater coverage of the transducer aperture per shot, minimizing the number of shots required to cover the entire aperture, and thus increasing the frame rate. Frame rate measures how many times a target is imaged per minute. Imaging at high frame rates is desirable, especially when tissue motion is involved, as moving tissue can blur the image. In embodiments, imager 120 operating at a higher frame rate may be able to produce higher quality images, as compared to conventional bulk piezoelectric elements.

[0092] In an embodiment, image quality can be improved by combining several frames of an image into one resulting frame with lower noise. In an embodiment, this averaging technique can be implemented to enhance image quality for a given increase in pMUT temperature by using low voltage and low power pMUTs at higher frame rates compared to conventional bulk piezoelectric elements. In an embodiment, aperture synthesis of ultrasound imaging may be used to allow image combining. Various frames of images may also be taken with different steering angles or from orthogonal steering directions to get a better view of the target.

[0093] FIG. 10A shows a schematic diagram of a piezoelectric element 1000 according to an embodiment of the present disclosure. FIG. 10B shows a symbolic representation of the piezoelectric element 1000 in FIG. 10A. As shown, the piezoelectric element 1000 is similar to the piezoelectric element 900, with the difference that the piezoelectric element 1000 has more than two electrodes. More specifically, the piezoelectric element 1000 may include an upper electrode (O) 100, a first lower electrode (X) 1006, a second lower electrode (T) 1012, a piezoelectric layer 1010 disposed between the upper and lower electrodes, and three conductors 1002, 1008 and 1014 electrically coupled to the lower and upper electrodes 1004, 1006 and 1012, respectively. (Hereinafter, the terms upper and lower simply refer to two opposite sides of the piezoelectric layer, and do not necessarily mean that the upper electrode is disposed above the lower electrode.)

[0094] Although a unimorph piezoelectric element is shown in Figure 10A purely for purposes of illustration, in embodiments, a multi-layer piezoelectric element comprised of multiple piezoelectric sub-layers and electrodes may be utilized. In embodiments, the piezoelectric layer 1010 may include at least one of PZT, PZT-N, PMN-Pt, AlN, Sc-AlN, ZnO, PVDF, and LiNiO3.

[0095] 10C shows a schematic cross-sectional view of a piezoelectric element 1000 according to an embodiment of the present disclosure. As shown, the piezoelectric element 1000 may be disposed on a membrane layer 1034 supported by a substrate 1030. In an embodiment, a cavity 1032 may be formed in the substrate 1030 to define the membrane. In an embodiment, the membrane layer 1034 may be formed by depositing SiO2 on the substrate 1030.

[0096] In an embodiment, the piezoelectric element 1000 may include a piezoelectric layer 1010 and a first electrode (O) 1002 electrically connected to a signal conductor (O) 1004. In an embodiment, the signal conductor (O) 1004 may be formed by depositing TiO2 and a metal layer on the membrane layer 1034. In an embodiment, the piezoelectric layer 1010 may be formed by a sputtering technique or by a sol-gel process.

[0097] In an embodiment, a second electrode (X) 1006 may be grown on the piezoelectric layer 1010 and electrically connected to the second conductor 1008. A third electrode (T) 1012 may also be grown on the piezoelectric layer 1010 and disposed adjacent to the second conductor 1012, but electrically isolated from the second conductor (X) 1008. In an embodiment, the second electrode (X) 1006 and the third electrode (T) 1012 may be formed by depositing a metal layer on the piezoelectric layer 1010 and patterning the metal layer. In an embodiment, the projected areas of the electrodes 1002, 1006 and 1012 may have any suitable shape, such as a square, a rectangle, a circle, an ellipse, etc.

[0098] Similar to the piezoelectric element 1000, the first electrode (O) 1002 may be electrically connected to the conductor (O) 1004 using metal, vias and interlayer dielectrics. In an embodiment, the first electrode (O) 1002 may be in direct contact with the piezoelectric layer 1010. The third conductor (T) 1014 may be deposited or grown on the opposite side of the piezoelectric layer 1010 to the first electrode (O) 1002.

[0099] 10D shows a schematic diagram of a piezoelectric element 1030 according to an embodiment of the present disclosure. As shown, the piezoelectric element 1030 may include two sub-piezoelectric elements (or simply sub-elements) 1031-1 and 1031-2. In an embodiment, each sub-element may be a three-terminal device, i.e., having one top electrode 1032-1 (or 1032-2), two bottom electrodes 1034-1 (or 1034-2), and 1036-1 (or 1036-2), and one piezoelectric layer 1035-1 (or 1035-2). In an embodiment, the top electrode 1032-1 may be electrically connected to the top electrode 1032-2 by a common conductor (O) 1031, the first bottom electrode (X) 1034-1 may be electrically connected to the first bottom electrode (X) 1034-2 by a common conductor (X) 1038, and the second bottom electrode (T) 1036-1 may be electrically connected to the second bottom electrode (T) 1036-2 by a common conductor (T) 1040. In an embodiment, the piezoelectric element 1030 may be disposed on one film, or each sub-element may be disposed on a separate film. It should be apparent to one skilled in the art that the conductor (O) 1032-1 may be electrically connected to the electrode (O) 1031 using metal, vias, interlayer dielectrics (ILD), etc. in a manner similar to the piezoelectric elements shown in Figures 12-16.

[0100] In an embodiment, the conductor (X) 1038 and the conductor (T) 1040 may all be grounded (or connected to a DC bias) during active operation of the imager. In an embodiment, the electrodes (O) 1032-1 and 1032-2 may be driven by a common transmit driver circuit and a common electrical signal, typically a signal waveform around the center frequency of the transducer. For example, if the center frequency is 2 MHz, a 2 MHz sinusoidal or square waveform is applied to the piezoelectric element 1030. This waveform may cause the piezoelectric element 1030 to resonate at 2 MHz and send pressure waves, such as 122, from the surface of the transducer. The pressure waves may be reflected from the target organ being imaged. In an embodiment, the reflected pressure waves may strike the piezoelectric element 1030, which is now connected to a signal receiver. The pressure waves may be converted to charge in the piezoelectric element 1030 by the piezoelectric layers 1035-1 and 1035-2. In an embodiment, this charge is processed by amplifiers, filters, and finally digitized by an A / D converter (not shown in FIG. 10D), followed by a digital decimator, and the data is finally interfaced to an FPGA or graphical processing unit (GPU). These processed signals from multiple piezoelectric elements may then be reconstructed into an image. The signal waveform driving the transmit driver may be a frequency-varying signal, a phase-varying signal, or other complex coded signal, such as a chirp or Golay code.

[0101] 10E shows a schematic diagram of a piezoelectric element 1050 according to an embodiment of the present disclosure. As shown, the piezoelectric element 1050 may include two sub-elements 1051-1 and 1051-2. In an embodiment, each sub-element may be a two-terminal device, i.e., have one top electrode 1052-1 (or 1052-2), one bottom electrode 1054-1 (or 1054-2), and one piezoelectric layer 1056-1 (or 1056-2). In an embodiment, the top electrode (O) 1052-1 may be electrically connected to the top electrode (O) 1052-2 by a common conductor (O) 1051, and the bottom electrode (X) 1054-1 may be electrically connected to the bottom electrode (X) 1054-2 by a common conductor (X) 1058. In an embodiment, the piezoelectric element 1050 may be disposed on one membrane, or each sub-element may be disposed on a separate membrane.

[0102] FIG. 10F shows a schematic diagram of a piezoelectric element 1070 according to an embodiment of the present disclosure. FIG. 10G shows a bottom view of a piezoelectric element 1070 according to an embodiment of the present disclosure. As shown, the piezoelectric element 1070 may include an upper electrode (O) 1074, a first lower electrode (X) 1080, a second lower electrode (T) 1076, a piezoelectric layer 1075 disposed between the upper and lower electrodes, and three conductors 1072, 1078 and 1082 electrically coupled to the lower and upper electrodes 1074, 1076 and 1080, respectively. (In FIG. 10G, the conductors are not shown.) In an embodiment, each of the first and second lower electrodes has an annular shape, and the second lower electrode (X) 1076 surrounds the first lower electrode (T) 1080.

[0103] 10H shows a schematic diagram of a piezoelectric element 1085 according to an embodiment of the present disclosure. As shown, the piezoelectric element 1085 may utilize a transverse mode of operation and may include a substrate 1091, a membrane 1090 secured to the substrate at one end, a bottom electrode (O) 1092 electrically coupled to a conductor 1089, a piezoelectric layer 1088, and a top electrode 1086 electrically coupled to a conductor 1087. In an embodiment, the membrane 1090 may be secured to the substrate 1091 at one end to vibrate in a transverse mode, as indicated by arrow 1093, i.e., the piezoelectric element may operate in a transverse mode.

[0104] It is noted that the piezoelectric element 1085 may have any suitable number of top electrodes, and that more than one piezoelectric element may be disposed on the membrane 1090. It is further noted that the substrate 1091 and membrane 1090 may be formed from one monolithic body, and the membrane may be formed by etching the substrate.

[0105] 11 shows a schematic diagram of a piezoelectric element 1100 according to an embodiment of the present disclosure. As shown, an electrode (O) 1104 may be disposed on a top surface of a piezoelectric layer 1110 and electrically connected to a conductor (O) 1102, which may be connected to an electrical circuit. A conductor (T1) 1108, a conductor (T2) 1114, and a conductor (X) 1118 may be connected to a bottom electrode (T1) 1106, an electrode (T2) 1112, and an electrode (X) 1116, respectively. An electrode (T1) 1106, an electrode (X) 1116, and an electrode (T2) 1112 may be disposed on a bottom surface of the piezoelectric layer 1110. In an embodiment, the piezoelectric element 1100 may be disposed on one membrane or three separate membranes.

[0106] 10A-11 each show a piezoelectric element (or sub-element) having either two terminals (O and X), or three terminals (O, X and T), or four terminals (O, X, T1 and T2). However, it should be apparent to one skilled in the art that a piezoelectric element (or sub-element) may have more than four terminals. For example, a piezoelectric element may have top and bottom (O) electrodes and more than three bottom electrodes.

[0107] Figures 12-16 illustrate steps for fabricating an exemplary piezoelectric element having four terminals according to an embodiment of the present disclosure. Figure 12 illustrates a top view of a membrane 1206 that may be formed by forming a membrane layer 1204 on a substrate 1202 and forming a cavity 1208 in the substrate. Figure 13 illustrates a cross-sectional view of the structure of Figure 12 taken along line 12-12. In an embodiment, membrane 1204 may be deposited by a suitable wafer processing technique.

[0108] FIG 14 illustrates a top view of a layer structure formed on membrane layer 1204, and FIG 15 illustrates a cross-sectional view of the layer structure of FIG 14 taken along line 14-14, according to an embodiment of the present disclosure. As shown, three top electrodes 1223, 1224-1 and 1224-2, a piezoelectric layer 1220, and a bottom electrode 1222 may be formed on membrane layer 1204. In an embodiment, top electrodes 1223, 1224-1 and 1224-2, piezoelectric layer 1220, and bottom electrode 1222 may be deposited by a suitable wafer processing technique, such as evaporation, sputtering, patterning, etc.

[0109] 16 shows a top view of a piezoelectric element 1600 according to an embodiment of the present disclosure. As shown, three conductors 1620, 1622-1 and 1622-2 may be electrically coupled to electrodes 1223, 1224-1 and 1224-2, respectively. Conductor (O) 1610 may also be electrically coupled to bottom electrode 1222 through one or more vias 1614. In an embodiment, electrical ground and source planes may reach bottom electrode 1222 through vias 1614 and conductor (O) 1610. In an embodiment, each of conductors 1620, 1622-1 and 1622-2 may be connected to ground or a DC bias voltage. In an embodiment, conductor 1620 may be connected to ground or a first DC bias voltage, and conductors 1622-1 and 1622-2 may be connected to ground or a second DC bias voltage.

[0110] In general, due to inherent asymmetries in the crystal structure of piezoelectric materials, electric polarity develops, generating electric dipoles. In macroscopic crystal structures, the dipoles are found to be randomly oriented by default, as shown on the left in FIG. 17A. When the material is subjected to mechanical stress, each dipole rotates from its original orientation to a direction that minimizes the overall electrical and mechanical energy stored in the dipole. If all dipoles are initially randomly oriented (i.e., zero net polarization), their rotation may not significantly change the macroscopic net polarization of the material, and thus the piezoelectric effect exhibited will be negligible. Thus, during the initial state, the dipoles need to be oriented in more or less the same direction, which is called the poling process. The direction in which the dipoles are aligned is known as the poling direction. FIG. 17 shows the dipole orientation of a piezoelectric material before, during, and after a poling process, according to an embodiment of the present disclosure.

[0111] As shown, prior to the poling process, the individual dipole moments are unaligned. During the poling process, the dipole moments may be aligned to point in the same direction. After poling, the dipole moments may remain fairly aligned, although some elements of random orientation may be present. In an embodiment, the poling process is performed by placing the piezoelectric material in a constant electric field at an elevated temperature, thereby forcing the dipoles to align.

[0112] In an embodiment, the piezoelectric element 1000 of FIG. 10A may be poled such that the portions of the piezoelectric layer on electrode (X) 1006 and electrode (T) 1012 may be poled in opposite directions. This type of poling may result in a boosted pressure output for the same transmit voltage compared to the pressure output obtained using a single poling direction configuration. Also, in an embodiment, this type of poling may improve receive sensitivity, where the reflected pressure wave may be differentially boosted to produce a larger charge output compared to a single poling direction configuration.

[0113] 17B shows a flow chart of an exemplary process for poling a piezoelectric element 1600 according to an embodiment of the present disclosure. To poll the piezoelectric element 1600, the piezoelectric element 1600 may be mounted in a high temperature chamber (step 1728), and the bottom electrode 1222 may be coupled to ground (step 1722), while the first top electrode 1224-1 (or 1224-2) may be coupled to a high positive voltage, such as 15V (step 1724), and the second top electrode 1223 may be coupled to a high negative voltage, such as -15V (step 1726). The piezoelectric element 1600 may then be exposed to high temperatures in the chamber for an extended period of time (step 1728).

[0114] Depending on the polarity of the first and second high voltages, the portion of the piezoelectric layer 1220 under the two electrodes 1224-1 and 1224-2 may be poled in the same or opposite direction as the portion of the piezoelectric layer 1220 under the electrode 1223. In an embodiment, for example, poling may be performed by applying a high voltage between the electrodes at high temperature, typically 150° C., for 30 minutes for some piezoelectric materials. For example, for a 1 μm thick piezoelectric layer, +15 V may be applied from the signal electrode to the T electrode and −15 V from the signal electrode to the X electrode. Once the piezoelectric material is poled, each of the X and T electrodes may be grounded or tied to a non-zero DC bias voltage, while the conductor (O) 1610 may be connected to an ASIC chip to be driven by a transmit driver during transmit operation, or to an LNA (e.g., 1811 in FIG. 18A) in the ASIC chip during receive operation. In an embodiment, the DC bias voltage may improve the sensitivity of the piezoelectric element 1600.

[0115] FIG. 18A illustrates an imaging assembly 1800 according to an embodiment of the present disclosure. As illustrated, the imaging assembly 1800 may include a transceiver substrate 1802 (which may be similar to the transceiver tile 210) and an ASIC chip 1804 electrically coupled to the transceiver substrate. In an embodiment, the transceiver substrate 1802 may include one or more piezoelectric elements 1806, where each piezoelectric element may be disposed on one or more membranes. In an embodiment, two or more piezoelectric elements may be disposed on a single membrane. In an embodiment, poling of the piezoelectric layer may be performed after the transceiver substrate 1802 is interconnected to the ASIC chip 1804. It is noted that the ASIC 1804 may be replaced with a suitable substrate including multiple circuits for driving the piezoelectric elements 1806 in the transceiver substrate 1802.

[0116] In an embodiment, poling may be performed on the transceiver tile / substrate 1802 after the transceiver substrate is 3D interconnected to the ASIC chip 1804. With conventional piezoelectric elements, it is difficult to perform the poling process on the transceiver tile after the transducer tile is coupled to the circuitry for driving the piezoelectric elements. This is because poling requires applying high voltages to the circuitry for controlling the piezoelectric elements, and such high voltages may damage the circuitry. In contrast, in an embodiment, poling may be performed on the transducer substrate 1802 that is already integrated with the ASIC chip 1804. In an embodiment, the ASIC chip 1804 allows for the application of a desired voltage to all first electrodes of the piezoelectric elements, and a high voltage may be applied to all second or additional electrodes.

[0117] In an embodiment, each piezoelectric element 1806a-1806n may have two or more electrodes, which may be connected to drive / receive electronics housed within the ASIC chip 1804. In an embodiment, each piezoelectric element (e.g., 1806a) may include a top conductor electrically connected to a conductor (O) (e.g., 1814a) and two bottom electrodes electrically connected to conductors (X,T) (e.g., 1810a and 1812a). In an embodiment, conductor 1810a may be electrically coupled to DC bias (X) 1832a or ground, and conductor (T) 1812a may be coupled to DC bias (T) 1834a or ground.

[0118] In an embodiment, the ASIC chip 1804 may include one or more circuits 1842a-1842n electrically coupled to one or more piezoelectric elements 1806a-1806n, respectively, and one control unit 1840 for controlling the circuits 1842a-1842n. In an embodiment, each circuit (e.g., 1842a) may include a transmit driver (1813a), a receiver amplifier (or simply amplifier) ​​(e.g., 1811a), and a switch (e.g., 1816a) having one terminal electrically coupled to the conductor (O) (1814a) and another terminal toggling between the two conductors coupled to the transmit driver 1813a and the amplifier 1811a. During a transmit (Tx) mode / process, the switch 1816a may connect the transmit driver 1813a to the piezoelectric element 1806a such that a signal is transmitted to the top electrode of the piezoelectric element 1806a. During a receive (Rx) mode / process, a switch 1816a may connect the amplifier 1811a to the piezoelectric element 1806a such that a signal is transmitted from the top electrode of the piezoelectric element 1806a to the amplifier 1811a.

[0119] It is noted that the transmit driver 1813a may include various electrical components. However, for simplicity, the transmit driver 1813a is represented by one driver. However, it should be apparent to one skilled in the art that the transmit driver may include a more complex driver with multiple functions. Although only one amplifier 1811a is shown in FIG. 18A, the amplifier 1811a may be connected to electrical components for processing the received signal. In an embodiment, the amplifier 1811a may be a low noise amplifier (LNA). In an embodiment, the circuit 1842n may have the same or similar structure as the circuit 1842a.

[0120] In an embodiment, all DC biases (X) 1832a-1832n may be connected to the same DC bias or ground, i.e., all of conductors (X) 1810a-1810n may be connected to a single DC bias or ground. Similarly, all DC biases (X) 1834a-1834n may be connected to the same or different DC biases, i.e., all of conductors (T) 1812a-1812n may be connected to a single DC bias or ground.

[0121] In an embodiment, the conductors (X, T, and O) 1810, 1812, and 1814 may be connected to the ASIC chip 1804 using an interconnect technique, such as copper pillar interconnects or bumps (e.g., 1882 in FIG. 18B ), as indicated by arrow 1880. In an embodiment, the circuit components within the ASIC chip 1804 may communicate with the outside of the ASIC chip 1804 using interconnects 1830. In an embodiment, the interconnects 1830 may be implemented using bond wires from a pad on the ASIC chip 1804 to another pad outside the ASIC chip. In an embodiment, in addition to wire bond pads, other types of interconnects may be used, such as bump pads or redistribution bumps on the ASIC chip 1804.

[0122] In an embodiment, the LNAs 1811 included in the circuitry 1842 may be implemented external to the ASIC chip 1804, such as part of a receive analog front end (AFE). In an embodiment, the LNAs may reside within the ASIC chip 1804, or another LNA and a programmable gain amplifier (PGA) may reside within the AFE. The gain of each LNA 1811 may be programmed in real time, allowing the LNAs to be part of a time gain compensation function (TGC) required for the imager.

[0123] In an embodiment, the LNA 1811 may be constructed using low voltage transistor technology and may be damaged if exposed to the high transmit voltages required by conventional transducers. Thus, in conventional systems, high voltage transmit / receive switches are used to isolate the high transmit voltage from the low voltage receive circuitry. Such switches are large and expensive, use high voltage (HV) processes, and degrade the signal sent to the LNA. In contrast, in an embodiment, low voltages may be used and thus the high voltage components of conventional systems may no longer be needed. Also, in an embodiment, by eliminating the conventional HV switch, performance degradation caused by the conventional HV switch may be avoided.

[0124] In an embodiment, the piezoelectric element 1806 may be connected to the LNA 1811 during receive mode by a switch 1816. The LNA 1811 may convert the charge in the piezoelectric element 1806 generated by the reflected pressure wave exerting pressure on the piezoelectric element into an amplified voltage signal with low noise. The signal-to-noise ratio of the received signal may be one of the important factors that determine the quality of the reconstructed image. Thus, it is desirable to reduce the inherent noise in the LNA itself. In an embodiment, the noise may be reduced by increasing the transconductance of the input stage of the LNA 1811, such as by using a higher current in the input stage. The increased current may cause increased power dissipation and heat. In an embodiment, the pMUT 1806 may be operated at a low voltage and may be in close proximity to the ASIC chip 1804, so that the power saved by the low voltage pMUT 1806 may be utilized to lower the noise in the LNA 1811 for a given acceptable total temperature rise compared to a conventional transducer operating at a high voltage.

[0125] 18B shows a schematic diagram of an imaging assembly 1850 according to an embodiment of the present disclosure. In an embodiment, the transceiver board 1852 and the ASIC chip 1854 may be similar to the transceiver board 1802 and the ASIC chip 1804, respectively. In conventional systems, the electronic circuitry for driving the piezoelectric transducer is typically located far away from the piezoelectric transducer and connected to the piezoelectric transducer using a coaxial cable. Generally, the coaxial cable increases parasitic loads such as additional capacitance to the electronic circuitry, and the additional capacitance causes an increase in noise and a loss of important performance parameters such as a loss of signal power. In contrast, as shown in FIG. 18B, the transmit drivers or drivers (or equivalently, circuits) 1862a-1862n may be directly connected to the piezoelectric elements (or equivalently, pixels) 1856a-1856n+i using low impedance three-dimensional (3D) interconnect mechanisms (indicated by arrows 1880) such as Cu pillars or solder bumps 1882, or wafer bonding or similar approaches or a combination of such techniques. In an embodiment, upon integrating the transceiver substrate 1852 into the ASIC chip 1854, the circuits 1862 may be located less than 100 μm (or the order of) away from the piezoelectric elements 1856 in the vertical direction. In an embodiment, any conventional device for impedance matching between the driving circuits 1862 and the piezoelectric elements 1856 may not be required, further simplifying the design of the imaging assembly 1800 and improving power efficiency. The impedance of the circuits 1862 may be designed to match the requirements of the piezoelectric elements 1856.

[0126] In an embodiment, in FIG. 18A, each of the piezoelectric elements 1806a-1806n may be electrically connected to a corresponding one of the circuits 1842a-1842n located in the ASIC chip 1804. In an embodiment, this configuration may allow the imager to generate a three-dimensional image. Similarly, in FIG. 18B, each of the piezoelectric elements 1856a-1856m may have three leads, represented as X, T, and O. The leads from each of the piezoelectric elements may be electrically connected by an interconnect 1882 to a corresponding one of the circuits 1862a-1862m located in the ASIC chip 1854. Furthermore, in an embodiment, the lines of the piezoelectric elements, such as 1856n+1-1856n+i, may be electrically coupled to a common circuit 1862n. In an embodiment, the transmit driver circuit 1862n may be implemented with a transmit driver. In an alternative embodiment, the transmit driver circuit 1862n may be implemented with a multi-level driver to facilitate various imaging modes.

[0127] It should be apparent to one skilled in the art that the ASIC chip 1854 may have any suitable number of circuits similar to the circuits 1862n. In an embodiment, the control unit 1892 may have the function of configuring the piezoelectric elements horizontally or vertically in a two-dimensional pixel array, configuring their length, and putting them in transmit or receive or polling mode or idle mode. In an embodiment, the control unit 1892 may perform the polling process after the transceiver board 1852 is combined with the ASIC chip 1854 by the three-dimensional integration technology 1882. In an embodiment, the transmit driver circuit 1843 may be implemented with a multi-level drive, as shown in FIG. 34, where the transmit driver output may have more than two output levels. FIG. 34 shows an embodiment where the output levels may be 0V or 6V or 12V. It is understood that these voltages may be different and may be, for example, -5V, 0V and +5V. The transmit driver may also be a two-level driver with a drive signal as shown in FIG. 33.

[0128] In an embodiment, leads 1882a-1882n may be signal conductors used to apply pulses to the electrodes (O) of piezoelectric element 1856. Similarly, leads 1884a-1884n, 1886a-1886n, and 1888a-1888n may be used to communicate signals to piezoelectric elements 1856a-1856n+i. It is noted that any other suitable number of leads may be used to communicate signals / data to imaging assembly 1800.

[0129] In an embodiment, each of lead (X) 1886 and lead (T) 1888 may be connected to a ground or a DC bias terminal. In an embodiment, digital control leads 1894 may be a digital control bus and may include one or more leads required to control and address various functions within the imaging assembly 1850. These leads may allow programmability of the ASIC chip 1854 using, for example, a communication protocol such as a Serial Peripheral Interface (SPI) or other protocol.

[0130] In an embodiment, the piezoelectric elements 1806 (or 1856) and the control electronics / circuitry 1842 (or 1862) may be formed on the same semiconductor wafer. In an alternative embodiment, the transceiver substrate 1802 (or 1852) and the ASIC chip 1804 (or 1854) may be fabricated separately and assembled with each other by a 3D interconnect technology, such as a metal interconnect technology using bumps 1882. In an embodiment, the interconnect technology can eliminate the low yield multiplication effect, thereby lowering manufacturing costs and maximizing the yield of the components independently.

[0131] In an embodiment, leads 1862a-1862n may be signal conductors used to apply pulses to the electrodes (O) of piezoelectric element 1806. Similarly, leads 1864a-1864n, 1866a-1866n and 1868a-1868n may be used to communicate signals to piezoelectric elements 1806a-1806n. It is noted that any other suitable number of leads may be used to communicate signals / data to imaging assembly 1800.

[0132] As discussed above, the LNA 1811 may operate in a charge-sensing mode and may have a programmable gain that may be configured in real time to provide gain compensation, respectively. In an embodiment, one or more temperature sensors may be located within the imager 120, as discussed in connection with FIG. 3B. In an embodiment, the ASIC may receive temperature data from the temperature sensor and use the temperature data to adjust the imaging frame rate or the signal-to-noise ratio of the LNA 1811.

[0133] 19A-1 shows a top view of a transceiver substrate 1902 and an ASIC chip 1906, and FIG. 19A-2 shows a side view of an imaging assembly 1901 according to an embodiment of the present disclosure. As shown, the imaging assembly 1901 may include a transceiver substrate 1902 interconnected to an ASIC chip 1906 by a suitable interconnect mechanism, such as bumps. In the following, bumps are shown as the interconnect mechanism, although other suitable interconnect mechanisms may be used in place of bumps.

[0134] In an embodiment, each piezoelectric element 1904 may be a two-terminal piezoelectric element, where the piezoelectric element is symbolically represented by two electrodes O and X. In an embodiment, a circuit element 1908 may include electrical components for driving a corresponding piezoelectric element 1904, where the circuit element 1908 is symbolically represented by a transmit driver. In an embodiment, an imaging element 1910 may include a piezoelectric element 1904 and a circuit element 1908, where the piezoelectric element 1904 may be electrically connected to the circuit element 1908 by two bumps.

[0135] FIG. 19B-1 shows a top view of the transceiver substrate 1911 and the ASIC chip 1913, and FIG. 19B-2 shows a side view of an imaging assembly 1915 according to an embodiment of the present disclosure. As shown, the imaging assembly 1915 may be similar to the imaging assembly 1901, with the difference that the two sub-piezoelectric elements are electrically coupled to the two sub-circuit elements by three bumps. More specifically, the piezoelectric element 1912 includes two sub-piezoelectric elements, each of which may be a two-terminal piezoelectric element, and the X electrodes of the two sub-piezoelectric elements may be electrically coupled to each other. In an embodiment, each O electrode of the sub-piezoelectric elements may be electrically coupled to a transmit driver of the corresponding sub-circuit element 1914, and the X electrodes of the two sub-piezoelectric elements may be electrically coupled to a common electrical terminal of the circuit element 1914. Thus, in each imaging element 1917, the piezoelectric elements 1912 may be interconnected to the circuit element 1914 by three bumps.

[0136] 19C illustrates a top view of a transceiver substrate 1920 and an ASIC chip 1924 according to an embodiment of the present disclosure. As illustrated, the transceiver substrate 1920 may be similar to the transceiver substrate 1902, with the difference that the three sub-piezoelectric elements are electrically coupled to the three sub-circuit elements by four bumps. More specifically, the piezoelectric element 1922 includes three sub-piezoelectric elements, each of which may be a two-terminal piezoelectric element, and the X electrodes of the three sub-piezoelectric elements may be electrically coupled to each other. In an embodiment, each O electrode of the sub-piezoelectric elements may be electrically coupled to a transmit driver of a corresponding sub-circuit element, and the X electrodes of the three sub-piezoelectric elements may be electrically coupled to a common electrical terminal of the circuit element 1926. In this manner, the piezoelectric elements 1922 may be interconnected to the circuit element 1926 by four bumps.

[0137] Note that the piezoelectric elements may have more than two terminals. Figure 19D illustrates a top view of a transceiver substrate 1930 and an ASIC chip 1934 according to an embodiment of the present disclosure. As shown, the transceiver substrate 1930 may be similar to the transceiver substrate 1902, with the difference that each piezoelectric element 1932 may be electrically coupled to a circuit element 1936 by three bumps. In an embodiment, the O electrode may be coupled to a transmit driver of the circuit element 1936 by a bump, and the X and T electrodes may be coupled to the circuit element 1936 by two bumps.

[0138] 19E illustrates a top view of a transceiver substrate 1940 and an ASIC chip 1944 according to an embodiment of the present disclosure. As illustrated, the piezoelectric element 1942 may include two sub-piezoelectric elements, each of which may be a three-terminal piezoelectric element, and the X electrodes of the two sub-piezoelectric elements may be electrically coupled to each other. In an embodiment, each O electrode of the sub-piezoelectric element may be electrically coupled to a transmit driver of a corresponding sub-circuit element by a bump, the X electrodes of the two sub-piezoelectric elements may be electrically coupled to a circuit element 1946 by a bump, and each T electrode of the sub-piezoelectric element may be electrically coupled to the circuit element 1946 by a bump. Thus, the piezoelectric element 1942 may be interconnected to the circuit element 1946 by five bumps.

[0139] 19F illustrates a top view of a transceiver substrate 1950 and an ASIC chip 1954 according to an embodiment of the present disclosure. As illustrated, the piezoelectric element 1952 may include two sub-piezoelectric elements, each of which may be a three-terminal piezoelectric element, and the X electrodes of the two sub-piezoelectric elements may be electrically coupled to each other, and the T electrodes of the two sub-piezoelectric elements may be electrically coupled to each other. In an embodiment, each O electrode of the sub-piezoelectric elements may be electrically coupled to a transmit driver of a corresponding sub-circuit element by a bump, and the X electrodes of the two sub-piezoelectric elements may be electrically coupled to the circuit element 1956 by a bump. Also, the T electrodes of the two sub-piezoelectric elements may be electrically coupled to the circuit element 1956 by a bump. In this manner, the piezoelectric element 1952 may be interconnected to the circuit element 1956 by four bumps.

[0140] 19G illustrates a top view of a transceiver substrate 1960 and an ASIC chip 1964 according to an embodiment of the present disclosure. As illustrated, a piezoelectric element 1962 may include two sub-piezoelectric elements, each of which may be a three-terminal piezoelectric element, in which the O electrodes of the two sub-piezoelectric elements may be electrically coupled to each other, the X electrodes of the two sub-piezoelectric elements may be electrically coupled to each other, and the T electrodes of the two sub-piezoelectric elements may be electrically coupled to each other. In this manner, the piezoelectric element 1962 may be interconnected to a circuit element 1966 by three bumps.

[0141] FIG. 20 shows a schematic diagram of an m×n array 2000 of piezoelectric elements 2002-11 to 2002-mn according to an embodiment of the present disclosure. As shown, each piezoelectric element may be a two-terminal piezoelectric element (such as piezoelectric element 900 in FIG. 9) and may have an electrode (O) (e.g., 2003-11) electrically coupled to a conductor (O) (e.g., 2004-11) and an electrode (X) electrically connected to ground or a DC bias voltage via a common conductor (X) 2007. In an embodiment, each signal conductor (O) may be independently managed by a circuit element (e.g., 1908). In an embodiment, each conductor (O) (e.g., 2004-mn) may be electrically coupled to a transmit driver of the circuit element, and all X electrodes (2006-11 to 2006-mn) of the piezoelectric element array may be connected to the common conductor (X) 2007. In an embodiment, the array 2000 may be disposed on a transceiver substrate as discussed in connection with FIGS. 19A-19G and electrically coupled to an ASIC chip by an interconnect mechanism such as m×n+1 bumps. More specifically, the m×n conductors (O) 2004-2004-mn may be coupled to the m×n transmit drivers of the ASIC chip by m×n bumps, and the common conductor (X) 2007 may be coupled to the ASIC chip by one bump. In an embodiment, such an exemplary configuration described herein is used to perform 3D imaging, where each piezoelectric element, including at least one sub-piezo element, can provide unique information in the array. In an embodiment, each piezoelectric element may have one or more membranes and vibrate at multiple modes and frequencies of the membrane. In an embodiment, each piezoelectric element 2002 may be driven by a pulse having the voltage profiles 3300 and 3400 of FIGS. 33 and 34.

[0142] In an embodiment, the O electrodes of each column (e.g., 2003-11 to 2003-m1) may be electrically coupled to a common conductor. For example, circuit elements within an ASIC chip may be electronically controlled such that the O electrodes of each column are electrically coupled to one another. In such a configuration, the O electrodes of each column may receive the same electrical pulse during a transmit mode through a common transmit driver or by multiple drivers with the same electrical drive signal. Similarly, the O electrodes of each column may simultaneously transmit the charge to a common amplifier during a receive mode. In other words, the piezoelectric elements of each column may be operated as a line unit (or equivalently, a line element).

[0143] FIG. 21 shows a schematic diagram of an n×n array 2100 of piezoelectric elements 2102-11 through 2102-mn according to an embodiment of the disclosure. As shown, each piezoelectric element may be a three-terminal piezoelectric element and may include electrodes O, X, and T. In an embodiment, the X electrodes (e.g., X11, X21, ..., Xm1) may be connected in series by column, and all of the X electrodes (X11 through Xmn) may be electrically coupled to a common conductor (X) 2106. The T electrodes (e.g., T11, T21, ..., Tm1) may be connected in series by column, and all of the T electrodes (T11 through Tmn) may be electrically coupled to a common conductor (T) 2108. A column of elements such as 2102-11, 2102-21 through 2102-m1, when connected together as described in an embodiment, constitutes a line element or column. In an embodiment, each of the O electrodes 2103-11 to 2103-mn may be electrically coupled to a transmit driver of a corresponding circuit element in an ASIC chip via one of the conductors O11 to Omn. In an embodiment, the array 2100 may be disposed on a transceiver substrate and electrically coupled to the ASIC chip by an interconnect mechanism such as m×n+2 bumps.

[0144] In an embodiment, the O electrodes of each column (e.g., 2103-11 to 2103-m1) may be electrically coupled to a common conductor. In such a configuration, the O electrodes of each column may receive the same electrical pulse through a common transmit driver during transmit mode. Similarly, the O electrodes of each column may transmit charge simultaneously to a common amplifier during receive mode. In other words, the piezoelectric elements of each column operate as a line unit. In an embodiment, each of the O electrodes in a column may be connected to a dedicated transmit driver, where the transmit driver input signal for all elements in the column is identical, thus generating substantially identical transmit drive outputs to appear on all piezoelectric elements during transmit operation. Such line elements are electronically controlled on an element-by-element basis, since each element has its own transmit driver. This has the advantage in driving large capacitive line elements. Each element has a smaller capacitance, minimizing timing delays for the elements on the column. In an embodiment, in receive mode, the charge from all elements in the column can be sensed by connecting it to an LNA. This is similar to what is done with 2D imaging. For 3D imaging, the charge on each element is sensed by connecting the O electrode of each element to an LNA during receive mode operation.

[0145] FIG. 22 shows a schematic diagram of an m×n array 2200 of piezoelectric elements 2202-11 through 2202-mn according to an embodiment of the present disclosure. As shown, array 2200 may be similar to array 2100, with the difference that the X electrodes (e.g., X12 through Xm2) in a column may be connected to a common conductor (e.g., 2206-1) and the T electrodes (e.g., T12 through Tm2) in a column may be connected to a common conductor (e.g., 2208-1). Thus, X electrodes (or T electrodes) in the same column may have the same voltage potential during operation. In an embodiment, each of the O electrodes may be electrically coupled to a transmit driver of a corresponding circuit element in an ASIC chip via one of conductors O11 through Omn. In an embodiment, array 2200 may be disposed on a transceiver substrate and electrically coupled to the ASIC chip by an interconnect mechanism such as m×n+2n bumps.

[0146] Compared to array 2100, array 2200 can use more bumps for connecting T and X electrodes to the ASIC chip. In general, the increased number of connections for T and X between the ASIC chip and the piezoelectric array can reduce the impedance of the X and T conductors when connected in parallel to ground or a DC bias source, reducing crosstalk. Crosstalk refers to the coupling of signals from the imaging element to other elements, which can cause interference and reduce image quality. Spurious electrical coupling can occur when any voltage drop due to current flowing in the X and T lines appears around piezoelectric elements that ideally should not be exposed to that voltage. In an embodiment, the X, T and O electrodes can be locally shorted when the piezoelectric elements are not transmitting or receiving under electronic control. Alternatively, an idle electrode can leave the O electrode grounded, the X electrode connected to other X electrodes in the array, and the T electrode connected to other T electrodes in the array.

[0147] FIG. 23 shows a schematic diagram of an m×n array 2300 of piezoelectric elements 2302-11 through 2302-mn according to an embodiment of the present disclosure. As shown, the array 2300 may be similar to the array 2100, with the difference that each piezoelectric element may be a five-terminal piezoelectric element, i.e., each piezoelectric element may include one bottom electrode (O) and four top electrodes (two X electrodes and two T electrodes). In an embodiment, the two X electrodes of each piezoelectric element may be connected in series per column, and all of the 2m×n X electrodes may be electrically coupled to a common conductor (X) 2306. Similarly, the two T electrodes of each piezoelectric element may be connected in series per column, and all of the 2m×n T electrodes may be electrically coupled to a common conductor (T) 2308. In an embodiment, each of the O electrodes may be electrically coupled to a transmit driver of a corresponding circuit element in the ASIC chip via one of the conductors O11 through Omn. In an embodiment, the array 2300 may be disposed on a transceiver substrate and electrically coupled to an ASIC chip by interconnect mechanisms such as m×n+2 bumps.

[0148] FIG. 24 illustrates a schematic diagram of an m×n array 2400 of piezoelectric elements 2402-11 through 2402-mn according to an embodiment of the present disclosure. As illustrated, array 2400 may be similar to array 2200, with the difference that each piezoelectric element may be a five-terminal piezoelectric element: one bottom electrode (O) and four top electrodes (two X electrodes and two T electrodes). In an embodiment, the two X electrodes of each piezoelectric element may be electrically connected in a row-wise direction to a conductor (e.g., 2406-1), and the two T electrodes of each piezoelectric element may be electrically connected in a row-wise direction to a common conductor (e.g., 2408-1). In an embodiment, each of the O electrodes may be electrically coupled to a transmit driver of a corresponding circuit element in an ASIC chip via one of the conductors O11 through Omn. In an embodiment, array 2400 may be disposed on a transceiver substrate and electrically coupled to the ASIC chip by an interconnect mechanism such as m×n+2n bumps.

[0149] FIG. 25 shows a schematic diagram of an m×n array 2500 of piezoelectric elements 2502-11 through 2502-mn according to an embodiment of the disclosure. As shown, array 2500 may be similar to array 2100 in that each piezoelectric element may have one bottom electrode (O) and two top electrodes (T), with the difference that all of the two top electrodes (T) of the piezoelectric elements (e.g., 2502-11 through 2502-m1) along a column may be electrically connected to a common conductor (e.g., 2508-1). In an embodiment, each of the O electrodes may be electrically coupled to a transmit driver of a corresponding circuit element in an ASIC chip via one of the conductors O11 through Omn. In an embodiment, array 2500 may be disposed on a transceiver substrate and electrically coupled to the ASIC chip by an interconnect mechanism such as m×n+n bumps.

[0150] 26 shows a schematic diagram of an m×n array 2600 of piezoelectric elements 2602-11 through 2602-mn according to an embodiment of the present disclosure. As shown, array 2600 may have similar electrical connections as array 2100, i.e., all of the X electrodes in the piezoelectric elements may be electrically coupled to a common conductor 2606 and all of the T electrodes in the piezoelectric elements may be electrically coupled to a common conductor 2608. Array 2600 may differ from array 2100 in that the top electrode (X, T) of one piezoelectric element (e.g., 2602-11) may have the same or different geometry as the top electrode (X, T) of another piezoelectric element (e.g., 2602-21).

[0151] For the piezoelectric arrays 2000 to 2500, the piezoelectric elements of each piezoelectric array may be the same as or different from each other. For example, the projected area of ​​the two upper electrodes of one piezoelectric element 2202-11 may have the same or different shape as the projected area of ​​the two upper electrodes of another piezoelectric element 2202-n1.

[0152] FIG. 27 illustrates a schematic diagram of an m×n array 2700 of piezoelectric elements 2702-11 through 2702-mn according to an embodiment of the disclosure. As illustrated, each piezoelectric element may include two signal electrodes (O) and one common electrode (X). In an embodiment, each signal electrode (O) may be electrically coupled to a transmit driver of a corresponding circuit element of an ASIC chip. For example, piezoelectric element 2702-11 may include two signal conductors O111 and O112 that may be electrically coupled to two circuit elements in the ASIC chip, respectively, and each signal electrode may generate a charge during a receive mode. In an embodiment, array 2700 may be disposed on a transceiver substrate and electrically coupled to the ASIC chip by an interconnect mechanism such as 2m×n+1 bumps. In an embodiment, all T electrodes in array 2700 may be electrically coupled to ground or a DC bias voltage via a common conductor (T) 2708.

[0153] In an embodiment, the signal conductors (O) in the arrays of Figures 20-27 may be electrically coupled to a circuit element, which may include a transistor switch similar to switch 1816 of Figure 18A, i.e., the switch may toggle between a transmit driver and an amplifier during the transmit and receive modes, respectively, such that the O electrode may generate pressure waves during the transmit mode and generate charge during the receive mode.

[0154] FIG. 28 illustrates an exemplary embodiment of an imaging system 2800 according to an embodiment of the present disclosure. As illustrated, the imaging system 2800 may include an array of piezoelectric elements 2802-11-2802-mn and circuit elements for controlling / communicating with the array. In an embodiment, each of the piezoelectric elements 2802-11-2802-mn may include three electrodes: first and second signal (O) electrodes and a T electrode. (For illustration purposes, the first and second O electrodes in each piezoelectric element refer to the left and right O electrodes of each piezoelectric element in FIG. 28.) In an embodiment, all of the T electrodes in the array 2800 may be electrically coupled to ground or a DC bias voltage via a conductor (T) 2808. In an embodiment, the first O electrodes of the piezoelectric elements in a row may be electrically coupled to a common conductor (e.g., O11) and the second O electrodes of the piezoelectric elements in the same row may be electrically coupled to another common conductor (e.g., O12). In an embodiment, during a receive mode, each of the first and second signal O electrodes may generate an electric charge that may be processed by a corresponding circuit.

[0155] In an embodiment, the first set of conductors O11, O21, ..., On1 may be electrically coupled to amplifiers 2810-1 to 2810-n, respectively, where charge appearing on the first column of O electrodes may be transferred to a corresponding amplifier via one of the O conductors. In an embodiment, the second set of conductors O12, O22, ..., On2 may be electrically coupled to switches 2812-1 to 2812-n, respectively. In an embodiment, each switch (e.g., 2812-1) may be connected to a transmit driver (e.g., 2816-1) during a transmit mode / process such that a signal pulse may be transmitted to the second column of O electrodes in the piezoelectric elements (e.g., 2801-11 to 2802-m1). In an embodiment, each switch (e.g., 2812-1) may be connected to a signal amplifier (e.g., 2814-1) during a receive mode / process, so that charge appearing on the second row of O electrodes in the piezoelectric elements (e.g., 2801-11 to 2802-m1) may be transmitted to the amplifier. In an embodiment, the piezoelectric elements 2802-11 to 2802-mn may be disposed in a transceiver substrate, while the switches 2812-1 to 2812-n, the transmit drivers 2816-1 to 2816-n, and the amplifiers 2810-1 to 2810-n and 2814-1 to 2814-n may be disposed in an ASIC chip, and the transceiver substrate may be electrically coupled to the ASIC chip by 2n+1 bumps.

[0156] In an embodiment, the first column of electrodes may be electrically coupled to a common conductor (e.g., O11) and the second column of electrodes may be electrically coupled to another common conductor (e.g., O12). Thus, in an embodiment, the imaging system 2800 may operate as a line imager, i.e., each of the first set of conductors O11-On2 may operate as a transmitting unit and / or a receiving unit during operation. As discussed above, during a receive mode, charge appearing on the first column of O electrodes connected to a conductor (e.g., O11) may be sent to an amplifier (e.g., 2810-1), which may be a low noise amplifier. The amplifier may then amplify the charge signal and convert the charge signal to an output voltage. In this manner, each column of first O electrodes may operate as a receive line imager. In an embodiment, during a receive mode, charge appearing on the second column of O electrodes connected to a conductor (e.g., O12) may be sent via a switch (e.g., 2812-1) to a signal amplifier (e.g., 2814-1), which may be a low noise amplifier. An amplifier can then amplify the charge signal and convert the charge signal to an output voltage. In this manner, each row of second O electrodes can operate as a receive line imager. In an embodiment, during a transmit mode, an electrical signal pulse can be sent from a transmit driver (e.g., 2816-1) through a switch (e.g., 2812-1) to a row of second O electrodes connected to a conductor (e.g., O12), such that the set of second O electrodes can generate pressure waves. In this manner, each row of second O electrodes can operate as a transmit line unit.

[0157] In an embodiment, the switches 2812, which may be transistor switches, may be set to a neutral position during receive mode (i.e., they are not coupled to either the transmit driver or amplifier). In such a case, only the second set of conductors O12, O22, ..., On2 may be operational during receive mode.

[0158] In an embodiment, a transmit driver (e.g., 2816-1) may send a signal to a column of piezoelectric elements (e.g., 2802-11 through 2802-m1) via a conductor (O12), while an amplifier (e.g., 2810-1) may receive a charge signal from the same column of piezoelectric elements (e.g., 2802-11 through 2802-m1). In such a case, each piezoelectric element (e.g., 2802-11) in the column may receive a signal from a transmit driver (e.g., 2816-1) via one conductor (e.g., O12) and simultaneously transmit a charge signal to an amplifier (e.g., 2810-1) via another conductor (e.g., O11), i.e., imaging system 2800 may perform simultaneous transmit and receive modes. This simultaneous operation of transmit and receive modes may be highly advantageous in continuous mode Doppler imaging, where high blood flow velocities may be imaged, as compared to pulsed Doppler imaging.

[0159] In an embodiment, the line units, which refer to a row of O electrodes electrically coupled to a common conductor, can operate as a transmitting unit or a receiving unit, or both. For example, during a transmitting mode, electrical signals can be sequentially transmitted to the conductors O12, O22, ..., On2, causing the line elements to generate pressure waves in sequence, and during a receiving mode, the reflected pressure waves can be processed and combined to generate a two-dimensional image of the target organ. In another example, during a transmitting mode, electrical drive signals can be simultaneously transmitted to the conductors O12, O22, ..., On2, and simultaneously, the reflected pressure waves can be processed using the charges generated from the conductors O11, O12 to On1, and ultrasonic waves can be simultaneously transmitted and received to form a two-dimensional image. The conductors O12 to On2 can also be used to receive charges from the piezoelectric line elements in a receiving mode of operation.

[0160] FIG. 29 illustrates an exemplary embodiment of an imaging system 2900 according to an embodiment of the present disclosure. As illustrated, the imaging system 2900 may include an array of piezoelectric elements 2902-11 through 2902-mn, each of which may include first and second signal (O) electrodes and a T electrode. In an embodiment, all of the T electrodes in the array may be electrically coupled to one common conductor (T) 2908, each row of the first O electrodes may be electrically connected to one of the conductors O1 through Om, and each column of the second O conductors may be electrically connected to a switch 2912 via one of the conductors O12 through On2. In an embodiment, each of the switches 2912-1 through 2912-n may toggle between a transmit driver (e.g., 2916-1) and an amplifier (e.g., 2914-1), which may be a low noise amplifier. In an embodiment, each of the conductors O1 through On may be connected to one of the amplifiers 2910-1 through 2910-m, which may be a low noise amplifier.

[0161] In an embodiment, during a transmit mode, a signal may be sent from a transmit driver (e.g., 2916-1) through a conductor (e.g., O12) to a second row of O electrodes such that the row of piezoelectric elements can generate pressure waves as a line unit. During the transmit mode, each switch (e.g., 2912-1) may be toggled to a corresponding transmit driver (e.g., 2916-1).

[0162] In an embodiment, imaging system 2900 may process the reflected pressure waves in two different ways. In a first way, amplifiers 2910-1 to 2910-n may receive charge signals from the first O electrodes, i.e., each amplifier may receive signals from a row of the first O electrodes. This way allows bi-planar imaging / mode, where the bi-planar images may provide orthogonal perspectives for a two-dimensional image. This way may also provide more than two-dimensional imaging capabilities. Bi-planar imaging may be useful for many applications, such as biopsy. Note that in this way, the transmit and receive modes may be performed simultaneously. In a second way, switch 2912 may be toggled to amplifier 2914 so that each amplifier receives and processes charge signals from a corresponding row of second O electrodes.

[0163] In an embodiment, a line unit, which refers to a column (or row) of O electrodes electrically coupled to an O conductor, may operate as a transmit unit or a receive unit, or both. In an embodiment, conductors O1-Om are arranged in an orthogonal direction relative to conductors O12-On2, but these directions are electronically programmed and electronically adjustable. For example, the gain of amplifiers 2910 and 2914 may be electronically adjustable if gain control leads are implemented in the amplifiers. In an embodiment, the length of each line element (i.e., the number of piezoelectric elements in each line element) may also be electronically adjusted. In an embodiment, this can be achieved by connecting all the signal electrodes of each piezoelectric element to corresponding nodes on an ASIC chip. Here, the ASIC appropriately programs the connections between the signal electrodes of the elements to be connected together, the transmit drivers, or the amplifiers.

[0164] 30 illustrates one embodiment of a piezoelectric element 3000 coupled to a circuit element 3001, according to an embodiment of the present disclosure. As illustrated, the piezoelectric element 3000 may include a first sub-piezoelectric element 3021-1 and a second sub-piezoelectric element 3021-2. The piezoelectric element 3000 may include a bottom electrode (X) 3002 shared by the first and second sub-piezoelectric elements and coupled to a conductor (X) 3006. In an embodiment, the first sub-piezoelectric element 3021-1 may include a signal (O) electrode 3003 electrically coupled to an amplifier 3010 via a conductor 3008. In an embodiment, the second sub-piezoelectric element 3021-2 may include a signal (O) electrode 3004 electrically coupled to a switch 3014 via a conductor 3012.

[0165] In an embodiment, the circuit element 3001 may be electrically coupled to the piezoelectric element 3000 and may include two amplifiers 3010 and 3016, such as low noise amplifiers, and a transmit driver 3018. In an embodiment, a switch 3014 may have one end connected to the O electrode 3004 through a conductor 3012 and the other end may be toggled between the amplifier 3016 for a receive mode and the transmit driver 3018 for a transmit mode. In an embodiment, the amplifier 3016 may be connected to other electronic circuits for further amplifying, filtering, and digitizing the received signal, but the amplifier is used to symbolically represent the electronic circuits. The transmit driver 3018 may be a multi-stage drive and may generate an output with two or more levels of signaling. The signaling may be unipolar or bipolar. In an embodiment, the transmit driver 3018 may include a switch under electronic control of the driver to interconnect the input to the driver's output, which is not explicitly shown in FIG. 30.

[0166] In an embodiment, the transmit driver 3018 signal may be pulse width modulated (PWM), where a weighting function may be created for the transmitted ultrasound signal by controlling the pulse width for each element. This may, for example, perform a windowing function where the transmit signal is weighted by a window function. In an embodiment, the weighting coefficient may be achieved by varying the duty cycle of the transmit signal, as is done during PWM signaling. This type of operation may allow transmit apodization, where the side lobes of the radiated signal are significantly attenuated, allowing for higher quality images.

[0167] In an embodiment, the transceiver array may be disposed in a transceiver substrate and may include an n×n array of piezoelectric elements 3000, and an n×n array of circuit elements 3001 may be disposed in an ASIC chip, with each piezoelectric element 3000 electrically coupled to a corresponding one of the n×n array of circuit elements 3001. In such a case, the transceiver substrate may include a 3n 2 20. The piezoelectric elements 3000 may be interconnected to the ASIC chip by bumps. In an embodiment, each column (or row) of the piezoelectric element array may operate as a line unit, as discussed in connection with FIG. 28 and FIG. 29. For example, the same pulse may be applied to a column of piezoelectric elements simultaneously, such that the columns of piezoelectric elements may generate pressure waves simultaneously. Note that each piezoelectric element 3000 of the n×n array of piezoelectric elements may be coupled to a corresponding one circuit element 3001 of the n×n array of circuit elements.

[0168] In an embodiment, the sub-piezoelectric element 3021-1 may be in a receive mode during the entire operation period, while the sub-piezoelectric element 3021-2 may be in either a transmit mode or a receive mode. In an embodiment, simultaneous operation of the transmit and receive modes may allow for continuous mode Doppler imaging.

[0169] In an embodiment, when the transmit driver 3018 transmits a signal to the electrode 3004, the power level of the pressure wave generated by the sub-piezoelectric element 3021-2 may be changed by using pulse width modulation (PWM) signaling. This is important, for example, when switching from B-mode to Doppler mode imaging. The signal power transmitted to the body can be long and tissue damage can occur if the power level is not reduced. Typically, in conventional systems, different fast settling power supplies are used for B-mode and various Doppler mode imaging, allowing the transmit drive voltage to be different in the two cases, for example to not generate excessive power in the Doppler mode. Unlike such conventional systems, in an embodiment, the power level can be changed by using a PWM signal for transmission without using a conventional fast settling power supply. In an embodiment, rapid switching between Doppler mode and B-mode imaging is desired to co-image these modes together. In an embodiment, the ground electrodes of the piezoelectric elements may be separated from each other and connected to ground separately. In embodiments, this separate ground may reduce noise and result in faster settling times. In embodiments, the transmitted power may be reduced by reducing the transmit column height under electronic control. This also facilitates using the same power supply for both Doppler and B-mode, meeting the power transmission requirements in each mode. This also allows for co-imaging.

[0170] 31 illustrates a circuit 3100 for controlling a plurality of piezoelectric elements, according to an embodiment of the present disclosure. In an embodiment, the circuit 3100 may be disposed within an ASIC chip, where the lines (columns or rows) of piezoelectric elements disposed within a transceiver substrate and the ASIC chip may be interconnected to the transceiver substrate by bumps. As shown, the circuit 3100 may include an array of circuit elements 3140-1 through 3140-n, where each circuit element may communicate signals with the O and X electrodes of a corresponding piezoelectric element.

[0171] As shown in FIG. 31, each circuit element (e.g., 3140-1) may include a first switch (e.g., 3102-1), a second switch (e.g., 3104-1), a third switch (e.g., 3106-1), and a transmit driver (e.g., 3108-1). An output from the transmit driver (e.g., 3108-1) may be sent to the O electrode of the piezoelectric element via a conductor (e.g., 3110-1). During a transmit mode, each circuit element may receive a transmit driver (drive) signal 3124 through a conductor 3122. Each second switch (e.g., 3104-1), which may be a transistor switch that may be controlled by a control unit 3150, may be turned on to send the signal 3124 to the transmit driver (e.g., 3108-1). (Electrical connections between the control unit 3150 and other components in the circuit 3100 are not shown in FIG. 31.) A transmit driver (e.g., 3108-1) may perform logical decoding, level shifting, buffer the input signal, and send a transmit signal to the O electrode via a conductor (e.g., 3110-1). In an embodiment, during the transmit mode, the first switch (e.g., 3102-1) may be turned off.

[0172] In an embodiment, the control unit 3150 may determine which piezoelectric elements need to be turned on during the transmit mode. If the control unit 3150 determines not to turn on the second piezoelectric element, the first switch (e.g., 3102-2) and the second switch (e.g., 3104-2) may be turned off, while the third switch (e.g., 3106-2) may be turned on so that the O electrode and the X electrode have the same potential (i.e., a net zero volt drive is applied to the piezoelectric layer). In an embodiment, the third switch 3106 may be optional.

[0173] In an embodiment, during a receive mode, a first switch (e.g., 3102-1) may be turned on so that charge appearing at the O electrode may be transmitted through conductors 3110-1 and 3120 to an amplifier 3128. The amplifier 3128 may then receive the charge signal (or equivalently, a sensor signal) 3126 and amplify the sensor signal. The amplified signal may be further processed to generate an image. During a receive mode, a second switch (e.g., 3104-1) and a third switch (e.g., 3106-1) may be turned off so that the received signal is not interfered with. Note that the entire array of circuit elements 3140-1 to 3140-n may share a common amplifier 3128, simplifying the design of the circuit 3100. In an embodiment, the X electrodes of the piezoelectric elements may be electrically coupled to ground or a DC bias voltage via conductors 3112-1 to 3112-n, where conductors 3112-1 to 3112-n may be electrically coupled to a common conductor 3152.

[0174] In an embodiment, circuit 3100 may be coupled to a column of piezoelectric elements (e.g., 2002-11 through 2002-n1) of Figure 20. In an embodiment, multiple circuits similar to circuit 3100 may be coupled to multiple columns of piezoelectric elements in the array of Figure 20, and conductor 3152 may be coupled to a common conductor (e.g., 2007 in Figure 20). In an embodiment, circuit 3100 may control a column of piezoelectric elements of Figures 20-27.

[0175] 32 illustrates a circuit 3200 for controlling a plurality of piezoelectric elements, according to an embodiment of the present disclosure. In an embodiment, the circuit 3200 may be disposed within an ASIC chip, where the lines (columns or rows) of piezoelectric elements disposed within a transceiver substrate and the ASIC chip may be interconnected to the transceiver substrate by bumps. As shown, the circuit 3200 may include an array of circuit elements 3240-1 through 3240-n, where each circuit element may communicate signals with the O, X, and T electrodes of a corresponding piezoelectric element.

[0176] As shown in FIG. 32, each circuit element (e.g., 3240-1) may include a first switch (e.g., 3202-1), a second switch (e.g., 3204-1), a third switch (e.g., 3206-1), a fourth switch (e.g., 3207-1), and a transmit driver (e.g., 3208-1). An output from the transmit driver (e.g., 3208-1) may be sent to the O electrode of the piezoelectric element via a conductor (e.g., 3210-1). During a transmit mode, each circuit element may receive a transmit driver (or drive) signal 3224 through a conductor 3222. Each second switch (e.g., 3204-1), which may be a transistor switch, may be controlled by a control unit 3250, and may be turned on to send the signal 3224 to the transmit driver (e.g., 3208-1). (Electrical connections between the control unit 3250 and other components in the circuit 3200 are not shown in FIG. 32.) The transmit driver (e.g., 3208-1) may logically decode the signal, level shift the signal, buffer the output signal, and send a transmit output signal via a conductor (e.g., 3210-1) to the O electrode. In an embodiment, during the transmit mode, the first switch (e.g., 3202-1) may be turned off.

[0177] In an embodiment, the control unit 3250 may determine which piezoelectric elements need to be turned on during the transmit mode. If the control unit 3250 determines not to turn on the second piezoelectric element, the first switch (e.g., 3202-2) and the second switch (e.g., 3204-2) may be turned off, while the third switch (e.g., 3206-2) and the fourth switch (e.g., 3207-2) may be turned on such that the O electrode and the X (and T) electrode have the same potential (i.e., a net zero volt drive is applied to the piezoelectric layer). In an embodiment, the third and fourth switches (e.g., 3206-2 and 3207-2) may be optional. It is understood that the three-level signaling and the transmit drivers that implement it are not explicitly shown. Similarly, the connections to the XT conductors and switches such as 3206-2, 3207-2 are shown in a simplified manner.

[0178] In an embodiment, during a receive mode, a first switch (e.g., 3202-1) may be turned on so that charge appearing at the O electrode may be transmitted to an amplifier 3228 via conductors 3210-1 and 3220. The amplifier 3228 may then amplify the charge (or sensor) signal 3226, which may be further processed to generate an image. During a receive mode, the second switch (e.g., 3204-1), the third switch (e.g., 3206-1), and the fourth switch (e.g., 3207-1) may be turned off so that the received signal is not interfered with.

[0179] Note that the entire array of circuit elements 3240-1 through 3240-n may share a common amplifier 3228, simplifying the design of circuit 3200. In an embodiment, the X electrodes of the piezoelectric elements may be electrically coupled to ground or a DC bias voltage via conductors 3212-1 through 3212-n, where conductors 3212-1 through 3212-n may be electrically coupled to common conductor 3252. In an embodiment, the T electrodes of the piezoelectric elements may be electrically coupled to ground or a DC bias voltage via conductors 3213-1 through 3213-n, where conductors 3213-1 through 3213-n may be electrically coupled to common conductor 3254.

[0180] In an embodiment, circuit 3200 may be coupled to a column of piezoelectric elements (e.g., 2102-11 through 2102-n1) of FIG. 21. In an embodiment, multiple circuits similar to circuit 3200 may be coupled to multiple columns of piezoelectric elements in the array of FIG. 21, and conductor 3252 may be coupled to a common conductor (e.g., 2106 of FIG. 20). Similarly, in an embodiment, conductor 3254 may be coupled to a common conductor (e.g., 2108 of FIG. 21). In an embodiment, circuit 3200 may control a column of piezoelectric elements of FIGS. 20-27.

[0181] In Figures 22-32, conductors are used to electrically couple an electrode to another electrode. For example, electrodes 2006-11 to 2006-m1 are electrically coupled to conductor 2007. In embodiments, the conductors in Figures 22-32 may be implemented in a variety of ways. For example, a metal interconnect layer is deposited and patterned on the substrate on which the piezoelectric elements are disposed or on a different substrate connected to the substrate, such as an ASIC.

[0182] 33 and 34 show example waveforms 3300 and 3400 for driving piezoelectric elements during transmit mode, according to an embodiment of the present disclosure. In general, piezoelectric materials can be vulnerable to damage caused by dielectric aging, which can be delayed or avoided by using a unipolar drive signal. Waveforms 3300 and 3400 represent voltage potentials between O and X electrodes and / or between O and T electrodes. As shown, these waveforms can be unipolar in nature and can be bi-level step waveforms 3300 (i.e., transmit drivers 2812, 2912, 3018, 3108, 3208, etc. are unipolar transmit drivers) or multi-level (e.g., tri-level) step waveforms 3400. The actual voltage amplitude can typically vary from 1.8V to 12.6V. In an embodiment, the multi-step waveform 3400 or a waveform with more steps can reduce heating in the piezoelectric element and has advantages for use during certain imaging modes such as Doppler or harmonic imaging.

[0183] In embodiments, the frequency of the pulses in waveforms 3300 and 3400 may vary depending on the nature of the signal required and should include frequencies to which the underlying membrane of the pMUT responds. In embodiments, the waveforms may also be complex signals such as linear or nonlinear frequency modulated chirp signals, or other coded signals using Golay codes.

[0184] In an embodiment, the circuit for driving the piezoelectric element may be further designed such that the shape of the transmission output from the underlying membrane may be symmetric. In an embodiment, for each signal pulse in the waveform 3300 (or 3400), the rising edge of the pulse may be substantially symmetric with the falling edge of the pulse with respect to the center of the pulse. This symmetry reduces the harmonic content of the transmission signal, especially the second harmonic and other even harmonic signals. In an embodiment, the signal pulse in the waveform 3300 (or 3400) may be a pulse width modulated (PWM) signal.

[0185] FIG. 35 illustrates a transmit drive signal waveform according to an embodiment of the present disclosure. As illustrated, the signal 3500 from the transmit driver may be symmetrical and bipolar, i.e., the magnitude (H1) and width (W1) of the peak maximum voltage are the same as the magnitude (H2) and width (W2) of the peak minimum voltage. Also, the slope of the rising edge 3502 is the same as the slope of the falling edge 3504. Furthermore, the rise time W3 is the same as the fall time W4, where the fall time W4 refers to the time interval between the beginning of the fall and the reference voltage. Furthermore, the rising edge 3506 has the same slope as the rising edge 3502.

[0186] During a transmit operation, a transmit driver, e.g., 3018 in FIG. 30, may be driven by an electrical waveform as shown in FIG. 33-34. FIG. 36 illustrates output signals of various circuits in an imaging assembly according to an embodiment of the present disclosure. In an embodiment, a waveform 3602 may be an output signal from a transmit driver, e.g., 3018, and may be sent to a piezoelectric element, e.g., 3000. In an embodiment, the piezoelectric element may have an inherent bandwidth and therefore output a sinusoidal output 3604 at its resonant frequency. If the output of the transmit driver connected to the O electrode of the piezoelectric element rises too slowly, it may not be able to charge the electrode to the desired final value, thus resulting in a low output signal, as shown in waveform 3606, where the final amplitude is less than 3602. On the other hand, if the transmit driver output signal settles too quickly, the transmit driver output signal has a bandwidth greater than the bandwidth limit of the piezoelectric element, and thus excess energy may be dissipated in heat. Thus, in an embodiment, the piezoelectric element may be charged at a rate such that it is fully charged, but not very quickly, as shown in waveform 3608. In an embodiment, waveform 3608, which represents the voltage potential between the upper and lower electrodes as a function of time, is closer in shape to the transducer output, and the difference in shape is smaller, resulting in a better match between the input and output signal bandwidths and less energy being lost to heat. In an embodiment, the driving impedance of the transmit driver is optimized to reduce energy loss. In other words, the impedance of the transmit driver is designed to drive the piezoelectric element optimally with respect to the time constant required for heat dissipation and sufficient voltage settling within a target time.

[0187] In an embodiment, the imager 120 may use a harmonic imaging technique, where harmonic imaging refers to transmitting pressure waves at the fundamental frequency of the membrane and receiving reflected pressure waves at the second or higher harmonic frequency of the membrane. In general, images based on reflected waves at the second or higher harmonic frequencies have higher quality than images based on reflected waves at the fundamental frequency. The symmetry of the transmit waveform can suppress the second or higher harmonic components of the transmit wave, thereby reducing the interference of these components with the second or higher harmonics in the reflected wave, enhancing the image quality of the harmonic imaging technique. In an embodiment, the waveform 3300 may have a 50% duty cycle to reduce the second or higher harmonics in the transmit wave.

[0188] In Figures 20-29, the array may include multiple line units, each of which includes multiple piezoelectric elements electrically coupled to each other. In an embodiment, the line units may be driven with multiple pulses with a phase difference (or equivalently, a delay). By adjusting the phase, the resulting pressure waves can be steered to a certain angle. This is called beamforming.

[0189] FIG. 37A shows a plot of the amplitude of the transmit pressure wave as a function of spatial position along the azimuth axis of the transducer according to an embodiment of the present disclosure. When the piezoelectric elements in the array are arranged in two dimensions, with the piezoelectric elements on a row in the Y direction connected to each other, and with multiple rows along the X direction, the X direction is known as the azimuth direction, and the Y direction is known as the elevation direction. As shown in FIG. 37A, the transmit pressure wave includes a main lobe and multiple side lobes. The main lobe can be used to scan tissue targets and has a high pressure amplitude. The side lobes have a lower amplitude, but degrade the quality of the image. Therefore, it is desirable to reduce their amplitude.

[0190] FIG. 37B illustrates various types of windows for the apodization process according to an embodiment of the present disclosure. In FIG. 37B, the x-axis represents the position of the piezoelectric element relative to the piezoelectric element at the center of the active window, and the y-axis represents the amplitude (or weighting applied to the piezoelectric element). As shown, for a rectangular window 3720, no weighting is given to any of the transmission lines, i.e., they are all of uniform amplitude (i.e., symbolically 1). On the other hand, when a weighting function such as that shown by a Hamming window 3722 is implemented, the central lines get a greater weighting than the edge lines. For example, to apply a Hamming window 3722 to the transducer tile 210 of FIG. 3B, the leftmost row of piezoelectric elements (labeled -N in FIG. 37B) and the rightmost row of piezoelectric elements (labeled N in FIG. 37B) may have the lowest weighting, while the central row of piezoelectric elements may have the highest weighting. This process is known as apodization. In an embodiment, various types of window weightings may be applied, with the illustrated Hamming window 3722 being intended to be merely an example. In an embodiment, apodization may be implemented by a variety of means, such as scaling the transmit driver output drive levels differently for different lines, by using a digital-to-analog converter (DAC), or by keeping the same drive level but reducing the number of pixels on the line. The net effect is that sidelobe levels can be reduced by the use of apodization, where the transmit drive weighting varies based on where a particular line is located within the activated transmit aperture.

[0191] In embodiments, a reduction in the voltage of the pulse or waveform can reduce the temperature of the transducer surface. Alternatively, for a given maximum allowable transducer surface temperature, a transducer operating at a lower voltage can result in better probe performance and better quality images. For example, for a probe with 192 piezoelectric elements, to reduce power consumption, the transmit pressure waves may be generated using only a portion of the probe (i.e., a subset of the piezoelectric elements), and the remaining elements are scanned sequentially in time using a multiplexer. Thus, in conventional systems, only a portion of the transducer elements may be used at any one time to limit temperature rise. In contrast, in embodiments, a lower voltage probe allows more piezoelectric elements to be simultaneously addressed, which can increase the image frame rate and improve image quality. Substantial power is also consumed in the receive path, where the receive signal is amplified using an LNA. Imaging systems typically use a large number of receive channels, with an amplifier for each receive channel. In embodiments, the temperature data can be used to turn off some receive channels to conserve power and reduce temperature.

[0192] In an embodiment, apodization may be achieved by varying the number of piezoelectric elements in each line unit according to a window function. In an embodiment, such a window approximation may be achieved by electronically controlling the number of piezoelectric elements on a line or by wiring the transducer array with the required number of elements.

[0193] In general, the heat generated by the probe may be a function of the pulse duration of the transmitted pulse / waveform. In general, the piezoelectric element may require a long pulse train to penetrate the pressure wave deeper into the target with a better signal-to-noise ratio (SNR). However, this also reduces the axial resolution and generates more heat in the piezoelectric element. Thus, in conventional systems, the number of pulses emitted is small, sometimes one or two. Longer pulses may generate more thermal energy, making their use impractical in conventional systems. In contrast, in embodiments, the pulses and waveforms 3300 and 3400 may have a significantly lower peak value, which may enable the use of long pulse trains, chirps, or other coded signaling. In embodiments, the longer pulse trains do not reduce the axial resolution, because matched filtering is performed at the receiver to compress the waveform and restore the resolution. This technique allows for a better signal-to-noise ratio and allows the signal to penetrate deeper into the body, allowing high quality imaging of targets deeper within the body.

[0194] In an embodiment, a layer of polydimethylsiloxane (PDMS) or other impedance matching material may be spun onto the transducer elements of Figures 4-19. This layer may improve the impedance match between the transducer elements and the body, thereby reducing reflections or losses of pressure waves at the interface between the transducer elements and the body.

[0195] 20-29, multiple line units may be generated by connecting pixels in the y-direction (or x-direction), where a line unit (or equivalently, a line element) refers to multiple piezoelectric elements electrically connected to each other. In an embodiment, one or more line units may also be generated by connecting piezoelectric elements along the x-direction. In an embodiment, the piezoelectric elements in a line unit may be fixedly wired.

[0196] As discussed in connection with FIG. 18A, each piezoelectric element 1806 may be electrically coupled to a circuit 1842, i.e., the number of piezoelectric elements in the transceiver board 1802 is the same as the number of circuits 1842 in the ASIC chip 1804. In such a case, the electrical connection of the piezoelectric elements in each column (or row) may be made electronically, i.e., the fixed wired conductors (e.g., 2007) for connecting the electrodes in the column (or row) are replaced by electronic switches. In other words, the piezoelectric elements in a line imager / unit may be electronically connected to each other. In the case of an electronically controlled line imager, the line imager / unit may be constructed by connecting each piezoelectric element of a two-dimensional matrix array to a corresponding control circuit (e.g., 1842) of a two-dimensional array of control circuits, where the control circuit is located in spatial proximity to the pixel. To create a line element, a number of drivers controlling the columns (or rows) of pixels may be electronically turned on. In an embodiment, the number of drivers in each line imager / unit can be electrically modified under program control and is electronically adjustable, i.e., the line imagers having piezoelectric elements are electrically configurable.

[0197] In an embodiment, the smaller capacitance of each pixel can be efficiently driven by distributed drive circuits without other equalizing elements between the driver and the pixel, eliminating the difficulty of driving very large line capacitances. In an embodiment, driver optimization allows symmetry in the rising and falling edges, allowing better linearity in the transmit output, and enabling harmonic imaging. (Symmetry was discussed in conjunction with Figures 33 and 34.) In an embodiment, electronic control may allow programmable aperture size, transmit apodization, and horizontal or vertical steering control, all of which may improve image quality. In an embodiment, the line imager / unit, configurable under electronic control, may be electrically modified under program control. For example, if fewer connected elements are desired in the y-direction, that number may be adjusted by software control, without the need to re-spin the control electronics or the piezoelectric array.

[0198] In an embodiment, each line unit may be designed to be composed of several subunits, with separate control for each subunit. The advantage of these subunits is that it may reduce the difficulty of driving large capacitive loads for the line units using a single external transmit driver. For example, if two line units are made instead of one containing the entire piezoelectric element in the row, two different transmit drivers (e.g. 2816) may be used, with each transmit driver controlling half of the load of the full line unit. Also, even if one driver is used, by separately driving the first half of the line unit and the second half of the line unit, the drive conditions may be improved due to the lower resistance connection to both ends of the line unit.

[0199] In an embodiment, both the length and orientation of the line units may be controlled. For example, in FIG. 20-FIG. 29, the line units may be arranged in both the x and y directions. For example, in FIG. 30, O electrodes along a column (e.g., 2003-11 to 2003-n1) may be electrically coupled to form one line unit, and O electrodes in other columns may be electrically coupled to form n line units extending along the x direction. More specifically, the line units extending along the x direction include n O electrodes (2003-12 to 2003-1n), ..., (2003-n2 to 2003-nn). In an embodiment, the arrangement of the line units along the orthogonal direction may be possible by controlling electrical circuits in an ASIC chip.

[0200] 20-30, each piezoelectric element may include two or more top (X and T) electrodes. In embodiments, the piezoelectric layers underlying these top electrodes may be poled in the same or opposite directions. Multiple poling directions, when combined with an appropriate applied signal electric field, may result in improvements in the transmit and receive sensitivity of the transducer and may also result in additional resonances that allow for wider bandwidth.

[0201] In Figures 20-30, each array may have one or more membranes disposed under the piezoelectric elements. In an embodiment, the membrane may have multiple vibration modes. In an embodiment, one membrane may vibrate in a fundamental mode at one frequency, and another membrane may vibrate at a different frequency determined by the membrane design and relative placement of the electrodes with different poling directions. In an embodiment, multiple membranes may be driven by the same set of electrodes, and each membrane may have a different fundamental frequency. In an embodiment, each membrane may respond to a wide range of frequencies, increasing its bandwidth. Such transducers with different poling directions may also help increase transmit and receive sensitivity while enabling high bandwidth transducers.

[0202] 22, 24, and 25, the X (or T) electrodes in a column may be electrically coupled to conductors. In an embodiment, these conductors may be electrically coupled to one common conductor. For example, in FIG. 22, conductors 2008-1 through 2208-n may be electrically coupled to one common conductor line, so that all T electrodes in array 2200 may be connected to ground or a common DC bias voltage.

[0203] 20-29, each array may include piezoelectric elements arranged in a two-dimensional array, and the number of elements in the x-direction may be the same as the number of elements in the y-direction, however, it should be apparent to one skilled in the art that the number of elements in the x-direction may be different from the number of elements in the y-direction.

[0204] In an embodiment, an ASIC chip (e.g., 1804) coupled to the transducer substrate (e.g., 1802) may include a temperature sensor that measures the surface temperature of the imager 120 that faces the human body during operation. In an embodiment, the maximum allowable temperature may be adjusted, which may limit the functionality of the imager since the temperature should not rise above an acceptable upper limit. In an embodiment, this temperature information may be used to improve image quality. For example, if the temperature is below the maximum allowable limit, more power may be consumed in the amplifier to reduce noise and improve the system signal-to-noise ratio for improved quality images.

[0205] In an embodiment, the power consumed by the imaging device 120 increases as the number of line units driven simultaneously increases. All line units in the imaging device 120 may need to be driven to complete transmission of pressure waves from the entire aperture. If only a few line units are driven at a time to transmit pressure waves, wait, and receive reflected echoes, it takes more time to complete one cycle of driving all the line units for the entire aperture, reducing the rate at which images are taken per second (frame rate). To improve this rate, more line units need to be driven at once. In an embodiment, the temperature information may allow the imaging device 120 to drive more lines to improve the frame rate.

[0206] 20-30, each piezoelectric element may have one bottom electrode (O) and one or more top electrodes (X and T) and may have two or more resonant frequencies. For example, each piezoelectric element 2502 in FIG. 25 may have one bottom electrode (O) and two top electrodes, with a first top and bottom electrode (O) responsive to a first frequency f1 and a second top and bottom electrode (O) responsive to a second frequency f2, which may be different from f1.

[0207] In an embodiment, the charge generated during the receive mode is transferred to amplifiers such as 1811, 2810, 2814, 2910, 2914, 3010, 3016, 3128, and 3228. The amplified signals may then be further processed by various electrical components. Thus, it should be clear to one skilled in the art that each of the amplifiers 1811, 2810, 2814, 2910, 2914, 3010, 3016, 3128, and 3228 refers to one or more electrical components / circuits that process the charge signals, i.e., each amplifier symbolically represents one or more electrical components / circuits for processing the charge signals.

[0208] 38 illustrates a schematic diagram of an imaging assembly 3800 according to an embodiment of the present disclosure. As illustrated, the imaging assembly 3800 may include a transceiver board 3801 having piezoelectric elements (not shown in FIG. 38); an ASIC chip 3802 electrically coupled to the transceiver board 3801; a receiver multiplexer 3820 electrically coupled to the ASIC chip 3802; a receiver analog front end (AFE) 3830; a transmitter multiplexer 3824 electrically coupled to the ASIC chip 3802; and a transmit beamformer 3834 electrically coupled to the second multiplexer 3824. In an embodiment, the ASIC chip 3802 may include a plurality of circuits 3804 connected to and configured to drive a plurality of piezoelectric elements in the transceiver board 3801. In an embodiment, each circuit 3804 may include a receiver amplifier (or simply amplifier) ​​3806, such as an LNA, a transmit driver 3808 for transmitting a signal to the piezoelectric element, and a switch 3810 for toggling between the amplifier 3806 and the transmit driver 3808. The amplifiers may have programmable gain and means for connecting them to the piezoelectric element that needs to be sensed. The transmit drivers have means for optimizing their impedance and means for connecting to the piezoelectric element to be driven.

[0209] In an embodiment, the receiver multiplexer 3820 may include multiple switches 3822 and the receiver AFE 3830 may include multiple amplifiers 3832. In an embodiment, each of the switches 3822 may electrically connect / disconnect the circuit 3804 to / from the amplifier 3832. In an embodiment, the transmitter multiplexer 3824 may include multiple switches 3826 and the transmit beamformer 3834 may include multiple transmit drivers 3836 and other circuitry not shown for controlling relative delays between the transmit driver waveforms of the various drivers and other circuitry not shown for controlling the frequency and number of pulses for each transmit driver. In an embodiment, each of the switches 3826 is turned on and connected to the circuit 3804 during a transmit operation while the switch 3822 is turned off while the switch 3810 is connected to the transmit driver 3808. Similarly, during receive operation, switch 3826 is off while switch 3822 is on, while switch 3810 is connected to amplifier 3806 .

[0210] In an embodiment, the switch 3810 may be toggled to the transmit driver 3808 during a transmit mode and to the amplifier 3806 during a receive mode. In an embodiment, a portion of the switch 3822 may be closed so that the corresponding circuit 3804 may be set to a receive mode. Similarly, a portion of the switch 3826 may be closed so that the corresponding circuit 3804 may be set to a transmit mode. Since a portion of the switch 3822 and a portion of the switch 3826 may be closed simultaneously, the imager assembly may be operated in both transmit and receive modes simultaneously. Also, the receiver multiplexer 3820 and the transmitter multiplexer 3824 reduce the number of ASIC pins. In an embodiment, the receiver multiplexer 3820, the receiver AFE 3830, the transmitter multiplexer 3824, and the transmitter beamformer 3834 may be included in the circuit 215 of FIG. 2.

[0211] In embodiments, each piezoelectric body may have more than two electrodes, one of which may be in a transmit mode to generate pressure waves while the other electrode is in a receive mode to generate an electric charge. This simultaneous operation of transmit and receive modes may allow for three-dimensional imaging.

[0212] While the invention is susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and have been described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims.

Claims

1. An imaging device having a transceiver board and an ASIC chip, The transceiver board includes: A substrate; At least one film disposed on the substrate; a plurality of piezoelectric elements disposed on the at least one membrane; Including, Each of the plurality of piezoelectric elements is A lower electrode; a piezoelectric layer disposed on the lower electrode; a first top electrode and a second top electrode disposed on the piezoelectric layer, the first top electrode being electrically and spatially separated from the second top electrode, the first top electrode responsive to a first frequency and the second top electrode responsive to a second frequency different from the first frequency; Including, the piezoelectric layer includes a first portion located under the first top electrode and poled in a first direction, and a second portion located under the second top electrode and poled in a second direction opposite to the first direction; the ASIC chip is electrically connected to the transceiver substrate by a three-dimensional interconnect mechanism; at least one circuit for controlling one or more of the plurality of piezoelectric elements; a control unit electrically coupled to the at least one circuit and controlling the at least one circuit; Including, 1. An imaging device comprising:

2. The imaging device of claim 1 , wherein the bottom electrode is a signal electrode, and the first top electrode and the second top electrode are common electrodes and are connected to one of a ground and a DC bias.

3. The at least one circuit comprises: a transmission driver for transmitting a transmission signal to the lower electrode; an amplifier for receiving a received signal from the lower electrode and amplifying the received signal; The imaging device according to claim 1 .

4. The at least one circuit further comprises: a switch having a first terminal electrically coupled to the bottom electrode and a second terminal that toggles between two conductors coupled to the transmit driver and the amplifier; The imaging device according to claim 3 .

5. 5. The imaging device of claim 4, wherein the second terminal of the switch toggles to the conductor coupled to the amplifier during a receive mode, whereby charge appearing on the bottom electrode is transferred to the amplifier.

6. 4. The imaging device of claim 3, wherein the transmit signal has rising and falling edges, the rising and falling edges being symmetrical with respect to one another and the high and low portions of the waveform being substantially equal.

7. The imaging device of claim 3 , wherein the transmit signal is a pulse wave modulated (PWM) signal.

8. The imaging device of claim 7 , wherein a width of the pulse wave modulated signal is adjusted to implement transmit apodization.

9. 9. The imaging device of claim 8, wherein the transmit signal has two or more levels, some of the levels being used to encode weights for the apodization.

10. 2. The imaging device of claim 1, wherein each of the plurality of piezoelectric elements further includes three conductors coupled to the lower electrode, the first upper electrode and the second upper electrode, respectively, and the three conductors are electrically connected to the at least one circuit by the three-dimensional interconnect mechanism.

11. The imaging device of claim 10 , wherein the three-dimensional interconnect mechanism includes at least one of a Cu pillar and a solder bump.

12. The imaging device of claim 1 , wherein each of the plurality of piezoelectric elements further includes a third upper electrode disposed on the piezoelectric layer and spatially separated from the first and second upper electrodes.

13. The imaging device of claim 1 , further comprising at least one temperature sensor for measuring a temperature of the imaging device.

14. the ASIC chip includes a low noise amplifier (LNA); The low noise amplifier (LNA) receiving temperature data from the at least one temperature sensor; Using the temperature data, (i) adjusting at least one of an imaging frame rate and a signal-to-noise ratio of the LNA; or (ii) Turning off some receive channels to reduce temperature when having a low noise amplifier (LNA) per channel; The imaging device according to claim 13.

15. The imaging device of claim 1 , further comprising a layer disposed over the plurality of piezoelectric elements and configured to reduce impedance mismatch at an interface between the piezoelectric elements and an object being imaged.

16. The imaging device of claim 1 , wherein the plurality of piezoelectric elements are arranged in a two-dimensional array.

17. 17. The imaging device of claim 16, wherein the two-dimensional array is configured to operate in a biplanar mode in which a portion of the piezoelectric elements in a column of the two-dimensional array simultaneously generate pressure waves and a portion of the piezoelectric elements in a row of the two-dimensional array simultaneously form electrical signals.

18. The imaging device of claim 1 , further comprising a cavity formed beneath the at least one membrane.

19. The imaging device of claim 1 , wherein the at least one circuit controls power delivered to a piezoelectric element, thereby controlling a penetration depth of pressure waves generated by the piezoelectric element.

20. at least one port for receiving one end of a cable configured to communicate with an external device; A Field Programmable Gate Array (FPGA); a communication unit for communicating with an external device through said cable; The imaging device of claim 1 , further comprising:

21. (i) the external device is one of a smartphone and a tablet; (ii) the port is any one of USB2, USB3, USB3.1, and USB-C; 21. The imaging device of claim 20.

22. a communication unit for wirelessly communicating signals to an external device having a display using a USB3 protocol; The cable is used to transfer power from the display.

21. The imaging device of claim 20.

23. a housing surrounding the imaging device; and a mechanism for dissipating the generated thermal energy to reduce a temperature of the transceiver board and the housing. The imaging device according to claim 1 .

24. The thermal imaging device according to claim 21, further comprising an additional housing enclosing the control unit and a mechanism for dissipating additional thermal energy; the additional housing is connected to the transceiver board and the housing by a cable and dissipates thermal energy generated by the control unit; The control unit includes a Field Programmable Gate Array (FPGA); 24. The imaging device of claim 23.

Images