5G-NR Multi-Cell Software Framework

Abstract

To provide a device, a system, and a technique that perform multi-cell physical layer (PHY) processing in fifth generation (5G) new radio (NR) networks.SOLUTION: In at least one embodiment, a PHY library that implements a PHY pipeline groups multi-user and / or multi-cell 5G-NR PHY operations for parallel execution as a result of one or more function calls to an application programming interface provided by the PHY library.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] At least one embodiment relates to processing resources used to perform and facilitate multi-cell physical layer (PHY) processing in a fifth generation (5G) New Radio (NR) network. For example, at least one embodiment relates to a processor or computing system used to perform parallelized multi-user and / or multi-cell 5G-NR PHY operations using a software PHY library that implements a PHY pipeline in accordance with various novel techniques described herein. [Background technology]

[0002] Processing physical layer (PHY) operations in fifth-generation (5G) New Radio (NR) communications networks can use significant memory, time, and other computing resources. This resource usage increases with the addition of additional users or computing cells to 5G-NR base stations in 5G-NR networks. The increasing ubiquity of wireless communication devices, along with the increasing deployment of 5G-NR network infrastructure, is increasing the demand for 5G-NR network processing resources. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram illustrating a fifth-generation (5G) New Radio (NR) physical layer (PHY) pipeline implemented by a PHY library, according to at least one embodiment. [Figure 2] FIG. 2 is a block diagram illustrating function calls to a PHY pipeline implemented by a PHY library to perform PHY operations, according to at least one embodiment. [Figure 3A] FIG. 1 is a block diagram illustrating a PHY descriptor, according to at least one embodiment. [Figure 3B]FIG. 2 is a block diagram illustrating an example PUSCH pipeline descriptor in a PHY pipeline implemented by a PHY library, according to at least one embodiment. [Figure 4A] FIG. 2 is a block diagram illustrating a hierarchical data organization for a PHY pipeline implemented by a PHY library, according to at least one embodiment. [Figure 4B] FIG. 2 is a block diagram illustrating a temporal data organization for a PHY pipeline implemented by a PHY library, according to at least one embodiment. [Figure 5] FIG. 2 is a block diagram illustrating an example PUSCH data structure for a PHY pipeline implemented by a PHY library, according to at least one embodiment. [Figure 6] FIG. 1 is a block diagram illustrating PHY descriptor buffering, according to at least one embodiment. [Figure 7] FIG. 1 is a block diagram illustrating batched parameter organization in a PHY operation batch, according to at least one embodiment. [Figure 8] FIG. 1 is a block diagram illustrating an example pipeline topology for executing a batched PHY operation workload, according to at least one embodiment. [Figure 9] FIG. 1 is a block diagram illustrating an example of a time slot-based PHY pipeline batch topology, according to at least one embodiment. [Figure 10] FIG. 1 is a block diagram illustrating the placement of batched PHY descriptors, according to at least one embodiment. [Figure 11] FIG. 1 is a block diagram illustrating an example application programming interface (API) to a physical layer PHY pipeline implemented by a PHY library, according to at least one embodiment. [Figure 12] FIG. 1 illustrates a process for performing PHY operations in a 5G-NR PHY pipeline implemented by a PHY library, according to at least one embodiment. [Figure 13] FIG. 1 illustrates an example data center system, according to at least one embodiment. [Figure 14A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 14B] 14B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 14A, according to at least one embodiment. [Figure 14C] FIG. 14B is a block diagram illustrating a system architecture of the autonomous vehicle example of FIG. 14A, according to at least one embodiment. [Figure 14D] FIG. 14B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 14A, according to at least one embodiment. [Figure 15] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 16] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 17] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 19A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 19B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 19C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 19D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 19E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 19F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 20] FIG. 1 illustrates an example integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 21A]FIG. 1 illustrates an example integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 21B] FIG. 1 illustrates an example integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 22A] FIG. 10 illustrates additional example graphics processor logic, according to at least one embodiment. [Figure 22B] FIG. 10 illustrates additional example graphics processor logic, according to at least one embodiment. [Figure 23] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 24A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 24B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 24C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 24D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 25] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 26] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 27] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 28] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 29] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 30] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 31]FIG. 1 is a block diagram of a graphics processing engine of a graphics processor, according to at least one embodiment. [Figure 32] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 33A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 33B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 34] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 35] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 36] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 37] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 38] FIG. 1 illustrates a network for transmitting data within a 5G wireless communication network, according to at least one embodiment. [Figure 39] FIG. 1 illustrates a network architecture for a 5G LTE wireless network, according to at least one embodiment. [Figure 40] FIG. 1 illustrates the basic functionality of any of the mobile telecommunications networks / systems operating according to LTE and 5G principles, according to at least one embodiment. [Figure 41] FIG. 1 illustrates a radio access network that may be part of a 5G network architecture, according to at least one embodiment. [Figure 42] FIG. 1 is a diagram of an example 5G mobile communication system in which multiple different types of devices are used, according to at least one embodiment. [Figure 43] FIG. 1 illustrates an example super system, according to at least one embodiment. [Figure 44] FIG. 1 illustrates a system architecture for a network, according to at least one embodiment. [Figure 45] FIG. 1 illustrates components of an example device, according to at least one embodiment. [Figure 46] FIG. 1 illustrates an example interface of a baseband circuit, according to at least one embodiment. [Figure 47] FIG. 1 illustrates an example of an uplink channel, according to at least one embodiment. [Figure 48] FIG. 1 illustrates a system architecture for a network, according to at least one embodiment. [Figure 49] FIG. 1 illustrates a control plane protocol stack, according to at least one embodiment. [Figure 50] FIG. 1 illustrates a user plane protocol stack, according to at least one embodiment. [Figure 51] FIG. 1 illustrates components of a core network, according to at least one embodiment. [Figure 52] FIG. 1 illustrates components of a system that supports network function virtualization (NFV), according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0004] FIG. 1 is a block diagram illustrating a fifth-generation (5G) New Radio (NR) physical layer (PHY) pipeline implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G New Radio (NR) library, according to at least one embodiment. In at least one embodiment, 5G-NR is a network communication standard for radio access technology, 5G refers to the fifth generation of wireless technology, and New Radio refers to a new air interface and radio access technology for cellular communication networks. In at least one embodiment, a 5G-NR network comprises base stations that process communication information from cells, such as towers, having multiple connected user equipment (UE), such as mobile phones. To process information from multiple cells, in one embodiment, each base station performs various processing operations, which are described further herein. In at least one embodiment, processing operations in a 5G-NR network are categorized into layers, including different layers, such as Layer 1 (L1) 106 or physical layer (PHY), which performs lower-level operations, and Layer 2 (L2) 102, which performs higher-level operations.

[0005] In at least one embodiment, Layer 2 (L2) 102 is a logical organization of hardware operations, software operations, and high-level operations performed by a base station comprising that hardware and software. In at least one embodiment, the high-level operations are 5G-NR computational operations that depend on or otherwise require interaction with lower-level operations performed in L1 / PHY 106 on the base station. In at least one embodiment, L2 102 includes one or more computational operations that facilitate 5G-NR network communications. In at least one embodiment, L2 102 operations prepare data and / or other information for computational operations performed by L1 / PHY 106. To invoke or otherwise interact with one or more computational operations performed by L1 / PHY 106, L2 102 uses the L2-L1 interface 104.

[0006] In at least one embodiment, the L2-L1 interface 104 is hardware and / or software instructions that, when executed, provide an interface between the L2 102 and the L1 106 in a 5G-NR network. In at least one embodiment, the L2-L1 interface 104 is an application programming interface (API). In at least one embodiment, the L2-L1 interface 104 is a hardware interface. In at least one embodiment, the L2-L1 interface 104 is another interface that facilitates interaction and transfer of data and / or other information between the L2 102 and the L1 106 in a 5G-NR network.

[0007] In at least one embodiment, Layer 1 (L1) 106, or physical layer (PHY), is a logical organization of hardware operations, software operations, and low-level operations performed by a base station comprising that hardware and software. In at least one embodiment, L1 / PHY 106 is implemented in hardware. In at least one embodiment, L1 / PHY 106 is implemented by one or more software libraries. In at least one embodiment, L1 / PHY 106 is implemented by one or more software libraries to facilitate acceleration of L1 / PHY 106 operations using one or more parallel processing units (PPUs), such as graphics processing units (GPUs).

[0008] In at least one embodiment, the L1 / PHY 106 is organized into physical channels, such as uplink and downlink. In at least one embodiment, each channel performs functions for transmitting and receiving data. In at least one embodiment, each channel performs functions for transmitting and receiving control information, cell discovery, and initial access. In at least one embodiment, uplink and downlink signal processing components for the L1 / PHY 106, such as software operations implemented in the physical layer (PHY) library 116, provide a signal processing pipeline with signal processing blocks for channel-specific operations for each L1 / PHY 106. In at least one embodiment, for downlink channels in which a baseband unit (BBU) performs transmitter communications, the signal processing blocks are determined by the 3rd Generation Partnership Project (3GPP) NR standard. In at least one embodiment, for uplink channels in which a BBU performs receiver communications, the signal processing blocks are implementation specific and may include various components that perform operations as described further herein.

[0009] In at least one embodiment, between the L1 / PHY 106 and L2 102 of a 5G-NR communication network or any other type of communication network, the L2-L1 interface 104 provides an interface between signal processing operations of the L1 / PHY 106 layer, such as operations performed by a software PHY library 116, such as cuPHY, cuBB, or any other software fifth generation 5G-NR library, to higher layers, such as the L2 102 of a BBU. In at least one embodiment, the L2-L1 interface 104 acts as an interface between components of the L1 / PHY 106, such as the PHY library 116 that perform signal processing operations, and higher layers (e.g., L2 102) of a 3rd Generation Partnership Project (3GPP) protocol stack.

[0010] In at least one embodiment, the L2-L1 interface interacts with or otherwise communicates with a physical layer (PHY) library driver 112. In at least one embodiment, the PHY library driver is software instructions that, when executed, orchestrate and / or invoke one or more L1 / PHY 106 signal processing operations performed by the physical layer (PHY) library 116. To perform or cause the invocation of the PHY library driver's 112 signal processing operations, in one embodiment, the PHY library driver 112 implements a physical layer (PHY) library driver interface 110. In at least one embodiment, the PHY library driver interface 110 is software instructions that, when executed, provide an application programming interface (API) for invoking one or more L1 / PHY 106 signal processing operations performed by the PHY library driver 112 and implemented at least in part by the PHY library 116.

[0011] In at least one embodiment, the physical layer (PHY) library 116 is software instructions that, when executed, perform various signal processing operations in accordance with a 5G-NR protocol stack, such as a 3GPP protocol stack. In at least one embodiment, the PHY library 116 comprises or otherwise provides a physical layer (PHY) library interface 114. In at least one embodiment, the PHY library interface 114 is software instructions that, when executed, provide an API to the PHY library 116 for performing the various signal processing operations performed by the PHY library 116. In at least one embodiment, the PHY library interface 114 is an API. In at least one embodiment, the PHY library interface 114 provides an API that conforms to a standard, such as the Small Cell Forum's FAPI interface. In at least one embodiment, the PHY library interface 114 provides an API that is proprietary.

[0012] In at least one embodiment, a PHY library 116, such as cuPHY, cuBB, or any other software fifth-generation 5G-NR library, manages software that executes on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), as described further herein. In at least one embodiment, the PHY library 116 manages a software kernel, or segments of software instructions, that performs one or more specific operations to implement signal processing operations for the L1 / PHY 106 of a 5G-NR wireless communication system, the software kernel being executed by one or more PPUs, such as GPUs, as described further herein.

[0013] In at least one embodiment, one or more PPUs, such as a GPU, perform all functions, such as all operations, of the L1 / PHY 106 in the signal processing pipeline. In at least one embodiment, one or more PPUs, such as a GPU, accelerate specific operations of the L1 / PHY 106 or blocks of L1 / PHY 106 operations in the signal processing pipeline. In at least one embodiment, the PHY library driver 112 and / or the PHY library 106 provide software, such as one or more interfaces 110, 114, or other APIs, to manage PPU interactions. In at least one embodiment, the PHY library 116 sends or otherwise provides one or more parameters and / or descriptors, as described below, to one or more software kernels being executed by the one or more PPUs, such as a GPU, to perform one or more signal processing operations of the L1 / PHY 106. In at least one embodiment, PHY library 116 and / or PHY library driver 112 manage output from one or more software kernels executed by one or more PPUs, such as GPUs.

[0014] In at least one embodiment, the PHY library 116 implements and / or executes signal processing operations for transmission of data and / or other information in the L1 / PHY 106 of a 5G-NR network. In at least one embodiment, the signal processing operations implemented and / or executed by the PHY library 116 include a physical uplink shared channel (PUSCH). In at least one embodiment, the PUSCH in 5G-NR is designated to carry multiplexed control information and user application data, as described further herein. In at least one embodiment, the signal processing operations implemented and / or executed by the PHY library 116 include a physical downlink shared channel (PDSCH). In at least one embodiment, the PDSCH carries user data and higher layer signaling, as described further herein.

[0015] In at least one embodiment, the signal processing operations performed and / or executed by PHY library 116 comprise components for control information transmission. In at least one embodiment, the control information transmission components include a physical downlink control channel (PDCCH) and a physical uplink control channel (PUCCH). In at least one embodiment, the PDCCH and PUCCH carry information regarding transmission formats and resource allocations related to the PDSCH and PUSCH channels, as described further below.

[0016] In at least one embodiment, the control information transmission component includes L1 / PHY 106 reference signals. In at least one embodiment, the L1 / PHY 106 reference signals in the control information transmission component are a demodulation reference signal (DMRS), a phase-tracking reference signal (PTRS), a sounding reference signal (SRS), and a channel-state information reference signal (CSI-RS). In at least one embodiment, the DMRS is used to estimate the wireless channel for demodulation, as described further herein. In at least one embodiment, the PTRS is utilized to enable compensation for oscillator phase noise, as described further herein. In at least one embodiment, the SRS and CSI-RS are utilized to perform channel state information (CSI) measurements for scheduling, beamforming, and / or link adaptation, as described further herein.

[0017] In at least one embodiment, the signal processing operations performed and / or executed by the PHY library 116 provide components for initial access and cell discovery. In at least one embodiment, cell discovery comprises at least a physical random access channel (PRACH) and a physical broadcast channel (PBCH), as described further herein. In at least one embodiment, a synchronization signal block (SS Block) can be broadcast to select a serving cell, as described further herein.

[0018] In at least one embodiment, the signal processing operations implemented and / or performed by the PHY library 116 include lower physical layer (Low PHY) functions that perform basic operations on 5G-NR signals, as described further herein. In at least one embodiment, the Low PHY functions include a fast Fourier transform (FFT) and an inverse fast Fourier transform (IFFT). In at least one embodiment, the FFT and IFFT convert frequency-based signal information into time-based data for processing, and vice versa, as described further herein. In at least one embodiment, the Low PHY functions include cyclic prefix (CP) insertion and removal. In at least one embodiment, the CP insertion and removal facilitates the execution of FFT and IFFT operations that perform convolution, as described further herein. In at least one embodiment, the Low PHY functions include transmit beamforming (Tx Beamforming) and receive beamforming (Rx Beamforming). In at least one embodiment, as further described herein, beamforming is a signal filtering technique used in 5G-NR and other wireless networks. In at least one embodiment, one or more antennas in one or more radio units, such as cells, transmit and receive signal data from one or more user equipment (UE), such as mobile phones and / or other wireless communication-enabled devices.

[0019] In at least one embodiment, the signal processing operations performed and / or executed by the PHY library 116 include other L1 / PHY 106 operations further described herein and / or required by the 3GPP standard or other 5G-NR standard documents. In order for the L1 / PHY 106 operations to interact with L2 102 or otherwise transfer data, the above L1 / PHY 106 operations use the L2-L1 interface 104 between L2 102 and L1 106, as described above.

[0020] 2 is a block diagram illustrating function calls 202 to a physical layer (PHY) pipeline implemented by a PHY library 210 to perform PHY operations, including those described above in conjunction with FIG. 1, according to at least one embodiment. In at least one embodiment, one or more components implementing a fifth-generation (5G) new radio (NR) network protocol stack, such as a Layer 2 (L2) or Layer 1 (L1) PHY driver, execute one or more function calls 202 to a PHY library interface 208, as described above. In at least one embodiment, the PHY library interface 208 is software instructions that, when executed, provide an application programming interface (API) to the PHY library 210. In at least one embodiment, the PHY library 210 is software instructions that, when executed, perform one or more L1 operations to perform one or more PHY functions of the 5G-NR protocol stack, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, PHY library 210 is a software implemented 5G-NR library such as cuPHY, cuBB, or any other software 5G-NR library.

[0021] In at least one embodiment, the one or more function calls 202 are software instructions that, when executed, invoke or otherwise call one or more functions provided by the API of the PHY library interface 208. In at least one embodiment, as further described below in conjunction with FIGS. 3A and 3B, the one or more function calls include one or more descriptors 204 as input to the one or more function calls. In at least one embodiment, the descriptors 204 are data structures, such as software containers, for parameters 206 for one or more components of the PHY pipeline implemented by the PHY library 210. In at least one embodiment, the descriptors 204 occur in the context of one or more kernel interfaces. In at least one embodiment, the descriptors 204 occur in the context of other interfaces of the 5G-NR platform. In at least one embodiment, as described further below, parameters 206 are data values ​​that indicate or include information provided to one or more operations performed by one or more components of a PHY pipeline implemented by PHY library 210. In at least one embodiment, parameters 206 include attributes of one or more PHY operations. In at least one embodiment, the attributes are data values ​​that indicate one or more properties of one or more PHY operations. For example, in one embodiment, the attributes indicate one or more cells that transmit information from one or more user equipment (UE) devices that are at least processed by one or more PHY operations implemented by PHY library 210. In other embodiments, the attributes indicate an identifier that is unique to one UE device or shared among multiple UE devices.

[0022] In at least one embodiment, as described further below, one or more function calls 202 invoke one or more functions provided by a PHY library interface 208 to a PHY library 210 and provide one or more descriptors 204 including one or more parameters 206 as input to the one or more functions provided by the PHY library interface 208. In at least one embodiment, the PHY library 210 performs one or more signal processing operations. In at least one embodiment, the one or more descriptors 204 including the one or more parameters 206 indicate one or more configurations of the one or more signal processing operations performed by the PHY library 210 to execute a batch 214 of one or more signal processing operations invoked by the one or more function calls 202.

[0023] In at least one embodiment, batch 214 is a logical organization of one or more signal processing operations or descriptors 204 and / or parameters 206 that make up one or more signal processing operations performed by PHY library 210. In at least one embodiment, PHY library 210 executes batch 214 according to one or more characteristics of one or more function calls 202. For example, in one embodiment, PHY library 210 executes batch 214 of one or more function calls 202 that correspond to single or multiple cell sites or other groupings of one or more user equipment (UE) in a 5G-NR network. In other embodiments, PHY library 210 executes batch 214 according to other logical organization of members and / or components of a 5G-NR network. To execute or otherwise support batch 214, in one embodiment, PHY library 210 includes structured data organization 212, as described further below. In at least one embodiment, data organization 212 is a logical organization of data that facilitates batching 214 by PHY library 210, such as through a tree or other linked data relationships between data containers of PHY library 210 as described above.

[0024] 3A is a block diagram illustrating a physical layer (PHY) descriptor 302 according to at least one embodiment. In at least one embodiment, the PHY descriptor 302 is a data container that includes component parameters 304, 306, and 308. In at least one embodiment, the component parameters 304, 306, and 308 are data that includes one or more values ​​or other data containers that describe the placement of control and / or data information for the PHY processing pipeline and / or components that process the information within the PHY processing pipeline, as described above in conjunction with FIG. 1.

[0025] In at least one embodiment, PHY descriptor 302 includes data values ​​indicating common parameters available across one or more processing components in the PHY pipeline. In at least one embodiment, as described below, PHY descriptor 302 includes data values ​​indicating kernel arguments 316 for one or more processing components in the PHY pipeline. In at least one embodiment, PHY descriptor 302 includes data values ​​indicating launch geometry, such as which computing units of one or more parallel processing units (PPUs), such as graphics processing units (GPUs), are used to execute different kernels to execute the PHY processing pipeline. In at least one embodiment, PHY descriptor 302 includes data values ​​indicating kernel selection parameters that determine which kernels executed by a PPU, such as a GPU, execute various computing components of the PHY processing pipeline. In at least one embodiment, PHY descriptor 302 includes data values ​​indicating other information that configures control and / or data processing by a central processing unit (CPU) and / or a PPU, such as a GPU.

[0026] In at least one embodiment, component parameters 304, 306, 308 are data containers that include one or more data values ​​usable to configure a PHY processing pipeline or a processing component of the PHY processing pipeline, as described in conjunction with FIG. 3B . In at least one embodiment, component parameters 304, 306, 308 include data values ​​that control data placement in memory, operation timing, data size, and / or data refresh rate. In at least one embodiment, component parameters 304, 306, 308 include data values ​​that control placement of data values ​​of component descriptor 310 in memory. In at least one embodiment, component parameters 304, 306, 308 include data values ​​that indicate update times and / or update rates of parameters to the PHY processing pipeline and / or processing components of that PHY processing pipeline. For example, in one embodiment, component parameters 304, 306, 308 include data values ​​that indicate that kernel arguments are to be updated early during a start time window, such as at setup time or run time by a driver, as described above in conjunction with FIG. 1 . In at least one embodiment, component parameters 304, 306, 308 include data values ​​that indicate the movement of parameters in memory as a bulk data transfer, such as by moving all parameters corresponding to one kernel of a PPU, such as a GPU.

[0027] In at least one embodiment, the component parameters 304, 306, 308 include a data container, such as a component descriptor 310. In at least one embodiment, the component descriptor 310 is a data value container that includes data values ​​usable to configure one or more processing components of a PHY pipeline. In at least one embodiment, the component descriptor 310 facilitates configuration of processing operations by a slot processing engine in a 5G-NR baseband device or other computing device to facilitate 5G-NR network operation. In at least one embodiment, the slot processing engine schedules computations to be performed during slots. In at least one embodiment, a slot is a time window for execution by a central processing unit (CPU) or a PPU, such as a GPU.

[0028] In at least one embodiment, component descriptor 310 includes one or more flags 312. In at least one embodiment, flags 312 are data values ​​indicating one or more binary or other data values ​​corresponding to processing components in the PHY pipeline. For example, in one embodiment, flags 312 include a binary data value indicating whether a processing component in the PHY pipeline is enabled. In at least one embodiment, component descriptor 310 includes a configuration 314 data value. In at least one embodiment, the configuration 314 data value is a data value usable to configure a processing component in the PHY pipeline. For example, in one embodiment, the configuration 314 data value indicates one or more kernels to be executed by a PPU, such as a GPU, to execute the processing component in the PHY pipeline indicated by component descriptor 310. In at least one embodiment, component descriptor 310 includes kernel arguments 316. In at least one embodiment, the kernel arguments are data values ​​indicating one or more data values ​​indicating the configuration of a kernel, such as a software kernel, to implement and execute processing component operations in the PHY pipeline. In at least one embodiment, the component descriptor 310 includes other data values ​​that can be used to configure the processing components of the PHY pipeline.

[0029] Figure 3B is a block diagram illustrating an example PUSCH pipeline descriptor 318 in a physical layer (PHY) pipeline implemented by a PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library, according to at least one embodiment, as described above in conjunction with Figure 1. In at least one embodiment, the PUSCH pipeline descriptor 318 is a PHY descriptor, as described above in conjunction with Figure 3A. That is, in one embodiment, the PUSCH pipeline descriptor 318 is an example data container that includes data values ​​and / or additional data containers usable to configure one or more operations to perform a PUSCH in the PHY pipeline, as described above in conjunction with Figure 1.

[0030] In at least one embodiment, an example PUSCH pipeline descriptor 318 includes containers 322, 324, 326, 328, 330, 332, 334, and 336, where each container 322, 324, 326, 328, 330, 332, 334, and 336 includes parameters specific to low-level PHY processing operations usable to perform a PUSCH in a fifth-generation (5G) new radio (NR) network. In at least one embodiment, the PUSCH pipeline descriptor 318 includes common parameters 320, which are data values ​​that indicate one or more configurations or other options shared among one or more containers 322, 324, 326, 328, 330, 332, 334, and 336 within the PUSCH pipeline descriptor 318.

[0031] In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, and 336 of the PUSCH pipeline descriptor 318 include individual containers specific to each low-level computational operation performed as part of the PUSCH computing pipeline represented by the PUSCH pipeline descriptor 318. In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, and 336 of an example PUSCH pipeline descriptor 318 include channel estimation parameters 322. In at least one embodiment, the channel estimation parameters 322 are data values ​​that include information usable to configure channel estimation operations performed during the PUSCH pipeline, as described further herein. In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, and 336 of an example PUSCH pipeline descriptor 318 include equalizer parameters 324. In at least one embodiment, the equalizer parameters 324 are data values ​​that include information usable to configure one or more equalization operations performed during the PUSCH pipeline. In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, 336 of the example PUSCH pipeline descriptor 318 include soft demapping parameters 326. In at least one embodiment, the soft demapping parameters 326 are data values ​​that include information usable to configure the soft demapping operations performed during the PUSCH pipeline.

[0032] The example PUSCH pipeline descriptor 318, in one embodiment, includes containers 322, 324, 326, 328, 330, 332, 334, 336 that include descrambling parameters 328. In at least one embodiment, the descrambling parameters 328 are data values ​​that include information usable to configure descrambling operations performed during the PUSCH pipeline. In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, 336 of the example PUSCH pipeline descriptor 318 include rate matching parameters 330. In at least one embodiment, the rate matching parameters 330 are data values ​​that include information usable to configure one or more rate matching operations performed during the PUSCH pipeline. In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, 336 of the example PUSCH pipeline descriptor 318 include low density parity check (LDPC) decoding parameters 332. In at least one embodiment, the LDPC decoding parameters 332 are data values ​​that include information usable to configure one or more LDPC decoding operations performed as part of the PUSCH pipeline.

[0033] In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, 336 of an example PUSCH pipeline descriptor 318 include code block cyclic redundancy check (CRC) parameters 334. The code block CRC parameters 334 are data values ​​that include information usable to configure one or more code block CRC operations, as described further herein, performed as part of the PUSCH pipeline corresponding to the PUSCH pipeline descriptor 318. In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, 336 of an example PUSCH pipeline descriptor 318 include transport block CRC parameters 336. In at least one embodiment, the transport block CRC parameters 336 are data values ​​that include information usable to configure one or more transport block CRC operations performed as part of the PUSCH pipeline.

[0034] In at least one embodiment, the containers 322, 324, 326, 328, 330, 332, 334, 336 of one or more example PUSCH pipeline descriptors 318 at least include a PUSCH component descriptor 338. In at least one embodiment, the PUSCH component descriptor 338 is a data container that includes data values ​​that indicate one or more configuration options for computational components of the PUSCH pipeline. For example, in one embodiment, the PUSCH component descriptor 338 includes an enable flag 340, which is a data value that indicates whether a given PUSCH component corresponding to the PUSCH component descriptor 338 is enabled or executed in the PUSCH pipeline. In at least one embodiment, the PUSCH component descriptor 338 includes a kernel count 342. In at least one embodiment, the kernel count 342 is a data value and / or data structure that selects kernels and provides arguments for those selected kernels. For example, kernel count 342, in one embodiment, is a bitmap, which is a data item including at least a one- or two-dimensional array of binary values, each binary value indicating whether a particular software kernel executes a PUSCH component operation on a parallel processing unit (PPU), such as a graphics processing unit (GPU). In at least one embodiment, PUSCH component descriptor 338 includes one or more kernel arguments 344, 346, 348 for each kernel selected by kernel selection bitmap 342. In at least one embodiment, kernel arguments 344, 346, 348 are data values ​​indicating one or more arguments or parameters to provide to each selected kernel for executing a PUSH component operation on a PPU, such as a GPU.

[0035] FIG. 4A is a block diagram illustrating a hierarchical data organization for a physical layer (PHY) pipeline implemented by a PHY library, according to at least one embodiment. In at least one embodiment, the hierarchical data organization improves the efficiency of data access and storage because searching and accessing one or more data values ​​in the tree is a fast computational operation and the tree structure has low storage overhead. In at least one embodiment, to organize the data as illustrated in FIG. 4A , at the root of the tree, cell parameters 402 include data values ​​indicating information such as cell-specific configuration information for a fifth-generation (5G) new radio (NR) network. By including all cell-specific information in a tree structure with cell-specific parameters 402 at the root of the tree, in one embodiment, information sharing between cells is eliminated, reducing data dependencies and allowing cells to be added to a 5G-NR network without modifying existing cell configurations. In at least one embodiment, cell parameters 402 include data values ​​including versioning information, device-specific information, and the number of represented cells, as well as other cell-specific information. In at least one embodiment, the number of cells represented is an attribute of a higher level of abstraction in a 5G-NR implementation. In at least one embodiment, the cell information represented by cell parameters 402 is visible to all other elements of the tree structure that correspond to the cells represented by the tree structure.

[0036] In at least one embodiment, the children of the parent cell parameters 402 node in the tree are the pipeline-specific parameters 404, 406, 408, 410. In at least one embodiment, the pipeline-specific parameters 404, 406, 408, 410 contain pipeline-level information, such as information that may be shared across different pipelines 404, 406, 408, 410, and the pipeline-level information is contained within each pipeline rather than being propagated back to the parent cell parameters 402. In at least one embodiment, the pipeline-specific parameters 404, 406, 408, 410 contain information that is visible from each pipeline-specific parameter 404, 406, 408, 410 node in the tree to all child and descending nodes in the tree.

[0037] In at least one embodiment, the pipeline-specific parameters 404, 406, 408, 410 include PHY channel parameters, such as PUCCH receive parameters 404. In at least one embodiment, the PUCCH receive parameters 404 are containers, as described above in conjunction with Figures 3A and 3B, that include parameters and / or other information specific to PUCCH receive operations in the PHY pipeline, as described above in conjunction with Figure 1. In at least one embodiment, the pipeline-specific parameters 404, 406, 408, 410 include PUSCH receive parameters 406. In at least one embodiment, the PUSCH receive parameters 406 are containers, as described above in conjunction with Figures 3A and 3B, that include parameters and / or other information specific to PUSCH receive operations in the PHY pipeline, as described above in conjunction with Figure 1. In at least one embodiment, the pipeline-specific parameters 404, 406, 408, 410 include PDSCH transmit parameters 408. In at least one embodiment, PDSCH transmission parameters 408 are a container, as described above in conjunction with Figures 3A and 3B, and include parameters and / or other information specific to PDSCH transmission operations in the PHY pipeline, as described above in conjunction with Figure 1. In at least one embodiment, pipeline specific parameters 404, 406, 408, 410 include PDCCH transmission parameters 410. In at least one embodiment, PDCCH transmission parameters 410 are a container, as described above in conjunction with Figures 3A and 3B, and include parameters and / or other information specific to PDCCH transmission operations in the PHY pipeline, as described above in conjunction with Figure 1.

[0038] In at least one embodiment, the container for each pipeline-specific parameter 404, 406, 408, 410 includes pipeline-specific operational parameters 412, 414, 416, 418. In at least one embodiment, the pipeline-specific operational parameters 412, 414, 416, 418 are component descriptors, as described above in conjunction with Figures 3A and 3B. In at least one embodiment, the pipeline-specific operational parameters 412, 414, 416, 418 include common parameters, as described above in conjunction with Figure 3B. In at least one embodiment, the pipeline-specific operational parameters 412, 414, 416, 418 include channel estimation parameters 414, rate matching parameters 416, low-density parity check (LDPC) parameters 418, as well as other component parameters not explicitly shown in Figure 4, such as cyclic redundancy check (CRC) parameters, as described above in conjunction with Figure 3B. In at least one embodiment, the pipeline-specific operation parameters 412, 414, 416, 418 include any other parameters corresponding to one or more PHY pipeline operations performed as part of a PHY pipeline implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein.

[0039] 4B is a block diagram illustrating a temporal data organization for a PHY pipeline implemented by a PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library described further herein, according to at least one embodiment. In at least one embodiment, parameters on a central processing unit (CPU) and / or a parallel processing unit (PPU), such as a graphics processing unit (GPU), are organized by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein, according to time considerations such as access rate and variability. In at least one embodiment, the temporally organized parameters include static parameters 422, semi-static parameters 424, and / or dynamic parameters 426.

[0040] In at least one embodiment, static parameters 422 are parameters that remain constant during execution, such as those described above in conjunction with FIGs. 3A and 3B. In at least one embodiment, static parameters 422 are initialized and stored or backed up in persistent memory by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein, at pipeline build and / or configuration time. In at least one embodiment, semi-static parameters 424 are parameters that change over a relatively small number of slots or calculation windows during 5G-NR pipeline execution, such as those described above in conjunction with FIGs. 3A and 3B. In at least one embodiment, semi-static parameters 424 are initialized upon the occurrence of a specific event, such as a configuration message from a higher layer (e.g., Layer 2, as described above in conjunction with FIG. 1). In at least one embodiment, dynamic parameters 426 are parameters that are updated per PHY pipeline execution slot, at the slot rate, and / or during execution slot configuration, such as those described above in conjunction with FIGs. 3A and 3B. In at least one embodiment, dynamic parameters 426 are parameters whose values ​​are updated frequently or whose values ​​change frequently.

[0041] In at least one embodiment, the temporally organized parameters have increasing flexibility 428. That is, in one embodiment, the static parameters 422 have low flexibility or a low ability to change, while the quasi-static parameters 424 have increased flexibility, and the dynamic parameters 426 are maximally flexible and can be updated or modified. In at least one embodiment, the temporally organized parameters have increasing performance 430 that is inversely correlated with flexibility 428. That is, in one embodiment, the dynamic parameters 426 have low performance due to frequent updates, while the quasi-static parameters 424 have increased performance due to less frequent updates and / or modifications, and the static parameters 422 have maximum performance due to their immutability.

[0042] 5 is a block diagram illustrating an example PUSCH pipeline data structure for a physical layer (PHY) pipeline implemented by a software PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library described further herein, according to at least one embodiment. In at least one embodiment, example PUSCH receive parameters 502 are PHY descriptors or PHY component descriptors, as described above in conjunction with FIG. 3A. In at least one embodiment, PUSCH receive parameters 502 include a pointer to parent 504 for hierarchical data organization, such as a pointer to parent in a tree structure, as described above in conjunction with FIG. 4A.

[0043] In at least one embodiment, the PUSCH reception parameters 502 include common parameters 506, where the common parameters are data values ​​that indicate one or more configuration options or other information shared between one or more component descriptors 510, 512, 514 that correspond to the descriptors of the PUSCH reception parameters 502. In at least one embodiment, the PUSCH reception parameters 502 include pointers 508 to children in a hierarchical organization, as described above in conjunction with FIG.

[0044] In at least one embodiment, the pointer to child 508 points to child component descriptors 510, 512, 514. In at least one embodiment, the child component descriptors 510, 512, 514 include computational components that implement the PUSCH receive pipeline, such as channel estimation parameters 510, rate matching parameters 512, low-density parity check (LDPC) parameters, and / or any other parameters corresponding to components that perform one or more computational operations to implement the PUSCH receive pipeline, as described above in conjunction with Figures 1 and 3B.

[0045] In at least one embodiment, as described above in conjunction with FIG. 4B, the common parameters 506, 516 in the PUSCH receive parameters 502 descriptor are organized into static parameters 518, quasi-static parameters 520, and / or dynamic parameters 522 by a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein. In at least one embodiment, the static parameters 518, 524 include i parameters 526, 528, where the i parameters 526, 528 are immutable, as described above in conjunction with FIG. 4B. In at least one embodiment, the quasi-static parameters 520, 530 include j parameters 532, 534, where the j parameters 532, 534 vary according to a slot frequency or other execution scheduling metric for one or more slots to execute a PHY pipeline, such as a PUSCH receive pipeline, as described above in conjunction with FIG. 4B. In at least one embodiment, the dynamic parameters 522, 536 include k parameters 538, 540, where the k parameters 538, 540 change and / or are updated frequently, as described above in conjunction with FIG. 4B.

[0046] In at least one embodiment, a parallel processing unit (PPU) 542, such as a graphics processing unit (GPU), stores static parameters 524, 544 in memory available for storing unchanging data values. In at least one embodiment, a PPU 542, such as a GPU, stores semi-static parameters 530, 546 in memory available for storing periodically updated data values. In at least one embodiment, a PPU 542, such as a GPU, stores dynamic parameters 536, 548 in memory available for data values ​​with high frequency of change and / or update.

[0047] FIG. 6 is a block diagram illustrating physical layer (PHY) descriptor buffering, according to at least one embodiment. In at least one embodiment, prior to slot execution time for a PHY pipeline corresponding to a static PHY descriptor 604, the static PHY descriptor 604 is assembled in a memory of a central processing unit (CPU) 602 by a software PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library described further herein, as described above in conjunction with FIGS. 3A and 4B, and copied to a memory of a parallel processing unit (PPU) 610, such as a memory of a graphics processing unit (GPU). In at least one embodiment, the static PHY descriptor 603 is assembled by the software PHY library during setup of the PHY pipeline corresponding to the static PHY descriptor. In at least one embodiment, the PPU 610, such as a GPU, stores the copied static PHY descriptor 612, as described above in conjunction with FIG. 5.

[0048] In at least one embodiment, a software PHY library, such as cuPHY, cuBB, or any other software fifth generation 5G-NR library further described herein, buffers the quasi-static PHY descriptor 606 and the dynamic PHY descriptor 608 on the CPU 602. In at least one embodiment, buffering the quasi-static PHY descriptor 606 and the dynamic PHY descriptor 608 facilitates processing of slots in the PHY pipeline corresponding to the quasi-static PHY descriptor 606 and the dynamic PHY descriptor 608. In at least one embodiment, a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library further described herein, buffers the quasi-static PHY descriptor 606 and the dynamic PHY descriptor 608 on the CPU 602 and copies the quasi-static PHY descriptor 606 and the dynamic PHY descriptor 608 to one or more PPUs 610. In at least one embodiment, one or more PPUs 610, such as a GPU, store a copied semi-static PHY descriptor 614 and a copied dynamic PHY descriptor 616, as described above in conjunction with FIG.

[0049] In at least one embodiment, as illustrated in Figure 6, the buffering of time-sorted PHY descriptors is used only when necessary. For example, in one embodiment, a pipeline level may require static, semi-static, and dynamic parameters contained in static PHY descriptors 604, 612, buffered semi-static PHY descriptors 606, 614, and buffered dynamic PHY descriptors 608, 616, but a component may only require the static PHY descriptors 604, 612 and / or buffered dynamic PHY parameters 608, 616. In at least one embodiment, the depth of the number of PHY channel processing pipelines and corresponding PHY descriptor buffers is adjusted by a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein, to compensate for processing latency. For example, up to N quasi-static PHY descriptors 606, 614 and up to M dynamic PHY descriptors 608, 616 may be buffered by a software PHY library in one embodiment to compensate for processing latency for execution slots during 5G-NR processing.

[0050] 7 is a block diagram illustrating batched parameter organization in a physical layer (PHY) operation batch, according to at least one embodiment. In at least one embodiment, a batch is a logical organization or combination of computational PHY operations in a PHY pipeline, such that the PHY operations are computed by one or more kernels on a parallel processing unit (PPU), such as a graphics processing unit (GPU). In at least one embodiment, a software PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library as described further herein, batches PHY operations according to different workload configurations. In at least one embodiment, an example workload configuration is a large number of cell sites with a small number of connected user equipment (UE), such as mobile phones, handled by a 5G-NR baseband unit (BBU). In at least one embodiment, another example workload configuration is a small number of cell sites with a large number of connected UE, handled by a 5G-NR BBU.

[0051] In at least one embodiment, a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein, batches parameters corresponding to PHY pipeline operations based on workload. For example, in one embodiment, the software PHY library batches parameters corresponding to PHY pipeline operations according to workload arrival. In at least one embodiment, the batching according to workload arrival arranges or groups parameters according to spatial characteristics, where the software PHY library batches parameters across concurrent workloads available in a given slot, a processing time slot, such as parameters configuring operations on information received from devices within a cell or across multiple cells. In other embodiments, the batching according to workload arrival groups parameters according to temporal characteristics, where the software PHY library batches parameter workloads across a time interval, such as by processing multiple symbols within an execution slot to sequentially perform operations such as PUSCH and PDSCH, processing multiple cells consecutively for a smaller workload per cell, or processing across multiple PHY channels.

[0052] Another example of batching PHY parameters corresponding to workload-based PHY pipeline operations is, in one embodiment, a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, that batches according to workload configuration. In at least one embodiment, batching according to workload configuration arranges or groups parameters according to homogeneous characteristics of the PHY operating parameters being batched. In at least one embodiment, homogeneous batching allows a single kernel to process multiple identically configured workloads. In at least one embodiment, batching according to homogeneous characteristics includes batching within a particular kernel-specific dimension by aggregating parameters that arrive at the software PHY library simultaneously or over time. In at least one embodiment, batching according to workload configuration arranges or groups parameters according to heterogeneous characteristics of the PHY operating parameters being batched. In at least one embodiment, heterogeneous batching allows several heterogeneous workloads to be set up and processed by a single component. In at least one embodiment, batching according to heterogeneous characteristics includes batching across kernel specialization dimensions to combine workloads into a single computation graph.

[0053] In at least one embodiment, the kernel specialization dimension is a kernel executed by a PPU, such as a GPU, that is customized by a software PHY library for each workload configuration to fit the problem size, leading to better execution time and / or throughput at the expense of increased startup overhead. In at least one embodiment, the kernel generalization dimension is a kernel executed by a PPU, such as a GPU, that is customized by a software PHY library to support multiple workloads, which may reduce the efficiency of the kernel.

[0054] FIG. 7 is a block diagram illustrating an example of batching of input parameters by a software PHY library. PUSCH batch configuration parameters 702, in one embodiment, are a data container containing parameters 704, 706, and 708 to be batched per PHY pipeline operation to perform PHY PUSCH, such as channel estimation batch parameters 704, channel equalization batch parameters 706, and low-density parity check (LDPC) batch parameters 708. In at least one embodiment, batch configuration parameters 702 specify how batching is performed, such as how to group parameters for UE group supersets. In at least one embodiment, batch configuration parameters 702 are part of each component. In at least one embodiment, batch configuration parameters 702 are part of the PHY pipeline. In at least one embodiment, the software PHY library performs heterogeneous batching according to workload type. A first LDPC batch parameter 710, in one embodiment, indicates the number of different workload types to be batched by the software PHY library. 7, first LDPC batch parameters 710 indicate three workload types that require three software kernels 712, 726, and 736 to perform LDPC operations. In at least one embodiment, the software PHY library batches or groups the parameters into the multiple kernels 712, 726, and 736 indicated by the first LDPC batch parameters 710. For the first type of LDPC batch parameters 714, 716, 718, 720, 722, and 724, in one embodiment, the software PHY library batches the batch parameters into the first LDPC kernel 712.

[0055] For the first type of LDPC batch parameters 714, 716, 718, 720, 722, 724, in one embodiment, the software PHY library heterogeneously groups or batches the LDPC batch parameters 714, 716, 718, 720, 722, 724 processed or executed by the first LDPC kernel 712 by workload type. In at least one embodiment, for the second type of LDPC batch parameters 728, 730, 732, 734, the software PHY library heterogeneously groups or batches the LDPC batch parameters 728, 730, 732, 734 processed or executed by the second LDPC kernel 726 by workload type. In at least one embodiment, for the third type of LDPC batch parameters 738, 740, 742, 744, 746, the software PHY library heterogeneously groups or batches the LDPC batch parameters 738, 740, 742, 744, 746 processed or executed by the third LDPC kernel 736 by workload type.

[0056] In at least one embodiment, batch parameters such as LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, and 746 are encoded in a type-length-value format for flexibility and efficient memory usage, as shown in Figure 7. In at least one embodiment, batch parameters such as LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, and 746 are encoded by the 5G-NR PHY library to use arrays of fixed maximum length for each group or batch type. In at least one embodiment, for each group or batch of LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746, a first LDPC batch parameter 714, 728, 738 indicates a type associated with each group or batch of LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746 processed by the respective LDPC kernel 712, 726, 736. In at least one embodiment, for each group or batch of LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746, the second LDPC batch parameter 716, 730, 740 indicates the length or number of parameters in each group or batch of LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746. In at least one embodiment, the remaining LDPC batch parameters 718, 720, 722, 724, 732, 734, 742, 744, 746 of a group or batch of LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746 include parameter data values ​​such as indices into a user equipment (UE) group superset 748, as described below.In other embodiments, the remaining LDPC batch parameters 718, 720, 722, 724, 732, 734, 742, 744, 746 of the group or batch of LDPC batch parameters 714, 716, 718, 720, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746 include any other parameter data values ​​that facilitate configuration of one or more PHY pipeline operations.

[0057] In at least one embodiment, the UE group superset 748 is a data container that includes batched PUSCH kernel parameters 750, 752, 754 for each kernel 712, 726, 736. In at least one embodiment, the software PHY library heterogeneously batches the PUSCH kernel parameters 750, 752, 754 into the UE group superset 748 according to one or more characteristics of the PUSCH kernel parameters 750, 752, 754, such as arrival time or slot execution time requirements. In at least one embodiment, the software PHY library heterogeneously batches parameters 714, 716, 718, 720, 722, 724, 728, 730, 732, 734, 738, 740, 742, 744, 746 for each computational operation, such as channel estimation 704, channel equalization 706, LDPC, and / or any other low-level PHY operation, into one or more kernels 712, 726, 736 according to the type of parameter. In at least one embodiment, the software PHY library heterogeneously batches parameters 750, 752, 754 into UE group supersets 748 according to other parameter characteristics, such as arrival time or slot execution time requirements.

[0058] 8 is a block diagram illustrating an example pipeline topology for executing a batched PHY operation workload, according to at least one embodiment. In at least one embodiment, one or more parallel processing units (PPUs), such as graphics processing units (GPUs), execute software kernels 802, 810, and 834, where each software kernel performs one or more PHY computation operations. In at least one embodiment, each software kernel 802, 810, and 834 performs one or more PHY computation operations using batched parameters, as described above in conjunction with FIG. 7. In at least one embodiment, each software kernel 802, 810, and 834 performs one or more PHY computation operations using batched parameters, where the batched parameters are grouped according to homogeneous workload configuration batches, as described above in conjunction with FIG. 7. In at least one embodiment, each software kernel 802, 810, 834 performs one or more PHY computational operations using batched parameters, where the batched parameters are grouped according to heterogeneous workload configuration batches, as described above in conjunction with Figure 7. In at least one embodiment, each software kernel 802, 810, 834 performs one or more PHY computational operations using batched parameters, where the batched parameters are grouped according to spatial grouping based on workload arrival, as described above in conjunction with Figure 7. In at least one embodiment, each software kernel 802, 810, 834 performs one or more PHY computational operations using batched parameters, where the batched parameters are grouped according to temporal grouping based on workload arrival, as described above in conjunction with Figure 7.

[0059] In at least one embodiment, software kernels 802, 810, and 834 perform one or more PHY computation operations in parallel with other software kernels 802, 810, and 834. In at least one embodiment, each software kernel 802, 814, and 834 performs one or more PHY computation operations configured based on parameters grouped or batched according to type in heterogeneous batches, as described above. In at least one embodiment, each software kernel 802, 810, and 834 performs one or more PHY computation operations for each pipeline stage 818, 820, 822, 826, and 828. In one embodiment, software kernels 802, 810, and 834 perform one or more PHY computation operations for each configuration specified by the batched parameters individually. Between PHY computation operations, one or more pipeline stages 818, 820, 822, 826, 828 store the computed data resulting from each PHY computation operation configured according to the batched parameters.

[0060] In at least one embodiment, one or more pipeline stages 818, 820, 822, 826, 828 are memories, such as registers, that store one or more values ​​received by the one or more pipeline stages 818, 820, 822, 826, 828 as output data from one or more parallel PHY computation operations performed by one or more kernels 802, 810, 834. In at least one embodiment, one or more pipeline stages 818, 820, 822, 826, 828 are shared across one or more kernels 802, 810, 834. In at least one embodiment, each of the one or more kernels 802, 810, 834 includes an individual pipeline stage that stores intermediate data results of one or more PHY computation operations performed by a corresponding one of the one or more kernels 802, 810, 834.

[0061] Between each pipeline stage 818, 820, 822, 826, 828, one or more kernels 802, 810, 834 each perform one or more PHY computation operations, where each computation operation performed by each kernel is configured with batched or grouped parameters specific to a workload, as described above in conjunction with FIG. 7. In at least one embodiment, the one or more PHY computation operations include channel estimation 804, 812, 836, as described further herein. In at least one embodiment, each channel estimation 804, 812, 836 operation is configured with a batch of parameters corresponding to a workload type, as described above in conjunction with FIG. 7. In at least one embodiment, the one or more PHY computation operations include channel estimation 806, 814, 838, as described further herein. In at least one embodiment, each channel estimation 806, 814, 838 operation is configured with a batch of parameters corresponding to a workload type, as described above in conjunction with FIG. 7.

[0062] In at least one embodiment, one or more PHY computation operations are shared among sets of configuration parameters grouped by batch. In at least one embodiment, the shared PHY computation operations include rate matching and scrambling analysis 824, code block cyclic redundancy check (CB CRC) and aggregation 830, transport block (TB) CRC 832, and / or any other PHY computation operation that can be shared among batches of configuration parameters. In at least one embodiment, one or more PHY computation operations that are not shared among one or more kernels 802, 810, 834 include low-density parity check (LDPC) decoding and / or encoding 808, 816, 840, as described further herein. In at least one embodiment, each LDPC decoding and / or encoding 808, 816, 840 operation is configured by a batch of parameters corresponding to a workload type, as described above in conjunction with FIG. 7.

[0063] 9 is a block diagram illustrating an example physical layer (PHY) batching topology based on workload time slots, according to at least one embodiment. In at least one embodiment, one or more kernels 906, 926, 946 perform one or more PHY computational operations, such as segmentation and code block cyclic redundancy check (Seg+CB CRC) 908, 928, 948, low-density parity check (LDPC) encoding / decoding 910, 930, 950, rate matching 912, 932, 952, scrambling 914, 934, 954, modulation 916, 936, 956, layer mapping 918, 938, 958, precoding 920, 940, 960, mapping 922, 942, 962, and / or any other fifth-generation (5G) new radio (NR) PHY pipeline operations, as further described herein. In at least one embodiment, the kernels 906, 926, 946 perform one or more PHY computational operations configured with parameters based on grouping according to temporal characteristics, such as slot execution time, as further described above in conjunction with FIG. 7.

[0064] In at least one embodiment, one or more kernels 906, 926, 946 execute one or more PHY computational operations configured with parameters batched according to an execution time slot. In at least one embodiment, slot execution start point 902 is the point after which one or more kernels 906, 926, 946 are scheduled for execution by a scheduler provided by a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described herein. In at least one embodiment, time slots 904, 924, 944 are window of slot execution time occurring after slot execution start point 902. From slot execution start point 902, in one embodiment, one or more software kernels 906 execute one or more PHY pipeline computational operations configured with parameters batched according to time slot t0 904. In at least one embodiment, one or more software kernels 926 execute one or more PHY pipeline computational operations configured with other parameters batched according to a later time slot t1 924. Delay t from slot execution start point 902 n After 944, in one embodiment, one or more kernels 946 may assign the time delay t n In at least one embodiment, each time slot t 1924 t n 944, t n ≧t1+t proc where X is the time to complete a process such as a PHY pipeline and / or one or more PHY pipeline operations.

[0065] 10 is a block diagram illustrating the placement of a batched physical layer (PHY) descriptor, according to at least one embodiment. In at least one embodiment, for a PUSCH pipeline as described further herein, a PUSCH pipeline batch descriptor 1002 is a container that includes one or more pipeline descriptors 1006, 1008, 1010 for multiple pipeline instances 1004 that perform batched PUSCH pipeline operations via a software PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library described herein. In at least one embodiment, the PUSCH pipeline batch descriptor 1002 or any other PHY pipeline batch descriptor includes one or more pointers to one or more pipeline descriptors 1006, 1008, 1010 along with data indicating the number of pipeline instances 1004. In at least one embodiment, each pointer to a pipeline descriptor 1006, 1008, 1010 is data that includes a memory address that indicates a storage location for a pipeline PHY descriptor, such as PUSCH pipeline PHY descriptor 1012.

[0066] In at least one embodiment, a pipeline PHY descriptor, such as PUSCH pipeline PHY descriptor 1012, is a data container that includes common parameters 1014 and one or more pointers to component descriptors 1016, 1018, 1020, as described above in conjunction with Figures 3 and 5. In at least one embodiment, the one or more pointers to component descriptors 1016, 1018, 1020 are data that include memory addresses that indicate storage locations for one or more component descriptors, such as PUSCH component batch descriptor 1022. In at least one embodiment, a component is one or more PHY computational operations that are performed by one or more kernels using one or more parallel processing units (PPUs), such as graphics processing units (GPUs), as described above.

[0067] In at least one embodiment, a component descriptor, such as the PUSCH component batch descriptor 1022, is a data container. In at least one embodiment, a component descriptor, such as the PUSCH component batch descriptor 1022, includes data indicating the number of component instances executed by individual kernels, each executing a different configuration indicated by the component parameters 1026, 1028, 1030, 1032. In at least one embodiment, a component descriptor, such as the PUSCH component batch descriptor 1022, includes parameters grouped according to heterogeneous batches within a PHY component, as described above in conjunction with FIG. 7, by a software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described herein. In at least one embodiment, a component descriptor, such as the PUSCH component batch descriptor 1022, includes pointers to batched component descriptors and / or parameters for the heterogeneous configurations, where N kernels each execute different configurations batched as the component parameters 1026, 1028, 1030, 1032. In at least one embodiment, a component descriptor, such as the PUSCH component batch descriptor 1022, includes a number of component instances 1024. In at least one embodiment, the number of component instances 1024 is a data value that indicates the number N3 of groups or batches of that component parameter 1026, 1028, 1030, 1032 to be executed by N3 kernels, each executing a different component configuration indicated by the component parameter 1026, 1028, 1030, 1032.

[0068] In at least one embodiment, one or more component parameters 1026, 1028, 1030, 1032 of a component descriptor, such as the PUSCH component batch descriptor 1022, are organized or batched by a software PHY library according to a temporal or homogeneous characteristic, such as a parameter update frequency, as described above in conjunction with FIGs. 4B and 7. In at least one embodiment, the software PHY library organizes the component parameters 1026, 1028, 1030, 1032 into component static parameters, such as PUSCH component static parameters 1034. In at least one embodiment, the software PHY library organizes other component parameters 1026, 1028, 1030, 1032 into component quasi-static parameters, such as the PUSCH component quasi-static parameters 1034. In at least one embodiment, the software PHY library organizes the component parameters 1026, 1028, 1030, 1032 into component dynamic parameters, such as the PUSCH component dynamic parameters 1038. In at least one embodiment, the component static parameters, such as PUSCH component static parameters 1034, the component quasi-static parameters, such as PUSCH component quasi-static parameters 1036, and the component dynamic parameters, such as PUSCH component dynamic parameters 1038, include pointers to batched component descriptors and / or parameters for homogeneous configurations, where each kernel batch processes multiple workloads having the same configuration.

[0069] FIG. 11 is a block diagram illustrating an example application programming interface (API) 1110 to a physical layer (PHY) pipeline implemented by a software PHY library to perform pipeline configuration and / or batching, as described above, according to at least one embodiment. In at least one embodiment, a software PHY library, such as cuPHY, cuBB, or any other software fifth-generation (5G) new radio (NR) library, implements the API 1110 to configure and perform PHY pipeline operations using configurations defined by parameters included in descriptors, as described above in conjunction with FIGS. 2 and 3. In at least one embodiment, the PHY pipeline API 1110 is software instructions that, when executed, provide a callable interface to perform one or more PHY pipeline operations. In at least one embodiment, the software PHY library providing the PHY pipeline API batches parameters received in descriptors as a result of one or more function calls 1102, 1104, 1106, 1108 to the PHY pipeline API 1110.

[0070] In at least one embodiment, the PHY pipeline API 1110 receives, as a result of one or more function calls 1102, 1104, 1106, 1108 to the PHY pipeline API 1110, one or more descriptors that include one or more parameters that configure one or more PHY operations and / or one or more components that perform the one or more PHY operations, as described above in conjunction with Figures 2 and 3. In at least one embodiment, the one or more function calls 1102, 1104, 1106, 1108 to the PHY pipeline API 1110 are software instructions that, when executed, invoke one or more functions provided by the PHY pipeline API 1110.

[0071] In at least one embodiment, one or more function calls 1102, 1104, 1106, 1108 to a PHY pipeline API 1110 invoke an initialization (init) or deinitialization (deinit) function 1102 provided by the PHY pipeline API 1110. In at least one embodiment, the init 1102 function is a logical organization of software instructions that, when executed, performs pipeline construction and / or configuration time operations for a PHY pipeline implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described herein. For example, the init 1102 function, when executed, performs object instantiation and / or memory allocation for the PHY library and / or any other software library, such as compute uniform device architecture (CUDA) or other parallel computing library described further herein. In at least one embodiment, the deinit function 1102 is a logical organization of software instructions that, when executed, tear down or otherwise halts pipeline execution and / or frees resources, such as memory, used by the pipeline.

[0072] In at least one embodiment, the initialization function, or create 1102 function, updates static parameters when executed, as described above in conjunction with FIG. 4B . In at least one embodiment, the create 1102 function updates one or more static parameters asynchronously with respect to slot execution. In at least one embodiment, the create 1102 function is executed by one or more parallel processing units (PPUs), such as a central processing unit (CPU) and / or a graphics processing unit (GPU), to initialize resources available to a software PHY library. In at least one embodiment, the create 1102 function is called less frequently than other functions of the PHY pipeline API 1110. In at least one embodiment, the create 1102 function has a time budget on the order of a few seconds. In at least one embodiment, the create 1102 function is executed as a result of one or more calls to the PHY pipeline API 1110 implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, to process cell information, such as sector-carrier information.

[0073] In at least one embodiment, one or more function calls 1102, 1104, 1106, 1108 to a PHY pipeline API 1110 invoke a configuration (config) or reconfiguration (reconfig) function 1104 provided by the PHY pipeline API 1110. In at least one embodiment, the config1104 function is a logical organization of software instructions that, when executed, performs a pipeline configuration update. In at least one embodiment, the config1104 function is a logical organization of software instructions that, when executed, performs a pipeline configuration update using parameters as described above in conjunction with FIGS. 2 and 3A, where the update frequency is less than the slot rate. For example, the config1104 function, when executed, updates the configuration using new parameters received as a result of the call to the above config1104 function of one or more PHY pipeline operations performed by a PHY library, such as cuPHY, cuBB, or compute uniform device architecture (CUDA), or any other parallel computing or any other software library, such as a 5G-NR library described further herein. In at least one embodiment, the reconfig function 1104 is a logical organization of software instructions that, when executed, adjusts the configuration of one or more PHY pipeline computational operations, as described above, during execution or between execution slots.

[0074] In at least one embodiment, the config and / or reconfig 1104 functions, as described above in conjunction with FIG. 4B , when executed, update static parameters. In at least one embodiment, the config and / or reconfig 1104 functions, as described above in conjunction with FIG. 4B , when executed, update semi-static parameters. In at least one embodiment, the config and / or reconfig 1104 functions asynchronously update one or more static parameters. In at least one embodiment, the config and / or reconfig 1104 functions asynchronously update one or more static parameters before a slot boundary. In at least one embodiment, the config and / or reconfig 1104 functions are executed by one or more PPUs, such as a CPU and / or GPU, to configure one or more PHY operations implemented by a software PHY library and performed by the CPU and / or one or more PPUs. In at least one embodiment, the config and / or reconfig 1104 functions are called less frequently than other functions of the PHY pipeline API 1110. In at least one embodiment, the config and / or reconfig 1104 functions are called with a similar frequency compared to other functions of the PHY pipeline API 1110. In at least one embodiment, the config and / or reconfig 1104 functions have a time budget of tens to hundreds of milliseconds. In at least one embodiment, the config and / or reconfig 1104 functions have a time budget of hundreds of microseconds. In at least one embodiment, the config and / or reconfig 1104 functions are executed as a result of one or more calls to the PHY pipeline API 1110 implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, to process signaling information such as region updates.In at least one embodiment, the config and / or reconfig 1104 functions are executed as a result of one or more calls to a PHY pipeline API 1110 implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, to process user equipment (UE) information, such as whether the UE is connected or inactive.

[0075] In at least one embodiment, one or more function calls 1102, 1104, 1106, 1108 to a PHY pipeline API 1110 invoke a setup 1106 function provided by the PHY pipeline API 1110. In at least one embodiment, the setup 1106 function is a logical organization of software instructions that, when executed, performs PHY descriptor setup with slot structure information required to run one or more PHY pipelines implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described herein. For example, the setup 1106 function, when executed, performs configuration and batch using descriptors with parameters, as described above, by a PHY library and / or other software library, such as compute uniform device architecture (CUDA) or any other parallel computing library described further herein.

[0076] In at least one embodiment, the setup 1106 function updates dynamic parameters when executed, as described above in conjunction with FIG. 4B . In at least one embodiment, the setup 1106 function updates one or more dynamic parameters synchronously before a slot execution boundary. In at least one embodiment, the setup 1106 function is executed by one or more PPUs, such as a CPU and / or GPU, to configure and / or batch one or more PHY pipeline operations implemented by a software PHY library. In at least one embodiment, the setup 1106 function is called more frequently than other functions in the PHY pipeline API 1110. In at least one embodiment, the setup 1106 function has a time budget of 125 microseconds or less. In at least one embodiment, the setup 1106 function is executed as a result of one or more calls to the PHY pipeline API 1110 implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, to process slot allocation information, such as downlink allocations and uplink grants.

[0077] In at least one embodiment, one or more function calls 1102, 1104, 1106, 1108 to a PHY pipeline API 1110 invoke an execute 1108 function provided by the PHY pipeline API 1110. In at least one embodiment, the execute 1108 function is a logical organization of software instructions that, when executed, performs pipeline invocations for one or more PHY pipelines implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described herein. For example, the execute 1108 function, when executed, triggers the initiation of one or more pipelines implemented by the PHY library and / or any other software library, such as compute uniform device architecture (CUDA) or any other parallel computing library described further herein, to be executed by one or more PPUs, such as a CPU and / or a GPU.

[0078] In at least one embodiment, the execute 1108 function, when executed, does not update any of the parameters described above in conjunction with FIG. 4B . In at least one embodiment, the execute 1108 function is executed synchronously upon slot execution and / or symbol reception. In at least one embodiment, the execute 1108 function is executed by one or more PPUs, such as a CPU and / or GPU, to initiate execution of one or more PHY pipelines implemented by a software PHY library. In at least one embodiment, the execute 1108 function is called more frequently than other functions in the PHY pipeline API 1110. In at least one embodiment, the execute 1108 function has an immediate time budget because it is the trigger that initiates slot execution. In at least one embodiment, the execute 1108 function is executed as a result of one or more calls to the PHY pipeline API 1110 implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, to act as a slot processing trigger that causes the launch of one or more PPU kernels and / or the launch of one or more computation graphs.

[0079] 12 illustrates a process 1200 for performing PHY operations in a fifth-generation (5G) new radio (NR) physical layer (PHY) pipeline implemented by a PHY library, such as cuPHY, cuBB, or any other software 5G-NR library described further herein, according to at least one embodiment. In at least one embodiment, process 1200 begins 1202 by building one or more PHY pipelines 104 to perform PHY operations. During pipeline construction 1204, in one embodiment, one or more data structures are allocated and initialized in memory corresponding to a central processing unit (CPU) and / or one or more parallel processing units (PPUs), such as a graphics processing unit (GPU), as described above in conjunction with FIG. 11.

[0080] In at least one embodiment, once the software PHY library builds 1204 one or more pipelines, the software PHY library configures 1206 the one or more pipelines according to configuration parameters received as a result of one or more function calls, as described above in conjunction with Figures 2 and 3A. After configuration 1206, in one embodiment, the software PHY library, such as cuPHY, cuBB, or any other software 5G-NR library, performs a setup 1208 operation to set up PHY pipeline operations for slot execution according to configuration information provided by one or more descriptors, as described above in conjunction with Figures 3A and 5. In at least one embodiment, setup 1208 includes a batch of one or more PHY operations based on parameters provided by one or more PHY descriptors, as described above in conjunction with Figures 7-9.

[0081] In at least one embodiment, once the software PHY library sets up 1208 one or more PHY pipelines according to one or more parameters contained in one or more descriptors received as a result of one or more function calls to the software PHY library interface, as described above in conjunction with Figures 1, 2, and 11, the software PHY library launches 1210 the one or more PHY pipelines. In one embodiment, the software PHY library launches 1210 one or more PHY pipelines executed in one or more slots by one or more PPUs, such as GPUs. In another embodiment, the software PHY library launches 1210 one or more PHY pipelines executed in one or more slots by a CPU, as described above in conjunction with Figure 11.

[0082] In at least one embodiment, launching 1210 one or more PHY pipelines may require the software PHY library to reconfigure 1212 some or all of the one or more PHY pipelines while the software PHY library is running. In at least one embodiment, if the one or more PHY pipelines or operations implementing the one or more PHY pipelines are reconfigured 1212 as a result of one or more function calls to a PHY library interface that include updated parameters and / or descriptors, then in one embodiment the PHY library reconfigures 1206 the one or more PHY pipelines and / or operations implementing the one or more PHY pipelines.

[0083] In at least one embodiment, the PHY library determines 1212 whether slot execution of one or more of the PHY pipelines is complete. In one embodiment, if slot execution of one or more of the PHY pipelines is complete 1212, process 1200 determines 1214 whether a reconfiguration is required. In at least one embodiment, if a reconfiguration is required 1214, process 1200 reconfigures 1206 the pipelines. In at least one embodiment, if reconfiguration 1214 is not required, process 1200 determines 1216 whether additional pipelines are to be executed. In at least one embodiment, if additional pipelines are to be executed 1216, process 1200 continues slot execution by setting up PHY descriptor 1208. In at least one embodiment, if additional pipelines are not to be executed 1216 or have not completed execution, process 1200 ends 1218.

[0084] The techniques described and proposed herein, in one embodiment, enable fifth-generation (5G) new radio (NR) operations, such as physical layer (PHY) operations of a PHY pipeline, to be executed in parallel using computing resources, such as one or more parallel processing units (PPUs), as described above in conjunction with FIG. 1 and further described herein. In other embodiments, the techniques described and proposed herein enable 5G-NR operations to be executed in parallel using other computing resources, such as one or more software kernels. As noted above, in one embodiment, one or more computing operations, such as a 5G-NR PHY operation, are categorized into groups according to computing resources, such as one or more kernels and / or one or more PPUs. In at least one embodiment, one or more computing operations, such as a 5G-NR PHY operation, are categorized into groups according to attributes indicative of other computing resources, such as the 5G-NR cell and / or user equipment (UE) connected to the 5G-NR cell.

[0085] In at least one embodiment, a software library, such as a 5G-NR PHY library, as described above, groups one or more computing operations such that the computing operations can be executed in parallel using a computing resource, such as a software kernel and / or a PPU. In at least one embodiment, the techniques described and proposed herein for enabling 5G-NR operations to be executed in parallel according to one or more computing resources are implemented using one or more circuits to cause the 5G-NR operations to be executed in parallel according to the techniques described above. In at least one embodiment, the techniques described and proposed herein are implemented in one or more systems including one or more processors, including, but not limited to, a PPU, such as a central processing unit and / or a graphics processing unit. In at least one embodiment, the techniques described and proposed herein for executing 5G-NR operations in parallel are implemented using a software library to perform one or more parallelization methods further described herein. In at least one embodiment, the techniques described and proposed herein for performing 5G-NR operations in parallel are embodied on a machine-readable or computer-readable medium as one or more instructions that group the 5G-NR operations according to attributes indicative of computing resources, as described above.

[0086] Data Center 13 illustrates an exemplary data center 1300 in which at least one embodiment may be used. In at least one embodiment, the data center 1300 includes a data center infrastructure layer 1310, a framework layer 1320, a software layer 1330, and an application layer 1340.

[0087] 13, data center infrastructure layer 1310 may include a resource orchestrator 1312, grouped computing resources 1314, and node computing resources (“node CRs”) 1316(1) through 1316(N), where “N” represents any positive integer. In at least one embodiment, node CRs 1316(1) through 1316(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 1316(1)-1316(N) may be a server having one or more of the computing resources described above.

[0088] In at least one embodiment, grouped computing resources 1314 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). In at least one embodiment, separate groups of node CRs within grouped computing resources 1314 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0089] In at least one embodiment, resource orchestrator 1312 may configure or otherwise control one or more nodes CR 1316(1)-1316(N) and / or grouped computing resources 1314. In at least one embodiment, resource orchestrator 1312 may include a software design infrastructure (“SDI”) management entity for data center 1300. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0090] In at least one embodiment shown in FIG. 13 , framework layer 1320 includes job scheduler 1332, configuration manager 1334, resource manager 1336, and distributed file system 1338. In at least one embodiment, framework layer 1320 may include frameworks to support software 1332 in software layer 1330 and / or one or more applications 1342 in application layer 1340. In at least one embodiment, software 1332 or applications 1342 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1320 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which can use distributed file system 1338 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1332 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1300. In at least one embodiment, configuration manager 1334 may be capable of configuring different tiers, such as software tier 1330 and framework tier 1320, which includes Spark and distributed file system 1338 to support large-scale data processing. In at least one embodiment, resource manager 1336 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 1338 and job scheduler 1332. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1314 in data center infrastructure tier 1310.In at least one embodiment, resource manager 1336 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 1312.

[0091] In at least one embodiment, software 1332 included in software layer 1330 may include software used by nodes CR 1316(1)-1316(N), grouped computing resources 1314, and / or at least a portion of distributed file system 1338 of framework layer 1320. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0092] In at least one embodiment, applications 1342 included in application layer 1340 may include one or more types of applications used by at least a portion of nodes CR 1316(1)-1316(N), grouped computing resources 1314, and / or distributed file system 1338 of framework layer 1320. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and machine learning applications including training or inference software, machine learning framework software (e.g., PyTorch, Tensorflow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0093] In at least one embodiment, any of configuration manager 1334, resource manager 1336, and resource orchestrator 1312 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable data center operators of data center 1300 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0094] In at least one embodiment, data center 1300 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1300. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1300 by using weight parameters calculated by one or more techniques described herein.

[0095] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0096] 14A illustrates an example of an autonomous vehicle 1400 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1400 (alternatively referred to herein as "vehicle 1400") may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 1400 may be a semi-tractor trailer truck for transporting cargo. In at least one embodiment, the vehicle 1400 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0097] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 1400 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1400 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0098] In at least one embodiment, vehicle 1400 may include components such as, without limitation, a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1400 may include a propulsion system 1450 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1450 may be coupled to a drive train of vehicle 1400, which may include, without limitation, a transmission to enable propulsion of vehicle 1400. In at least one embodiment, propulsion system 1450 may be controlled in response to receiving a signal from throttle / accelerator 1452.

[0099] In at least one embodiment, steering system 1454, which may include without limitation a steering wheel, is used to steer vehicle 1400 (e.g., along a desired path or route) when propulsion system 1450 is operating (e.g., when the vehicle is moving). In at least one embodiment, steering system 1454 may receive signals from steering actuator 1456. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1446 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1448 and / or brake sensor.

[0100] In at least one embodiment, controller 1436, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 14A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1400. For example, in at least one embodiment, controller 1436 may send signals to operate vehicle brakes via brake actuator 1448, to operate steering system 1454 via steering actuator 1456, and to operate propulsion system 1450 via throttle / accelerator 1452. In at least one embodiment, controller 1436 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1400. In at least one embodiment, the controllers 1436 may include a first controller 1436 for autonomous driving functions, a second controller 1436 for functional safety functions, a third controller 1436 for artificial intelligence functions (e.g., computer vision), a fourth controller 1436 for infotainment functions, a fifth controller 1436 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1436 may handle two or more of the above functionalities, two or more controllers 1436 may handle a single functionality, and / or some combination thereof.

[0101] In at least one embodiment, controller 1436 provides signals to control one or more components and / or systems of vehicle 1400 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 1458 (e.g., global positioning system sensors), RADAR sensors 1460, ultrasonic sensors 1462, LIDAR sensors 1464, inertial measurement units (“IMUs”), and the like. 14A ), a long-range camera (not shown in FIG. 14A ), a mid-range camera (not shown in FIG. 14A ), a speed sensor 1444 (e.g., for measuring the speed of the vehicle 1400), a vibration sensor 1442, a steering sensor 1440, a brake sensor (e.g., as part of a brake sensor system 1446), and / or other types of sensors.

[0102] In at least one embodiment, one or more of the controllers 1436 may receive input (e.g., represented by input data) from the instrument cluster 1432 of the vehicle 1400 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1434, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1400. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 14A )), location data (e.g., the location of the vehicle 1400 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by the controller 1436, etc. For example, in at least one embodiment, the HMI display 1434 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0103] In at least one embodiment, vehicle 1400 further includes network interface 1424, which may use a wireless antenna 1426 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1424 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. Additionally, in at least one embodiment, the wireless antenna 1426 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area networks ("LPWAN") such as LoRaWAN, SigFox, etc.

[0104] In at least one embodiment, the software physical layer (PHY) library 116 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide area networks ("LPWAN") such as LoRaWAN, SigFox, etc.

[0105] 14B illustrates example camera locations and fields of view for autonomous vehicle 1400 of FIG. 14A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 1400.

[0106] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1400. In at least one embodiment, the camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0107] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0108] In at least one embodiment, one or more of the cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from the interior of the vehicle (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. For side view cameras, in at least one embodiment, the camera may again be integrated into the four pillars at each corner of the vehicle.

[0109] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of the vehicle 1400 may be used for a surroundings view to facilitate identification of the path and obstacles ahead and, in conjunction with the controller 1436 and / or one or more of the control SoCs, may assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0110] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1470 may be used to sense objects (e.g., pedestrians, cross traffic, or bicyclists) coming into view from the periphery. While FIG. 14B shows only one wide-angle camera 1470, in other embodiments, there may be any number (including zero) of wide-angle cameras 1470 on the vehicle 1400. In at least one embodiment, any number of long-range cameras 1498 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1498 may also be used for object detection and classification, as well as basic object tracking.

[0111] In at least one embodiment, any number of stereo cameras 1468 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1468 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1400 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1468 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1400 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1468 may be used in addition to or instead of those described herein.

[0112] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of the vehicle 1400 (e.g., side view cameras) may be used for the surrounding view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1474 (e.g., four surrounding cameras 1474 as shown in FIG. 14B ) may be disposed on the vehicle 1400. In at least one embodiment, the surrounding cameras 1474 may include, without limitation, any number and combination of wide-angle cameras 1470, fisheye cameras, and / or 360-degree cameras. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 1400. In at least one embodiment, the vehicle 1400 may use three surrounding cameras 1474 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0113] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1400 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras also suitable as front cameras described herein (e.g., long-range camera 1498, and / or mid-range camera 1476, stereo camera 1468, infrared camera 1472, etc.).

[0114] FIG. 14C is a block diagram illustrating an example system architecture for the autonomous vehicle 1400 of FIG. 14A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1400 of FIG. 14C is shown as connected via a bus 1402. In at least one embodiment, the bus 1402 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1400 used to assist in controlling various features and functions of the vehicle 1400, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1402 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1402 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1402 may be an ASIL B compliant CAN bus.

[0115] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or instead of CAN. In at least one embodiment, any number of buses 1402 may be present, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1402 may be used to perform different functions and / or to provide redundancy. For example, a first bus 1402 may be used for collision avoidance functions and a second bus 1402 may be used for actuation control. In at least one embodiment, each bus 1402 may communicate with any of the components of the vehicle 1400, or two or more buses 1402 may communicate with the same component. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1404, each of controllers 1436, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1400) and may be connected to a common bus, such as a CAN bus.

[0116] In at least one embodiment, vehicle 1400 may include one or more controllers 1436, such as those described herein with respect to FIG. 14A. In at least one embodiment, controller 1436 may be used for a variety of functions. In at least one embodiment, controller 1436 may be coupled to any of a variety of other components and systems of vehicle 1400 and may be used to control vehicle 1400, artificial intelligence of vehicle 1400, and / or infotainment of vehicle 1400, etc.

[0117] In at least one embodiment, vehicle 1400 may include any number of SoCs 1404. Each of SoCs 1404 may include, without limitation, a central processing unit ("CPU") 1406, a graphics processing unit ("GPU") 1408, a processor 1410, a cache 1412, an accelerator 1414, a data store 1416, and / or other components and features not shown. In at least one embodiment, SoC 1404 may be used to control vehicle 1400 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1404 may be incorporated into a system (e.g., that of vehicle 1400) having a high definition ("HD") map 1422 that can obtain map refreshes and / or updates via a network interface 1424 from one or more servers (not shown in FIG. 14C ).

[0118] In at least one embodiment, CPU 1406 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1406 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1406 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1406 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 MB of L2 cache). In at least one embodiment, CPU 1406 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1406 to be active at any given time.

[0119] In at least one embodiment, one or more of the CPUs 1406 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPU 1406 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0120] In at least one embodiment, GPU 1408 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1408 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1408 may use an extended tensor instruction set. In one embodiment, GPU 1408 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1408 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1408 may use a compute application programming interface (API). In at least one embodiment, the GPU 1408 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA).

[0121] In at least one embodiment, one or more of the GPUs 1408 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 1408 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0122] In at least one embodiment, one or more of GPUs 1408 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some instances, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0123] In at least one embodiment, the GPU 1408 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 1408 to directly access the page tables of the CPU 1406. In at least one embodiment, when the GPU 1408 memory management unit ("MMU") encounters a miss, an address translation request may be sent to the CPU 1406. In at least one embodiment, in response, the CPU 1406 may look up the virtual-to-physical address mapping in its page tables and send the translation back to the GPU 1408. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 1406 and the GPU 1408 memory, thereby simplifying programming the GPU 1408 and porting applications to the GPU 1408.

[0124] In at least one embodiment, GPU 1408 may include any number of access counters that can record the frequency of GPU 1408's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0125] In at least one embodiment, one or more of the SoCs 1404 may include any number of caches 1412, including those described herein. For example, in at least one embodiment, the caches 1412 may include a level 3 (“L3”) cache available to both the CPU 1406 and the GPU 1408 (e.g., connected to both the CPU 1406 and the GPU 1408). In at least one embodiment, the caches 1412 may include a write-back cache that can record line state through the use of a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may also be used.

[0126] In at least one embodiment, one or more of the SoCs 1404 may include one or more accelerators 1414 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1404 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1408 and offload some of the GPU 1408's tasks (e.g., freeing up more cycles for the GPU 1408 to perform other tasks). In at least one embodiment, accelerator 1414 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0127] In at least one embodiment, the accelerator 1414 (e.g., a hardware-accelerated cluster) may include a deep learning accelerator (“DLA”). The DLA may include, without limitation, one or more tensor processing units (“TPU”), which may be further configured to provide tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). The DLA may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the DLA's design allows for improved performance per millimeter over typical general-purpose GPUs, typically significantly exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, a CNN for object identification and detection using data from a camera sensor, a CNN for distance estimation using data from a camera sensor, a CNN for emergency vehicle detection and identification using data from microphone 1496, a CNN for face recognition and vehicle owner identification using data from a camera sensor, and / or a CNN for security and / or safety events.

[0128] In at least one embodiment, the DLA may perform any function of the GPU 1408, and a designer may target either the DLA or the GPU 1408 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1408 and / or other accelerators 1414.

[0129] In at least one embodiment, the accelerator 1414 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1438, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0130] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, and / or the like. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0131] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1406. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0132] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0133] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0134] In at least one embodiment, the accelerator 1414 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1414. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0135] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0136] In at least one embodiment, one or more of the SoCs 1404 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0137] In at least one embodiment, accelerator 1414 (e.g., a hardware accelerator cluster) has diverse uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that require low-latency, low-power, and predictable run times, even with small data sets. In at least one embodiment, in an autonomous vehicle such as vehicle 1400, the PVA is designed to run traditional computer vision algorithms because they are effective for object detection and integer arithmetic.

[0138] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0139] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0140] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence allows the system to make further decisions regarding which detections should be considered positive detections rather than false detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 1466 that correlates with the orientation of the vehicle 1400, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 1464 or a RADAR sensor 1460), among others.

[0141] In at least one embodiment, one or more of the SoCs 1404 may include a data store 1416 (e.g., memory). In at least one embodiment, the data store 1416 may be on-chip memory of the SoC 1404, which may store neural networks running on the GPU 1408 and / or DLA. In at least one embodiment, the capacity of the data store 1416 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1416 may comprise an L2 or L3 cache.

[0142] In at least one embodiment, one or more of the SoCs 1404 may include any number of processors 1410 (e.g., embedded processors). In at least one embodiment, the processors 1410 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1404 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1404, and / or manage the power state of the SoC 1404. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1404 may use the ring oscillator to detect the temperature of the CPU 1406, GPU 1408, and / or accelerator 1414. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1404 in a low power state, and / or place the vehicle 1400 in a driver-safety shutdown mode (e.g., bring the vehicle 1400 to a safety shutdown).

[0143] In at least one embodiment, processor 1410 may further include a set of embedded processors capable of acting as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0144] In at least one embodiment, processor 1410 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0145] In at least one embodiment, the processor 1410 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1410 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 1410 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0146] In at least one embodiment, processor 1410 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 1470, surrounding camera 1474, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 1404 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0147] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0148] In at least one embodiment, the video image combiner may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image combiner may also be used to combine the user interface when the operating system desktop is in use, eliminating the need for the GPU 1408 to continually render new surfaces. In at least one embodiment, the video image combiner may be used to offload the GPU 1408 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0149] In at least one embodiment, one or more of the SoCs 1404 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1404 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0150] In at least one embodiment, one or more of the SoCs 1404 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. The SoCs 1404 may be used to process data from cameras (e.g., connected via gigabit multimedia serial links and Ethernet), data from sensors (e.g., LIDAR sensors 1464, RADAR sensors 1460, etc., which may be connected via Ethernet), data from bus 1402 (e.g., vehicle 1400 speed, steering wheel position, etc.), data from GNSS sensors 1458 (e.g., connected via Ethernet or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1404 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1406.

[0151] In at least one embodiment, the SoC 1404 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 1404 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1414, when combined with the CPU 1406, GPU 1408, and data store 1416, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0152] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language, such as the C programming language, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0153] Embodiments described herein enable multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU1420) may include text and word recognition, enabling the supercomputer to read and understand traffic signs, including signs for which the neural network was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0154] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1408.

[0155] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1400. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1404 provides security against theft and / or carjacking.

[0156] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1496 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1404 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1458. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in the United States, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1462 until the emergency vehicle has passed.

[0157] In at least one embodiment, vehicle 1400 may include a CPU 1418 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1418 may include, for example, an X86 processor. CPU 1418 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1404 and / or monitoring the status and health of controller 1436 and / or infotainment system on a chip (“infotainment SoC”) 1430.

[0158] In at least one embodiment, vehicle 1400 may include GPU 1420 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1404 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU 1420 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1400.

[0159] In at least one embodiment, vehicle 1400 may further include a network interface 1424, which may include, without limitation, a wireless antenna 1426 (e.g., one or more wireless antennas 1426 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1424 may be used to enable wireless connectivity over the Internet with the cloud (e.g., servers and / or other network devices), other vehicles, and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 140 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1400 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1400). In at least one embodiment, the above-described functionality may be part of a cooperative adaptive cruise control function of the vehicle 1400.

[0160] In at least one embodiment, the network interface 1424 may include an SoC that provides modulation and demodulation functionality and enables the controller 1436 to communicate over a wireless network. In at least one embodiment, the network interface 1424 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0161] In at least one embodiment, vehicle 1400 may further include a data store 1428, which may include, without limitation, off-chip (e.g., not on SoC 1404) storage. In at least one embodiment, data store 1428 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0162] In at least one embodiment, vehicle 1400 may further include GNSS sensors 1458 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1458 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0163] In at least one embodiment, vehicle 1400 may further include a RADAR sensor 1460. RADAR sensor 1460 may be used by vehicle 1400 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. RADAR sensor 1460 may use CAN and / or bus 1402 for control (e.g., to transmit data generated by RADAR sensor 1460) and to access object tracking data, and in some instances may have Ethernet access to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1460 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1460 are pulse-Doppler RADAR sensors.

[0164] In at least one embodiment, the RADAR sensor 1460 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 meter range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1460 may help distinguish between static and moving objects and may be used by the ADAS system 1438 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 1460 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the four central antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1400 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting the lane of vehicle 1400.

[0165] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1460 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1438 to provide blind spot detection and / or lane change assistance.

[0166] In at least one embodiment, vehicle 1400 may further include ultrasonic sensors 1462. In at least one embodiment, ultrasonic sensors 1462 may be positioned at the front, rear, and / or sides of vehicle 1400 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1462 may be used, and different ultrasonic sensors 1462 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1462 may operate at functional safety level ASIL B.

[0167] In at least one embodiment, vehicle 1400 may include a LIDAR sensor 1464. The LIDAR sensor 1464 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 1464 may be functional safety level ASIL B. In at least one embodiment, vehicle 1400 may include multiple LIDAR sensors 1464 (e.g., two, four, six, etc.), which may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0168] In at least one embodiment, the LIDAR sensor 1464 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1464 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 1464 may be used. In such an embodiment, the LIDAR sensor 1464 may be implemented as a small device that can be integrated into the front, rear, sides, and / or corners of the vehicle 1400. In at least one embodiment, the LIDAR sensor 1464 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1464 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0169] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1400 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1400 to the object. In at least one embodiment, flash LIDAR allows a highly accurate, distortion-free image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1400. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0170] In at least one embodiment, the vehicle may further include an IMU sensor 1466. In at least one embodiment, the IMU sensor 1466 may be positioned at the center of the rear axle of the vehicle 1400. In at least one embodiment, the IMU sensor 1466 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, the IMU sensor 1466 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 1466 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0171] In at least one embodiment, the IMU sensor 1466 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1466 enables the vehicle 1400 to estimate its orientation by directly observing changes in velocity and correlating them from the GPS to the IMU sensor 1466 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1466 and the GNSS sensor 1458 may be combined into a single integrated unit.

[0172] In at least one embodiment, vehicle 1400 may include microphones 1496 located in and / or around vehicle 1400. In at least one embodiment, microphones 1496 may be used for, among other things, emergency vehicle detection and identification.

[0173] In at least one embodiment, vehicle 1400 may further include any number of camera types, including stereo camera 1468, wide-angle camera 1470, infrared camera 1472, perimeter camera 1474, long-range camera 1498, mid-range camera 1476, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1400. In at least one embodiment, the types of cameras used vary depending on vehicle 1400. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1400. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1400 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera is described in further detail herein above with respect to Figures 14A and 14B.

[0174] In at least one embodiment, vehicle 1400 may further include a vibration sensor 1442. In at least one embodiment, vibration sensor 1442 may measure vibration of a component of vehicle 1400, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1442 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0175] In at least one embodiment, vehicle 1400 may include an ADAS system 1438. ADAS system 1438 may include, without limitation, an SoC in some instances. In at least one embodiment, the ADAS systems 1438 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0176] In at least one embodiment, the ACC system may use a RADAR sensor 1460, a LIDAR sensor 1464, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately preceding the vehicle 1400 and automatically adjusts the speed of the vehicle 1400 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1400 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0177] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by network interface 1424 and / or wireless antenna 1426 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, the V2V communication concept provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 1400 and in the same lane), while the I2V communication concept provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 1400 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0178] In at least one embodiment, the FCW system is designed to alert the driver to hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0179] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0180] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1400 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or brake control to correct the vehicle 1400 if the vehicle 1400 begins to drift out of its lane.

[0181] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1460 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0182] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1400. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0183] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major issue because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1400 itself determines whether to follow the results from the primary computer (e.g., first controller 1436) or the secondary computer (e.g., second controller 1436). For example, in at least one embodiment, the ADAS system 1438 may be a backup and / or secondary computer for transmitting perceptual information to a rationality module of the backup computer. In at least one embodiment, the rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1438 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0184] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0185] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary and secondary computers. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 1404.

[0186] In at least one embodiment, the ADAS system 1438 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides the same overall result, the supervisory MCU may have greater confidence that the overall result is correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0187] In at least one embodiment, the output of the ADAS system 1438 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1438 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0188] In at least one embodiment, vehicle 1400 may further include an infotainment SoC 1430 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1430 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1430 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, reverse parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1400. For example, infotainment SoC 1430 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1434, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1430 may also be used to provide information (e.g., visual and / or auditory) to a vehicle user, such as information from an ADAS system 1438, autonomous driving information such as a vehicle maneuver plan, a trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0189] In at least one embodiment, infotainment SoC 1430 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1430 may communicate with other devices, systems, and / or components of vehicle 1400 via bus 1402 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 1430 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1436 (e.g., vehicle 1400's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1430 may place vehicle 1400 in a driver-safety shutdown mode, as described herein.

[0190] In at least one embodiment, vehicle 1400 may further include an instrument cluster 1432 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). Instrument cluster 1432 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1432 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between infotainment SoC 1430 and instrument cluster 1432. In at least one embodiment, instrument cluster 1432 may be included as part of infotainment SoC 1430, or vice versa.

[0191] 14D is a diagram of a system 1476 for communicating between a cloud-based server and the autonomous vehicle 1400 of FIG. 14A, according to at least one embodiment. In at least one embodiment, the system 1476 may include any number and type of vehicles, including, without limitation, a server 1478, a network 1490, and the vehicle 1400. The server 1478 may include, without limitation, multiple GPUs 1484(A)-1484(H) (collectively referred to herein as GPUs 1484), PCIe switches 1482(A)-1482(H) (collectively referred to herein as PCIe switches 1482), and / or CPUs 1480(A)-1480(B) (collectively referred to herein as CPUs 1480). The GPUs 1484, CPUs 1480, and PCIe switches 1482 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1488 developed by NVIDIA and / or a PCIe connection 1486. ​​In at least one embodiment, the GPUs 1484 are connected to each other via an NVLink and / or an NVSwitch SoC, and the GPUs 1484 and PCIe switches 1482 are connected via a PCIe interconnect. In at least one embodiment, eight GPUs 1484, two CPUs 1480, and four PCIe switches 1482 are illustrated, but this is not intended to be limiting. In at least one embodiment, each of the servers 1478 may include any number of GPUs 1484, CPUs 1480, and / or PCIe switches 1482 in any combination, without limitation. For example, in at least one embodiment, the servers 1478 may each include 8, 16, 32, and / or more GPUs 1484.

[0192] In at least one embodiment, server 1478 may receive image data from the vehicle over network 1490 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1478 may transmit neural network 1492, updated neural network 1492, and / or map information 1494, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 1490. In at least one embodiment, updates to map information 1494 may include, without limitation, updates to HD map 1422, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1492, updated neural network 1492, and / or map information 1494 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1478 and / or other servers).

[0193] In at least one embodiment, server 1478 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1490) and / or used by server 1478 to remotely monitor the vehicle.

[0194] In at least one embodiment, server 1478 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1478 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1484, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1478 may also include a deep learning infrastructure using a CPU-powered data center.

[0195] In at least one embodiment, the deep learning infrastructure of server 1478 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1400. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1400, such as a series of images and / or objects that vehicle 1400 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1400; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1400 has failed, server 1478 may send a signal to vehicle 1400 instructing the fail-safe computer of vehicle 1400 to take control, notify the occupants, and complete a safe stopping maneuver.

[0196] In at least one embodiment, server 1478 may include a GPU 1484 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 1315 is used to execute one or more embodiments. Details regarding hardware structure 1315 are provided herein in conjunction with FIG. 13A and / or FIG. 13B.

[0197] Computer Systems 15 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof 1500 formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1500 may include components such as, without limitation, a processor 1502 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1500 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1500 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux), embedded software, and / or graphical user interfaces may also be used.

[0198] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0199] In at least one embodiment, computer system 1500 may include, without limitation, a processor 1502, which may include one or more execution units 1508 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 15 is a single-processor desktop or server system, while in other embodiments, system 15 may be a multiprocessor system. In at least one embodiment, processor 1502 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1502 may be coupled to a processor bus 1510, which may transmit digital signals between processor 1502 and other components within computer system 1500.

[0200] In at least one embodiment, processor 1502 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1504. In at least one embodiment, processor 1502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1502. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1506 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0201] In at least one embodiment, processor 1502 also includes an execution unit 1508, including, without limitation, logic for performing integer and floating-point operations. In at least one embodiment, processor 1502 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1508 may include logic for a packed instruction set 1509. In at least one embodiment, including packed instruction set 1509, along with associated circuitry for executing the instructions, in the instruction set of general-purpose processor 1502 allows operations used by many multimedia applications to be performed using packed data in general-purpose processor 1502. In one or more embodiments, many multimedia applications can be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0202] In at least one embodiment, execution unit 1508 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1500 may include, without limitation, memory 1520. In at least one embodiment, memory 1520 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1520 may store instructions 1519 and / or data 1521 represented by data signals that may be executed by processor 1502.

[0203] In at least one embodiment, a system logic chip may be coupled to the processor bus 1510 and the memory 1520. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1516, and the processor 1502 may communicate with the MCH 1516 via the processor bus 1510. In at least one embodiment, the MCH 1516 may provide a high-bandwidth memory path 1518 to the memory 1520 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1516 may route data signals between the processor 1502, the memory 1520, and other components of the computer system 1500, and may bridge data signals between the processor bus 1510, the memory 1520, and the system I / O 1522. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1516 may be coupled to memory 1520 via a high-bandwidth memory path 1518, and the graphics / video card 1512 may be coupled to the MCH 1516 via an Accelerated Graphics Port (“AGP”) interconnect 1514.

[0204] In at least one embodiment, computer system 1500 may use system I / O 1522, a proprietary hub interface bus, to couple MCH 1516 to I / O controller hub (“ICH”) 1530. In at least one embodiment, ICH 1530 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1520, a chipset, and processor 1502. Examples may include, without limitation, an audio controller 1529, a firmware hub ("flash BIOS") 1528, a wireless transceiver 1526, data storage 1524, a legacy I / O controller 1523 including a user input and keyboard interface, a serial expansion port 1527 such as a Universal Serial Bus ("USB"), and a network controller 1534. In at least one embodiment, data storage 1524 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0205] In at least one embodiment, Figure 15 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 15 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in Figure cc may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1500 may be interconnected using a compute express link (CXL) interconnect.

[0206] 16 is a block diagram illustrating an electronic device 1600 for utilizing a processor 1610, according to at least one embodiment. In at least one embodiment, electronic device 1600 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0207] In at least one embodiment, system 1600 may include a processor 1610 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, including, without limitation, processor 1610 coupled using a bus or interface, such as an I / C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 16 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 16 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 16 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 16 may be interconnected using a Compute Express Link (CXL) interconnect.

[0208] In at least one embodiment, FIG. 16 includes a display 1624, a touch screen 1625, a touch pad 1630, a Near Field Communications unit ("NFC") 1645, a sensor hub 1640, a thermal sensor 1646, an Express Chipset ("EC") 1635, a Trusted Platform Module ("TPM") 1638, a BIOS / firmware / flash memory ("BIOS,FW flash") 1622, a DSP 1660, a drive ("SSD or HDD") 1620, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN"), and a wireless local area network ("WLAN") 1646. The memory may include a Bluetooth unit 1650, a Bluetooth unit 1652, a Wireless Wide Area Network unit (“WWAN”) 1656, a Global Positioning System (GPS) 1655, a camera such as a USB 3.0 camera (“USB 3.0 camera”) 1654, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1615, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0209] In at least one embodiment, other components may be communicatively coupled to the processor 1610 via the components described above. In at least one embodiment, an accelerometer 1641, an ambient light sensor (“ALS”) 1642, a compass 1643, and a gyroscope 1644 may be communicatively coupled to the sensor hub 1640. In at least one embodiment, a thermal sensor 1639, a fan 1637, a keyboard 1646, and a touchpad 1630 may be communicatively coupled to the EC 1635. In at least one embodiment, a speaker 1663, headphones 1664, and a microphone (“mic”) 1665 may be communicatively coupled to an audio unit (audio codec and class D amplifier) ​​1664, which may be communicatively coupled to the DSP 1660. In at least one embodiment, the audio unit 1664 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1657 may be communicatively coupled to the WWAN unit 1656. In at least one embodiment, components such as the WLAN unit 1650 and Bluetooth unit 1652, and the WWAN 1656 may be implemented in a Next Generation Form Factor (“NGFF”).

[0210] 17 illustrates, according to at least one embodiment, a computer system 1700. In at least one embodiment, the computer system 1700 is configured to implement the various processes and methods described throughout this disclosure.

[0211] In at least one embodiment, computer system 1700 includes at least one central processing unit ("CPU") 1702 connected to a communication bus 1710 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1700 includes main memory 1704 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1704, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1722 provides an interface with other computing devices and networks to receive data from other systems and transmit data from computer system 1700 to other systems.

[0212] In at least one embodiment, computer system 1700 includes, without limitation, input device(s) 1708, a parallel processing system 1712, and a display device 1706, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1708, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0213] 18 illustrates a computer system 1800 according to at least one embodiment. In at least one embodiment, computer system 1800 may include, without limitation, a computer 1810 and a USB stick 1820. In at least one embodiment, computer system 1810 may include, without limitation, any number and type of processor (not shown) and memory. In at least one embodiment, computer 1810 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0214] In at least one embodiment, USB stick 1820 includes, without limitation, a processing unit 1830, a USB interface 1840, and USB interface logic 1850. In at least one embodiment, processing unit 1830 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1830 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core 1830 comprises an application specific integrated circuit ("ASIC") optimized to perform any amount and type of operations related to machine learning. For example, in at least one embodiment, processing core 1830 is a tensor processing unit ("TPC") optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing core 1830 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0215] In at least one embodiment, USB interface 1840 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1840 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1840 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1850 may include any amount and type of logic that enables processing unit 1830 to interface with a device (e.g., computer 1810) via USB connector 1840.

[0216] 19A illustrates an exemplary architecture in which multiple GPUs 1910-1913 are communicatively coupled to multiple multi-core processors 1905-1906 via high-speed links 1940-1943 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 1940-1943 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0217] Additionally, in one embodiment, two or more of GPUs 1910-1913 may be interconnected via high-speed links 1929-1930, which may be implemented using the same or different protocol / links as used for high-speed links 1940-1943. Similarly, two or more of multi-core processors 1905-1906 may be connected via high-speed link 1928, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 19A may be achieved using the same protocol / links (e.g., via a common interconnect fabric).

[0218] In one embodiment, each multi-core processor 1905-1906 is communicatively coupled to processor memory 1901-1902 via memory interconnects 1926-1927, respectively, and each GPU 1910-1913 is communicatively coupled to GPU memory 1920-1923 via GPU memory interconnects 1950-1953, respectively. Memory interconnects 1926-1927 and 1950-1953 may utilize the same or different memory access technologies. By way of example, and not limitation, processor memory 1901-1902 and GPU memory 1920-1923 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or non-volatile memory such as 3D XPoint or Nano-RAM. In one embodiment, some portions of processor memory 1901-1902 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0219] As described herein, the various processors 1905-1906 and GPUs 1910-1913 may each be physically coupled to a particular memory 1901-1902, 1920-1923, but a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, each of the processor memories 1901-1902 may have 64 GB of system memory address space, and each of the GPU memories 1920-1923 may have 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0220] 19B shows further details of the interconnection between multi-core processor 1907 and graphics acceleration module 1946 according to one example embodiment. Graphics acceleration module 1946 may include one or more GPU chips integrated on a line card that is coupled to processor 1907 via high-speed link 1940. Alternatively, graphics acceleration module 1946 may be integrated in the same package or chip as processor 1907.

[0221] In at least one embodiment, the illustrated processor 1907 includes multiple cores 1960A-1960D, each having a translation lookaside buffer 1961A-1961D and one or more caches 1962A-1962D. In at least one embodiment, the cores 1960A-1960D may include various other components, not shown, for executing instructions and processing data. The caches 1962A-1962D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1956 may be included in the caches 1962A-1962D and shared by the set of cores 1960A-1960D. For example, one embodiment of the processor 1907 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. The processor 1907 and graphics acceleration module 1946 are connected to system memory 1914, which may include processor memory 1901-1902 of FIG. 19A.

[0222] Coherence is maintained for data and instructions stored in the various caches 1962A-1962D, 1956, and system memory 1914 through inter-core communication via a coherence bus 1964. For example, each cache may have associated cache coherence logic / circuitry for communicating via the coherence bus 1964 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 1964 to monitor cache accesses.

[0223] In one embodiment, proxy circuit 1925 communicatively couples graphics acceleration module 1946 to coherence bus 1964 to enable graphics acceleration module 1946 to participate in cache coherence protocols as a peer of cores 1960A-1960D. In particular, interface 1935 provides a connection to proxy circuit 1925 over high-speed link 1940 (e.g., PCIe bus, NVLink, etc.), and interface 1937 connects graphics acceleration module 1946 to link 1940.

[0224] In one implementation, the accelerator integrated circuit 1936 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1931, 1932, N of the graphics acceleration module 1946. The graphics processing engines 1931, 1932, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1931, 1932, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1946 may be a GPU having multiple graphics processing engines 1931-1932, N, or the graphics processing engines 1931-1932, N may be individual GPUs integrated into a common package, line card, or chip.

[0225] In one embodiment, the accelerator integrated circuitry 1936 includes a memory management unit (MMU) 1939 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing the system memory 1914. The MMU 1939 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 1938 stores commands and data for efficient access by the graphics processing engines 1931-1932, N. In one embodiment, data stored in the cache 1938 and the graphics memory 1933-1934, M is kept coherent with the core caches 1962A-1962D, 1956, and the system memory 1914. As noted above, this may be accomplished via the proxy circuit 1925 on behalf of the cache 1938 and memories 1933-1934, M (e.g., sending updates regarding modifications / accesses of cache lines in the processor caches 1962A-1962D, 1956 to the cache 1938 and receiving updates from the cache 1938).

[0226] A set of registers 1945 stores context data for threads executed by graphics processing engines 1931-1932, and a context management circuit 1948 manages thread contexts. For example, the context management circuit 1948 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1948 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 1948 may restore the register values. In one embodiment, the interrupt management circuit 1947 receives and processes interrupts received from system devices.

[0227] In one implementation, virtual / effective addresses from the graphics processing engine 1931 are translated to real / physical addresses in the system memory 1914 by the MMU 1939. One embodiment of the accelerator integration circuit 1936 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1946 and / or other accelerator devices. The graphics accelerator modules 1946 may be dedicated to a single application running on the processor 1907 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1931-1932, N, are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0228] In at least one embodiment, the accelerator integrated circuit 1936 acts as a bridge to the system for the graphics acceleration module 1946, providing address translation and system memory caching services. Additionally, the accelerator integrated circuit 1936 may provide a virtualization facility for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1931-1932.

[0229] The hardware resources of the graphics processing engines 1931-1932, N are explicitly mapped into the real address space seen by the host processor 1907, so that any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 1936 is to physically separate the graphics processing engines 1931-1932, N so that they appear as independent units to the system.

[0230] In at least one embodiment, one or more graphics memories 1933-1934, M are respectively coupled to each of the graphics processing engines 1931-1932, N. The graphics memories 1933-1934, M store instructions and data that are processed by the respective graphics processing engines 1931-1932, N. The graphics memories 1933-1934, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0231] In one embodiment, to reduce data traffic over link 1940, a biasing technique is used to ensure that the data stored in graphics memory 1933-1934, M is data that will be most frequently used by graphics processing engines 1931-1932, N, and preferably is data that is not used (or at least not frequently used) by cores 1960A-1960D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and therefore preferably not needed by graphics processing engines 1931-1932, N) in the cores' caches 1962A-1962D, 1956, and system memory 1914.

[0232] FIG. 19C shows another exemplary embodiment in which the accelerator integration circuitry 1936 is integrated within the processor 1907. In at least this embodiment, the graphics processing engines 1931-1932, N communicate directly with the accelerator integration circuitry 1936 via high-speed link 1940 via interface 1937 and interface 1935 (again, any form of bus or interface protocol can be utilized). The accelerator integration circuitry 1936 may perform the same operations as described with respect to FIG. 19B, but may potentially operate at a higher throughput given its proximity to the coherence bus 1964 and caches 1962A-1962D, 1956. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integration circuitry 1936 and a programming model controlled by the graphics acceleration module 1946.

[0233] In at least one embodiment, graphics processing engines 1931-1932, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1931-1932, N, achieving virtualization within a VM / partition.

[0234] In at least one embodiment, the graphics processing engines 1931-1932, N may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize the graphics processing engines 1931-1932, N to allow access by each operating system. In a single-partition system without a hypervisor, the graphics processing engines 1931-1932, N are owned by the operating system. In at least one embodiment, the operating system may virtualize the graphics processing engines 1931-1932, N to provide access to each process or application.

[0235] In at least one embodiment, the graphics acceleration module 1946 or an individual graphics processing engine 1931-1932,N selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1914 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engine 1931-1932,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0236] FIG. 19D illustrates an exemplary accelerator integration slice 1990. As used herein, a "slice" comprises a designated portion of the processing resources of the accelerator integration circuitry 1936. An application effective address space 1982 in system memory 1914 stores a process element 1983. In one embodiment, the process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on the processor 1907. The process element 1983 contains the process state of the corresponding application 1980. A work descriptor (WD) 1984 contained in the process element 1983 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 1984 is a pointer to a job request queue in the application's address space 1982.

[0237] The graphics acceleration module 1946 and / or the individual graphics processing engines 1931-1932, N may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending a WD 1984 to the graphics acceleration module 1946 to start a job in a virtualized environment.

[0238] In at least one embodiment, the dedicated process programming model is implementation specific, in which a single process owns the graphics acceleration module 1946 or an individual graphics processing engine 1931. Because the graphics acceleration module 1946 is owned by a single process, when the graphics acceleration module 1946 is allocated, the hypervisor initializes the accelerator integration circuitry 1936 for the owning partition, and the operating system initializes the accelerator integration circuitry 1936 for the owning process.

[0239] In operation, a WD fetch unit 1991 in the accelerator integrated slice 1990 fetches the next WD 1984, which contains an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1946. As shown, data from the WD 1984 is stored in registers 1945 and may be used by the MMU 1939, the interrupt management circuit 1947, and / or the context management circuit 1948. For example, one embodiment of the MMU 1939 includes segment / page walk circuitry for accessing a segment / page table 1986 within the OS virtual address space 1985. The interrupt management circuit 1947 may process interrupt events 1992 received from the graphics acceleration module 1946. When performing graphics operations, effective addresses 1993 generated by the graphics processing engines 1931-1932, N are translated into real addresses by the MMU 1939.

[0240] In one embodiment, the same set of registers 1945 may be replicated for each graphics processing engine 1931-1932, N, and / or graphics acceleration module 1946 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 1990. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0241] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0242] In one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or graphics processing engine 1931-1932, N. The WD 1984 contains all the information the graphics processing engine 1931-1932, N needs to do its work, or it can be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0243] 19E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1998 in which a process element list 1999 is stored. The hypervisor real address space 1998 is accessible through a hypervisor 1996 that virtualizes the graphics acceleration module engine of the operating system 1995.

[0244] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 1946. There are two programming models in which the graphics acceleration module 1946 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0245] In this model, the system hypervisor 1996 owns the graphics acceleration module 1946 and makes its functions available to all operating systems 1995. In order for the graphics acceleration module 1946 to support virtualization by the system hypervisor 1996, the graphics acceleration module 1946 may comply with the following: 1) an application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1946 must provide a mechanism for saving and restoring context. 2) the application's job request must be guaranteed by the graphics acceleration module 1946 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 1946 must provide the ability to preempt job processing. 3) the graphics acceleration module 1946 must ensure fairness between processes when operating in a specified shared programming model.

[0246] In at least one embodiment, the application 1980 must make a system call to the operating system 1995 with a graphics acceleration module 1946 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module 1946 type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module 1946 type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1946 and may be in the form of a graphics acceleration module 1946 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 1946. In one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. If the implementation of the accelerator integrated circuit 1936 and the graphics acceleration module 1946 does not support a User Permission Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. The hypervisor 1996 may optionally apply the current Permission Mask Override Register (AMOR) value before placing the AMR in the process element 1983. In at least one embodiment, the CSRP is one of the registers 1945 that contains the effective address of an area in the application's address space 1982 for the graphics acceleration module 1946 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0247] Upon receiving the system call, the operating system 1995 may verify that the application 1980 is registered and authorized to use the graphics acceleration module 1946. The operating system 1995 then calls the hypervisor 1996 with the information shown in Table 3. [Table 3]

[0248] Upon receiving the hypervisor call, the hypervisor 1996 verifies that the operating system 1995 is registered and authorized to use the graphics acceleration module 1946. The hypervisor 1996 then places the process element 1983 into a process element linked list of the corresponding graphics acceleration module 1946 type. The process element may include the information shown in Table 4. [Table 4]

[0249] In at least one embodiment, the hypervisor initializes registers 1945 of multiple accelerator integrated slices 1990.

[0250] As shown in Figure 19F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 1901-1902 and GPU memories 1920-1923. In this implementation, operations performed on GPUs 1910-1913 utilize the same virtual / effective memory address space as those used to access processor memories 1901-1902, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1901, a second portion is allocated to second processor memory 1902, a third portion is allocated to GPU memory 1920, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memories 1901-1902 and GPU memories 1920-1923, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0251] In one embodiment, bias / coherence management circuits 1994A-1994E in one or more of the MMUs 1939A-1939E ensure cache coherence between the caches of one or more host processors (e.g., 1905) and the caches of the GPUs 1910-1913 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. While multiple instances of bias / coherence management circuits 1994A-1994E are shown in FIG. 19F, the bias / coherence circuits may also be implemented within the MMUs of one or more host processors 1905 and / or within the accelerator integration circuit 1936.

[0252] One embodiment allows the GPU-attached memory 1920-1923 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the GPU-attached memory 1920-1923 can be accessed as system memory without cumbersome cache coherence overhead, providing a beneficial operating environment for GPU offload. This configuration allows the host processor 1905 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access the GPU-attached memory 1920-1923 without cache coherence overhead can be crucial to the execution time of the offloaded computation. For example, in cases where there is significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1910-1913. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0253] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (i.e., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU-attached memories 1920-1923, with or without a bias cache in the GPU 1910-1913 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the bias table may be maintained entirely within the GPU.

[0254] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 1920-1923 is accessed prior to the actual access to the GPU memory, resulting in the following actions: First, a local request from a GPU 1910-1913 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 1920-1923. A local request from a GPU that finds its page in the host bias is forwarded to the processor 1905 (e.g., via the high-speed link described above). In one embodiment, a request from the processor 1905 that finds the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1910-1913. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0255] One mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1905 bias to GPU bias, but not for transitions in the opposite direction.

[0256] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages non-cacheable by the host processor 1905. To access these pages, the processor 1905 may request access from the GPU 1910, which may or may not immediately grant the access. Therefore, to reduce communication between the processor 1905 and the GPU 1910, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 1905, or vice versa.

[0257] To implement one or more embodiments, a hardware structure 1315 is used. Details regarding the hardware structure (x) 1315 are provided herein in conjunction with Figures 13A and / or 13B.

[0258] 20 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general-purpose processor cores.

[0259] 20 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2000 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 2000 includes one or more application processors 2005 (e.g., CPUs), at least one graphics processor 2010, and may further include an image processor 2015 and / or a video processor 2020, any of which may be modular IP cores. In at least one embodiment, integrated circuit 2000 includes peripheral or bus logic including a USB controller 2025, a UART controller 2030, an SPI / SDIO controller 2035, and an I.sup.2S / I.sup.2C controller 2040. In at least one embodiment, the integrated circuit 2000 may include a display device 2045 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2050 and a mobile industry processor interface (MIPI) display interface 2055. In at least one embodiment, storage may be provided by a flash memory subsystem 2060 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2065 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 2070. In at least one embodiment, some integrated circuits further include an embedded implementation of a physical layer (PHY) library 116.

[0260] 21A-21B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0261] 21A-21B are block diagrams illustrating exemplary graphics processors for use within an SoC according to embodiments described herein. FIG. 21A illustrates an exemplary graphics processor 2110 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. FIG. 21B illustrates a further exemplary graphics processor 2140 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 2110 of FIG. 21A is a low-power graphics processor core. In at least one embodiment, the graphics processor 2140 of FIG. 21B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 2110, 2140 can be a variation of the graphics processor 2010 of FIG. 20.

[0262] In at least one embodiment, the graphics processor 2110 includes a vertex processor 2105 and one or more fragment processors 2115A-2115N (e.g., 2115A, 2115B, 2115C, 2115D-2115N-1, and 2115N). In at least one embodiment, the graphics processor 2110 can execute different shader programs through separate logic, such that the vertex processor 2105 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2115A-2115N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2105 executes the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processors 2115A-2115N generate a frame buffer that is displayed on a display device using the primitive and vertex data generated by the vertex processor 2105. In at least one embodiment, the fragment processors 2115A-2115N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0263] In at least one embodiment, graphics processor 2110 further includes one or more memory management units (MMUs) 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B. In at least one embodiment, one or more MMUs 2120A-2120B provide virtual-to-physical address mapping for graphics processor 2110, including vertex processor 2105 and / or fragment processors 2115A-2115N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 2125A-2125B. In at least one embodiment, one or more MMUs 2120A-2120B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 2005, image processor 2015, and / or video processor 2020 of Figure 20, allowing each processor 2005-2020 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2130A-2130B enable graphics processor 2110 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection.

[0264] In at least one embodiment, graphics processor 2140 includes one or more MMUs 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B of graphics processor 2110 of FIG. 21A. In at least one embodiment, graphics processor 2140 includes one or more shader cores 2155A-2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F-2155N-1, and 2155N), which provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 2140 includes an inter-core task manager 2145 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2155A-2155N, and a tiling unit 2158 for accelerating tiling operations for tile-based rendering, in which scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0265] 22A-22B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 22A illustrates a graphics core 2200, which, in at least one embodiment, may be included in graphics processor 2010 of Figure 20, or, in at least one embodiment, may be integrated shader cores 2155A-2155N, as in Figure 21B. Figure 22B illustrates a highly parallel, general-purpose graphics processing unit 2230 suitable for incorporation into a multi-chip module in at least one embodiment.

[0266] In at least one embodiment, graphics core 2200 includes a shared instruction cache 2202, a texture unit 2218, and a cache / shared memory 2220, which are common to execution resources within graphics core 2200. In at least one embodiment, graphics core 2200 may include multiple slices 2201A-2201N, or partitions per core, and a graphics processor may include multiple instances of graphics core 2200. Slices 2201A-2201N may include supporting logic, including local instruction caches 2204A-2204N, thread schedulers 2206A-2206N, thread dispatchers 2208A-2208N, and sets of registers 2210A-2210N. In at least one embodiment, slices 2201A-2201N may include a set of additional functional units (AFUs 2212A-2212N), floating point units (FPUs 2214A-2214N), integer arithmetic logic units (ALUs 2216-2216N), address calculation units (ACUs 2213A-2213N), double precision floating point units (DPFPUs 2215A-2215N), and matrix processing units (MPUs 2217A-2217N).

[0267] In at least one embodiment, the FPUs 2214A-2214N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 2215A-2215N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2216A-2216N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2217A-2217N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 2217A-2217N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, AFUs 2212A-2212N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0268] FIG. 22B illustrates a general-purpose processing unit (GPGPU) 2230 that, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 2230 can be directly linked to other instances of the GPGPU 2230 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 2230 includes a host interface 2232 for enabling connection to a host processor. In at least one embodiment, the host interface 2232 is a PCI Express interface. In at least one embodiment, the host interface 2232 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2230 receives commands from the host processor and, using a global scheduler 2234, distributes execution threads associated with those commands to a set of compute clusters 2236A-2236H. In at least one embodiment, compute clusters 2236A-2236H share cache memory 2238. In at least one embodiment, cache memory 2238 can act as a higher level cache for cache memories within compute clusters 2236A-2236H.

[0269] In at least one embodiment, GPGPU 2230 includes memory 2244A-2244B coupled to compute clusters 2236A-2236H via a set of memory controllers 2242A-2242B. In at least one embodiment, memory 2244A-2244B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0270] In at least one embodiment, compute clusters 2236A-2236H each include a set of graphics cores, such as graphics core 2200 of FIG. 22A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 2236A-2236H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0271] In at least one embodiment, multiple instances of GPGPU 2230 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2236A-2236H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2230 communicate through host interface 2232. In at least one embodiment, GPGPU 2230 includes I / O hub 2239, which couples GPGPU 2230 to GPU link 2240, which enables direct connection to other instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2230 are located in separate data processing systems and communicate via a network device accessible via host interface 2232. In at least one embodiment, GPU link 2240 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2232.

[0272] In at least one embodiment, the GPGPU 2230 can be configured to train a neural network. In at least one embodiment, the GPGPU 2230 can be used within an inference platform. In at least one embodiment, when the GPGPU 2230 is used for inference, the GPGPU may include fewer compute clusters 2236A-2236H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2244A-2244B may differ between the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2230 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network. In at least one embodiment, the inference configuration of the GPGPU 2230 can support the execution of software operations implemented by the software physical layer (PHY) library 116.

[0273] 23 is a block diagram illustrating a computing system 2300 according to at least one embodiment. In at least one embodiment, computing system 2300 includes a processing subsystem 2301 having one or more processors 2302 and system memory 2304 that communicate via an interconnection path that may include a memory hub 2305. In at least one embodiment, memory hub 2305 may be a separate component within a chipset component or may be integrated within one or more processors 2302. In at least one embodiment, memory hub 2305 is coupled to an I / O subsystem 2311 via communication link 2306. In at least one embodiment, I / O subsystem 2311 includes an I / O hub 2307 that can enable computing system 2300 to receive input from one or more input devices 2308. In at least one embodiment, the I / O hub 2307 can enable a display controller, which may be included in one or more processors 2302 and provide output to one or more display devices 2310A. In at least one embodiment, the one or more display devices 2310A coupled to the I / O hub 2307 can include local, internal, or embedded display devices.

[0274] In at least one embodiment, processing subsystem 2301 includes one or more parallel processors 2312 coupled to memory hub 2305 via a bus or other communication link 2313. In at least one embodiment, communication link 2313 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 2312 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 2312 form a graphics processing subsystem that can output pixels to one of one or more display devices 2310A coupled via I / O hub 2307. In at least one embodiment, the one or more parallel processors 2312 may also include a display controller and display interface (not shown) that allows for direct connection to one or more display devices 2310B.

[0275] In at least one embodiment, a system storage unit 2314 may be connected to an I / O hub 2307 to provide a storage mechanism for the computing system 2300. In at least one embodiment, an I / O switch 2316 may be used to provide an interface mechanism to enable communication between the I / O hub 2307 and other components, such as a network adapter 2318 and / or a wireless network adapter 2319, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2320. In at least one embodiment, the network adapter 2318 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2319 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0276] In at least one embodiment, computing system 2300 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2307. In at least one embodiment, the communication paths interconnecting the various components of FIG. 23 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol, such as the NV-Link high-speed interconnect or interconnect protocol.

[0277] In at least one embodiment, one or more parallel processors 2312 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2312 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2300 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2312, memory hub 2305, processor 2302, and I / O hub 2307 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2300 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2300 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0278] Processor 24A illustrates a parallel processor 2400 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2400 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2400 is a variation of one or more parallel processors 2312 shown in FIG. 23 according to an example embodiment.

[0279] In at least one embodiment, parallel processor 2400 includes parallel processing units 2402. In at least one embodiment, parallel processing units 2402 include I / O units 2404 that enable communication with other devices, including other instances of parallel processing units 2402. In at least one embodiment, I / O units 2404 may be directly connected to other devices. In at least one embodiment, I / O units 2404 are connected to other devices through the use of a hub or switch interface, such as memory hub 2305. In at least one embodiment, the connection between memory hub 2305 and I / O units 2404 forms communication link 2313. In at least one embodiment, I / O units 2404 are connected to host interface 2406 and memory crossbar 2416, where host interface 2406 receives commands directed to the execution of processing operations and memory crossbar 2416 receives commands directed to the execution of memory operations.

[0280] In at least one embodiment, when host interface 2406 receives command buffers via I / O unit 2404, host interface 2406 can direct work operations to execute these commands to front end 2408. In at least one embodiment, front end 2408 is coupled to scheduler 2410, which is configured to distribute commands or other work items to processing cluster array 2412. In at least one embodiment, scheduler 2410 ensures that processing cluster array 2412 is properly configured and in a valid state before tasks are distributed to processing cluster array 2412 of processing cluster array 2412. In at least one embodiment, scheduler 2410 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2410 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, allowing for rapid preemption and context switching of threads executing in the processing array 2412. In at least one embodiment, host software can signal the scheduling workload in the processing array 2412 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 2412 by scheduler 2410 logic in the microcontroller that includes the scheduler 2410.

[0281] In at least one embodiment, processing cluster array 2412 can include up to “N” processing clusters (e.g., cluster 2414A, cluster 2414B through cluster 2414N). In at least one embodiment, each cluster 2414A through 2414N of processing cluster array 2412 can execute a large number of simultaneous threads. In at least one embodiment, scheduler 2410 can allocate work to clusters 2414A through 2414N of processing cluster array 2412 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2410 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2412. In at least one embodiment, different clusters 2414A through 2414N of processing cluster array 2412 can be allocated to process different types of programs or perform different types of computations.

[0282] In at least one embodiment, processing cluster array 2412 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2412 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2412 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0283] In at least one embodiment, the processing cluster array 2412 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2412 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2412 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2402 may transfer data from system memory via the I / O unit 2404 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2422) during processing and then written back to system memory.

[0284] In at least one embodiment, when graphics processing is performed using parallel processing unit 2402, scheduler 2410 can be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2414A-2414N of processing cluster array 2412. In at least one embodiment, portions of processing cluster array 2412 can be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2414A-2414N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2414A-2414N for further processing.

[0285] In at least one embodiment, the processing cluster array 2412 can receive processing tasks to be performed via a scheduler 2410, which receives commands defining the processing tasks from the front end 2408. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2410 can be configured to fetch the index corresponding to the task or can receive the index from the front end 2408. In at least one embodiment, the front end 2408 can be configured to ensure that the processing cluster array 2412 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0286] In at least one embodiment, each of one or more instances of parallel processing unit 2402 can be coupled to parallel processor memory 2422. In at least one embodiment, parallel processor memory 2422 can be accessed via memory crossbar 2416, which can receive memory requests from processing cluster array 2412 as well as I / O unit 2404. In at least one embodiment, memory crossbar 2416 can access parallel processor memory 2422 via memory interface 2418. In at least one embodiment, memory interface 2418 can include multiple partition units (e.g., partition unit 2420A, partition unit 2420B through partition unit 2420N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2422. In at least one embodiment, the number of partition units 2420A-2420N is configured to be equal to the number of memory units, such that a first partition unit 2420A has a corresponding first memory unit 2424A, a second partition unit 2420B has a corresponding memory unit 2424B, and an Nth partition unit 2420N has a corresponding Nth memory unit 2424N. In at least one embodiment, the number of partition units 2420A-2420N does not have to be equal to the number of memory devices.

[0287] In at least one embodiment, the memory units 2424A-2424N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2424A-2424N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2422, render targets, such as frame buffers or texture maps, may be stored across the memory units 2424A-2424N, allowing the partition units 2420A-2420N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2422 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0288] In at least one embodiment, any one of the clusters 2414A-2414N in the processing cluster array 2412 can process data that is to be written to any one of the memory units 2424A-2424N in the parallel processor memory 2422. In at least one embodiment, the memory crossbar 2416 can be configured to forward the output of each cluster 2414A-2414N to any partition unit 2420A-2420N or to another cluster 2414A-2414N that can perform further processing operations on the output. In at least one embodiment, each cluster 2414A-2414N can communicate with a memory interface 2418 through the memory crossbar 2416 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2416 has connections to memory interface 2418 for communicating with I / O units 2404, as well as connections to local instances of parallel processor memory 2422, allowing processing units in different processing clusters 2414A-2414N to communicate with system memory or other memory not local to parallel processing units 2402. In at least one embodiment, memory crossbar 2416 can use virtual channels to separate traffic streams between clusters 2414A-2414N and partition units 2420A-2420N.

[0289] In at least one embodiment, multiple instances of parallel processing unit 2402 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2402 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2402 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2402 or parallel processor 2400 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0290] FIG. 24B is a block diagram of a partition unit 2420 according to at least one embodiment. In at least one embodiment, the partition unit 2420 is an instance of one of the partition units 2420A-2420N of FIG. 24A. In at least one embodiment, the partition unit 2420 includes an L2 cache 2421, a frame buffer interface 2425, and a raster operations unit (ROP) 2426. The L2 cache 2421 is a read / write cache configured to execute load and store operations received from the memory crossbar 2416 and the ROP 2426. In at least one embodiment, read misses and urgent writeback requests are output by the L2 cache 2421 to the frame buffer interface 2425 for processing. In at least one embodiment, updates are also sent to the frame via the frame buffer interface 2425 for processing. In at least one embodiment, frame buffer interface 2425 interfaces with one of the memory units of a parallel processor memory, such as memory units 2424A-2424N (eg, in parallel processor memory 2422) of FIG.

[0291] In at least one embodiment, ROP2426 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2426 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2426 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP2426 may be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0292] In at least one embodiment, ROP 2426 is included within each processing cluster (e.g., clusters 2414A-2414N of FIG. 24) rather than within partition unit 2420. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2416. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2310 of FIG. 23, may be routed for further processing by processor 2302, or may be routed for further processing by one of the processing entities in parallel processor 2400 of FIG. 24A.

[0293] FIG. 24C is a block diagram of a processing cluster 2414 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 2414A-2414N of FIG. 24. In at least one embodiment, processing cluster 2414 may be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0294] In at least one embodiment, operation of the processing clusters 2414 may be controlled via a pipeline manager 2432, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2432 receives instructions from the scheduler 2410 of FIG. 24 and manages the execution of those instructions via the graphics multiprocessor 2434 and / or the texture unit 2436. In at least one embodiment, the graphics multiprocessor 2434 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing clusters 2414. In at least one embodiment, one or more instances of the graphics multiprocessor 2434 may be included within the processing clusters 2414. In at least one embodiment, the graphics multiprocessor 2434 may process data, and a data crossbar 2440 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2432 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through data crossbar 2440.

[0295] In at least one embodiment, each graphics multiprocessor 2434 in a processing cluster 2414 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0296] In at least one embodiment, instructions sent to processing cluster 2414 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 2434. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 2434. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 2434. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 2434, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on graphics multiprocessor 2434.

[0297] In at least one embodiment, the graphics multiprocessor 2434 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2434 can forgo the internal cache and use cache memory (e.g., L1 cache 2448) within the processing cluster 2414. In at least one embodiment, each graphics multiprocessor 2434 can also access an L2 cache within a partition unit (e.g., partition units 2420A-2420N in FIG. 24), which may be shared among all processing clusters 2414 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2434 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2402 may be used as global memory. In at least one embodiment, processing cluster 2414 includes multiple instances of graphics multiprocessor 2434 that can share common instructions and data, which may be stored in L1 cache 2448.

[0298] In at least one embodiment, each processing cluster 2414 may include an MMU 2445 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2445 may reside within memory interface 2418 of FIG. 24. In at least one embodiment, MMU 2445 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses for tiles (tiling is described in more detail) and optionally cache line indices. In at least one embodiment, MMU 2445 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2434 or an L1 cache, or processing cluster 2414. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0299] In at least one embodiment, processing cluster 2414 may be configured such that each graphics multiprocessor 2434 is coupled to a texture unit 2436 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2434 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2434 outputs processed tasks to data crossbar 2440 to provide the processed tasks to another processing cluster 2414 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2416. In at least one embodiment, a pre-ROP 2442 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2434 and direct the data to the ROP units, which may be located within partition units (e.g., partition units 2420A-2420N of FIG. 24 ) as described herein. In at least one embodiment, the pre-ROP 2442 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0300] 24D illustrates a graphics multiprocessor 2434 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2434 couples with a pipeline manager 2432 of a processing cluster 2414. In at least one embodiment, the graphics multiprocessor 2434 has an execution pipeline including, but not limited to, an instruction cache 2452, an instruction unit 2454, an address mapping unit 2456, a register file 2458, one or more general-purpose graphics processing unit (GPGPU) cores 2462, and one or more load / store units 2466. The GPGPU cores 2462 and the load / store units 2466 are coupled to a cache memory 2472 and a shared memory 2470 via a memory and cache interconnect 2468.

[0301] In at least one embodiment, instruction cache 2452 receives a stream of instructions to execute from pipeline manager 2432. In at least one embodiment, instructions are cached in instruction cache 2452 and dispatched for execution by instruction unit 2454. In at least one embodiment, instruction unit 2454 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit within GPGPU core 2462. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2456 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2466.

[0302] In at least one embodiment, register file 2458 provides a set of registers to the functional units of graphics multiprocessor 2434. In at least one embodiment, register file 2458 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2462, load / store unit 2466) of graphics multiprocessor 2434. In at least one embodiment, register file 2458 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 2458. In one embodiment, register file 2458 is partitioned among the different warps being executed by graphics multiprocessor 2434.

[0303] In at least one embodiment, the GPGPU cores 2462 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 2434. The GPGPU cores 2462 may have similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 2462 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, the graphics multiprocessor 2434 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangular copy or pixel-blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0304] In at least one embodiment, GPGPU core 2462 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2462 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can execute in parallel via a single SIMD8 logical unit.

[0305] In at least one embodiment, memory and cache interconnect 2468 is an interconnect network connecting each functional unit of graphics multiprocessor 2434 to register file 2458 and shared memory 2470. In at least one embodiment, memory and cache interconnect 2468 is a crossbar interconnect that allows load / store unit 2466 to implement load and store operations between shared memory 2470 and register file 2458. In at least one embodiment, register file 2458 can operate at the same frequency as GPGPU cores 2462, and therefore data transfers between GPGPU cores 2462 and register file 2458 have very low latency. In at least one embodiment, shared memory 2470 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2434. In at least one embodiment, cache memory 2472 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 2436. In at least one embodiment, shared memory 2470 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 2462 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2472.

[0306] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into the same package or chip as the core or may be communicatively coupled to the core via an internal (i.e., internal to the package or chip) processor bus / interconnect. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions. In at least one embodiment, the GPU uses dedicated circuitry / logic to efficiently process software functions implemented by a software physical layer (PHY) library 116.

[0307] FIG. 25 illustrates a multi-GPU computing system 2500, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2500 may include a processor 2502 coupled to multiple general-purpose graphics processing units (GPGPUs) 2506A-D via a host interface switch 2504. In at least one embodiment, the host interface switch 2504 is a PCI Express switch device that couples the processor 2502 to a PCI Express bus, via which the processor 2502 can communicate with the GPGPUs 2506A-D. The GPGPUs 2506A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2516. In at least one embodiment, the GPU-to-GPU links 2516 are connected to each of the GPGPUs 2506A-D via dedicated GPU links. In at least one embodiment, the P2P GPU link 2516 allows direct communication between each of the GPGPUs 2506A-D without requiring communication through the host interface bus 2504 to which the processor 2502 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to the P2P GPU link 2516, the host interface bus 2504 remains available for access to system memory or for communication with other instances of the multi-GPU computing system 2500, for example, via one or more network devices. In at least one embodiment, the GPGPUs 2506A-D are connected to the processor 2502 through the host interface switch 2504, and in at least one embodiment, the processor 2502 includes direct support for the P2P GPU link 2516 and can be directly connected to the GPGPUs 2506A-D.

[0308] 26 is a block diagram of a graphics processor 2600 according to at least one embodiment. In at least one embodiment, graphics processor 2600 includes a ring interconnect 2602, a pipeline front end 2604, a media engine 2637, and graphics cores 2680A-2680N. In at least one embodiment, ring interconnect 2602 couples graphics processor 2600 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2600 is one of multiple processors integrated within a multi-core processing system.

[0309] In at least one embodiment, graphics processor 2600 receives batches of commands via ring interconnect 2602. In at least one embodiment, the incoming commands are interpreted by command streamer 2603 of pipeline front end 2604. In at least one embodiment, graphics processor 2600 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2680A-2680N. In at least one embodiment, for 3D geometry processing commands, command streamer 2603 supplies the commands to geometry pipeline 2636. In at least one embodiment, for at least some media processing commands, command streamer 2603 supplies the commands to video front end 2634, which is coupled to media engine 2637. In at least one embodiment, the media engine 2637 includes a Video Quality Engine (VQE) 2630 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 2633 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2636 and the media engine 2637 each spawn execution threads for thread execution resources provided by at least one graphics core 2680A.

[0310] In at least one embodiment, graphics processor 2600 includes scalable thread execution resources characterized by modular cores 2680A-2680N (sometimes referred to as core slices), each having multiple sub-cores 2650A-2650N, 2660A-2660N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2600 can have any number of graphics cores 2680A-2680N. In at least one embodiment, graphics processor 2600 includes graphics core 2680A having at least a first sub-core 2650A and a second sub-core 2660A. In at least one embodiment, graphics processor 2600 is a low-power processor having a single sub-core (e.g., 2650A). In at least one embodiment, graphics processor 2600 includes multiple graphics cores 2680A-2680N, each including a set of first sub-cores 2650A-2650N and a set of second sub-cores 2660A-2660N. In at least one embodiment, each of first sub-cores 2650A-2650N includes at least a first set of execution units 2652A-2652N and media / texture samplers 2654A-2654N. In at least one embodiment, each of second sub-cores 2660A-2660N includes at least a second set of execution units 2662A-2662N and samplers 2664A-2664N. In at least one embodiment, each sub-core 2650A-2650N, 2660A-2660N shares a set of shared resources 2670A-2670N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0311] FIG. 27 is a block diagram illustrating the micro-architecture of a processor 2700 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2700 may execute instructions, including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2700 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2710 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0312] In at least one embodiment, processor 2700 includes an in-order front end (“front end”) 2701 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 2701 may include several units. In at least one embodiment, an instruction prefetcher 2726 fetches instructions from memory and provides the instructions to an instruction decoder 2728, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2728 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”), that the machine can execute. In at least one embodiment, instruction decoder 2728 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2730 may assemble decoded uops into program-order sequences, or traces, in uop queue 2734 for execution. In at least one embodiment, when trace cache 2730 encounters a complex instruction, microcode ROM 2732 provides the uops necessary to complete the operation.

[0313] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2728 may access the microcode ROM 2732 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 2728. In at least one embodiment, if an operation requires a large number of micro-ops to complete, the instruction may be stored in the microcode ROM 2732. In at least one embodiment, the trace cache 2730 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2732, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2732 has finished sequencing micro-ops for an instruction, the machine front end 2701 may resume fetching micro-ops from the trace cache 2730.

[0314] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2703 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. Out-of-order execution engine 2703 includes, without limitation, allocator / register renamer 2740, memory uop queue 2742, integer / floating point uop queue 2744, memory scheduler 2746, fast scheduler 2702, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2704, and simple floating point scheduler ("simple FP scheduler") 2706. In at least one embodiment, fast scheduler 2702, slow / general purpose floating point scheduler 2704, and simple floating point scheduler 2706 are also collectively referred to herein as "uop schedulers 2702, 2704, 2706." In at least one embodiment, allocator / register renamer 2740 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2740 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2740 also allocates each uop's entry to one of two uop queues—memory uop queue 2742 for memory operations and integer / floating point uop queue 2744 for non-memory operations—before memory scheduler 2746 and uop schedulers 2702, 2704, 2706. In at least one embodiment, uop schedulers 2702, 2704, 2706 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 2702 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2704 and simple floating point scheduler 2706 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2702, 2704, 2706 arbitrate for dispatch ports to schedule uops for execution.

[0315] In at least one embodiment, execution block b11 includes, without limitation, integer register file / bypass network 2708, floating point register file / bypass network (“FP register file / bypass network”) 2710, address generation units (“AGUs”) 2712 and 2714, fast arithmetic logic units (ALUs) (“fast ALUs”) 2716 and 2718, slower arithmetic logic unit (“slower ALU”) 2720, floating point ALU (“FP”) 2722, and floating point move unit (“FP move”) 2724. In at least one embodiment, integer register file / bypass network 2708 and floating point register file / bypass network 2710 are also referred to herein as “register files 2708, 2710.” In at least one embodiment, AGUs 2712 and 2714, fast ALUs 2716 and 2718, slow ALU 2720, floating-point ALU 2722, and floating-point move unit 2724 are also referred to herein as "execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724." In at least one embodiment, execution block b11 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0316] In at least one embodiment, register files 2708, 2710 may be located between uop schedulers 2702, 2704, 2706 and execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724. In at least one embodiment, integer register file / bypass network 2708 performs integer operations. In at least one embodiment, floating point register file / bypass network 2710 performs floating point operations. In at least one embodiment, each of register files 2708, 2710 may include, without limitation, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 2708, 2710 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2708 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 2710 may include, without limitation, 128-bit wide entries.

[0317] In at least one embodiment, execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724 may execute instructions. In at least one embodiment, register files 2708 and 2710 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2700 may include any number and combination of execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724, without limitation. In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 may execute floating-point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2722 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2716, 2718. In at least one embodiment, the high-speed ALUs 2716, 2718 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2720 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, with most complex integer operations proceeding to the low-speed ALU 2720. In at least one embodiment, memory load / store operations may be performed by the ALUs 2712, 2714. In at least one embodiment, fast ALU 2716, fast ALU 2718, and slow ALU 2720 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2716, fast ALU 2718, and slow ALU 2720 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 may be implemented to support wide operands having various bit widths.In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0318] In at least one embodiment, the uop schedulers 2702, 2704, 2706 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2700, the processor 2700 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0319] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0320] 28 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808 and may be a single-processor desktop system, a multi-processor workstation system, or a server system having multiple processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0321] In at least one embodiment, system 2800 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2800 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 2800 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0322] In at least one embodiment, the one or more processors 2802 each include one or more processor cores 2807 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a particular instruction set 2809. In at least one embodiment, the instruction set 2809 may facilitate computing via complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW). In at least one embodiment, each of the processor cores 2807 may process a different instruction set 2809, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2807 may also include other processing devices, such as a digital signal processor (DSP).

[0323] In at least one embodiment, processor 2802 includes cache memory 2804. In at least one embodiment, processor 2802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2802. In at least one embodiment, processor 2802 also uses an external cache (e.g., a level 3 (L3) cache or last level cache (LLC)) (not shown), which may be shared among processor cores 2807 using known cache coherence techniques. In at least one embodiment, processor 2802 further includes a register file 2806, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2806 may include general-purpose registers or other registers.

[0324] In at least one embodiment, the one or more processors 2802 are coupled to one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as, in one embodiment, a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2810 is not limited to a DMI bus, but may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between memory devices and other components of the system 2800, while the platform controller hub (PCH) 2830 provides connectivity to I / O devices via a local I / O bus.

[0325] In at least one embodiment, memory device 2820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for serving as process memory. In at least one embodiment, memory device 2820 may operate as system memory for system 2800, storing data 2822 and instructions 2821 for use by one or more processors 2802 when executing applications or processes. In at least one embodiment, memory controller 2816 also couples to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 within processor 2802 to perform graphics and media operations. In at least one embodiment, a display device 2811 may be connected to processor 2802. In at least one embodiment, display device 2811 may include one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). In at least one embodiment, display device 2811 may include a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0326] In at least one embodiment, platform controller hub 2830 allows peripheral devices to connect to memory device 2820 and processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2824 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensor 2825 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 2826 may be a WiFi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2828 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2834 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high-definition audio controller. In at least one embodiment, system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.In at least one embodiment, platform controller hub 2830 can also connect to one or more universal serial bus (USB) controller 2842 connected input devices, such as a keyboard and mouse 2843 combination, a camera 2844, or other USB input devices.

[0327] In at least one embodiment, instances of memory controller 2816 and platform controller hub 2830 may be integrated into a separate external graphics processor, such as external graphics processor 2812. In at least one embodiment, platform controller hub 2830 and / or memory controller 2816 may be external to one or more processors 2802. For example, in at least one embodiment, system 2800 may include external memory controller 2816 and platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with processor 2802.

[0328] In at least one embodiment, the external graphics processor 2812 may be used to perform one or more functions implemented by the software physical layer (PHY) library 116. 【0...

Claims

1. A processor having one or more circuits that group and execute Fifth Generation New Radio (5G-NR) operations in parallel based at least in part on attributes of a common user equipment.

2. 2. The processor of claim 1, wherein causing 5G-NR operations to be performed in parallel includes grouping the one or more operations based at least in part on one or more attributes that cause operations of each group to be performed using the one or more computing resources.

3. 3. The processor of claim 2, wherein the one or more attributes indicate one or more 5G-NR cells.

4. 2. The processor of claim 1, wherein causing 5G-NR operations to be performed in parallel includes receiving one or more parameters indicating the one or more computing resources on which the one or more operations are performed.

5. 2. The processor of claim 1, wherein causing 5G-NR operations to be performed in parallel includes configuring the one or more operations to be performed in parallel based at least on one or more parameters indicative of the one or more computing resources.

6. 2. The processor of claim 1 , wherein the one or more computing resources include one or more kernels that perform the one or more operations, each kernel of the one or more kernels performing one or more groups of the one or more computing operations based at least in part on parameters indicative of one or more attributes of the one or more computing operations.

7. 2. The processor of claim 1 , wherein the one or more circuits cause a software library to receive one or more parameters indicating the one or more computing resources on which the one or more operations are to be executed, and to group the one or more operations to be executed in parallel using the one or more computing resources.

8. 2. The processor of claim 1, wherein the one or more operations include one or more physical layer (PHY) operations from one or more devices associated with one or more cells of a 5G-NR network.

9. The processor of claim 1 , wherein the one or more circuits further cause the 5G-NR operations to be performed in parallel by one or more parallel processing units.

10. A processing method by a processor, comprising grouping and executing fifth generation new radio (5G-NR) operations in parallel based at least in part on attributes of common user equipment.

11. 11. The method of claim 10, further comprising grouping the one or more operations by a 5G-NR physical layer (PHY) library, the 5G-NR PHY library grouping the one or more operations based at least in part on one or more attributes such that each group of operations is performed using the one or more computing resources, wherein the 5G-NR PHY library receives the one or more attributes as a result of one or more function calls to an application programming interface.

12. 11. The method of claim 10, wherein the one or more computing resources include one or more software kernels that perform the one or more operations using one or more parallel processing units.

13. 11. The method of claim 10, wherein a 5G-NR physical layer (PHY) library receives one or more parameters configuring each of the one or more operations as a result of one or more function calls to the 5G-NR PHY library, and stores each of the one or more parameters based at least in part on whether each of the one or more parameters is updated when the one or more operations are performed.

14. 11. The method of claim 10, wherein a 5G-NR physical layer (PHY) library determines which of the one or more computing resources are used to perform the one or more operations in parallel based at least in part on one or more attributes of the one or more operations, the one or more attributes indicating at least a 5G-NR cell.

15. The method of claim 10, wherein the one or more operations correspond to one or more 5G-NR cells, and a 5G-NR physical layer (PHY) library selects the one or more computing resources on which the one or more operations are to be performed based at least in part on the one or more 5G-NR cells.

16. 11. The method of claim 10, further comprising causing a 5G-NR physical layer (PHY) library to receive one or more parameters at least indicative of the one or more computing resources and configure the one or more operations to be performed by the one or more computing resources based at least in part on the one or more parameters.

17. The method of claim 10, wherein the one or more computing resources comprise at least a parallel processing unit of a 5G-NR baseband device that performs the one or more computing operations.

18. A system comprising one or more processors that group Fifth Generation New Radio (5G-NR) operations to be executed in parallel based at least in part on attributes of common user equipment.

19. 20. The system of claim 18, wherein the one or more computing resources comprise at least one parallel processing unit, and the one or more operations are performed in parallel by one or more kernels executed by the at least one parallel processing unit, and the one or more kernels are selected by the software library based at least in part on one or more parameters received by a software library.

20. The system of claim 19, wherein the one or more parameters indicate at least one attribute for each of the one or more operations, the at least one attribute indicating one or more 5G-NR cells that generate information processed by the one or more operations.

21. 20. The system of claim 18, comprising instructions that, when executed by the one or more processors, implement the software library to batch the one or more operations into groups according to one or more parameters received as a result of one or more function calls to a software library, wherein operations of each group are executed in parallel using the one or more computing resources.

22. 20. The system of claim 18, wherein the one or more processors cause the one or more operations to be executed in parallel during one or more execution slots, the one or more execution slots comprising periods during which the one or more computing resources are available to execute the one or more operations.

23. 20. The system of claim 18, further comprising a software library, the software library comprising instructions that, when executed, cause the software library to receive one or more parameters indicating one or more configurations of the one or more operations, and group the one or more operations to be executed in parallel using the one or more computing resources, the software library grouping the one or more operations based at least in part on the one or more configurations, the one or more configurations indicating the one or more computing resources available to perform the one or more operations.

24. 20. The system of claim 18, wherein the one or more computing resources comprise one or more parallel processing units that perform the first group of one or more operations and the second group of one or more operations in parallel.

25. When executed by one or more processors, the one or more processors are caused to at least: A machine-readable medium having stored thereon a set of instructions for grouping and executing Fifth Generation New Radio (5G-NR) operations in parallel based at least in part on a common user equipment attribute.

26. 26. The machine-readable medium of claim 25, further comprising instructions that, when executed by the one or more processors, implement a 5G-NR physical layer (PHY) library that causes the one or more processors to group the one or more operations into one or more groups, each group of the one or more groups being executed by one or more software kernels determined by a software library based at least in part on the one or more computing resources.

27. 26. The machine-readable medium of claim 25, further comprising instructions that, when executed by the one or more processors, implement a 5G-NR physical layer (PHY) library that causes the one or more processors to receive one or more parameters that configure the one or more operations to be executed in parallel, the one or more parameters including information indicative of the one or more computing resources on which the one or more operations are to be executed.

28. 26. The machine-readable medium of claim 25, further comprising instructions that, when executed by the one or more processors, implement the 5G-NR physical layer (PHY) library to cause the one or more processors to group the one or more operations based at least in part on one or more attributes of the one or more operations indicated by one or more parameters provided to a 5G-NR PHY library, the one or more attributes being usable by the 5G-NR PHY library to select the one or more computing resources on which the one or more operations are to be performed.

29. 26. The machine-readable medium of claim 25, wherein the one or more computing resources comprise at least one parallel processing unit, the at least one parallel processing unit comprising one or more execution units that perform one or more groups of the one or more operations in parallel.

30. 26. The machine-readable medium of claim 25, further comprising instructions that, when executed by the one or more processors, cause the one or more processors to group the one or more operations according to one or more parameters received as a result of one or more function calls to an interface provided by a software library, and for each group, perform the one or more operations using one or more kernels, the one or more kernels implementing the software library executed in parallel using the one or more computing resources.

31. 26. The machine-readable medium of claim 25, further comprising instructions that, when executed by the one or more processors, cause the one or more processors to group the one or more operations according to at least one attribute of the one or more operations and perform each group of the one or more operations in parallel using the one or more computing resources, wherein the at least one attribute is indicative of a 5G-NR cell.

32. 26. The machine-readable medium of claim 25, wherein the one or more computing resources comprise at least one parallel processing unit, the at least one parallel processing unit operable to perform the one or more operations in parallel.

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