Printed wiring board and information processing device

Abstract

To provide a printed wiring board capable of achieving a stable operation despite its high speed and large capacity by reducing a crosstalk.SOLUTION: A printed wiring board comprises: an outermost conductive layer including a plurality of conductive pads; a first conductive layer including a first inner layer wiring and laminated on the conductive layer; a second conductive layer including a second inner layer wiring and laminated on the conductive layer and the first conductive layer; a first signal via connecting one of the plurality of conductive pads and the first inner layer wiring; a second signal via connecting the other one of the plurality of conductive pads and the second inner layer wiring; and a stitching via connected to the ground. The first inner layer wiring and the second inner layer wiring constitute a common wiring route laminated and arranged in a connection area arranged with the conductive pad.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a printed wiring board and an information processing device. [Background technology]

[0002] A memory device mounted on an information processing device includes, for example, a plurality of SDRAMs (Synchronous Dynamic Random Access Memories) and a memory controller (controller LSI: Large Scale Integration) that controls writing and reading of the SDRAMs. The plurality of SDRAMs and the memory controller are mounted on a printed wiring board. Address (Add), command (Cmd), and control (Ctrl) signals are transmitted from the memory controller to each SDRAM via a wiring pattern formed on the printed wiring board, called a multi-drop wiring.

[0003] One technology related to such information processing devices is disclosed in the following Patent Document 1. Patent Document 1 states that "the wiring of the address / command system (RTcmd / add) is routed so as to detour toward one of the DDR-SDRAMs 5 and then cross both DDR-SDRAMs 4 and 5, thereby reducing crossings with the wiring of the data system (RTdq / dqs)." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-245393 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in printed wiring boards equipped with memories such as the above-mentioned SDRAM, further increases in speed and capacity are essential to improve the performance of information processing devices, and to achieve this, it is necessary to ensure a greater voltage margin against external noise such as crosstalk.

[0006] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a printed wiring board and an information processing device that are capable of realizing stable operation while being high speed and having a large capacity by reducing crosstalk. [Means for solving the problem]

[0007] In order to solve the above problems, for example, the configurations described in the claims are adopted. The present application includes multiple means for solving the above-mentioned problems. One example is a printed wiring board comprising: an outermost conductive layer having a plurality of conductive pads; a first conductive layer having a first inner layer wiring and laminated on the conductive layer; a second conductive layer having a second inner layer wiring and laminated on the conductive layer and the first conductive layer; a first signal via connecting one of the conductive pads to the first inner layer wiring; a second signal via connecting another of the conductive pads to the second inner layer wiring; and a stitching via connected to ground, wherein the first inner layer wiring and the second inner layer wiring form a common wiring route that is stacked and arranged within a connection area in which the conductive pads are arranged. Effect of the Invention

[0008] According to the present invention, it is possible to provide a printed wiring board and an information processing device that can realize stable operation while being high speed and having a large capacity by reducing crosstalk. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic configuration diagram showing a first example of an information processing device including a printed wiring board to which the present invention is applied; [Diagram 2]FIG. 11 is a schematic configuration diagram showing a second example of an information processing device including a printed wiring board to which the present invention is applied. [Diagram 3] FIG. 1 is a diagram showing a multi-drop wiring topology to which the present invention is applied. [Figure 4] 1 is an exploded perspective view for explaining a layer structure of a printed wiring board to which the present invention is applied; [Diagram 5] 1 is a plan view of an element mounting area of ​​a printed wiring board to which the present invention is applied; [Figure 6] FIG. 1 is a plan view showing a wiring structure of a printed wiring board according to a first embodiment. [Figure 7] 1 is an exploded perspective view of a main part showing a wiring structure of a printed wiring board according to a first embodiment. [Figure 8] FIG. 1 is a diagram (part 1) for explaining crosstalk between vias. [Figure 9] 1 is a diagram for explaining details of a wiring layout in an element mounting area of ​​a printed wiring board to which the present invention is applied. [Figure 10] FIG. 11 is a plan view showing a wiring structure of a printed wiring board according to a modified example of the first embodiment. [Figure 11] 3 is a diagram showing an eye pattern obtained in the printed wiring board of the first embodiment. FIG. [Figure 12] 13 is a diagram showing an eye pattern obtained in a printed wiring board according to a modified example of the first embodiment. FIG. [Figure 13] 13 is a diagram showing an eye pattern obtained when the third layer of the printed wiring board of the first embodiment is used. FIG. [Figure 14] FIG. 11 is a diagram showing an eye pattern obtained when the tenth layer of the printed wiring board of the first embodiment is used. [Figure 15] FIG. 11 is a plan view showing a wiring structure of a printed wiring board according to a second embodiment. [Figure 16] 11 is an exploded perspective view of a main part showing a wiring structure of a printed wiring board according to a second embodiment. [Figure 17] FIG. 2 is a diagram (part 2) for explaining crosstalk between vias. [Figure 18]13 is a diagram showing an eye pattern obtained in a printed wiring board according to a second embodiment. FIG. [Figure 19] FIG. 11 is a diagram (part 1) showing an eye pattern obtained when the third layer and the tenth layer of the printed wiring board of the second embodiment are interchanged. [Figure 20] FIG. 13 is a second diagram showing an eye pattern obtained when the third layer and the tenth layer of the printed wiring board of the second embodiment are interchanged. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings. Note that components common to each embodiment are given the same reference numerals, and some of the overlapping descriptions will be omitted.

[0011] <Overall configuration of information processing device> <First example> Fig. 1 is a schematic diagram showing a first example of an information processing device including a printed wiring board to which the present invention is applied. The information processing device 100 shown in Fig. 1 includes a printed wiring board 101. One memory controller 110 and a plurality of memory elements 111-115 are directly mounted on the printed wiring board 101. Although Fig. 1 shows a state in which the plurality of memory elements 111-115 are mounted only on one main surface side of the printed wiring board 101, the plurality of memory elements may be mounted on both sides of the printed wiring board 101.

[0012] The memory controller 110 and each of the memory elements 111-115 are connected by, for example, a multi-drop wiring 102. Each of the memory elements 111-115 is a DDR SDRAM (Double-Data-Rate SDRAM), and writing and reading of data in each of the memory elements 111-115 is controlled by the memory controller 110. To perform this control, address, command, and control signals are transmitted from the memory controller 110 to each of the memory elements 111-115 via the multi-drop wiring 102.

[0013] <Second example> Fig. 2 is a schematic diagram showing a second example of an information processing device including a printed wiring board to which the present invention is applied. In the information processing device 100' shown in Fig. 2, a connector 103 is attached to a printed wiring board 101. A plurality of memory elements 111-115 mounted on a sub-substrate 106 are connected to the connector 103. The sub-substrate 106 on which the plurality of memory elements 111-115 are mounted in this manner is called a DIMM (Dual Inline Memory Module) card or the like. A memory controller 110 is directly mounted on the printed wiring board 101.

[0014] 2 may also have a plurality of memory elements 111-115 mounted on both sides of a printed wiring board 101 with a sub-substrate 106 interposed therebetween, similar to the information processing device 100 shown in FIG.

[0015] Also in the information processing device 100' shown in FIG. 2, for example, address, command, and control signals are transmitted from the memory controller 110 via the multi-drop wiring 102, branched at the sub-board 106, and then to each of the memory elements 111-115.

[0016] <Outline of the printed wiring board structure> Fig. 3 is a diagram showing a multi-drop wiring topology to which the present invention is applied. Note that multi-drop wiring 102 of this example may be applied to either the case in which memory elements 111-115 are directly mounted on printed wiring board 101 as shown in Fig. 1, or the case in which memory elements 111-115 are mounted on printed wiring board 101 via connector 103 and sub-board 106 as shown in Fig. 2.

[0017] As shown in FIG. 3, the multi-drop wiring 102 is connected to the memory controller 110 at the starting end (one end) side, and to the termination resistor 116 (omitted in FIG. 1 and FIG. 2) at the end (other end). Then, the memory elements 111-115 are connected to the intermediate portion between them as signal receiving elements. Such a multi-drop wiring 102 has the memory controller 110, the memory elements 111-115, and the lead-in wiring SL0-SL6 connected to the lead-in wiring SL0-SL6, and the signal transmission vias V0-V6 connected to the lead-in wiring SL0-SL6, and the signal lines TL0-TL5 connecting between the signal transmission vias V0-V6. Note that, although only one set of wiring is shown as the multi-drop wiring topology in the drawing, the multi-drop wiring 102 is provided corresponding to each signal line such as an address, command, and control signal.

[0018] 4 is an exploded perspective view for explaining the layer structure of a printed wiring board to which the present invention is applied. Printed wiring board 101 on which multi-drop wiring 102 is provided has a plurality of conductive layers L1-Ln. Each of the conductive layers L1-Ln is a layer formed on the front and back surfaces of each insulating substrate, not shown here. The outermost conductive layer L1 on one main surface side of printed wiring board 101 has outer layer wiring 10 including lead-in wiring SL0-SL6.

[0019] In addition, the conductive layers L2 to Ln-1 in the middle of the printed wiring board 101 and the outermost conductive layer Ln on the other main surface side are provided with inner layer wiring 20 including signal lines TL0 to TL5, or with a solid conductive film 30.

[0020] The solid conductive film 30 is used as, for example, a power source or a ground, and may be patterned to have a certain area. The solid conductive film 30 is preferably arranged to sandwich one or two conductive layers including the inner layer wiring 20. When the solid conductive film 30 is arranged to sandwich two conductive layers including the inner layer wiring 20, it is preferable that the two conductive layers are arranged with a large gap between them and are arranged close to each solid conductive film 30. This makes it possible to prevent crosstalk between the inner layer wirings 20 arranged on different conductive layers. When multiple memory elements are mounted on both sides of the printed wiring board 101, the outermost conductive layer Ln on the other main surface side becomes a layer having the outer layer wiring 10 including the lead-in wiring.

[0021] This printed wiring board 101 also includes signal transmission vias V1-V6 for mutually connecting the outer layer wiring 10 and the inner layer wiring 20. Each solid conductive film 30 has an opening 30a that is slightly larger than the signal transmission vias V1-V6 in order to ensure insulation from the signal transmission vias V1-V6.

[0022] Fig. 5 is a plan view of an element mounting area of ​​a printed wiring board to which the present invention is applied, and is a plan view of element mounting area 101a for mounting one of elements such as memory controller 110 and memory elements 111-115 shown in Figs. 1-4. As shown in Fig. 5, a plurality of conductive pads 40 are arranged in element mounting area 101a of the printed wiring board. Each conductive pad 40 is a pad for connecting an element to printed wiring board 101.

[0023] Here, the memory controller 110 and memory elements 111-115 shown in Figs. 1-4 are assumed to have a ball grid array (BGA) type package structure. In this case, each element has bonding balls arranged in a matrix on the bottom surface. If each of these elements is an SDRAM, the bonding balls are arranged according to the pitch arrangement defined by the JEDEC Standard, for example, 0.8 mm pitch arrangement for DDR4. In this case, the conductive pads 40 provided on each element mounting area 101a of the printed wiring board are arranged in a matrix corresponding to the arrangement of the bonding balls, and are arranged, for example, at the same arrangement pitch P1 in the row and column direction. The arrangement pitch P1 is, for example, 0.8 mm.

[0024] In the illustrated example, two locations within the element mounting area 101a serve as connection areas 101b in which the conductive pads 40 are arranged.

[0025] Furthermore, the element mounting area 101a is provided with a plurality of signal vias 50 and stitching vias 60. Each signal via 50 corresponds to, for example, one of the signal transmission vias V0 to V6 shown in Figures 3 and 4. As an example, when the element mounting area 101a is an area where the memory element 111 shown in Figures 3 and 4 is mounted, each signal via 50 is the signal transmission via V1 shown in Figures 3 and 4. Furthermore, the stitching via 60 is a via for ensuring a return path for the adjacent signal via 50, and is a ground via connected to the ground (or power supply).

[0026] The signal vias 50 and the stitching vias 60 are either through vias that penetrate the printed wiring board 101 or vias that penetrate only some layers of the printed wiring board 101. Such signal vias 50 and stitching vias 60 are not limited to through vias formed by a drilling method, and may be any of various general and inexpensive via structures represented by a laser method, a B2IT method, and a pad-on-via formed by filling a through via, or may be other via structures.

[0027] These signal vias 50 and stitching vias 60 are arranged inside and outside the connection area 101b, and in the connection area 101b in which the conductive pads 40 are arranged, they are arranged between the arrays of the conductive pads 40. The signal vias 50 and stitching vias 60 may be arranged in a matrix shape as shown in the figure between the arrays of the conductive pads 40, or may be arranged only in necessary portions of the matrix. The layout of the wiring including the signal vias 50 and stitching vias 60 in the connection area 101b will be described in detail in each of the following embodiments.

[0028] In addition, in addition to the conductive pads 40, signal vias 50, and stitching vias 60 described above, any of the lead-in wirings SL0 to SL5 shown in Figures 3 and 2 are provided in the element mounting area 101a on the outermost layer of the printed wiring board, but the lead-in wirings SL0 to SL5 are not shown in Figure 5.

[0029] Below, an embodiment of the wiring structure of a printed wiring board will be described, which includes outer layer wiring 10 constituting lead-in wiring SL0 to SL5, inner layer wiring 20 constituting signal lines TL0 to TL5, signal vias 50 corresponding to signal transmission vias V1 to V6, and stitching vias 60.

[0030] First Embodiment Fig. 6 is a plan view showing the wiring structure of the printed wiring board of the first embodiment, and corresponds to an enlarged view of a part of the connection area 101b in which the conductive pads 40 are arranged, as described with reference to Fig. 5. Fig. 7 is an exploded perspective view of a main part showing the wiring structure of the printed wiring board of the first embodiment, and is an exploded perspective view of the printed wiring board of a part corresponding to Fig. 6.

[0031] 6 and 7 also show the wiring provided on each layer of the printed wiring board. The wiring is outer layer wiring 10 formed on the outermost layer of the printed wiring board, and inner layer wiring 20 formed on an intermediate layer of the printed wiring board. Hereinafter, the wiring structure of the printed wiring board of the first embodiment will be described based on these Figs. 6 and 7 and with reference to Figs. 3 and 4 above. In Figs. 6 and 7, the reference numerals of components that are the same as those shown in Figs. 3 and 4 are shown in parentheses.

[0032] <Outline of wiring route> First, an overview of the wiring path arranged in the connection area 101b of the printed wiring board will be described. Here, two of the multiple conductive pads 40 provided on the outermost conductive layer L1 of the multiple conductive layers are treated as a pair of a first pad 41 and a second pad 42, and a set of wiring connected to them is treated as a pair wiring, and the path will be described. For this reason, other wiring paths are omitted from FIG. 7.

[0033] The first pad 41 and the second pad 42 are respectively connected to a first signal via 51 and a second signal via 52 by the outer layer wiring 10. The first pad 41 is connected to the first signal via 51 arranged adjacent to the first pad 41 via the outer layer wiring 10. The second pad 42 is connected to the second signal via 52 arranged adjacent to the second pad 42 via the outer layer wiring 10. Here, "adjacently arranged" refers to a state in which the pads are arranged closest to each other, and the same applies hereinafter.

[0034] The outer layer wiring 10 can be shortened by connecting the first pad 41 and the second pad 42 to the adjacent first signal via 51 and second signal via 52, respectively, through the outer layer wiring 10. In addition, it is preferable that the first signal via 51 and the second signal via 52 are disposed adjacent to each other.

[0035] Each of the outer layer wirings 10 constitutes one of the lead-in wirings SL0 to SL5 (see FIGS. 3 and 4). As an example, each of the outer layer wirings 10 constitutes the lead-in wiring SL1. In this case, the first signal via 51 and the second signal via 52 connected to each of the outer layer wirings 10 (the lead-in wiring SL1) each become a signal transmission via V1 (see FIGS. 3 and 4).

[0036] The inner layer wiring 20 is a first inner layer wiring 21 connected to the first signal via 51 and a second inner layer wiring 22 connected to the second signal via 52, which constitute a pair of wirings. The first inner layer wiring 21 and the second inner layer wiring 22 are arranged in different conductive layers. Here, the first inner layer wiring 21 is wired in the m1 conductive layer Lm1 (first conductive layer), and the second inner layer wiring 22 is wired in the m2 conductive layer Lm2 (second conductive layer), and each is wired in a different conductive layer. One side of such first inner layer wiring 21 connected to the first signal via 51 (V1) corresponds to the signal line TL0 shown in FIG. 3 and FIG. 4, and the other side corresponds to the signal line TL1 shown in FIG. 3 and FIG. 4. Similarly, one side of the second inner layer wiring 22 connected to the first signal via 51 (V1) corresponds to the signal line TL0 shown in Figures 3 and 4, and the other side corresponds to the signal line TL1 shown in Figures 3 and 4.

[0037] [Common Wiring Route] Here, the above-mentioned set of pair wirings is assumed to be wired with a common wiring route [R] arranged in a stacked manner in a planar view. That is, the first inner layer wiring 21 and the second inner layer wiring 22 constituting the set of pair wirings are wired on both sides of the first signal via 51 and the second signal via 52 to which they are connected, on the common wiring route [R] arranged in a stacked manner in a planar view. It is preferable that such a common wiring route [R] is configured by drawing out the first inner layer wiring 21 and the second inner layer wiring 22 from the first signal via 51 and the second signal via 52 and stacking them at positions overlapping with the adjacent pads 40a adjacent to the first signal via 51 and the second signal via 52, respectively.

[0038] In the illustrated example, in the pair wiring of the first inner layer wiring 21 and the second inner layer wiring 22, the signal line TL0 provided on the m1 conductive layer Lm1 and the m2 conductive layer Lm2 is arranged to overlap, and the signal line TL1 provided on the m1 conductive layer Lm1 and the m2 conductive layer Lm2 is arranged to overlap, and each of them constitutes a common wiring route [R]. In FIG. 6, for the sake of explanation, the first inner layer wiring 21 and the second inner layer wiring 22 are shown in shifted positions in each common wiring route [R]. However, the first inner layer wiring 21 and the second inner layer wiring 22 may completely coincide in plan view in each common wiring route [R], or may be shifted as shown. In each common wiring route [R], the first inner layer wiring 21 and the second inner layer wiring 22 may be arranged with an overlap to the extent that insulation between the first inner layer wiring 21 and the second inner layer wiring 22 and other signal vias 50 and stitching vias 60 can be ensured.

[0039] The common wiring route [R] as described above is provided in the connection area 101b where more stitching vias 60 are required due to the dense arrangement of the signal vias 50. The common wiring route [R] may be extended outside the connection area 101b, but is provided at least in the connection area 101b. Each common wiring route [R] is preferably laid starting from an adjacent pad 40a adjacent to each of the first signal via 51 and the second signal via 52, and is laid at least until it reaches the edge of the connection area 101b. In addition, if the common wiring route [R] is a route laid between the array of conductive pads 40, the first inner layer wiring 21 and the second inner layer wiring 22 merge with the common wiring route [R] at a position where they overlap the adjacent pad 40a that is arranged closest to the conductive pad 40.

[0040] The wiring structure having the above-mentioned common wiring route [R] may be provided in at least one element mounting area 101a among the areas mounting the memory controller 110 and the memory elements 111-115 shown in Figures 3 and 4. However, a significant effect is achieved by providing at least one element mounting area 101a among the areas mounting the memory elements 111-115, which are signal receiving elements.

[0041] Furthermore, the wiring structure having a common wiring route [R] may be applied to all signal lines of a multi-drop wiring routed to one element mounting area 101a, or may be applied only to any signal lines that require improvement in waveform quality.

[0042] Here, in general, in a printed wiring board using through vias, it is preferable to arrange a signal line in a conductive layer with a short via stub, that is, in a conductive layer far from the outermost conductive layer L1 (see FIG. 7), for a single signal. However, in a parallel bus composed of multiple single-ended signals, such as DDR, where crosstalk between vias becomes apparent, if a conductive layer far from the outermost conductive layer L1 is used, the via length to the outermost conductive layer L1 becomes long, and the influence of crosstalk becomes large. Therefore, from the viewpoint of suppressing crosstalk between vias, it is preferable to select a layer close to the outermost conductive layer L1 (see FIG. 7) for the m1 conductive layer Lm1 and the m2 conductive layer Lm2, and shorten the effective via length of the first signal via 51 and the second signal via 52, because this improves the waveform quality. In addition, in the case of pair wiring, the first signal line 21 arranged on the m1 conductive layer Lm1 close to the outermost conductive layer L1 (see FIG. 7) has better waveform quality than the second signal line 22.

[0043] [Placement of stitching via 60] Next, the arrangement of stitching vias 60 in a printed wiring board having the above-mentioned common wiring route [R] will be described. The stitching vias 60 are arranged at a position where there are no outer layer wirings 10, inner layer wirings 20, or signal vias 50. In addition, it is preferable that the stitching vias 60 are arranged as close as possible to each signal via 50, and as an example, it is preferable that the stitching vias 60 are arranged at a distance of about 1 mm from each signal via 50. Furthermore, it is preferable that a plurality of stitching vias 60 are arranged at the above-mentioned distance from each signal via 50.

[0044] 8 is a diagram (part 1) for explaining crosstalk between vias, and is a diagram for explaining formula (1) expressing the mutual inductance [Lm] that causes crosstalk. In formula (1) expressing the mutual inductance [Lm], the distance between the aggressor via 50a and the stitching via 60 is d1, the distance between the aggressor via 50a and the victim via 50b is d2, the distance between the stitching via 60 and the victim via 50b is d3, the height of these vias is h, the magnetic permeability is μ, and the radius of the stitching via 60 is R.

[0045] As shown in this figure, in a configuration in which a stitching via 60 is arranged between an aggressor via 50a and a victim via 50b, which are assumed to be signal vias, it is assumed that a current flows from the inner layer wiring 20 to the aggressor via 50a in the direction of the arrow in the figure. In this case, a fringe electric field F5 is formed around the aggressor via 50a. In addition, a return current flows in the opposite direction to the aggressor via 50a in the stitching via 60 arranged close to the aggressor via 50a, and as a result, a fringe electric field F6 in the opposite direction is formed around the stitching via 60.

[0046] 8, it can be seen that the mutual inductance [Lm] that causes crosstalk can be reduced by reducing the distance between the aggressor via 50a and the victim via 50b and the stitching via 60. In addition, it can be seen that the more stitching vias 60 there are, the less return current flows through each stitching via 60, and therefore the crosstalk to the victim via 50b is reduced.

[0047] [Wire layout details] Fig. 9 is a diagram for explaining details of the wiring layout in the element mounting area of ​​a printed wiring board to which the present invention is applied, and corresponds to an enlarged view of the main part of Fig. 6. As shown in Fig. 9, the element mounting area has a connection area 101b in which conductive pads 40 are arranged in a matrix. In this connection area 101b, the arrangement pitch P1 of the conductive pads 40 and the arrangement pitch P2 of the signal vias 50 and stitching vias 60 are approximately equal.

[0048] This is because, as described above with reference to FIG. 5, elements such as a memory controller mounted on a printed wiring board are BGA type, and bonding balls are arranged at equal intervals in a matrix on the bottom surface of each element. In this case, among the conductive pads 40 arranged in a matrix according to the arrangement of the bonding balls, either the signal via 50 or the stitching via 60 is arranged at the center of four conductive pads 40 arranged at the vertices of a rectangle. With this layout, when the conductive pads 40 are arranged in a matrix at high density in the connection area 101b of the element on which the bonding pads are densely mounted, the signal via 50 can be arranged while ensuring insulation from the conductive pads 40. In addition, the stitching via 60 can be arranged at a close distance of the arrangement pitch P2 (≈P1) from the signal via 50. It is preferable that the signal via 50 is arranged at a necessary position among the centers of the four conductive pads 40 arranged at the vertices of the rectangle, and the stitching via 60 is arranged at more of the other positions.

[0049] Moreover, the distance d11 between the center of the signal via 50 and the position Ps1 where the inner layer wiring 20 deviates from the common wiring route [R] is approximately equal to √2×P1×(1 / 2) (formula (2)). In other words, this is equivalent to the position Ps1 where the inner layer wiring 20 merges from the signal via 50 into the common wiring route [R] being directly below the conductive pad 40. Note that the position Ps1 where the inner layer wiring 20 merges into the common wiring route [R] is also the position where the inner layer wiring 20 deviates from the common wiring route [R] and starts changing the route.

[0050] Furthermore, the arrangement pitch P2 of the signal vias 50 and the stitching vias 60 may be such that one inner layer wiring 20 can be laid between the signal vias 50 and the stitching vias 60. In other words, the arrangement pitch P2 of the signal vias 50 and the stitching vias 60 may be narrow enough that only one inner layer wiring can be laid between the signal vias 50 and the stitching vias 60.

[0051] Specifically, the condition is considered in which the line width W1 of the inner layer wiring 20 and the clearance diameter C1 of the signal via 50 and stitching via 60 are such that only one inner layer wiring 20 can be laid between the signal via 50 and the stitching via 60. The clearance diameter C1 is the diameter of the signal via 50 and the stitching via 60 including the gap (clearance) for ensuring insulation against the inner layer wiring 20. This clearance diameter C1 is approximately equal to the diameter of the opening 30a in each solid conductive film 30 (see FIG. 4).

[0052] In this case, the width required for arranging two inner layer wirings 20 in parallel is 3×W1, assuming that the gap (spacing) required between the inner layer wirings 20 is approximately the same as the line width W1. Therefore, the condition under which only one inner layer wiring can be laid between the signal via 50 and the stitching via 60 is when formula (3) in the figure is satisfied. In the connection area 101b, the signal via 50 and the stitching via 60 are arranged under such conditions. This is preferable because the inner layer wiring 20 constituting the common wiring route [R] is arranged at a position overlapping each solid conductive film 30 (see FIG. 4).

[0053] <Advantages of the First Embodiment> [Common wiring route [R]] The printed wiring board of the first embodiment described above has a common wiring route [R] in which the inner layer wirings 20 connected to the two conductive pads 40 via the signal vias 50 are laminated in different conductive layers. With this configuration, the planar layout area of ​​the inner layer wirings 20 arranged on a plurality of conductive layers is made compact, improving the degree of freedom in arranging the stitching vias 60, and it is possible to arrange the stitching vias 60 in close proximity to a greater number of signal vias 50. This makes it possible to reduce crosstalk between the signal vias 50 in the printed wiring board, and to stabilize the operation of the information processing device by providing resistance to various variables while achieving higher speed and larger capacity.

[0054] In addition, by laminating the first inner layer wiring 21 and the second inner layer wiring 22 of different layers in a common wiring route [R], two inner layer wirings can be arranged between adjacent signal vias 50 at an arrangement pitch P2, making it possible to wire to two conductive pads 40. This makes it possible to mount an element with bonding pads mounted at a high density.

[0055] Furthermore, since the layout of the first inner layer wiring 21 and the second inner layer wiring 22 can be made common in the common wiring route [R], it is possible to reduce the labor required for design work.

[0056] [Position of inner layer wiring 20] In particular, the common wiring route [R] of the first embodiment has a configuration in which the first inner layer wiring 21 and the second inner layer wiring 22 connected to the first signal via 51 and the second signal via 52 are pulled out to positions overlapping with the adjacent pads 40a adjacent to the first signal via 51 and the second signal via 52, respectively, and laminated. This allows the first inner layer wiring 21 and the second inner layer wiring 22 to be laid out by effectively utilizing the placement portion of the conductive pad 40 where the stitching via 60 cannot be placed, thereby further increasing the degree of freedom in the placement of the stitching via 60. As a result, as shown below, it is possible to achieve even higher speed and larger capacity while still stabilizing the operation.

[0057] 10 is a plan view showing the wiring structure of a printed wiring board according to a modified example of the first embodiment, in which the first inner layer wiring 21 constituting the common wiring route [R] is not drawn out to a position overlapping with the adjacent pad 40a adjacent to the first signal via 51. In such a configuration, a large number of unplaceable portions 60' are generated where stitching vias 60 cannot be placed, whereas in the configuration of the first embodiment, the occurrence of unplaceable portions 60' is suppressed.

[0058] Fig. 11 is a diagram showing an eye pattern obtained with the printed wiring board of the first embodiment. Fig. 12 is a diagram showing an eye pattern obtained with a printed wiring board of a modified example of the first embodiment, the printed wiring board having the configuration shown in Fig. 10. Here, the eye pattern is a display in which a large number of signal waveform transitions are sampled and superimposed. In Figs. 11 and 12, the received waveform appearing at the signal transmission via V1 is shown as an eye pattern. The wider the line in the eye pattern (the wider the so-called eye mask [E]), the better the quality of the waveform.

[0059] In the eye pattern obtained by the configuration of the first embodiment of FIG. 11, the eye mask [E] is open compared to the eye pattern of FIG. 12. That is, in the eye pattern of FIG. 12, the intrusion of the ringback [A] due to crosstalk into the digital threshold is seen. In contrast, in the eye pattern of FIG. 11, the ringback [A] is suppressed to be small, and the eye mask [E] is in a state of being widely open. Comparing the voltage margin of the eye mask [E] in FIG. 11 and FIG. 12, it is 52 [mV] in FIG. 11 and -5 [mV] in FIG. 12. This shows that the voltage margin of the eye mask [E] can be secured by applying the first embodiment, and the waveform quality is good. Therefore, it can be seen that the configuration of the first embodiment makes it possible to arrange the stitching via 60 close to the signal via 50, thereby reducing crosstalk and improving the waveform quality.

[0060] [Laying layer of inner layer wiring 20] In addition, in the printed wiring board having the common wiring route [R] of the first embodiment, the first inner layer wiring 21 and the second inner layer wiring 22 constituting the common wiring route [R] are conductive layers close to the outermost conductive layer L1 (see FIG. 7) on which elements are mounted. This makes it possible to shorten the effective via lengths of the first signal via 51 and the second signal via 52, thereby improving the waveform quality.

[0061] FIG. 13 is a diagram showing an eye pattern obtained when the third layer of the printed wiring board of the first embodiment is used, and the received waveform appearing at the first signal via 51 shown in FIG. 7 is shown as an eye pattern (signal A). FIG. 14 is a diagram showing an eye pattern obtained when the tenth layer of the printed wiring board of the first embodiment is used, and the received waveform appearing at the second signal via 52 shown in FIG. 7 is shown as an eye pattern (signal B). Comparing the eye patterns of FIG. 13 and FIG. 14, it can be seen that the signal A in FIG. 13, which has a short via length from the inner layer wiring 20 to the outermost conductive layer L1 on which elements are mounted, has a larger voltage margin of the eye mask [E] and better waveform quality than the signal B in FIG. 14, which has a long via length. Therefore, by arranging the first inner layer wiring 21 and the second inner layer wiring 22 constituting the common wiring route [R] in a conductive layer close to the outermost conductive layer L1 (see FIG. 7) on which elements are mounted, it is possible to suppress crosstalk to the surrounding signal vias 50 when multiple signals change simultaneously.

[0062] The above-mentioned effects realize stable operation of elements that are resistant to variables such as fluctuations in the power supply voltage of computers that control various equipment, changes in ambient temperature, and manufacturing variations in the elements to be mounted. Furthermore, the configurations of the first embodiment and the modified examples can be realized by the commonly used VIA method, and do not increase the difficulty of manufacturing printed wiring boards.

[0063] The above-mentioned first embodiment and modified example are not limited to application to a printed wiring board with a multi-drop wiring structure. However, the multi-drop wiring applied to the signal lines of the address, command, and control signals among the signals constituting the DDR involves multiple branches and loads, and is therefore prone to waveform distortion due to unnecessary reflection. In addition, the wiring length is longer than that of the data wiring, and crosstalk noise (Far-end crosstalk: FEXT) superimposed from nearby signals becomes apparent. Therefore, when variable factors such as power supply voltage fluctuation, temperature change, and manufacturing variations of elements are added, it becomes impossible to receive digital signals normally. Therefore, the configuration of the first embodiment and modified example can obtain a remarkable effect when applied to a multi-drop wiring. In addition, although the above-mentioned first embodiment and modified example use an SDRAM as a signal receiving device, the signal receiving device may be another device.

[0064] Furthermore, in the above-mentioned first embodiment and modified example, a configuration has been described in which the signal vias 50 are arranged between the array of conductive pads 40. However, the present invention can also be applied to a configuration in which the signal vias 50 are arranged at positions where they overlap the conductive pads 40. In this case, for example, referring to FIG. 9, the outer layer wiring 10 (lead-in wiring SL1) is not necessary, and a common wiring route [R] is laid between the stacked layers of the signal vias 50 and the conductive pads 40, and the stitching via 60 is arranged at a position where it does not overlap these.

[0065] Second Embodiment Fig. 15 is a plan view showing the wiring structure of the printed wiring board of the second embodiment, and corresponds to an enlarged view of a part of the connection area 101b in which the conductive pads 40 are arranged, as described with reference to Fig. 5. Fig. 16 is an exploded perspective view of a main part showing the wiring structure of the printed wiring board of the second embodiment, and is an exploded perspective view of the printed wiring board of a part corresponding to Fig. 15.

[0066] 15 and 16 also show the wiring provided on each layer of the printed wiring board. The wiring is outer layer wiring 10 formed on the outermost conductive layer of the printed wiring board, and inner layer wiring 20 formed on an intermediate layer of the printed wiring board. Hereinafter, the wiring structure of the printed wiring board of the second embodiment will be described based on these Figs. 15 and 16 and with reference to Figs. 3 and 4. In Figs. 15 and 16, the reference numerals of components that are the same as those shown in Figs. 3 and 4 are shown in parentheses.

[0067] <Outline of wiring route> The wiring path of the printed wiring board of the second embodiment shown in Figures 15 and 16 differs from the wiring path of the printed wiring board of the first embodiment described with reference to Figures 6 and 7 in that the pair of wirings constituting the common wiring route [R] are layer-swapped via a signal via 50, but the other configurations are similar. Here, layer-swapping refers to switching of the conductive layers on which wiring is performed midway. In the following, two of the multiple conductive pads 40 provided on the outermost conductive layer L1 are treated as a pair of a first pad 41 and a second pad 42, and a set of wirings connected to these are treated as a pair of wirings, and the path is described.

[0068] The first pad 41 and the second pad 42 are respectively connected to a first signal via 51 and a second signal via 52 by an outer layer wiring 10. The first pad 41 is connected to the first signal via 51 arranged adjacent to the first pad 41 via the outer layer wiring 10. The second pad 42 is connected to the second signal via 52 arranged adjacent to the second pad 42 via the outer layer wiring 10. The above points are the same as in the first embodiment.

[0069] Of these, the outer layer wirings 10 constitute any of the lead-in wirings SL0 to SL5 (see FIGS. 3 and 4). Here, as an example, each outer layer wiring 10 constitutes the lead-in wiring SL1. In this case, the first signal via 51 and the second signal via 52 connected to each outer layer wiring 10 become signal transmission vias V1 (see FIGS. 3 and 4) connected to the lead-in wiring SL1, respectively. This is also the same as in the first embodiment.

[0070] The inner layer wiring 20 has, for example, a first inner layer wiring 21 wired in the m1-th conductive layer Lm1 and a second inner layer wiring 22 wired in the m2-th conductive layer Lm2. The first inner layer wiring 21 and the second inner layer wiring 22 are connected to a first signal via 51 connected to the first pad 41. The first inner layer wiring 21 and the second inner layer wiring 22 are also connected to a second signal via 52 connected to the second pad 42. In this respect, the configuration is different from that of the first embodiment.

[0071] In this case, the first inner layer wiring 21 connected to the first signal via 51 corresponds to the signal line TL0 shown in Figures 3 and 4, and the second inner layer wiring 22 connected to the first signal via 51 corresponds to the signal line TL1 shown in Figures 3 and 4. Moreover, the first inner layer wiring 21 connected to the second signal via 52 corresponds to the signal line TL1 shown in Figures 3 and 4, and the second inner layer wiring 22 connected to the second signal via 52 corresponds to the signal line TL0 shown in Figures 3 and 4.

[0072] [Common Wiring Route] Here, one pair of wirings connected to the above-mentioned first pad 41 and second pad 42 is wired with a common wiring route [R] arranged in a stacked manner in a plan view. The common wiring route [R] has the same configuration as that described in the first embodiment.

[0073] In this common wiring route [R], the pair wiring is wired by layer-swapping via the signal via 50, and the conductive layers are switched. That is, the signal lines TL0 and TL1 connected to the first signal via 51 are layer-switched from the first inner layer wiring 21 to the second inner layer wiring 22 at the first signal via 51. And the signal lines TL0 and TL1 connected to the second signal via 52 are layer-switched from the second inner layer wiring 22 to the first inner layer wiring 21 at the second signal via 52. In these two common wiring routes [R], the signal lines TL0 and TL1 connected to the first signal via 51 and the signal lines TL0 and TL1 connected to the second signal via 52 are layer-swapped. In addition, due to this layer swap, the first signal via 51 and the second signal via 52 are sections in which the current directions are opposite to each other.

[0074] It is preferable that the layer exchange structure described above is implemented between adjacent signal vias 50. The layer exchange structure may be applied to all signal lines of the multi-drop wiring wired to one element mounting area 101a, or may be applied only to any signal lines that require improvement in waveform quality. Furthermore, the layer exchange structure described above may be applied to all signal lines connected to the signal transmission vias V0 to V6 shown in Figures 3 and 4, or may be applied only to signal lines connected to any signal vias whose waveform quality is desired to be improved.

[0075] <Effects of the second embodiment> The printed wiring board of the second embodiment described above has a configuration in which the first inner layer wiring 21 and the second inner layer wiring 22 connected to the first signal via 51 and the second signal via 52 in the configuration of the first embodiment are layer-swapped at the first signal via 51 and the second signal via 52. This makes it possible for the printed wiring board of the second embodiment to more effectively reduce crosstalk between the signal vias 50 compared to the printed wiring board of the first embodiment.

[0076] Fig. 17 is a diagram (part 2) for explaining crosstalk between vias. Fig. 17 shows a configuration in which a stitching via 60 is disposed adjacent to a first signal via 51 and a second signal via 52 that exchange layers of a pair of wiring. As shown in this figure, when a signal is transmitted through a pair of wiring consisting of a first inner layer wiring 21 and a second inner layer wiring 22, the first signal via 51 and the second signal via 52 become aggressor vias, and a current flows in the opposite direction through these first signal via 51 and second signal via 52 as shown by the arrows in the figure.

[0077] Then, opposite fringe electric fields F51 and F52 are formed around the first signal via 51 and the second signal via 52 through which current flows. Also, a return current flows in the opposite direction to the first signal via 51 in the stitching via 61 arranged adjacent to the first signal via 51, and as a result, a fringe electric field F61 opposite to the fringe electric field F51 is formed around the stitching via 61. Similarly, a return current flows in the opposite direction to the second signal via 52 in the stitching via 62 arranged adjacent to the second signal via 52, and as a result, a fringe electric field F62 opposite to the fringe charge F52 is formed around the stitching via 62.

[0078] In this way, the fringe magnetic fields of the pair of the first signal via 51 and the second signal via 52 and the stitching vias 61 and 62 arranged adjacent thereto are oriented in directions that cancel each other out, thereby reducing the effect of crosstalk on the surrounding signal vias 50. This makes it possible to more effectively suppress crosstalk on the surrounding signal vias 50 when multiple signals change simultaneously.

[0079] Fig. 18 is a diagram showing an eye pattern obtained in the printed wiring board of the second embodiment. The printed wiring board from which this eye pattern was obtained has a configuration (Fig. 16) in which the signal line TL1 connected to the first signal via 51 and the signal line TL1 connected to the second signal via 52 are layer-swapped in the configuration (see Fig. 7) from which the eye pattern in Fig. 11 was obtained.

[0080] Comparing Fig. 18 with Fig. 11, the voltage margin from the threshold in the eye mask [E] is 52 [mV] in Fig. 11, whereas it is 83 [mV] in Fig. 18, so the voltage margin is increased. This shows that by applying the second embodiment to the common wiring route [R] described in the first embodiment and exchanging layers, crosstalk is further suppressed, the above-mentioned ringback is alleviated, and the waveform quality is improved.

[0081] Fig. 19 is a diagram (part 1) showing an eye pattern obtained when the third layer and the tenth layer of the printed wiring board of the second embodiment are swapped, and the received waveform appearing at the first signal via 51 shown in Fig. 16 is shown as an eye pattern (signal A). Fig. 20 is a diagram (part 2) showing an eye pattern obtained when the third layer and the tenth layer of the printed wiring board of the second embodiment are swapped, and the received waveform appearing at the second signal via 52 shown in Fig. 16 is shown as an eye pattern (signal B). In this case, the m1 conductive layer Lm1 in Fig. 16 is the third layer of the conductive layers, and the m2 conductive layer Lm2 is the tenth layer of the conductive layers.

[0082] 19 and 20 are compared with the eye patterns obtained in the printed wiring boards of Figures 13 and 14 where layer swapping has not been performed, it can be seen that the difference in voltage margin between signals A and B is smaller in the eye patterns of Figures 19 and 20. This shows that by swapping layers of the inner layer wiring 20 that shares the common wiring route [R] at adjacent signal vias 50, it is possible to reduce the difference in waveform quality between signals A and B that have the same threshold.

[0083] The present invention is not limited to the above-described embodiments and modifications, and further includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. [Explanation of symbols]

[0084] 10…Outer layer wiring 21…First inner layer wiring 22…Second inner layer wiring 40...Conductive pad 40a...adjacent pad (closest conductive pad) 41 First pad (conductive pad) 42 2nd pad (conductive pad) 51…First signal via 52…2nd signal via 60,61,62…Stitching vias 100, 100'...Information processing device 101...Printed wiring board 101b…Connection area 110...Memory controller (element) 111...Memory element (element) L1: Outermost conductive layer Lm1: m1 conductive layer Lm2…m2th conductive layer P1: Arrangement pitch (conductive pads 40) [R]…Common wiring route TL0~TL5…Signal line

Claims

1. an outermost conductive layer having a plurality of conductive pads; a first conductive layer having a first inner layer wiring and laminated on the conductive layer; a second conductive layer having a second inner layer wiring and laminated on the conductive layer and the first conductive layer; a conductive film disposed between the first conductive layer and the second conductive layer; a first signal via connecting one of the conductive pads to the first inner layer wiring; a second signal via connecting another one of the conductive pads and the second inner layer wiring; and a ground-connected stitching via; the first inner layer wiring and the second inner layer wiring form a common wiring route that is laminated and arranged via the conductive film in a connection area in which the conductive pads are arranged, the conductive pads are arranged in a matrix at a predetermined pitch in the connection area; The distance between the first signal via and the second signal via is approximately equal to the predetermined arrangement pitch. Printed wiring board.

2. The stitching vias are arranged at intervals substantially equal to the predetermined arrangement pitch with respect to at least one of the first signal vias and the second signal vias. The printed wiring board according to claim 1 .

3. the first signal via, the second signal via and the stitching via are disposed between the array of the plurality of conductive pads; each of the first signal via and the second signal via is connected to one of the plurality of conductive pads by an outer layer wiring provided on the outermost conductive layer; The first inner layer wiring and the second inner layer wiring join the common wiring route at a position where they overlap with the conductive pad that is disposed closest among the conductive pads. The printed wiring board according to claim 1 .

4. The common wiring route is laid so as to pass through a position overlapping with the conductive pad. The printed wiring board according to claim 3 .

5. the first signal via is connected only to the first inner layer wiring; The second signal via is connected only to the second inner layer wiring. The printed wiring board according to any one of claims 1 to 4.

6. the first signal via is connected to a signal line formed by the first inner layer wiring and the second inner layer wiring; the second signal via is connected to a signal line formed by the second inner layer wiring and the first inner layer wiring, The two signal lines are wired in such a manner that they are interchanged between the first conductive layer and the second conductive layer in the first signal via and the second signal via. The printed wiring board according to any one of claims 1 to 4.

7. an outermost conductive layer having a plurality of conductive pads; a first conductive layer having a first inner layer wiring and laminated on the conductive layer; a second conductive layer having a second inner layer wiring and laminated on the conductive layer and the first conductive layer; a conductive film disposed between the first conductive layer and the second conductive layer; a first signal via connecting one of the conductive pads to the first inner layer wiring; a second signal via connecting another one of the conductive pads and the second inner layer wiring; and a ground-connected stitching via; the first inner layer wiring and the second inner layer wiring form a common wiring route that is laminated and arranged via the conductive film in a connection area in which the conductive pads are arranged, the first signal via is connected to a signal line formed by the first inner layer wiring and the second inner layer wiring; the second signal via is connected to a signal line formed by the second inner layer wiring and the first inner layer wiring, The two signal lines are wired in such a manner that they are interchanged between the first conductive layer and the second conductive layer in the first signal via and the second signal via. Printed wiring board.

8. An information processing device including a printed wiring board and an element mounted on the printed wiring board, The printed wiring board comprises: an outermost conductive layer having a plurality of conductive pads connected to said element; a first conductive layer having a first inner layer wiring and laminated on the conductive layer; a second conductive layer having a second inner layer wiring and laminated on the conductive layer and the first conductive layer; a conductive film disposed between the first conductive layer and the second conductive layer; a first signal via connecting one of the conductive pads to the first inner layer wiring; a second signal via connecting another one of the conductive pads and the second inner layer wiring; and a ground-connected stitching via; the first inner layer wiring and the second inner layer wiring form a common wiring route that is laminated and arranged via the conductive film in a connection area in which the conductive pads are arranged, the conductive pads are arranged in a matrix at a predetermined pitch in the connection area; The distance between the first signal via and the second signal via is approximately equal to the predetermined arrangement pitch. Information processing device.

9. An information processing device including a printed wiring board and an element mounted on the printed wiring board, The printed wiring board comprises: an outermost conductive layer having a plurality of conductive pads connected to said element; a first conductive layer having a first inner layer wiring and laminated on the conductive layer; a second conductive layer having a second inner layer wiring and laminated on the conductive layer and the first conductive layer; a conductive film disposed between the first conductive layer and the second conductive layer; a first signal via connecting one of the conductive pads to the first inner layer wiring; a second signal via connecting another one of the conductive pads and the second inner layer wiring; and a ground-connected stitching via; the first inner layer wiring and the second inner layer wiring form a common wiring route that is laminated and arranged via the conductive film in a connection area in which the conductive pads are arranged, the first signal via is connected to a signal line formed by the first inner layer wiring and the second inner layer wiring; the second signal via is connected to a signal line formed by the second inner layer wiring and the first inner layer wiring, The two signal lines are wired in such a manner that they are interchanged between the first conductive layer and the second conductive layer in the first signal via and the second signal via. Information processing device.

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