Semiconductor Device

Abstract

A semiconductor device (1) comprises: a semiconductor layer (40); a first vertical MOS transistor (10) and a second vertical MOS transistor (20) that are formed in the semiconductor layer (40); a metal layer (30) that is in contact with and connected to the entire back side surface of the semiconductor layer (40); and a support (42) that is bonded to the back side of the metal layer (30) with an adhesive (41) therebetween. In a plan view, the support (42) has a larger area than the semiconductor layer (40) and encompasses the semiconductor layer (40); the thickness of the support (42) is greater than the thickness of the semiconductor layer (40); the height of the adhesive (41) along a side surface of the semiconductor layer (40) is less than that of a top surface of the semiconductor layer (40) in a cross-sectional view of the semiconductor device (1), the cross-sectional view including the center of the semiconductor layer (40) and the outer circumference of the semiconductor layer (40) in a plan view; and in the cross-sectional view, a semiconductor chip (2), which is the portion of the semiconductor device (1) excluding the support (42) and the adhesive (41), has a curved shape that is convex in the direction toward the support (42).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device Regarding do. [Background technology]

[0002] In order to protect lithium-ion batteries from overcharging and / or over-discharging, a dual-configuration vertical MOS transistor capable of controlling bidirectional conduction with a single chip is used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 4,616,413 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to reduce the on-resistance of a dual-configuration vertical MOS transistor, it is preferable that the dual-configuration vertical MOS transistor (hereinafter, the dual-configuration vertical MOS transistor is also referred to as a "semiconductor chip") has a large area in a plan view and a thin semiconductor substrate. However, such a structure increases the warping of the semiconductor chip and reduces its strength. Patent Document 1 discloses a structure in which a printed circuit board is attached to a rigid metal plate via a conductive adhesive.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device including a dual-configuration vertical MOS transistor that can minimize the area of ​​a rigid metal plate in a planar view in a structure in which a rigid metal plate is attached via a conductive adhesive. [Means for solving the problem]

[0006] To solve the above problems, face-down mounting is possible. HalfA semiconductor device comprising: a semiconductor substrate; a low-concentration impurity layer formed on a front surface side of the semiconductor substrate; and a semiconductor layer formed by combining the semiconductor substrate and the low-concentration impurity layer, the semiconductor substrate and the low-concentration impurity layer being a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a metal layer in contact with the entire rear surface side of the semiconductor substrate; and a support body bonded to the rear surface side of the metal layer via an adhesive, the support body having an area larger than that of the semiconductor layer in the plan view and containing the semiconductor layer, the support body having a thickness larger than that of the semiconductor layer, and including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, the height of the adhesive along a side surface of the semiconductor layer being less than a top surface of the semiconductor layer in a cross-sectional view of the semiconductor device, and the semiconductor chip excluding the support body and the adhesive being viewed in the cross-sectional view, the semiconductor chip has a curved shape that is convex in a direction approaching the support body.

[0007] According to the above configuration, in a dual-configuration vertical MOS transistor, it is possible to reduce the on-resistance, reduce the warpage of the semiconductor chip, and improve the strength of the semiconductor chip. Effect of the Invention

[0008] An object of the present disclosure is to provide a semiconductor device including a dual-configuration vertical MOS transistor, which reduces the on-resistance of the semiconductor chip, reduces warpage of the semiconductor chip, and improves the strength of the semiconductor chip. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 2A] FIG. 2A is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 2B]FIG. 2B is a schematic cross-sectional view showing a main current flowing through the semiconductor device according to the first embodiment. [Figure 3A] FIG. 3A is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a schematic perspective view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 4A] FIG. 4A is a flow diagram showing a part of the manufacturing process of the semiconductor device according to the first embodiment. [Figure 4B] FIG. 4B is a cross-sectional view illustrating a step of face-down mounting the semiconductor device according to embodiment 1. As shown in FIG. [Figure 5A] FIG. 5A is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 5B] FIG. 5B is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 5C] FIG. 5C is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 6A] FIG. 6A is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to Comparative Example 1 of the first embodiment. [Figure 6B] FIG. 6B is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to Comparative Example 1 of the first embodiment. [Figure 7] FIG. 7 is a graph showing the relationship between the amount of warpage of the semiconductor chip according to the first embodiment and the length of the base of the fillet of the conductive adhesive. [Figure 8A] FIG. 8A is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to Comparative Example 2 of Embodiment 1. FIG. [Figure 8B] FIG. 8B is a cross-sectional SEM image showing an example of the structure of a semiconductor device according to Comparative Example 2 of Embodiment 1. [Figure 9] FIG. 9 is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 10A] FIG. 10A is a schematic cross-sectional view showing an example of the structure of a semiconductor device of Modification 1 according to Embodiment 1. FIG. [Figure 10B]FIG. 10B is a schematic cross-sectional view showing an example of the structure of the semiconductor device of Modification 2 according to Embodiment 1. As shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a flow diagram showing a part of the manufacturing process of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a specific example of a semiconductor device according to one aspect of the present disclosure will be described with reference to the drawings. Each embodiment shown here shows one specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily an exact drawing. In each figure, the same reference numerals are given to substantially the same configurations, and duplicated explanations are omitted or simplified.

[0011] (Embodiment 1) [1. Structure of semiconductor device] FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device. FIG. 2A is a plan view thereof, and the size and shape of the semiconductor device are examples except that the semiconductor device is rectangular (square or oblong). The size, shape and arrangement of the pads are also examples. FIG. 2B is a cross-sectional view showing a schematic view of a main current flowing through the semiconductor device. FIGS. 1 and 2B are cut surfaces taken along II in FIG. 2A.

[0012] 1 and 2B, the semiconductor device 1 has a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0013] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40, and is made of silicon of the first conductivity type containing impurities of the first conductivity type. The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40, and is formed in contact with the semiconductor substrate 32, and is of the first conductivity type, containing impurities of the first conductivity type at a concentration lower than the concentration of the impurities of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0014] As shown in Figures 1 and 2A, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 in the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 in the semiconductor layer 40.

[0015] Here, as shown in Fig. 2A, the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40, and are one side and the other side that divide the semiconductor layer 40 in half in terms of area. In Fig. 2A, a virtual boundary line 90 between the first region A1 and the second region A2 is shown by a dashed line (for ease of understanding, the dashed line showing the boundary line 90 is shown extended to the outside of the semiconductor layer 40 and the semiconductor device 1). In Fig. 2A, the dashed line showing the first region A1 and the second region A2 does not strictly coincide with the semiconductor layer 40 and the boundary line 90 for ease of understanding, and is shown inside with a slight margin, but the outer periphery of the first region A1 and the outer periphery of the second region A2 substantially coincide with the outer periphery of the semiconductor layer 40 and the boundary line 90.

[0016] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40 (semiconductor substrate 32) and is made of, for example, silver (Ag) or copper (Cu). The metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material. The metal layer 30 is formed on the entire back surface of the semiconductor layer 40 (semiconductor substrate 32), and the thickness of the metal layer 30 is desirably 10 μm or more.

[0017] The support 42 is formed in indirect contact with the rear surface side of the metal layer 30 via an adhesive 41. The support 42 is typically at least twice as thick as the semiconductor layer 40, and is, for example, a flat metal plate with a uniform thickness of 200 [μm] within its surface. Hereinafter, the support 42 may also be referred to as a thick-film metal plate 42. It is desirable for the thick-film metal plate 42 to have a conductivity similar to that of the metal layer 30, and for example, a conductivity of 30×10 at 20° C. 6 [S / m] or more, and is typically made of a metal material mainly made of copper (Cu). The adhesive 41 is conductive, and is typically a silver paste, and hereinafter, the adhesive 41 may be referred to as a conductive adhesive 41.

[0018] As shown in FIG. 1, in this disclosure, a structure obtained by removing the support 42 and the adhesive 41 from the semiconductor device 1 is referred to as a semiconductor chip 2. As shown in FIG. 1, the semiconductor chip 2 has a curved shape that is convex toward the support 42. The curved shape is, for example, a shape caused by warping. The amount of warping of the semiconductor chip 2 is the difference between the highest position and the lowest position in the Z direction on the upper or lower surface of the semiconductor layer 40 or the lower surface of the metal layer 30 when the semiconductor chip 2 is viewed in cross section. When the warping generated in the semiconductor chip 2 is a warp that is convex toward the support 42, the highest position is the outer periphery of the semiconductor layer 40 in a plan view, particularly the corners, and the lowest position is the center of the semiconductor layer 40 in a plan view.

[0019] The center of the semiconductor layer 40 in a plan view refers to the intersection of diagonals of the semiconductor layer 40 in a plan view. In addition, the cross-sectional view of the semiconductor device 1 in this disclosure refers to the cross-section of the semiconductor device 1 viewed from a plane that includes both the center of the semiconductor layer 40 in the semiconductor chip 2 in a plan view and the outer periphery of the semiconductor layer 40 in the semiconductor chip 2 in a plan view. In this case, the outer periphery of the semiconductor layer 40 may be any position on the outer periphery of the semiconductor layer 40.

[0020] 1 and 2A, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in a first region A1 of the semiconductor layer 40 (low-concentration impurity layer 33). A first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed in the first body region 18.

[0021] The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 formed to a depth from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a part of the low-concentration impurity layer 33, and the first gate conductor 15 is formed inside the first gate trench 17 and on the first gate insulating film 16. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the first gate pad 119.

[0022] The first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13. The portion 12 of the first source electrode 11 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

[0023] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0024] The thickness of the first source electrode 11 including the portions 12 and 13 is, for example, not less than 2 μm and not more than 8 μm.

[0025] A second body region 28 containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28.

[0026] The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 formed to a depth from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a part of the low-concentration impurity layer 33, and the second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the second gate pad 129.

[0027] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23. The portion 22 of the second source electrode 21 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, as a non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 22 may be plated with gold or the like.

[0028] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0029] The thickness of the second source electrode 21 including the portions 22 and 23 is, for example, not less than 2 μm and not more than 8 μm.

[0030] With the above-described configuration of transistor 10 and transistor 20, semiconductor substrate 32 functions as a common drain region in which the first drain region of transistor 10 and the second drain region of transistor 20 are common to each other. A part of the low-concentration impurity layer 33 on the side in contact with semiconductor substrate 32 may also function as the common drain region. Note that low-concentration impurity layer 33 is also a drift layer common to transistor 10 and transistor 20, and may be referred to as drift layer 33 in this specification.

[0031] Furthermore, metal layer 30 functions as a common drain electrode that commonizes the drain electrode of transistor 10 and the drain electrode of transistor 20. When adhesive 41 is a silver paste and support 42 is a thick-film metal plate, not only metal layer 30 but also conductive adhesive 41 and thick-film metal plate 42 function as a common drain electrode.

[0032] As shown in FIG. 1, the first body region 18 and the first source region 14 is covered with an interlayer insulating layer 34 having an opening, and through the opening of the interlayer insulating layer 34, a first body region 18 and The first source electrode 11 is connected to a portion 13 of the first source electrode 11 which is connected to the first source region 14. The interlayer insulating layer 34 and the first source electrode 11 The portion 13 is covered with a passivation layer 35 having an opening through which the first source electrode 11 It is connected to part 12 which is connected to part 13 of the

[0033] Second Body Region 28 and the second source region 24 is covered with an interlayer insulating layer 34 having an opening, and through the opening of the interlayer insulating layer 34, a second body region 28; and The second source electrode 21 is connected to a portion 23 of the second source electrode 21 which is connected to the second source region 24. 21 The portion 23 is covered with a passivation layer 35 having an opening through which the second source electrode 24 is inserted. 21 It is connected to part 22 which is connected to part 23 of the

[0034] Therefore, the multiple first source pads 111 and the multiple second source pads 121 respectively refer to regions where the first source electrodes 11 and the second source electrodes 21 are partially exposed on the surface of the semiconductor device 1, that is, portions of so-called terminals. Similarly, the one or more first gate pads 119 and the one or more second gate pads 129 respectively refer to regions where the first gate electrode 19 (not shown in FIGS. 1, 2A, and 2B) and the second gate electrode 29 (not shown in FIGS. 1, 2A, and 2B) are partially exposed on the surface of the semiconductor device 1, that is, portions of so-called terminals.

[0035] In the present disclosure, in plan view, the first region A1 includes only components constituting the first vertical MOS transistor 10, and the second region A2 includes only components constituting the second vertical MOS transistor 20. The boundary line 90 may be considered as an imaginary line that traces the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Although it has a finite width, it may also be considered as the interval itself (even in the case of the interval, it can be recognized as a line with the naked eye or when viewed at low magnification).

[0036] In the semiconductor device 1, for example, the first conductivity type may be N type and the second conductivity type may be P type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being N-type semiconductors, and the first body region 18 and the second body region 28 being P-type semiconductors.

[0037] In addition, in the semiconductor device 1, for example, the first conductivity type may be P type and the second conductivity type may be N type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being P-type semiconductors, and the first body region 18 and the second body region 28 being N-type semiconductors.

[0038] [2. Operation of dual-configuration vertical MOS transistor] In the following description, the conductive operation of the semiconductor device 1 will be described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors, in which the first conductivity type is N-type and the second conductivity type is P-type.

[0039] 3A and 3B are respectively a plan view and a perspective view of an approximate unit configuration of a transistor 10 (or a transistor 20) repeatedly formed in the X direction and the Y direction of the semiconductor device 1. For ease of understanding, the semiconductor substrate 32, the metal layer 30, the conductive adhesive 41, the thick-film metal plate 42, the passivation layer 35, the first source electrode 11 (or the second source electrode 21), and the interlayer insulating layer 34 are not shown in FIG.

[0040] The structure of the transistor 10 is similar to that of the transistor 20. Therefore, in the following, the reference numeral of the transistor 10 will be used to describe the approximate unit configuration.

[0041] The Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and is the direction in which the semiconductor device extends. 1 In this disclosure, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0042] 3A and 3B, the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and contains the same second conductivity type impurity as the first body region 18. The first source region 14 and the first connection portion 18a are alternately and periodically arranged in the Y direction. The same applies to the transistor 20.

[0043] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage equal to or higher than a threshold value is applied to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as a reference, a conductive channel is formed in the second body region 28 near the second gate insulating film 26. As a result, a main current flows through the path of the first source electrode 11-the first connection portion 18a-the first body region 18-the low-concentration impurity layer 33-the semiconductor substrate 32-the metal layer 30-the conductive adhesive 41-the thick film metal plate 42-the conductive adhesive 41-the metal layer 30-the semiconductor substrate 32-the low-concentration impurity layer 33-the conductive channel formed in the second body region 28-the second source region 24-the second source electrode 21, and the semiconductor device 1 becomes conductive. In this conductive path, a PN junction is present at the contact surface between the second body region 28 and the low-concentration impurity layer 33, and functions as a body diode.

[0044] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage equal to or higher than the threshold value is applied to the first gate electrode 19 (first gate conductor 15) with the first source electrode 11 as a reference, a conductive channel is formed in the first body region 18 near the first gate insulating film 16. As a result, a main current flows through the path of the second source electrode 21-the second connection portion 28a-the second body region 28-the low-concentration impurity layer 33-the semiconductor substrate 32-the metal layer 30-the conductive adhesive 41-the thick film metal plate 42-the conductive adhesive 41-the metal layer 30-the semiconductor substrate 32-the low-concentration impurity layer 33-the conductive channel formed in the first body region 18-the first source region 14-the first source electrode 11, and the semiconductor device 1 becomes conductive. In this conductive path, a PN junction is present at the contact surface between the first body region 18 and the low-concentration impurity layer 33, and functions as a body diode.

[0045] 2B shows a schematic diagram of the bidirectional flow of the main current with arrows. The flow of the main current in the horizontal direction (X direction) occurs in each of the layers of the metal layer 30, the conductive adhesive 41, the thick-film metal plate 42, and the semiconductor substrate 32. Since the resistivity of the metal layer 30 and the thick-film metal plate 42 is lower than that of the other layers, by making the metal layer 30 or the thick-film metal plate 42 thicker, the cross-sectional area of ​​the main current path is enlarged, and the on-resistance of the semiconductor device 1 can be reduced.

[0046] [3. Manufacturing method of semiconductor device] A method for manufacturing the semiconductor device 1 will now be described.

[0047] 4A is a simplified diagram showing part of the manufacturing process of the semiconductor device 1 in the present embodiment 1. The structure of each dual-configuration vertical MOS transistor, which will be separated later, is formed in a grid shape on a silicon wafer by step 501.

[0048] Next, in step 502, the back side of the silicon wafer (corresponding to the semiconductor substrate 32 in terms of each dual-configuration vertical MOS transistor to be individually separated later) is thinned. In the thinning process in step 502, it is preferable to control the thickness of the semiconductor layer 40 to be 15 μm or more and 100 μm or less, and more preferably, to be 15 μm or more and 75 μm or less.

[0049] Next, in step 503, a metal layer 30 is formed on the entire surface of the thinned back side of the silicon wafer. The metal layer 30 may be a multi-layer structure including, for example, multiple metal layers, but it is preferable that the surface that contacts and connects with the conductive adhesive 41 in the next step 504 is mainly made of silver (Ag) or copper (Cu). The multiple metal layers may be formed individually by any method such as vapor deposition, sputtering, or plating. In the metal layer formation in step 503, the thickness of the metal layer 30 is preferably 10 μm or more.

[0050] Next, in step 504, the silicon wafer is diced using a blade to separate each dual-configuration vertical MOS transistor. Since the thick-film metal plate 42 is not yet bonded to each of the separated dual-configuration vertical MOS transistors, each of the separated dual-configuration vertical MOS transistors is in a state that can be called the semiconductor chip 2 described above.

[0051] In step 504, the metal layer 30 formed on the back side of the silicon wafer in step 503 is also cut together with the silicon wafer, but the metal layer 30 that is physically pushed out by the blade extends along the side of the semiconductor chip 2. As a result, a protrusion (so-called burr) that extends toward the lower back side of the semiconductor chip 2 (in the -Z direction) is formed on the outer periphery of the metal layer 30 of the individual semiconductor chip 2.

[0052] Note that dicing with a blade is just one example, and the dual-configuration vertical MOS transistors may be divided into individual pieces by a method other than blade dicing, such as dicing with a laser, although protrusions are difficult to form when dicing with a laser.

[0053] Next, in step 505, a thick-film metal plate 42 to which a conductive adhesive 41 such as silver paste has been applied in advance is prepared, and the back side of the metal layer 30 of the semiconductor chip 2 is bonded to the thick-film metal plate 42. The amount of pressure applied is set to, for example, 5 μm to 10 μm, and the thickness of the conductive adhesive 41 after hardening and bonding is calculated to be a target value (for example, 20 μm to 60 μm), and the conductive adhesive 41 is applied to the surface of the thick film metal plate 42.

[0054] The conductive adhesive 41 is an adhesive for bonding the back surface side of the metal layer 30 to the thick film metal plate 42. When viewed after the conductive adhesive 41 has hardened and the thick film metal plate 42 has been bonded, it is desirable that the entire back surface side of the metal layer 30 is evenly covered with the conductive adhesive 41.

[0055] The thick-film metal plate 42 is selected to have an area larger than that of the semiconductor substrate 32 in a plan view, and during bonding, the plates are aligned so that a margin of approximately equal width is provided from the outer periphery of the metal layer 30 to the outer periphery of the closest thick-film metal plate 42 in a plan view. As an example, as shown in Fig. 2A, the thick-film metal plate 42 has a similar shape to the semiconductor layer 40. The semiconductor layer 40 and the thick-film metal plate 42 having similar shapes means that the semiconductor layer 40 and the thick-film metal plate 42 have the same shape in a plan view and differ only in area.

[0056] Furthermore, if the thick metal plate 42 is a so-called flat plate, which has a uniform thickness macroscopically and has no steps or uneven shapes, it is convenient for bonding the semiconductor layer 40. In the present embodiment 1, the thick metal plate 42 will be described as being a flat plate.

[0057] During bonding, it is common to place the semiconductor chip 2, which has a relatively small area, on the thick film metal plate 42, which has a relatively large area, as the receiving side. The conductive adhesive 41 may protrude from the back surface of the metal layer 30 in a plan view. The amount of protruding conductive adhesive 41 may or may not be uniform along the outer periphery of the semiconductor layer 40 in a plan view. FIG. 2A shows, as an example, a case in which the protruding conductive adhesive 41 is uniform. Alternatively, the protruding conductive adhesive 41 may partially creep up along the side surface of the semiconductor chip 2 as shown in FIG. 1, forming a roughly triangular fillet.

[0058] In step 505, in order to harden the conductive adhesive 41 such as silver paste, the thick film metal plate 42 is heat-treated at a high temperature while the semiconductor chip 2 is attached. The heat treatment temperature is preferably 200°C or less, for example, 170°C. The conductive adhesive 41 hardens at around 170°C, and the metal layer 30 and the thick film metal plate 42 are bonded to form the semiconductor device 1.

[0059] In addition Thick film metal plate 42During the heat treatment in which the temperature is raised to 170°C, the semiconductor chip 2 warps. As described above, the thickness of the semiconductor layer 40 is preferably 15 μm or more and 75 μm or less, and the thickness of the first source electrode 11 and the second source electrode 21 is preferably 2 μm or more and 8 μm or less. The thickness of the metal layer 30 is preferably 10 μm or more, and in this thickness configuration, the semiconductor chip 2 at 170°C warps in a convex manner in the direction approaching the thick metal plate 42 (the -Z direction in the cross-sectional view of FIG. 1).

[0060] FIG. 4B is a schematic diagram showing the semiconductor device 1 when it is mounted face-down.

[0061] [4. Discussion] Hereinafter, the effects achieved by the semiconductor device 1 in the first embodiment will be described.

[0062] In a dual-configuration vertical MOS transistor, in order to reduce the on-resistance during conduction, it is required to make the semiconductor substrate 32 (semiconductor layer 40) thin and the metal layer 30 thick. A semiconductor chip 2 configured in this way is prone to warping that convexly forms in the -Z direction at high temperatures. The thinner the semiconductor layer 40 and the thicker the metal layer 30, the greater the warping that occurs at high temperatures.

[0063] In particular, when a dual-configuration vertical MOS transistor with low on-resistance is required, it is effective to increase the area in a plan view of the semiconductor chip 2 in order to increase the total gate width of the channel. However, if the area is large, the warping of the semiconductor chip 2 increases significantly.

[0064] When mounting the semiconductor chip 2 face-down on the mounting board, a reflow process must be performed using a solder joint material at a high temperature of approximately 240°C. It is known that if the amount of warping of the semiconductor chip 2 at 240°C exceeds 40μm, mounting problems are likely to occur regardless of the direction of the warping, so it is necessary to keep the amount of warping of the semiconductor chip 2 below 40μm.

[0065] In the semiconductor device 1 according to the first embodiment, the semiconductor chip 2 is bonded to the thick film metal plate 42 at about 170°C, which is lower than 240°C, so the amount of warping of the semiconductor chip 2 can be fixed at the same level as that which occurs at about 170°C. If a material that does not remelt, such as silver paste, is selected as the conductive adhesive 41, the warping of the semiconductor chip 2 already bonded to the thick film metal plate 42 will not increase during the reflow process (240°C) when mounting the semiconductor device 1 face-down on the mounting board, as shown in Fig. 4B.

[0066] Therefore, the configuration of the semiconductor device 1 according to the first embodiment is particularly effective for a semiconductor chip 2 having a structure in which the amount of warping is large, that is, a semiconductor chip 2 in which the thickness of the semiconductor layer 40 is thin, the area of ​​the semiconductor chip 2 in a plan view is large, and further the thickness of the metal layer 30 is thick. Furthermore, if the thick-film metal plate 42 is sufficiently thick, the thick-film metal plate 42 serves as a support for the semiconductor chip 2, and therefore the reduction in strength of the semiconductor chip 2 caused by making the semiconductor layer 40 thin can be compensated for.

[0067] However, in the semiconductor device 1 according to the first embodiment, when the semiconductor chip 2 is bonded to the thick-film metal plate 42 via the conductive adhesive 41, the conductive adhesive 41 protruding from the semiconductor chip 2 partially creeps up onto the side surface of the semiconductor chip 2, forming a fillet that is roughly triangular in cross section, as shown typically in Fig. 1. Therefore, if the area of ​​the thick-film metal plate 42 is not sufficiently larger than the area of ​​the semiconductor layer 40 in plan view, there is a concern that the protruding conductive adhesive 41 will not be contained within the thick-film metal plate 42.

[0068] Furthermore, when viewed in cross-section, if the protruding conductive adhesive 41 creeps up to the top surface of the semiconductor chip 2, there is a possibility that the semiconductor device 1 may short-circuit. Therefore, the height to which the conductive adhesive 41 creeps up from the surface of the thick metal plate 42 along the side of the semiconductor chip 2 (the height of the fillet of the conductive adhesive 41) must be less than the top surface of the semiconductor layer 40.

[0069] Therefore, in the semiconductor device 1 of this embodiment 1, (1) the area of ​​the thick film metal plate 42 in a planar view must be prepared taking into account the fact that the conductive adhesive 41 will protrude by the length of the bottom side of the fillet of the conductive adhesive 41, and (2) the thickness of the semiconductor chip 2 must be adjusted taking into account the fact that the conductive adhesive 41 will creep up by the height of the fillet of the conductive adhesive 41.

[0070] The semiconductor device 1 of this embodiment 1 controls the curvature of the semiconductor chip 2, thereby determining the appropriate size of the thick film metal plate 42 in a planar view for the above-mentioned (1), and preventing a short circuit of the semiconductor chip 2 caused by the protrusion (fillet) of the conductive adhesive 41 for the above-mentioned (2).

[0071] First, we will explain the above point (1).

[0072] As described above, in the semiconductor device 1 according to the first embodiment, the thick metal plate 42 needs to be large enough to contain, in a plan view, the semiconductor chip 2 and the conductive adhesive 41 protruding from the semiconductor chip 2. Therefore, by bonding the semiconductor chip 2 to the thick metal plate 42, the area of ​​the semiconductor device 1 is inevitably larger than the area of ​​the semiconductor chip 2 in a plan view.

[0073] In order to keep the area of ​​the semiconductor device 1 as small as possible from the area of ​​the semiconductor chip 2 when viewed in a plan view, it is necessary to make the area of ​​the thick film metal plate 42 as small as possible, and to achieve this, it is important to reduce the length by which the conductive adhesive 41 protrudes.

[0074] Therefore, in the semiconductor device 1 of this embodiment 1, the thickness of the metal layer 30 is set to be 10 μm or more, and the warp of the semiconductor chip 2 at 170° C. is controlled to be convex in the direction approaching the support 42 (-Z direction).

[0075] 1, when the back surface of the metal layer 30 warps so as to be convex in the direction approaching the thick film metal plate 42 (-Z direction), the outer periphery of the semiconductor chip 2 is curved in the direction relatively away from the support 42 (+Z direction) due to the warping. When the semiconductor chip 2 has such a curved shape, the pressure of the conductive adhesive 41 on the outer periphery of the semiconductor chip 2 is reduced, and the effect of suppressing the length by which the conductive adhesive 41 protrudes from the semiconductor chip 2 can be enjoyed.

[0076] Therefore, in a cross-sectional view of the semiconductor device 1, when the semiconductor chip 2 of the semiconductor device 1 is viewed excluding the thick film metal plate 42 and the conductive adhesive 41, it is desirable that the semiconductor chip 2 has a curved shape that is convex in the direction approaching the thick film metal plate 42. In other words, it is desirable that the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the outer periphery of the semiconductor layer 40 in a plan view is thicker than the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the center of the semiconductor layer 40 in a plan view.

[0077] 5A, 5B, and 5C show cross-sectional SEM images of the semiconductor device 1 according to the first embodiment mounted face-down on a mounting board. FIG. 5B is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in FIG. 5A, and FIG. 5C is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in FIG. 5B. In the semiconductor device 1 shown in FIG. 5A, FIG. 5B, and FIG. 5C, the thickness of the semiconductor layer 40 is 53 [μm], the thickness of the first source electrode 11 and the second source electrode 21 is 4 [μm], the thickness of the metal layer 30 is 10 [μm], and the thickness of the thick film metal plate 42 is 200 [μm].

[0078] 5B and 5C show the interface position between the semiconductor layer 40 and the metal layer 30 at the center of the semiconductor layer 40 in a plan view, extended to the outer periphery of the semiconductor layer 40 in a plan view. Also, horizontal line B in Fig. 5C shows the interface position between the semiconductor layer 40 and the metal layer 30 at the outer periphery of the semiconductor layer 40 in a plan view.

[0079] 5C, horizontal line A is closer to thick-film metal plate 42 (in the -Z direction) than horizontal line B, and the distance in the Z direction between horizontal line A and horizontal line B is 10 μm. Therefore, semiconductor chip 2 has a warped shape that is convex in the direction approaching thick-film metal plate 42 (in the -Z direction), and the amount of warping is 10 μm.

[0080] As shown in FIG. 5C, when the amount of warping of the semiconductor chip 2 is 10 μm, the protruding length of the conductive adhesive 41 (the length of the bottom side of the fillet of the conductive adhesive 41) is 128 μm, and the thick film metal plate 42 must have a margin of at least 128 μm from the outer periphery of the semiconductor chip 2.

[0081] Here, Fig. 6A and Fig. 6B show cross-sectional SEM images of Comparative Example 1 according to the present embodiment 1. Fig. 6B is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in Fig. 6A. In the semiconductor device 1 shown in Fig. 6A and Fig. 6B, the thickness of the semiconductor layer 40 is 53 [μm], the thickness of the first source electrode 11 and the second source electrode 21 is 4 [μm], the thickness of the metal layer 30 is 3 [μm], and the thickness of the thick film metal plate 42 is 200 [μm]. In this thickness configuration, the semiconductor chip 2 has a warped shape with a convex shape in the direction away from the thick film metal plate 42 (+Z direction), and the amount of warping is 2 [μm].

[0082] As shown in Figure 6B, when the semiconductor chip 2 warps by 2 [μm] in the +Z direction, the length that the conductive adhesive 41 protrudes (the length of the base of the fillet of the conductive adhesive 41) is 150 [μm], which is longer than the length of the base of the fillet of the conductive adhesive 41, 128 [μm], formed when the semiconductor chip 2 warps by 10 [μm] in the -Z direction in the semiconductor device 1 of this embodiment 1.

[0083] That is, by warping the semiconductor chip 2 so as to be convex in the -Z direction, the pressure applied by the conductive adhesive 41 on the outer periphery of the semiconductor chip 2 is reduced, and the length of the conductive adhesive 41 protruding from the semiconductor chip 2 in plan view is reduced. Therefore, for the purpose of specifying an appropriate size of the thick film metal plate 42, the inventors have investigated the relationship between the amount of warping of the semiconductor chip 2 and the protruding length of the conductive adhesive 41 (the length of the base of the fillet of the conductive adhesive 41) in the semiconductor device 1 according to the first embodiment.

[0084] 7 shows a graph showing the relationship between the length of the base of the fillet of the conductive adhesive 41 and the amount of warping of the semiconductor chip 2. The horizontal axis is the amount of warping w [μm] of the semiconductor chip 2, and the vertical axis is the length b [μm] of the base of the fillet formed by the protruding conductive adhesive 41. The thickness of the semiconductor layer 40 is set to 53 [μm], and semiconductor chips 2 with different amounts of warping are produced by adjusting the thickness of the metal layer 30, and the length of the base of the fillet of the conductive adhesive 41 for each amount of warping is plotted.

[0085] The circle plot shows the relationship between the length b of the bottom of the fillet of the conductive adhesive 41 and the amount of warping w of the semiconductor chip 2 when the pressing amount of the conductive adhesive 41 is 5 μm, where b and w have a relationship of b=-0.75×w+135.3. The square plot shows the relationship between the length b of the bottom of the fillet of the conductive adhesive 41 and the amount of warping w of the semiconductor chip 2 when the pressing amount of the conductive adhesive 41 is 10 μm, where b and w have a relationship of b=-1.5×w+270.6.

[0086] The amount of pushing in of the conductive adhesive 41 refers to the amount by which the semiconductor chip 2 is further pushed into the thick film metal plate 42 after the entire back surface of the metal layer 30 is evenly covered with the conductive adhesive 41 in order to ensure adhesion between the metal layer 30 and the conductive adhesive 41 during bonding in step 505.

[0087] The area of ​​the semiconductor layer 40 in plan view is S [μm 2 ], and the amount of conductive adhesive 41 pushed in is P [μm], the amount of conductive adhesive 41 protruding is S × P [μm 3Therefore, as the pushing-in amount of the conductive adhesive 41 increases, the amount of the conductive adhesive 41 that protrudes increases. In order to minimize the amount of the conductive adhesive 41 that protrudes and to ensure stable adhesion between the metal layer 30 and the conductive adhesive 41, it is desirable for the pushing-in amount of the conductive adhesive 41 to be in the range of 5 μm to 10 μm.

[0088] In the semiconductor device 1 according to the first embodiment, in order for the thick-film metal plate 42 to contain the protruding portion of the conductive adhesive 41 in a plan view, it is sufficient to secure a margin equal to the length of the bottom side of the fillet of the conductive adhesive 41 when the amount of pressing of the conductive adhesive 41 is in the range of 5 μm to 10 μm. Therefore, when the shortest length of the closest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick-film metal plate 42 in a plan view is M μm, the margin is -0.75×w + As long as the relationship 135.3 (plot line with circles)≦M≦-1.5×w+270.6 (plot line with squares) is satisfied, there is no need to expand the area of ​​the thick metal plate 42 beyond this range. By adjusting the warp direction and amount of warp w of the semiconductor chip 2, it is possible to reduce the area of ​​the thick metal plate 42.

[0089] In addition, the minimum length M of the closest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick metal plate 42 in a plan view refers to the margin described in the explanation of step 504. That is, as an example, it refers to the minimum length of the margin provided with approximately equal width from the outer periphery of the metal layer 30 to the outer periphery of the thick metal plate 42 closest to it in a plan view.

[0090] However, as a result of the inventors' investigations, if the amount of warping of the semiconductor chip 2 at 170°C exceeds 30 μm, the physical adhesion between the metal layer 30 and the conductive adhesive 41 around the outer periphery of the semiconductor chip 2 deteriorates, and the conductive adhesive 41 may peel off from the metal layer 30.

[0091] 8A and 8B show cross-sectional SEM images of Comparative Example 2 according to the first embodiment. FIG. 8B is an enlarged cross-sectional SEM image of the portion surrounded by the dashed line in FIG. 8A. In the semiconductor device 1 shown in FIGS. 8A and 8B, the thickness of the semiconductor layer 40 is 40 μm, the thickness of the first source electrode 11 and the second source electrode 21 is 4 μm, the thickness of the metal layer 30 is 25 μm, and the thickness of the thick metal plate 42 is 200 μm. In this thickness configuration, the semiconductor chip 2 is warped in a convex shape in the direction approaching the thick metal plate 42 (-Z direction), and the amount of warping is 35 μm.

[0092] 8B, when the warpage of the semiconductor chip 2 is 35 μm, a space is generated between the metal layer 30 and the conductive adhesive 41 at the periphery of the semiconductor chip 2, and it is found that the metal layer 30 and the conductive adhesive 41 are not in close contact with each other. If the warpage is too large, there is a concern that the conductive adhesive 41 may peel off near the periphery of the metal layer 30 in a plan view. Therefore, in order to reduce the amount of protrusion of the conductive adhesive 41 while stably ensuring the adhesion of the bond between the metal layer 30 and the thick film metal plate 42, it is preferable that the warpage of the semiconductor chip 2 at 170° C. is 30 μm or less.

[0093] The direction of warping (also referred to as the direction of curvature) and the amount of warping (also referred to as the amount of curvature) of the semiconductor chip 2 at high temperatures are determined by the relationship between the physical properties, such as the linear expansion coefficient and Young's modulus, of the semiconductor layer 40, the first source electrode 11, the second source electrode 21, and the metal layer 30, and their respective thicknesses.

[0094] The metal species constituting the first source electrode 11 and the second source electrode 21 and the metal species constituting the metal layer 30 often have similar linear expansion coefficients, so the direction of warping of the semiconductor chip 2 is often determined only by the relationship between the metal layer 30 and the thicknesses of the first source electrode 11 and the second source electrode 21.

[0095] Since the thickness of the first source electrode 11 and the thickness of the second source electrode 21 are typically 2 μm or more and 8 μm or less, respectively, it is desirable to set the thickness of the metal layer 30 to 10 μm or more in order to control the warpage to be convex in the -Z direction. This is because, by making the thickness of the metal layer 30 thicker than the thicknesses of the first source electrode 11 and the second source electrode 21, a larger thermal stress is generated in the metal layer 30 at high temperatures, and the semiconductor chip 2 takes on a curved shape that is convex in the direction in which the metal layer 30 is provided (the -Z direction).

[0096] The amount of warping is determined by the relative relationship between the thickness of the semiconductor layer 40 and the metal layer 30, and increases as the semiconductor layer 40 becomes thinner and as the metal layer 30 becomes thicker. Therefore, by adjusting the thickness of the semiconductor layer 40 and the metal layer 30, it is possible to control the amount of warping of the semiconductor chip 2 at 170° C. to 30 μm or less.

[0097] In the semiconductor device 1 according to the first embodiment, when the amount of conductive adhesive 41 applied to the surface of the thick-film metal plate 42 and the amount of conductive adhesive 41 pressed in are constant, and the adhesiveness of the bond between the metal layer 30 and the thick-film metal plate 42 via the conductive adhesive 41 is stably ensured, the volume of the conductive adhesive 41 protruding from the semiconductor chip 2 (the volume of the fillet of the conductive adhesive 41) is constant. While the volume of the fillet of the conductive adhesive 41 is constant, the height of the fillet of the conductive adhesive 41 (the amount of the conductive adhesive 41 creeping up from the surface of the thick-film metal plate 42 along the side of the semiconductor chip 2) varies depending on the length of the base of the fillet of the conductive adhesive 41.

[0098] Next, we will explain the above item (2).

[0099] In the semiconductor device 1 according to the first embodiment, when the semiconductor layer 40 has a long side length L1 [μm] and a short side length L2 [μm] (when the semiconductor layer 40 is a square, L1=L2), the amount of the conductive adhesive 41 protruding from the semiconductor chip 2 is L1×L2×P [μm 3In addition, the conductive adhesive 41 protruding from the semiconductor chip 2 forms a fillet that is approximately triangular in cross section, so if the height of the fillet of the conductive adhesive 41 is ht [μm], the volume of the fillet of the conductive adhesive 41 is (b×ht / 2)×2×(L1+L2) [μm 3 However, it is assumed that the amount of conductive adhesive 41 protruding in plan view is uniform along the outer periphery of semiconductor layer 40.

[0100] The amount of conductive adhesive 41 protruding from the semiconductor chip 2 is L1×L2×P [μm 3 ] and the volume of the fillet of conductive adhesive 41 ( b×ht / 2)×2 ×(L1+L2) [μm 3 ], the height of the fillet of the conductive adhesive 41 is ht=P×L1×L2 / {b×(L1+L2)}. Note that it is assumed that the amount of warping of the semiconductor chip 2 is 30 μm or less, and that the conductive adhesive 41 is not peeled off between the metal layer 30 and the thick film metal plate 42.

[0101] If the conductive adhesive 41 creeps up to the top surface of the semiconductor chip 2, there is a possibility that the semiconductor device 1 may short-circuit. Therefore, the amount by which the conductive adhesive 41 creeps up from the surface of the thick metal plate 42 along the side of the semiconductor chip 2 (the height of the fillet of the conductive adhesive 41) must be less than the top surface of the semiconductor layer 40.

[0102] In the semiconductor device 1 according to the first embodiment, the semiconductor chip 2 is controlled to be convex in the direction approaching the support 42 (-Z direction), and the outer periphery of the semiconductor chip 2 is curved in the direction relatively away from the support 42 (+Z direction) due to warping. When the semiconductor chip 2 has such a curved shape, the distance from the surface of the thick metal plate 42 to the upper surface of the semiconductor chip 2 becomes longer on the outer periphery of the semiconductor chip 2 in a plan view, so that it is possible to obtain the effect of preventing the conductive adhesive 41 protruding from the semiconductor chip 2 from creeping up to the upper surface of the semiconductor chip 2.

[0103] In the semiconductor device 1 according to the first embodiment, when the thickness of the semiconductor chip 2 at the center of the semiconductor chip 2 in plan view is H [μm] and the thickness of the conductive adhesive 41 is T [μm], if the relationship ht <H + T + w holds, the conductive adhesive 41 does not climb up to the upper surface of the semiconductor layer 40.

[0104] That is, by controlling the direction and amount of warping of the semiconductor chip 2, the length of the conductive adhesive 41 protruding from the semiconductor chip 2 in plan view can be suppressed, and it is possible to prevent the conductive adhesive 41 protruding from the semiconductor chip 2 in cross-sectional view from climbing up to the upper surface of the semiconductor chip 2.

[0105] Incidentally, FIG. 9 is a cross-sectional SEM image of the outer periphery of the semiconductor device 1 according to the first embodiment. As shown in FIG. 9, the metal layer 30 may have protrusions in the direction (-Z direction) toward the thick film metal plate 42 on the surface that joins the conductive adhesive 41. As an example, this protrusion is a burr formed when the metal layer 30 is physically stretched when the semiconductor chip 2 is singulated from the wafer state using a blade. In the case of a burr, it is often continuously formed along the outer periphery of the metal layer 30 in plan view.

[0106] In the semiconductor device 1 according to the first embodiment, if there is even a partial portion where the height of the burr at the outer periphery of the semiconductor chip 2 is 5 [μm] or more from the back surface of the metal layer 30, it serves as an anchor effect for the bonding between the metal layer 30 and the conductive adhesive 41, and there is an effect of improving the adhesion with the conductive adhesive 41.

[0107] Furthermore, as a result of the inventors' study, in the adhesion between the metal layer 30 and the conductive adhesive 41, it is desirable that the surface of the metal layer 30 that joins the conductive adhesive 41 is a metal species other than nickel (Ni). Typically, when silver (Ag) or copper (Cu) is used as the main material, it has been found that the adhesion of the bonding between the metal layer 30 and the conductive adhesive 41 can be stably ensured.

[0108] Hereinafter, a modified example of the semiconductor device 1 according to the first embodiment will be described.

[0109] FIG. 10A shows a schematic cross-sectional view of Modification 1 of the semiconductor device 1 according to the first embodiment. In the semiconductor device 1 according to Modification 1, the support 42 has a curved shape that is convex toward the semiconductor chip 2. The curved shape of the support 42 is, for example, a shape caused by warping of the support 42 during heat treatment when the metal layer 30 and the support 42 are bonded via the conductive adhesive 41. The amount of warping of the support 42 is the difference between the highest position and the lowest position in the Z direction on the upper or lower surface of the support 42 when viewed in cross section. When the warping of the support 42 is a warping that is convex toward the semiconductor chip 2, the highest position is the center of the support 42 in a plan view, and the lowest position is the outer periphery of the support 42 in a plan view, particularly a corner on the outer periphery.

[0110] The direction and amount of warping of the support 42 can be controlled by adjusting the amount of warping of the semiconductor chip 2 generated at 170°C, the thickness and / or material of the support 42, and the thickness and / or material of the conductive adhesive 41, or the bonding conditions. The easiest way to adjust is to make the thickness of the support 42 thinner. If the thickness of the support 42 is made thinner, the amount of warping of the support 42 at the time when the semiconductor device 1 is completed can be increased, but the rigidity of the semiconductor device 1 will decrease. For this reason, as a guideline, it is preferable that the thickness of the support 42 is designed so that the amount of warping of the support 42 is smaller than the amount of warping of the semiconductor chip 2.

[0111] As shown in FIG. 10A, in semiconductor device 1, when the amount of curvature of support 42 is smaller than the amount of curvature of semiconductor chip 2 and support 42 has a curved shape that is convex in the direction toward semiconductor chip 2, the pressure applied to conductive adhesive 41 is reduced compared to when support 42 is not curved, and the length by which conductive adhesive 41 protrudes from semiconductor layer 40 in a planar view can be reduced.

[0112] Fig. 10B shows a schematic cross-sectional view of Modification 2 of the semiconductor device 1 according to the embodiment 1. In the semiconductor device 1 according to Modification 2, the support 42 has a curved shape that is convex in a direction away from the semiconductor chip 2. As shown in Fig. 10B, in the semiconductor device 1, when the amount of curvature of the support 42 is smaller than the amount of curvature of the semiconductor chip 2 and the support 42 has a curved shape that is convex in a direction away from the semiconductor chip 2, it is possible to prevent voids from being generated between the semiconductor chip 2 and the conductive adhesive 41 near the center of the semiconductor layer 40 in a plan view, compared to when the support 42 is not curved.

[0113] (Embodiment 2) A semiconductor device 100 according to a second embodiment, which is obtained by partially modifying the configuration of the semiconductor device 1 according to the first embodiment, will be described below.

[0114] The semiconductor device 100 according to the second embodiment is an example in which the support 42, which is the thick film metal plate according to the first embodiment, is changed to an insulating support 420.

[0115] Here, regarding the semiconductor device 100 of embodiment 2, the components similar to those of the semiconductor device 1 of embodiment 1 have already been explained, so they are given the same reference numerals and their detailed explanations are omitted, and the explanation focuses on the differences from the semiconductor device 1.

[0116] [1. Configuration of Semiconductor Device] 11 shows a schematic cross-sectional view of a semiconductor device 100 according to embodiment 2. This embodiment differs from the semiconductor device 1 according to embodiment 1 in that the support 42 is changed to an insulating support 420.

[0117] [2. Manufacturing method of semiconductor device] 12 shows a simplified diagram of a part of the manufacturing process of the semiconductor device 100 according to embodiment 2. Steps 501 to 504 are the same as those of the manufacturing process of the semiconductor device 1 according to embodiment 1. Step 506 corresponds to step 505 in embodiment 1.

[0118] In the second embodiment, the semiconductor chip 2 is bonded to the insulating support 420 in step 506. In step 506, the conductive adhesive 41 is applied to the upper surface of the insulating support 420 in advance. Conductivity The adhesive 41 is, for example, a silver paste, which hardens at a high temperature of 170° C., and bonds the semiconductor chip 2 and the insulating support 420 together.

[0119] [3. Consideration] In the semiconductor device 100 according to this embodiment, since the insulating support 420 is used, the rigidity can be improved compared to the thick film metal plate according to the first embodiment. An example of a material with good rigidity is a silicon substrate. When the silicon substrate is used as the insulating support 420, the same effect as that of the semiconductor device 1 according to the first embodiment, which uses a thick film metal plate, can be achieved with a thinner dimension.

[0120] In addition, since the semiconductor device according to the present disclosure includes the metal layer 30, it is possible to realize a sufficiently low on-resistance by using the metal layer 30 as a conductive path. Therefore, the semiconductor device 100 according to the second embodiment is useful in the case of a semiconductor chip 2 including the metal layer 30 on the back side of the semiconductor layer 40.

[0121] As with the semiconductor device 1 of embodiment 1, in the semiconductor device 100 of embodiment 2, the presence of the metal layer 30 in the semiconductor chip 2 can cause the direction of warping that occurs in the semiconductor chip 2 at 170°C to be convex in the direction approaching the support 42.

[0122] Although the semiconductor device according to one aspect of the present disclosure has been described above based on the first and second embodiments and the first and second modifications, the present disclosure is not limited to these embodiments and modifications. As long as it does not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to these embodiments and forms constructed by combining components in different embodiments and modifications may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0123] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path. [Explanation of symbols]

[0124] 1, 100 Semiconductor device 2. Semiconductor chips 10 Transistor (first vertical MOS transistor) 11 First source electrode 12, 13 parts 14 First Source Region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First Body Region 18a First connection area 19 First gate electrode 20 Transistor (second vertical MOS transistor) 21 Second source electrode 22, 23 parts 24 Second Source Region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second Body Region 28a Second connection area 29 Second gate electrode 30 metal layer 32 Semiconductor Substrate 33 Low concentration impurity layer (drift layer) 34 Interlayer insulation layer 35 Passivation Layer 40 Semiconductor layer 41 Adhesive (conductive adhesive) 42 Support (thick film metal plate) 90 Border 111 First Source Pad 119 First Gate Pad 121 Second Source Pad 129 Second Gate Pad 420 Insulating Support A1 First Area A2 Second Area

Claims

1. A semiconductor device capable of face-down mounting, A semiconductor substrate; a low concentration impurity layer formed on a front surface side of the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are combined to form a semiconductor layer, a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a metal layer in contact with the entire back surface of the semiconductor substrate; A support body is bonded to a back surface side of the metal layer via an adhesive, In the plan view, the support has an area larger than that of the semiconductor layer and contains the semiconductor layer; the thickness of the support is greater than the thickness of the semiconductor layer; In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a height of the adhesive along a side surface of the semiconductor layer is less than a top surface of the semiconductor layer; When the semiconductor chip of the semiconductor device is viewed in cross section without the support and the adhesive, the semiconductor chip has a curved shape that is convex toward the support. Semiconductor device.

2. In the plan view, the semiconductor layer has a rectangular shape, At the outer periphery of the semiconductor layer in the plan view, the thickness of the adhesive directly below the semiconductor layer is greater than the thickness of the adhesive directly below the semiconductor layer at the center of the semiconductor layer in the plan view. The semiconductor device according to claim 1 .

3. When the amount of curvature of the semiconductor chip is w [μm] and the shortest distance from the outer periphery of the semiconductor layer to the outer periphery of the support in the plan view is M [μm], The relationship -0.75 x w + 135.3 ≤ M ≤ -1.5 x w + 270.6 is established. The semiconductor device according to claim 1 .

4. In the plan view, a length of a side of the semiconductor layer along a first direction is L1 [μm], a length of a side of the semiconductor layer along a second direction perpendicular to the first direction is L2 [μm], and a length of the adhesive sticking out from the outer periphery of the semiconductor chip is b [μm]; When the thickness of the semiconductor chip is H [μm] and the thickness of the adhesive is T [μm] at the center of the semiconductor chip in the plan view, The relationship P×L1×L2 / {b×(L1+L2)}<H+T+w(5[μm]≦P≦10[μm]) is established. The semiconductor device according to claim 3 .

5. In the cross-sectional view, the support has a curved shape that is convex in a direction toward the semiconductor chip, The amount of curvature of the support is smaller than the amount of curvature of the semiconductor chip. The semiconductor device according to claim 3 .

6. In the cross-sectional view, the support has a curved shape that is convex in a direction away from the semiconductor chip, The amount of curvature of the support is smaller than the amount of curvature of the semiconductor chip. The semiconductor device according to claim 3 .

7. In the plan view, the metal layer has an outer periphery provided with a protrusion protruding toward the adhesive, In the cross-sectional view of the protrusion, the protrusion has a height of 5 μm or more. The semiconductor device according to claim 3 .

8. The metal layer has a multi-layer structure, and the surface that is bonded to the adhesive does not contain nickel. The semiconductor device according to claim 3 .

9. The adhesive is a conductive adhesive containing conductive particles and made of a resin that is thermally cured at 200° C. or less. The semiconductor device according to claim 3 .

10. The support is made of a metal, The electrical conductivity of the support is equal to that of the metal layer. The semiconductor device according to claim 3 .

Images