PACKAGED ELECTRONIC DEVICE HAVING SUBSTRATE WITH THERMALLY CONDUCTIVE ADHESIVE LAYER - Patent application

Abstract

The packaged electronic device includes a power semiconductor die having a first terminal and a second terminal, a leadframe having a bottom surface and a top surface including a die pad area, a first lead and a second lead, the first lead being integral with the leadframe and electrically connected to the first terminal of the power semiconductor die through the leadframe, a dielectric substrate, and a thermally conductive adhesive layer on the top surface of the dielectric substrate, where the power semiconductor die is on the die pad area of ​​the leadframe and the leadframe is on the top surface of the thermally conductive adhesive layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 159,925, filed January 27, 2021, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to packaged electronic devices, and more particularly to techniques for isolating the power semiconductor die in such devices from the primary thermal interface of the device package. [Background technology]

[0003] A power semiconductor device refers to a device that includes one or more semiconductor dies designed to pass large currents (e.g., tens or hundreds of amperes) and / or can block high voltages (e.g., hundreds, thousands, or tens of thousands of volts). Power semiconductor dies are often fabricated from wide bandgap semiconductor materials, such as silicon carbide ("SiC") or gallium nitride ("GaN") based semiconductor materials. Power semiconductor dies are often packaged to provide packaged electronic devices. A wide variety of packaged electronic devices are known in the art, including metal oxide semiconductor field effect transistors ("MOSFETs"), metal insulator semiconductor field effect transistors ("MISFETs"), insulated gate bipolar junction transistors ("IGBTs"), Schottky diodes, and the like.

[0004] A power MOSFET is one of the widely used packaged electronic devices. A power MOSFET is a three-terminal device having gate, drain, and source terminals and a semiconductor layer structure often referred to as a semiconductor body. A source region and a drain region separated by a channel region are formed in the semiconductor body, and a gate electrode (which may function as the gate terminal or be electrically connected to the gate terminal) is disposed adjacent to the channel region. A MOSFET may be turned on (to pass current through the channel region between the source and drain regions) by applying a bias voltage to the gate electrode, and may be turned off (to prevent current from flowing through the channel region) by removing the gate electrode (or reducing the bias voltage below a threshold level).

[0005] Both discrete and multi-chip power packaged electronic devices are commercially available. Discrete power packaged electronic devices refer to packaged power semiconductor modules that include a single power semiconductor die such as a packaged MOSFET, Schottky diode, IGBT, etc. Multi-chip power packaged electronic devices refer to power semiconductor modules that include two or more power semiconductor dies (usually interconnected) provided within a common package. Discrete power packaged electronic devices dominate the power electronics industry because they can be realized at very low cost and easily combined to form more complex circuits.

[0006] Power packaged electronic devices typically generate a large amount of heat during operation of the device due to the high voltages applied to these devices and / or the large currents flowing through the semiconductor die, bond wires, and leads. To prevent this heat from damaging the device, the semiconductor die is typically mounted on a metal submount that acts as a heat sink to transfer heat away from the package. For example, aluminum blocks are commonly used as submounts, and the top surfaces of these blocks can be plated with metals such as nickel or silver that allow discrete semiconductor devices to be mounted on the submount. Summary of the Invention [Means for solving the problem]

[0007] According to some embodiments of the present invention, there is provided a packaged electronic device comprising: a power semiconductor die including a first terminal and a second terminal, a leadframe including a bottom side and a top side including a die pad area, a first lead and a second lead, a dielectric substrate, and a thermally conductive adhesive layer on a top surface of the dielectric substrate, wherein the power semiconductor die is on the die pad area of ​​the leadframe and the leadframe is on a top surface of the thermally conductive adhesive layer.

[0008] In some embodiments, the first lead may be integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame. In some embodiments, the dielectric substrate may comprise a ceramic substrate and the thermally conductive adhesive layer comprises a metallic braze layer. The metallic braze layer may be attached, for example, directly to the ceramic substrate and to the underside of the lead frame.

[0009] In some embodiments, the second lead may not be electrically connected to the die pad region and may be electrically connected to the second terminal of the power semiconductor die. For example, the second lead may be electrically connected to the second terminal of the power semiconductor die via a bond wire.

[0010] In some embodiments, the packaged electronic device may further include an overmolded package encapsulating the top and sides of the power semiconductor die and / or a lower metal clad layer on the bottom surface of the dielectric substrate. The lead frame and the lower metal clad layer may be formed of the same metal in some embodiments. The metal braze layer may be a first metal braze layer and a second metal braze layer may be provided between the top surface of the lower metal clad layer and the bottom surface of the dielectric substrate.

[0011] In some embodiments, the first lead and the die pad area may be part of a monolithic leadframe structure.

[0012] In some embodiments, the packaged electronic device may further comprise an upper metal clad layer on top of the metal braze layer, and a substrate attach metal layer interposed between the upper metal clad layer and the lead frame.

[0013] According to a further embodiment of the present invention, there is provided a packaged electronic device comprising a dielectric substrate, a first metal clad layer on a lower surface of the dielectric substrate, a leadframe having a top surface including a die pad area and a bottom surface on the upper surface of the dielectric substrate, and a power semiconductor die on the die pad area of ​​the leadframe.

[0014] According to further embodiments of the present invention, the packaged electronic device may further include an overmold encapsulant encapsulating the top and side surfaces of the power semiconductor die and at least the top surface of the dielectric substrate, a first metal braze layer between the first metal clad layer and the ceramic substrate, and / or a second metal braze layer on the top surface of the ceramic substrate. In some embodiments, a second metal clad layer may be provided on the top surface of the second metal braze layer, and the lead frame is attached to the top surface of the second metal clad layer by a substrate attachment metal layer. In some embodiments, the second metal braze layer may be directly attached to both the top surface of the ceramic substrate and the bottom surface of the lead frame.

[0015] In some embodiments, the dielectric substrate may be a ceramic substrate. In some embodiments, the lead frame may further comprise a first lead integral with and electrically connected to the die pad area. In some embodiments, the packaged electronic device may also comprise a second lead electrically connected to a terminal of the power semiconductor die via a bond wire.

[0016] According to yet another embodiment of the present invention, there is provided a packaged electronic device comprising a dielectric substrate, a first metal cladding layer on a lower surface of the dielectric substrate, a power semiconductor die disposed on an upper surface of the dielectric substrate, an overmold encapsulant surrounding a top and side surface of the power semiconductor die and at least partially surrounding a sidewall of the dielectric substrate while exposing at least a portion of the first metal cladding layer, and first and second leads each extending through the overmold encapsulant and electrically connected to the power semiconductor die. The power semiconductor die is electrically insulated from the first metal cladding layer.

[0017] In some embodiments, the power substrate may be a ceramic substrate and the first metal braze layer may be on a top surface of the ceramic substrate.

[0018] In some embodiments, the packaged electronic device further comprises a leadframe including a top surface including a die pad area. A bottom surface of the leadframe may be mounted on the top surface of the first metal braze layer, and the power semiconductor die may be mounted on the die pad area. In some embodiments, the first metal braze layer may be attached directly to the ceramic substrate and to the bottom surface of the leadframe.

[0019] In some embodiments, the first lead may be integral to the lead frame and may be electrically connected to a first terminal of the power semiconductor die.

[0020] In some embodiments, the second lead may not be electrically connected to the die pad area, but may be electrically connected to the second terminal of the power semiconductor die via a bond wire.

[0021] In some embodiments, the first metal clad layer is attached to the bottom surface of the ceramic substrate via a second metal braze layer.

[0022] In some embodiments, the device may further comprise an upper metal clad layer on top of the first metal braze layer, and a substrate attach metal layer interposed between the upper metal clad layer and the lead frame. [Brief description of the drawings]

[0023] [Figure 1] 1 is a schematic cross-sectional view of a conventional packaged discrete electronic device. [Diagram 2] 1 is a schematic cross-sectional view of another conventional packaged electronic device. [Diagram 3] 1 is a schematic cross-sectional view of a packaged electronic device according to an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic perspective view of the packaged electronic device of FIG. 3 before an overmold encapsulant is applied. [Diagram 5] 4 is a schematic cross-sectional view of a packaged electronic device according to a further embodiment of the present invention. [Figure 6] FIG. 6 is a schematic perspective view of the packaged electronic device of FIG. 5 before an overmold encapsulant is applied. [Figure 7] FIG. 5 is a schematic cross-sectional view of a variation of the packaged electronic device of FIGS. 3 and 4. [Figure 8] FIG. 7 is a schematic cross-sectional view of a variation of the packaged electronic device of FIGS. 5 and 6. [Figure 9] FIG. 5 is a schematic cross-sectional view of another variation of the packaged semiconductor device of FIGS. 3 and 4. [Figure 10]FIG. 7 is a schematic cross-sectional view of another variation of the packaged electronic device of FIGS. 5 and 6. [Figure 11] FIG. 5 is a schematic cross-sectional view of another variation of the packaged electronic device of FIGS. 3 and 4 formed by direct bonding. [Figure 12] FIG. 7 is a schematic cross-sectional view of another variation of the packaged electronic device of FIGS. 5 and 6 formed by direct bonding. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] It should be noted that when multiple similar elements are shown in the drawings, they may be identified using a two-part reference number, and such elements may be referred to herein individually by their full reference number (e.g., terminal 12-1) and collectively by the first part of their reference number (e.g., terminal 12).

[0025] Packaged discrete electronic devices are typically mounted on printed circuit boards of a larger electronic system. These printed circuit boards may be referred to herein as customer motherboards. Packaged discrete electronic devices are typically mounted on heat sinks on the customer motherboard so that heat dissipated through the primary thermal interface of the packaged discrete electronic device is also dissipated from the customer motherboard. The primary thermal interface of a packaged electronic device refers to the primary path for dissipating heat from within the packaged electronic device. Heat sinks on customer motherboards are typically implemented as metal (e.g., copper or aluminum) pads or blocks. Heat sinks on customer motherboards are often electrically active (i.e., non-zero voltage).

[0026] Many conventional packaged discrete electronic devices do not electrically insulate the power semiconductor die from the primary thermal interface of the package. Instead, a thermally conductive but electrically insulating material, such as a thin dielectric layer (e.g., a silicone layer), is interposed between the packaged discrete electronic device and a heat sink on the customer motherboard. This thin dielectric layer may be referred to herein as a "thermal pad." The thermal pad electrically insulates the primary thermal interface between the package (and therefore the power semiconductor die) and the customer motherboard from the electronic circuitry on the customer motherboard. Using such a thermal pad to electrically insulate the packaged semiconductor device from the customer motherboard is acceptable and convenient for packaged electronic devices that operate at lower voltages (e.g., tens of volts) and current levels. However, when electronic devices designed to withstand thousands or tens of thousands of volts are introduced, the capacitive coupling across the thermal pad may be strong enough to adversely affect the performance of the packaged discrete electronic device and / or may degrade the thermal pad material, which may result in a short circuit between the primary thermal interface and the metal pad on the customer motherboard. Such shorts typically render packaged discrete electronic devices inoperable and may damage or even destroy the devices.

[0027] According to an embodiment of the present invention, there is provided a packaged electronic device including power semiconductor dies each electrically isolated from its primary thermal interface. The packaged electronic devices disclosed herein may exhibit improved reliability and / or current carrying capacity (rating) compared to conventional solutions, with little or no additional cost, and possibly at lower cost when used in a high volume manufacturing environment.

[0028] According to some embodiments of the present invention, a packaged electronic device is provided that includes a dielectric (e.g., ceramic) substrate having a metal braze layer on its upper surface. The metal braze layer may be attached directly to the body of a lead frame that includes integral leads. The dielectric substrate conducts heat well and provides excellent voltage insulation (capable of insulating tens of thousands of volts). Furthermore, the dielectric substrate with its metal braze layer may exhibit excellent thermo-mechanical reliability.

[0029] In some embodiments, a packaged electronic device is provided that includes a leadframe having a die pad area on a top surface thereof, and a power semiconductor die having at least a first terminal and a second terminal disposed on the die pad area of ​​the leadframe. As used herein, a "terminal" of the power semiconductor die refers to a conductive (e.g., metal) structure on the die through which an electrical signal may be input to and / or output from the die. The terminal may comprise, for example, a conductive pad, a block, a contact, or the like. The device also includes a plurality of leads, a first of which is integral with the leadframe and electrically connected to the first terminal of the power semiconductor die through the leadframe. The device further includes a dielectric substrate having a thermally conductive adhesive layer, such as a metal braze layer, on a top surface of the dielectric substrate. The leadframe is disposed on top of the metal braze layer.

[0030] In another embodiment, a packaged electronic device is provided that includes a dielectric substrate, a first metal clad layer on a bottom surface of the dielectric substrate, a leadframe having a top surface including a die pad area and a bottom surface mounted to the top surface of the dielectric substrate, and a power semiconductor die mounted on the die pad area of ​​the leadframe.

[0031] In yet another embodiment, packaged electronic devices are provided that include a dielectric substrate having a first metal clad layer on its underside, a power semiconductor die mounted on the power substrate, and an overmold encapsulant that surrounds a top and side of the power semiconductor die and at least partially surrounds a sidewall of the dielectric substrate while exposing at least a portion of the first metal clad layer and a plurality of leads extending through the overmold encapsulant and electrically connected to the power semiconductor die. In these devices, the power semiconductor die is electrically isolated from the first metal clad layer.

[0032] In all of the above embodiments, the dielectric substrate may be a ceramic substrate. In some embodiments, the metal braze layer may be attached directly to both the top surface of the ceramic substrate and the bottom surface of the leadframe. The device may include both integral leads that are part of the monolithic leadframe structure and floating leads that are not attached to the leadframe or electrically connected to the die pad areas of the leadframe (although they may be connected to the leadframe through the power semiconductor die). These floating leads may be connected directly to the terminals of the power semiconductor die or may be connected to the terminals of the power semiconductor die through bond wires. The overmolded package may encapsulate the top and side surfaces of the power semiconductor die and at least a portion of the top and side surfaces of the dielectric substrate.

[0033] In some embodiments, the dielectric substrate may further include an upper metal clad layer on top of the metal braze layer, and a substrate attachment metal layer interposed between the upper metal clad layer and the lead frame.

[0034] Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It will be understood that the features of the different embodiments disclosed herein may be combined in any manner to provide many additional embodiments. Thus, although various features of the present invention are described below with reference to specific examples, it will be understood that these features may be added to other embodiments and / or used in place of the exemplary features of other embodiments to provide many additional embodiments. Thus, the present invention should be understood to encompass these various combinations. In addition, although the exemplary embodiments focus on implementing MOSFETs, it will be understood that the same techniques may be used for other packaged electronic devices such as insulated gate bipolar transistors (IGBTs), Schottky diodes, gate-controlled thyristors, etc.

[0035] FIG. 1 is a schematic cross-sectional view of a conventional state-of-the-art packaged discrete electronic device 1. As shown in FIG. 1, the packaged device 1 includes a power semiconductor die 10, a submount in the form of a leadframe 30 with one or more integral leads 34, one or more floating leads 36, and an overmolded encapsulant 50. The leadframe 30, the leads 34, 36, and the overmolded encapsulant 50 together form a package 20 for the power semiconductor die 10. The leadframe 30 includes a die attach area 32 and one or more integral leads 34. The floating leads 36 may be initially integral with the leadframe 30, but may be separated from the leadframe 30 during the manufacturing process and may be held in place by the overmolded encapsulant 50. The power semiconductor die 10 is bonded (e.g., soldered) to the die attach area 32 on the top surface of the leadframe 30 using a die attach material 14. The power semiconductor die 10 may include multiple terminals 12. For example, a power MOSFET may include a gate terminal, a source terminal, and a drain terminal. These terminals 12 are typically located on the top and / or bottom surfaces of the power semiconductor die 10 and may comprise, for example, exposed metal pads. The terminals 12 (e.g., source terminals of a power MOSFET) are provided on the bottom surface of the power semiconductor die 10 and are electrically connected to integral leads 34 through die attach material 14 and lead frame 30. One or more bond wires 16 connect the terminals 12 on the top surface of the power semiconductor die 10 to floating leads 36. Each terminal 12 may be connected to a single floating lead 36 or multiple floating leads 36. The insulating encapsulant 50 may comprise an overmolded encapsulant formed to cover the top and side surfaces of the power semiconductor die 10 and at least a portion of the lead frame 30.

[0036] The packaged discrete electronic device 1 is typically mounted on a customer motherboard. As described above, the packaged discrete electronic device 1 is typically mounted on a metal pad on the customer motherboard, and a thermal pad, such as a silicone layer, is interposed between the metal pad on the customer motherboard and the underside of the leadframe 30 to electrically isolate the power semiconductor die 10 from the customer motherboard. The leads 34, 36 may be connected to other pads, dies, etc. on the customer motherboard.

[0037] 2 is a schematic cross-sectional view of a conventional packaged discrete electronic device 2. The conventional packaged discrete electronic device 2 includes a power semiconductor die 10, a submount in the form of a power substrate 40, and an overmolded encapsulant 50. As used herein, the term "power substrate" refers to a dielectric substrate having metal cladding layers on both sides thereof. The leads 36, power substrate 40, and overmolded encapsulant 50 together form a package 20 for the power semiconductor die 10. The leads 36 include floating leads that may be held in place by the overmolded encapsulant 50.

[0038] The power board 40 includes a ceramic substrate 42. A lower metal clad layer 46-1 is formed on the lower surface of the ceramic substrate 42, and an upper metal clad layer 46-2 is formed on the upper surface of the ceramic substrate 42. There are mainly two types of power boards. The first type is known as an Active Metal Brazed ("AMB") power board, which includes first and second metal brazing layers 44-1, 44-2 that are used to bond the first and second metal clad layers 46-1, 46-2, respectively, to the ceramic substrate 42. Although soldering cannot be used to bond metal to a dielectric surface, brazing can be used. Metal brazing materials have some similarities to solder, but the bonding process is performed at high temperatures, most commonly in a vacuum. This results in a very reliable bond compared to traditional soldering. The second type of power substrate is called a direct bonded substrate (or more commonly, a direct bonded copper or "DBC" power substrate, since the metal clad layers 46-1, 46-2 are typically copper layers). DBC power substrates are formed by pressing the metal clad layers 46-1, 46-2 directly against the dielectric substrate 42 while being heat treated in a controlled atmosphere. DBC power substrates are not as reliable as AMB power substrates.

[0039] The power semiconductor die 10 is bonded (e.g., soldered) to the top surface of the second metal clad layer 46-2 using a die attach material 14. A first terminal 12 of the power semiconductor die 10 is located on its top surface and is electrically connected to the first floating lead 36-1 via a first bond wire 16. A second terminal 12 of the power semiconductor die 10 is provided on its bottom surface and is electrically connected to the second floating lead 36-2 via the die attach material 14 and the top metal clad layer 46-2. It should be noted that multiple bond wires 36 may be attached between the terminal 12 and / or the top metal clad layer 46-2 and the respective floating leads 36-1, 36-2. Similarly, multiple floating leads 36-1 and / or 36-2 may be provided, each connected by bonding a wire 16 to the terminal 12 or the top metal clad layer 46-2, respectively. An overmold encapsulant 50 covers the top and sides of the power semiconductor die 10 and most of the power substrate 40. The power substrate 40 serves as a primary thermal interface for dissipating heat generated in the power semiconductor die 10 from the device package 20. A ceramic substrate 42, which is part of this primary thermal interface, electrically insulates the power semiconductor die 10 from a customer motherboard (not shown) on which the packaged electronic device 2 may be installed.

[0040] FIG. 3 is a schematic cross-sectional view of a packaged electronic device 100 according to an embodiment of the present invention. FIG. 4 is a schematic perspective view of the packaged electronic device 100 of FIG. 3 before an insulating encapsulant is applied. With reference to FIGS. 3 and 4, the packaged electronic device 100 includes a power semiconductor die 110, a submount in the form of a lead frame 130 with integral leads 134, a floating lead 136, a power substrate 140, and an insulating encapsulant 150. The lead frame 130, the leads 134, 136, the power substrate 140, and the insulating encapsulant 150 together form a package 120 for the power semiconductor die 110. The lead frame 130 includes a die attachment area 132 and one or more integral leads 134. The floating lead 136 may be initially integral with the lead frame 130, but may be separated from the lead frame 130 during the manufacturing process and may be held in place by the insulating encapsulant 150. Power semiconductor die 110 is attached (eg, soldered) using die attach material 114 to a die attach area 132 on the top surface of leadframe 130 .

[0041] The power semiconductor die 110 may be a semiconductor device designed to block high voltage levels (e.g., hundreds of volts or more) and / or pass large currents. The power semiconductor die 110 may be formed using wide bandgap semiconductor materials such as silicon carbide and / or gallium nitride-based and / or aluminum nitride-based semiconductor systems (e.g., GaN, AlGaN, InGaN, AlN, etc.). Other wide bandgap materials may be used, such as devices formed in other III-V or II-VI semiconductor systems. The power semiconductor die 110 may comprise, for example, a MOSFET, a MISFET, an IGBT, a Schottky diode, a gate-controlled thyristor, etc. The power semiconductor die 110 may have a vertical structure in which the top surface of the die includes at least one terminal and the bottom surface of the die also includes at least one terminal. For example, the device may comprise a vertical MOSFET having a vertically extending drift region through which current flows during on-state operation.

[0042] The power semiconductor die 110 includes a number of terminals 112. For example, if the power semiconductor die 110 is a power MOSFET, the power semiconductor die may include three terminals 112. These terminals 112 are typically located on the top and / or bottom surface of the power semiconductor die 110 and may comprise, for example, exposed metal pads. In the embodiment of Figures 3 and 4, the device includes three terminals 112: a gate terminal 112-1 and a drain terminal 112-2 located on the top surface of the power semiconductor die 110, and a source terminal 112-3 located on the bottom surface of the power semiconductor die 110 (the drain terminal 112-2 is not visible in Figure 3). One or more bond wires 116 connect the terminals 112-1, 112-2 on the top surface of the power semiconductor die 110 to respective floating leads 136-1, 136-2. It should be noted that multiple floating leads 136-1 and / or 136-2 may be provided, and bond wires 116 may extend between the multiple floating leads 136-1 or 136-2 and the respective terminals 112-1 or 112-2. The source terminal 112-3 is electrically connected to the integral lead 134 through the die attach material 114 and the lead frame 130. The insulating encapsulant 150 may comprise an overmolded encapsulant formed to cover the top and side surfaces of the power semiconductor die 110 and the lead frame 130, as well as at least a portion of the power substrate 140. However, it will be understood that embodiments of the present invention are not limited thereto. For example, in other embodiments, the insulating encapsulant may include a silicone gel or another compound. The insulating encapsulant 150 may hold the floating leads 136 in their proper positions.

[0043] The power substrate 140 includes a dielectric substrate 142, first and second metal braze layers 144-1, 144-2, and lower and upper metal clad layers 146-1, 146-2. The dielectric substrate 142 may comprise any insulating substrate. In some embodiments, the dielectric substrate 142 may comprise a ceramic substrate. In an exemplary embodiment, the dielectric substrate 142 may be formed of aluminum oxide (alumina), aluminum nitride, or silicon nitride. The thickness of the dielectric substrate 142 may be selected based on the voltage blocking capability of the packaged electronic device 100 (to ensure sufficient electrical isolation) and material cost considerations. For example, assuming the dielectric substrate 142 is formed of alumina, for a packaged electronic device 100 with a blocking voltage rating of 800 volts, the thickness may be in the range of 0.2 mm, and for a packaged electronic device 100 with a blocking voltage rating of 10,000 volts, the thickness may be in the range of 0.5 to 1.0 mm.

[0044] The first metal braze layer 144-1 is formed on the lower surface of the dielectric substrate 142 and is used to bond the lower metal clad layer 146-1 to the dielectric substrate 142. Similarly, the second metal braze layer 144-2 is formed on the upper surface of the dielectric substrate 142 and is used to bond the upper metal clad layer 146-2 to the dielectric substrate 142. The first and second metal braze layers 144-1, 144-2 may comprise a metal alloy including two or more metals, such as, for example, copper, silver, nickel, gold, etc. The first and second metal braze layers 144-1, 144-2 may be thin layers (e.g., they may have a thickness between 1 and 10 microns). The first and second metal clad layers 146-1, 146-2 may comprise plated metal layers including a metal (or other suitable metal) such as copper or aluminum. Since the thickness of the dielectric substrate 142 typically varies based on the voltage rating of the device (as higher voltage ratings require a thicker dielectric substrate 142 to achieve a given level of electrical isolation), the first and second metal clad layers 146-1, 146-2 may be thicker or thinner than the dielectric substrate 142. In some embodiments, the lead frame 130 and the metal clad layers 146 may be formed of the same metal or metal alloy, although embodiments of the invention are not limited thereto. Each metal clad layer 146 may be bonded to the ceramic substrate 142 by depositing a respective metal braze layer 144 onto the ceramic substrate 142, then depositing a metal clad layer onto the metal braze layer 144, and curing the power substrate 140 at an elevated temperature, e.g., 500-1000° C., for an appropriate time.

[0045] The bottom surface of the leadframe 130 is bonded (e.g., soldered) to the top surface of the power substrate 140 via a substrate attachment material 160. The substrate attachment material 160 may include, for example, solder and sintered materials. The top metal clad layer 146-2 facilitates bonding the power substrate 140 to the leadframe 130 via the substrate attachment material 160. The thickness of the top metal clad layer 146-2 may vary based on the current rating of the device. The bottom metal clad layer 146-1 facilitates bonding the power substrate 140 to metal pads on a customer motherboard (not shown).

[0046] The power substrate 140 serves as a highly thermally conductive path that functions as a primary thermal interface to dissipate heat generated in the power semiconductor die 110 from the packaged electronic device 100. The dielectric substrate 142, which is typically a ceramic substrate, electrically insulates the power semiconductor die 110 from a customer motherboard (not shown) on which the packaged electronic device 100 may be installed. Thus, the packaged electronic device 100 provides electrical insulation not provided by the conventional packaged electronic device 1 of FIG. 1 and may be bonded to a customer motherboard without the need for any thermal pads, such as silicon pads. Because the lead frame 130 is electrically insulated from the customer motherboard, the packaged electronic device 100 may include integral leads 134. As discussed above, integral leads cannot be used when the conventional packaged electronic device 1 of FIG. 1 is a high power device, because the thermal pads of the customer motherboard typically do not provide sufficient electrical insulation. The provision of integral leads 134 avoids the need to use bond wire connections 116 to electrically connect terminals on the underside of power semiconductor die 110 to the device leads, as required in the conventional packaged electronic device 2 of Figure 2. Furthermore, elimination of integral leads 134 would typically require retooling existing production lines, which may be cost-prohibitive.

[0047] Figure 5 is a schematic cross-sectional view of a packaged electronic device 200 according to a further embodiment of the present invention, and Figure 6 is a schematic perspective view of the packaged electronic device 200 of Figure 5 before an overmold encapsulant is applied.

[0048] 5 and 6, it can be seen that packaged electronic device 200 is similar to packaged discrete electronic device 100 described above with reference to Figures 3 and 4. Accordingly, elements of packaged electronic device 200 that are identical or substantially identical to corresponding elements of packaged electronic device 100 are labeled using the same reference numbers used in Figures 3 and 4, and thus further description of these similar elements will generally be omitted.

[0049] As can be seen from the figures, the main differences between packaged electronic device 200 and packaged electronic device 100 are that (1) the power substrate 240 of packaged electronic device 200 is replaced in packaged electronic device 200 with a substrate structure 240 that does not include an upper metal clad layer (i.e., upper metal clad layer 146-2 of packaged electronic device 100 is omitted), and (2) packaged electronic device 200 does not include substrate attachment material 160. Thus, in packaged electronic device 200, lead frame 130 is bonded to substrate structure 240 via second braze metal layer 144-2. This arrangement reduces the number of layers in the primary thermal path, since upper metal clad layer 146-2 and substrate attachment material 160 are omitted. As a result, the thermal resistance of the heat dissipation path between packaged electronic device 200 and the heat sink of the customer motherboard may be reduced, which results in increased heat transfer. This may enable the device to handle higher current levels and improve device reliability. In addition, omitting two layers reduces material costs and potentially simplifies device manufacturing.

[0050] Packaged electronic device 200 may also have several additional advantages over packaged electronic device 100 described above.

[0051] First, one potential failure point in a packaged electronic device (such as packaged electronic device 100) that is attached to a submount using a substrate attachment material is that the substrate attachment material may not form a strong bond between the submount and the leadframe. A brazed connection between the ceramic substrate 142 and the leadframe 130 provided in packaged electronic device 200 may be a more reliable connection, and thus packaged electronic device 200 may be less prone to failure.

[0052] Second, it may be important that the leadframe 130 is mounted to the submount structure (here, the substrate structure 240) without tilt (i.e., the planes defined by the mounting surfaces of the substrate structure 240 and the leadframe 130 need to be parallel to each other). In practice, it may be difficult to ensure that this is the case when the leadframe 130 is mounted to the power substrate 140 using the substrate mounting material 160, and therefore the thickness of the substrate mounting material 160 may need to be carefully controlled, and other steps may need to be taken to ensure that the distance between the mating surfaces of the power substrate 140 and the leadframe 130 is maintained highly uniform. When the substrate structure 240 is brazed to the leadframe 130, the distance between the substrate structure 240 and the leadframe 130 may be maintained uniform, eliminating the need for special process steps that are required when the power substrate 140 and the leadframe 130 are joined to each other using the substrate mounting material 160.

[0053] Third, the substrate attach process steps used in forming the packaged electronic device 100 of FIGS. 3 and 4 include a reflow step in which the device 100 is heated to melt the substrate attach material 160 and bond the lead frame 130 to the power substrate 140. This step is not necessary in the manufacture of the packaged electronic device 200 and may therefore facilitate shorter cycle times in mass production manufacturing. Furthermore, because the substrate attach step included in the manufacturing process of the packaged electronic device 100 is omitted, only one soldering step is required in the manufacture of the power semiconductor 200, i.e., the die attach step used to place the power semiconductor die 110 on the lead frame 130. In manufacturing the packaged electronic device 100, it may be necessary to use a die attach material 114 with a high melting point to ensure that the die attach material 114 does not reflow during the subsequent substrate attach soldering step (the substrate attach material may be selected to have a lower melting point). Because the substrate attach soldering step may be omitted in manufacturing the packaged electronic device 200, a wider selection of die attach materials 114 may be used, which may allow the use of materials that reduce cost and / or improve reliability.

[0054] FIG. 7 is a schematic cross-sectional view of a packaged electronic device 100A, which is a variation of the packaged electronic device 100 of FIGS. 3 and 4. As can be seen by comparing FIGS. 3 and 7, the packaged electronic device 100A is identical to the packaged semiconductor device 100, except that the bond wires 116 are omitted in the packaged semiconductor device 100A, since the floating leads 136 are directly bonded to the terminals 112 on the top surface of the power semiconductor die 110. In the packaged electronic device 100A, the gate terminal 112-1 and the drain terminal 112-2 are located on opposite sides of the top surface of the semiconductor die 110, and the floating leads 136-1, 136-2 are likewise on opposite sides of the device 100A. In other embodiments, all three leads 134, 136-1, 136-2 may extend from the same side of the device.

[0055] Figure 8 is a schematic cross-sectional view of a packaged electronic device 200A, which is a variation of the packaged electronic device 200 of Figures 5 and 6. The packaged electronic device 200A is a variation of the packaged electronic device 200 that includes the same modifications as the packaged electronic device 100A includes, as compared to the packaged electronic device 100. In particular, the packaged electronic device 200A omits the bond wires 116 and instead has floating leads 136 that are directly bonded to the terminals 112-1, 112-2 on the top surface of the power semiconductor die 110.

[0056] FIG. 9 is a schematic cross-sectional view of a packaged electronic device 100B, which is another variation of the packaged electronic device 100 of FIGS. 3 and 4. As can be seen by comparing FIGS. 3 and 9, the packaged electronic device 100B is identical to the packaged electronic device 100, except that the packaged electronic device 100B is not a "discrete" device, but instead includes two power semiconductor dies 110-1, 110-2. In an exemplary embodiment, the two power semiconductor dies 110-1, 110-2 may be power MOSFETs electrically connected in parallel. As shown, a pair of floating gate leads 136-1, 136-2 are electrically connected to the gate terminal 112-1 of the power semiconductor die 110 by bond wires 116 (in other embodiments, a single floating gate lead 136 may be provided). The drain terminal of each die 110 (not visible in FIG. 9) may be connected to one or more floating drain leads 136 (also not visible in FIG. 9). The source terminal 112-3 of each power semiconductor die 110 may be on a bottom surface of the respective power semiconductor die 110 and may be connected to one or more integral leads 134 via the lead frame 130.

[0057] Figure 10 is a schematic cross-sectional view of a packaged electronic device 200B, which is another variation of the packaged electronic device 200 of Figures 5 and 6. Packaged electronic device 200B corresponds to packaged electronic device 100B in that it includes two power semiconductor dies 110 rather than a single power semiconductor die.

[0058] It will be understood that when multiple power semiconductor dies 110 are included in a packaged electronic device according to an embodiment of the present invention, the semiconductor dies 110 may be the same or different and may be electrically connected to each other and to the package leads 134, 136 in various ways. Thus, in exemplary embodiments, for example, multiple power MOSFETs connected in series or parallel may be provided, multiple power Schottky diodes connected in series or parallel may be provided, or one or more power MOSFETs and one or more power Schottky diodes may be connected in series or parallel.

[0059] One potential concern with providing a dielectric substrate 142 in the primary heat dissipation path is that the dielectric substrate 142 typically has a different coefficient of thermal expansion compared to the metal layers of the primary heat dissipation path. As the packaged electronic device heats and cools (thermal cycles) during normal operation, this may create stresses and strains in the stack of materials and may weaken the bonds between the different layers of the primary heat dissipation path. This may reduce device performance and may damage and destroy the device. Thus, the thickness of the metal layers formed on both sides of the dielectric substrate 142 may be selected such that the metal layers above and below the dielectric substrate 142 expand / contract at similar rates. This may improve device reliability. In another application, the thickness of the metal layers 146 formed on either surface of the dielectric substrate 142 may be selected to provide a desired flat or convex curvature to the exposed back surface of the package. The presence of a flat or convex mounting surface allows for more efficient and reliable heat evacuation when mounted to a heat sink compared to a concave back surface.

[0060] Although embodiments of the present invention are described above that include a dielectric substrate having a metal brazing layer, it will be understood that embodiments of the present invention are not so limited. For example, in other embodiments, one or more of the metal brazing layers may be replaced with a thermally conductive adhesive. Such embodiments may reduce thermo-mechanical reliability compared to a brazed interface, but may be sufficient for applications with reduced temperature cycling (e.g., low power devices, devices used in climate-controlled environments) and low vibration applications (e.g., many non-automotive applications).

[0061] The power semiconductor die is attached to a submount, such as a power substrate, but these known devices do not include a leadframe having integral leads connected to the terminals of the power semiconductor die.

[0062] According to a further embodiment of the present invention, a packaged electronic device is provided that includes one or more power semiconductor dies mounted on a lead frame that is attached to a dielectric substrate using a thermally conductive adhesive. Figures 11 and 12 show variations of the packaged electronic devices of Figures 3 and 4 and Figures 5 and 6, respectively, having such a configuration. As shown in Figure 11, the packaged electronic device 100C is identical to the packaged semiconductor device 100, except that the substrate attachment material layer 160 is replaced with a thermally conductive adhesive paste 162 (e.g., a ceramic-filled or metal-filled adhesive paste) such that the lead frame 130 is attached to the power substrate 140 by a direct bonding process. Figure 12 is a schematic cross-sectional view of a packaged electronic device 200C, which is a variation of the packaged electronic device 200 of Figures 5 and 6. The packaged electronic device 200C corresponds to the packaged electronic device 100C of Figure 11, since the second metal braze layer 144-2 is replaced with a thermally conductive adhesive paste 162. One example of such an adhesive paste may be the ceramic-filled or metal-filled adhesive paste 162 in the embodiment of FIG. 12 so that the dielectric substrate 142 may be attached to the lead frame 130 .

[0063] As discussed above, according to embodiments of the present invention, a leadframe may be bonded to an underlying dielectric substrate using either (1) a metal braze layer or (2) a ceramic or metal filled adhesive paste. Here, the term thermally conductive adhesive layer refers to a thermally conductive bonding layer between a leadframe and its underlying submount, and includes both a metal braze layer and a ceramic or metal filled adhesive paste.

[0064] Although embodiments of the present invention have been described above with reference to a packaged electronic device including a power semiconductor die, it will be understood that embodiments of the present invention are not so limited. For example, all of the embodiments disclosed herein may include one or more radio frequency ("RF") semiconductor dies in place of the power semiconductor die. For example, the semiconductor die included in the packaged electronic device may include a high electron mobility transistor ("HEMT") amplifier designed to amplify an RF signal.

[0065] The embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the present invention are shown. It will be understood, however, that the present invention may be embodied in many different forms and should not be construed as being limited to the above-described embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0066] Terms such as first, second, etc. may be used throughout this specification to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0067] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0068] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it can be directly on or extending directly onto the other element, or intervening elements may be present. When an element is referred to as being "attached," "connected," or "coupled" to another element, it will also be understood that it can be directly attached, connected, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly attached," "directly connected," or "directly coupled" to another element, there are no intervening elements present.

[0069] Relative terms such as "lower" or "upper" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation shown in the figures.

[0070] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected.

[0071] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. a power semiconductor die having a first terminal and a second terminal; a leadframe including a bottom surface and a top surface including a die pad area; a first lead and a second lead; A dielectric substrate; a lower metal cladding layer on a lower surface of the dielectric substrate; a lower metal braze layer between the lower metal cladding layer and the dielectric substrate; an upper metal cladding layer on a top surface of the dielectric substrate; an upper metallic braze layer between the dielectric substrate and the upper metallic clad layer; a substrate attachment material, comprising a solder or sintered material, between the upper metal clad layer and the lead frame; 1. A packaged electronic device comprising: A packaged electronic device, wherein the power semiconductor die is on the die pad area of ​​the leadframe, and the leadframe is on top of the substrate mounting material.

2. 2. The packaged electronic device of claim 1 , wherein the first lead is integral with the lead frame and is electrically connected to the first terminal of the power semiconductor die through the lead frame.

3. The packaged electronic device of claim 2 , wherein the dielectric substrate comprises a ceramic substrate.

4. 4. The packaged electronic device of claim 3, wherein the top metal braze layer is attached directly to the ceramic substrate and to a lower surface of the top metal clad layer.

5. 5. The packaged electronic device of claim 1, further comprising an overmolded package encapsulating a top and side surface of the power semiconductor die.

6. 6. The packaged electronic device of claim 1, wherein the leadframe and the lower metal cladding layer are formed of the same metal.

Images