Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device which is capable of reducing the stress to be generated in a capacitor due to a temperature change of the semiconductor device, thereby being capable of suppressing breakage of the capacitor. This semiconductor device is provided with an insulating substrate, a semiconductor element, a capacitor, a first lead having a surface, and a second lead having a surface; the insulating substrate is provided with an insulating layer and a conductor pattern that is provided on the insulating layer; the semiconductor element is bonded onto the conductor pattern; the first lead is electrically connected to the semiconductor element; the surface of the first lead and the surface of the second lead face each other; the capacitor is positioned between the surface of the first lead and the surface of the second lead facing each other; and the capacitor is connected to the first lead and the second lead.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 008424 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device having a capacitor, there is a possibility that a temperature change in the semiconductor device will cause stress in the capacitor, resulting in damage to the capacitor. In conventional semiconductor devices, such a problem has not been sufficiently taken into consideration.

[0005] The present disclosure is made to solve the above problems, and has an object to provide a semiconductor device that can reduce the stress generated in a capacitor due to temperature changes in the semiconductor device, thereby suppressing damage to the capacitor. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure comprises an insulating substrate, a semiconductor element, a capacitor, a first lead having a surface, and a second lead having a surface, the insulating substrate comprises an insulating layer and a conductor pattern provided on the insulating layer, the semiconductor element is bonded onto the conductor pattern, the first lead is electrically connected to the semiconductor element, the surface of the first lead and the surface of the second lead face each other, the capacitor is located between the surfaces of the first lead and the second lead that face each other, and the capacitor is connected to the first lead and the second lead.Cage , A first metal terminal and a second metal terminal are attached to the capacitor, the first metal terminal contacting the side opposite to the surface of the first lead, and the second metal terminal contacting the side opposite to the surface of the second lead, thereby sandwiching the first lead and the second lead between the first metal terminal and the second metal terminal. It is a semiconductor device.

Advantages of the Invention

[0007] According to the present disclosure, a semiconductor device is provided that can reduce the stress generated in a capacitor due to a temperature change in the semiconductor device, thereby suppressing damage to the capacitor.

[0008] Also, the objects, features, aspects, and advantages related to the technology disclosed in the present specification will become more apparent from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0009] [Figure 1] It is a top view showing the semiconductor device of Embodiment 1. [Diagram 2] It is a side view showing the semiconductor device of Embodiment 1. [Diagram 3] It is a top view showing the semiconductor device of Embodiment 2. [Figure 4] It is a side view showing the semiconductor device of Embodiment 2. [Diagram 5] It is a cross-sectional view of the semiconductor device of Embodiment 2 taken along line A-A of FIG. 3. [Figure 6] It is a top view showing the semiconductor device of Embodiment 3. [Figure 7] It is a top view showing the semiconductor device of Embodiment 4. [Figure 8] It is a cross-sectional view of the semiconductor device of Embodiment 4 taken along line B-B of FIG. 7. [Figure 9] It is a flowchart showing the manufacturing method of the semiconductor device of Embodiment 2.

Modes for Carrying Out the Invention

[0010] <A. Embodiment 1> <A-1. Configuration> Fig. 1 is a top view showing a semiconductor device 101 according to the first embodiment. Fig. 2 is a side view showing the semiconductor device 101 according to the first embodiment.

[0011] The semiconductor device 101 includes a semiconductor element 1 , a solder 2 , an insulating substrate 6 , a wire 7 , a wire 8 , a wire 9 , a base plate 10 , a solder 11 , a lead 12 a , a lead 12 b , a lead 13 , a lead 14 , and a capacitor 15 .

[0012] The insulating substrate 6 includes an insulating layer 4, a conductive pattern 3 provided on one main surface of the insulating layer 4, and a conductive pattern 5 provided on the other main surface of the insulating layer 4.

[0013] The conductor pattern 5 is joined to the base plate 10 via the solder 11. In other words, the insulating substrate 6 is joined onto the base plate 10 via the solder 11.

[0014] The insulating substrate 6 may not include the conductive pattern 5. In that case, the insulating layer 4 is joined to the base plate 10. The insulating layer 4 is directly joined to the base plate 10, for example. The base plate 10 and the insulating substrate 6 may be integrated by directly joining the insulating layer 4 to the base plate 10. The base plate 10 is attached to a cooling fin, for example.

[0015] The semiconductor element 1 is a switching element. For example, the semiconductor element 1 is a bipolar transistor, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated-Gate Bipolar Transistor), or an RC-IGBT (Reverse-Conducting IGBT). Although FIG. 1 shows a case where the semiconductor device 101 includes one semiconductor element (i.e., the semiconductor element 1), the semiconductor device 101 may include multiple semiconductor elements. For example, the semiconductor device 101 may include multiple switching elements. Also, for example, the semiconductor device 101 may include a switching element and a diode.

[0016] Conductive pattern 3 includes conductive pattern 3a, conductive pattern 3b, conductive pattern 3c, and conductive pattern 3d.

[0017] The semiconductor element 1 is joined onto the conductor pattern 3b via the solder 2. In other words, the semiconductor element 1 is joined onto the conductor pattern 3 via the solder 2.

[0018] The semiconductor element 1 includes a signal electrode 1a and a power electrode 1b.

[0019] The signal electrode 1a is an electrode for inputting a signal that controls the on / off of the semiconductor element 1, which is a switching element, to the semiconductor element 1. The signal electrode 1a is a gate electrode when the semiconductor element 1 is a MOSFET or an IGBT. The signal electrode 1a is a base electrode when the semiconductor element 1 is a bipolar transistor.

[0020] The power electrode 1b is an emitter electrode when the semiconductor element 1 is an IGBT or a bipolar transistor, and is a source electrode when the semiconductor element 1 is a MOSFET.

[0021] The power electrode 1b and the conductor pattern 3a are connected by a wire 7. The power electrode 1b and the conductor pattern 3c are connected by a wire 8. The signal electrode 1a and the conductor pattern 3d are connected by a wire 9.

[0022] Lead 12a is joined to conductor pattern 3a. Lead 12b is joined to conductor pattern 3b. Lead 13 is joined to conductor pattern 3c. Lead 14 is joined to conductor pattern 3d. Leads 12a, 12b, 13, and 14 may each be joined to conductor pattern 3 via a bonding material (not shown) such as solder, or may be joined directly to conductor pattern 3.

[0023] Leads 12a and 12b are power leads.

[0024] Leads 13 and 14 are signal leads.

[0025] The lead 13 is electrically connected to the power electrode 1b via the conductor pattern 3c and the wire 8. The potential of the power electrode 1b can be detected from outside the semiconductor device 101 via the lead 13.

[0026] The lead 14 is electrically connected to the signal electrode 1a via the conductor pattern 3d and the wire 9. A gate signal for controlling the semiconductor element 1 can be input to the semiconductor element 1 from outside the semiconductor device 101 via the lead 14.

[0027] Lead 13 has a surface 130. Lead 14 has a surface 140.

[0028] The leads 13 and 14 are, for example, flat leads. The faces 130 and 140 are, for example, the main faces of the flat leads 13 and 14, respectively, and extend with a certain width.

[0029] The leads 13 and 14 are arranged such that the surfaces 130 and 140 face each other. The surfaces 130 and 140 face each other in the in-plane direction of the insulating substrate 6.

[0030] The capacitor 15 is, for example, a ceramic capacitor. By using a ceramic capacitor as the capacitor 15, the performance of the semiconductor device 101 can be easily improved.

[0031] Capacitor 15 is disposed between surface 130 and surface 140. Capacitor 15 is connected to lead 13 and lead 14.

[0032] Capacitor 15 is bonded to surfaces 130 and 140 by a bonding material (not shown) such as solder, for example.

[0033] One electrode (not shown) of capacitor 15 is electrically connected to lead 13 , and the other electrode (not shown) of capacitor 15 is electrically connected to lead 14 .

[0034] When capacitor 15 is mounted on conductor pattern 3, deformation of insulating substrate 6 due to temperature change may cause stress in capacitor 15, which may result in damage to capacitor 15. When capacitor 15 is mounted on conductor pattern 3, base plate 10 may be significantly deformed due to temperature change, and this deformation is transmitted to capacitor 15 via deformation of insulating substrate 6, causing large stress in capacitor 15.

[0035] In semiconductor device 101 of the present embodiment, capacitor 15 is mounted between leads 13 and 14, and therefore the effect of deformation of insulating substrate 6 on capacitor 15 is suppressed, and stress generated in capacitor 15 is reduced. This suppresses damage to capacitor 15, and improves the reliability of semiconductor device 101.

[0036] If capacitor 15 is connected to leads 13 and 14 at a position away from insulating substrate 6, the stress generated in capacitor 15 due to deformation of insulating substrate 6 can be further reduced. Capacitor 15 may be located, for example, at a distance from insulating substrate 6 that is equal to or greater than the distance between faces 130 and 140. Capacitor 15 may be located, for example, at a distance from insulating substrate 6 that is equal to or greater than twice the distance between faces 130 and 140.

[0037] By reducing the stress generated in capacitor 15, it becomes possible to use a capacitor having low mechanical strength as capacitor 15.

[0038] The semiconductor element 1 is, for example, a semiconductor element using either a silicon semiconductor or a wide bandgap semiconductor. The wide bandgap semiconductor is a semiconductor having a larger bandgap than the silicon semiconductor. The wide bandgap semiconductor is, for example, a SiC semiconductor or a GaN semiconductor. When the semiconductor element 1 is a semiconductor using a wide bandgap semiconductor, the semiconductor device 101 can operate at high speed. Further, when the semiconductor element 1 is a semiconductor using a wide bandgap semiconductor, it can operate at a higher temperature than when the semiconductor element 1 is a semiconductor using a silicon semiconductor. When the semiconductor element operates at a high temperature, the insulating substrate 6 is likely to be deformed, but in the semiconductor device 101 of the present embodiment, the influence of the deformation of the insulating substrate 6 on the capacitor 15 is suppressed, and the damage of the capacitor 15 is suppressed.

[0039] In the present embodiment, the case where the two leads (that is, lead 13 and lead 14) to which the capacitor 15 is connected are electrically connected to the same semiconductor element (that is, semiconductor element 1) has been described as an example. However, for example, one of the two leads to which the capacitor 15 is connected may be electrically connected to the semiconductor element 1, and the other may be drawn out to the outside of the semiconductor device 101 without being electrically connected to the semiconductor element 1. Further, for example, the two leads to which the capacitor 15 is connected may be electrically connected to different semiconductor elements, respectively. Further, for example, the capacitor 15 may be connected to a power lead.

[0040] In the semiconductor device 101, the semiconductor element 1 and the capacitor 15 may be sealed with a sealing material, and the semiconductor device 101 may include a case that houses the semiconductor element 1 inside.

[0041] <B. Embodiment 2> <B-1. Configuration> FIG. 3 is a top view showing the semiconductor device 102 of Embodiment 2. FIG. 4 is a side view showing the semiconductor device 102 of Embodiment 2. FIG. 5 is a cross-sectional view taken along line A-A of FIG. 3.

[0042] Semiconductor device 102 differs from semiconductor device 101 of embodiment 1 in that it includes case 16, and the positions of leads 13 and 14 are regulated by case 16. Semiconductor device 102 also differs from semiconductor device 101 of embodiment 1 in that semiconductor element 1 and capacitor 15 are encapsulated by encapsulant 17. In other respects, semiconductor device 102 of the present embodiment is similar to semiconductor device 101 of embodiment 1.

[0043] In Fig. 3, for ease of viewing, the sealing material 17 is omitted. In Fig. 4, for ease of viewing, only a portion of the case 16 is shown, and the sealing material 17 is shown so as not to hide other elements.

[0044] The positions of the leads 13 and 14 are restricted by the case 16 to positions where the capacitor 15 can be mounted between the leads 13 and 14. This makes it possible to suppress changes in the distance between the leads 13 and 14, making it easier to mount the capacitor 15 between the leads 13 and 14 during manufacturing. In addition, the efficiency of tasks such as checking the position where the capacitor 15 is to be mounted is improved. This improves productivity and yield. In addition, the quality of the semiconductor device 102 is improved by preventing the leads 13 and 14 from being misaligned.

[0045] The leads 13 and 14 are, for example, insert-molded into the case 16 , so that the positions of the leads 13 and 14 are regulated by the case 16 .

[0046] A protrusion 160 is provided on the inner peripheral surface of case 16, protruding toward the inside of case 16. Lead 13 faces protrusion 160 on the side opposite surface 130, and lead 14 faces protrusion 160 on the side opposite surface 140. Protrusion 160 regulates the positions of leads 13 and 14.

[0047] In FIGS. 3 to 5, a case where one convex portion is provided on the inner peripheral surface of the case 16 is shown, but a plurality of convex portions may be provided on the inner peripheral surface of the case 16, and the convex portion with which the lead 13 faces on the side opposite to the surface 130 may be different from the convex portion with which the lead 14 faces on the side opposite to the surface 140.

[0048] The positions of the lead 13 and the lead 14 may be regulated by insert molding the lead 13 and the lead 14 into the case 16, or the positions of the lead 13 and the lead 14 may be regulated by the convex portion 160.

[0049] Also in this embodiment, since the capacitor 15 is mounted between the lead 13 and the lead 14, the stress generated in the capacitor 15 due to the temperature change of the semiconductor device 102 is reduced, the breakage of the capacitor 15 is suppressed, and the reliability of the semiconductor device 102 is improved.

[0050] <B-2. Manufacturing method> FIG. 9 is a flowchart showing an example of a method for manufacturing a semiconductor device according to this embodiment.

[0051] First, the insulating substrate 6 and the base plate 10 are joined (step S1). Next, the semiconductor element 1 is joined to the insulating substrate 6 (step S2). Next, wiring is performed using the wires 7, 8, and 9 (step S3).

[0052] Next, the leads 13 and 14 are insert molded into the case 16 in such an arrangement that the surfaces 130 and 140 face each other (step S4). At this time, the leads 13 and 14 are arranged at positions where the capacitor 15 can be mounted between the leads 13 and 14.

[0053] Next, the capacitor 15 is connected to the leads 13 and 14, and the capacitor 15 is mounted between the leads 13 and 14 (step S5). Next, the case 16 is attached to the base plate 10 (step S6). Next, the semiconductor element 1 and the capacitor 15 are sealed with the sealing material 17 (step S6).

[0054] Through the above processes, the semiconductor device 102 is obtained. Step S4 and step S5 may be performed before step S1, S2, and S3, or may be performed in parallel with step S1, S2, and S3. Also, step S5 may be performed after step S6 is performed.

[0055] <C. Embodiment 3> FIG. 6 is a top view showing the semiconductor device 103 of Embodiment 3.

[0056] In the semiconductor device 103, the lead 13 includes a guide 13a protruding in a direction perpendicular to the surface from the surface 130. Also, in the semiconductor device 103, the lead 14 includes a guide 14a protruding in a direction perpendicular to the surface from the surface 140. The semiconductor device 103 is the same as the semiconductor device 101 of Embodiment 1 except for these points.

[0057] The guide 13a faces the capacitor 15 in the in-plane direction of the surface 130. The guide 14a faces the capacitor 15 in the in-plane direction of the surface 140.

[0058] The guide 13a and the guide 14a are located between the capacitor 15 and the insulating substrate 6.

[0059] In the semiconductor device 103, since the guide 13a is provided on the lead 13 and the guide 14a is provided on the lead 14, a pocket for mounting the capacitor 15 is formed.

[0060] When manufacturing the semiconductor device 103, the position of the capacitor 15 in the in-plane direction of the surface 130 or the surface 140 is regulated by the guide 13a and the guide 14a. Thereby, when mounting the capacitor 15 on the lead 13 and the lead 14, the positioning of the capacitor 15 becomes easy, and the working efficiency is improved. Also, since it is not necessary to support the capacitor 15 with a jig or the like, the limitation on the place where the capacitor 15 is mounted is relaxed.

[0061] In this embodiment, the case where the lead 13 includes the guide 13a and the lead 14 includes the guide 14a has been described. However, either the lead 13 may include the guide 13a or the lead 14 may include the guide 14a.

[0062] Also in this embodiment, since the capacitor 15 is mounted between the lead 13 and the lead 14, the stress generated in the capacitor 15 due to the temperature change of the semiconductor device is reduced, the breakage of the capacitor 15 is suppressed, and the reliability of the semiconductor device 103 is improved.

[0063] In the semiconductor device 103, the semiconductor element 1 and the capacitor 15 may be sealed with a sealing material, and the semiconductor device 103 may include a case that houses the semiconductor element 1 inside. Similar to the semiconductor device 102 of Embodiment 2, the semiconductor device 103 may include a case 16 that regulates the positions of the lead 13 and the lead 14.

[0064] <D. Embodiment 4> FIG. 7 is a top view showing the semiconductor device 104 of Embodiment 4. FIG. 8 is a cross-sectional view of the semiconductor device 104 taken along line B-B of FIG. 7.

[0065] The semiconductor device 104 is different from the semiconductor device 101 of Embodiment 1 in that the capacitor 15 is connected to the lead 13 and the lead 14 via the metal terminals 18. The semiconductor device 104 is the same as the semiconductor device 101 of Embodiment 1 in other respects.

[0066] Two metal terminals 18 are attached to the capacitor 15. The two metal terminals 18 are attached to the capacitor 15 via a bonding material (not shown) such as solder, for example.

[0067] The two metal terminals 18 each include a pressing portion 18a. The pressing portion 18a has a convex shape toward the capacitor 15, for example, as shown in FIG. 8.

[0068] Pressing portion 18a of one metal terminal 18 contacts surface 131 opposite surface 130 of lead 13, and pressing portion 18a of the other metal terminal 18 contacts surface 141 opposite surface 140 of lead 14. This causes leads 13 and 14 to be sandwiched between the two metal terminals 18, and also electrically connects capacitor 15 to leads 13 and 14. Capacitor 15 and lead 13, and capacitor 15 and lead 14 are electrically connected via metal terminals 18, respectively. Metal terminal 18 may or may not contact surface 130 and surface 140.

[0069] When manufacturing semiconductor device 104, metal terminals 18 are attached to capacitor 15, and then capacitor 15 is mounted between leads 13 and 14 by sandwiching leads 13 and 14 with metal terminals 18, thereby making it possible to electrically connect capacitor 15 to leads 13 and 14.

[0070] Before capacitor 15 is attached to leads 13 and 14, the distance between pressing portions 18a of two metal terminals 18 attached to capacitor 15 is shorter than the distance between surface 131 of lead 13 and surface 141 of lead 14, for example, as shown by the dashed line in Fig. 8. The two pressing portions 18a sandwich leads 13 and 14 using elastic force, so that when capacitor 15 is attached to leads 13 and 14, electrical connection between capacitor 15 and leads 13 and 14 can be more reliably established.

[0071] The metal terminal 18 and the leads 13 and 14 may be joined via a joining material such as solder.

[0072] In this embodiment as well, by mounting capacitor 15 between lead 13 and lead 14, the stress generated in capacitor 15 is reduced, damage to capacitor 15 is suppressed, and the reliability of semiconductor device 104 is improved.

[0073] In semiconductor device 104, semiconductor element 1 and capacitor 15 may be sealed with a sealing material, and semiconductor device 104 may include a case that houses semiconductor element 1. Semiconductor device 104 may include case 16 that regulates the positions of leads 13 and 14, similar to semiconductor device 102 of the second embodiment.

[0074] Also in the semiconductor device 104 of this embodiment, the leads 13 may be provided with guides 13a, and the leads 14 may be provided with guides 14a.

[0075] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0076] 1 semiconductor element, 1a signal electrode, 1b power electrode, 2 solder, 3,3a,3b,3c,3d conductor pattern, 4 insulating layer, 5 conductor pattern, 6 insulating substrate, 7,8,9 wire, 10 base plate, 12a,12b,13,14 leads, 13a,14a guides, 15 capacitor, 16 case, 17 sealing material, 18 metal terminal, 18a pressing portion, 101,102,103,104 semiconductor device, 130,131,140,141 surfaces, 160 convex portion.

Claims

1. An insulating substrate; A semiconductor element; A capacitor; a first lead having a surface; a second lead having a surface; Equipped with the insulating substrate includes an insulating layer and a conductor pattern provided on the insulating layer; the semiconductor element is bonded onto the conductor pattern, the first lead is electrically connected to the semiconductor element; the surface of the first lead and the surface of the second lead face each other, the capacitor is located between the surface of the first lead and the surface of the second lead that face each other, the capacitor is connected to the first lead and the second lead; The capacitor has a first metal terminal and a second metal terminal attached thereto; the first metal terminal contacts the first lead on a side opposite to the surface thereof, and the second metal terminal contacts the second lead on a side opposite to the surface thereof, thereby sandwiching the first lead and the second lead between the first metal terminal and the second metal terminal; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the surface of the first lead and the surface of the second lead face each other in an in-plane direction of the insulating substrate; Semiconductor device.

3. 3. The semiconductor device according to claim 1, the second lead is electrically connected to the semiconductor element; Semiconductor device.

4. 4. The semiconductor device according to claim 3, the semiconductor element is a switching element, the semiconductor element includes a power electrode and a signal electrode; the signal electrodes are electrodes for signals that control on / off of the semiconductor element, the first lead is electrically connected to the power electrode; the second lead is electrically connected to the signal electrode; Semiconductor device.

5. 5. The semiconductor device according to claim 1, a guide is formed on the first lead, protruding in a direction perpendicular to the surface of the first lead and facing the capacitor in an in-plane direction of the surface of the first lead, or a guide is formed on the second lead, protruding in a direction perpendicular to the surface of the second lead and facing the capacitor in an in-plane direction of the surface of the second lead, or both of them. Semiconductor device.

6. 6. The semiconductor device according to claim 1, Further comprising a base plate, The insulating substrate is bonded onto a base plate. Semiconductor device.

7. 7. The semiconductor device according to claim 1, The semiconductor element is a semiconductor element including a SiC semiconductor. Semiconductor device.

8. 8. The semiconductor device according to claim 1, Further comprising a case for accommodating the semiconductor element therein, the first lead and the second lead are insert-molded into the case; Semiconductor device.

9. 8. The semiconductor device according to claim 1, Further comprising a case for accommodating the semiconductor element therein, At least one protrusion protruding toward the inside of the case is provided on an inner peripheral surface of the case, the first lead faces any one of the at least one protrusions on a side opposite to the surface of the first lead, the second lead faces any one of the at least one protrusions on a side opposite to the surface of the second lead; Semiconductor device.

10. 10. The semiconductor device according to claim 9, the first lead and the second lead are insert-molded into the case; Semiconductor device.

11. A method for manufacturing the semiconductor device according to any one of claims 1 to 7, comprising the steps of: The semiconductor device further includes a case that houses the semiconductor element therein, the first lead and the second lead are insert-molded into the case in such a manner that the surface of the first lead and the surface of the second lead face each other; After the insert molding, the capacitor is connected to the first lead and the second lead. A method for manufacturing a semiconductor device.

12. A method for manufacturing the semiconductor device according to any one of claims 8 to 10, comprising the steps of: the first lead and the second lead are insert-molded into the case in such a manner that the surface of the first lead and the surface of the second lead face each other; After the insert molding, the capacitor is connected to the first lead and the second lead. A method for manufacturing a semiconductor device.

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