Detection device, fingerprint detection device and vein detection device

Abstract

To provide a detection device, a fingerprint detection device, and a vein detection device capable of improving the detection accuracy.SOLUTION: A detection device includes: optical sensors arranged in matrix; a plurality of switching elements, gate lines, and signal lines corresponding to the optical sensors; and a detection circuit that is supplied with signals from the optical sensors through the signal lines, column by column, in a predetermined order, in a reading period of a predetermined row. A drive signal is supplied to the gate lines row by row to bring the switching elements belonging to the predetermined row into a coupled state. A reset potential is supplied to the optical sensors and the signal lines belonging to the predetermined row after completion of the reading period of the predetermined row and before start of the reading period of a row next to the predetermined row.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present invention relates to a detection device, a fingerprint detection device, and a vein detection device. [Background technology]

[0002] 2. Description of the Related Art Optical sensors capable of detecting fingerprint patterns and blood vessel patterns are known (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-32005 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a detection method in which a plurality of optical sensors are scanned and output signals are read out sequentially from the sensors, variations in the order of scanning or in the timing of resetting the optical sensors can cause variations in the detected output signals.

[0005] An object of the present invention is to provide a detection device, a fingerprint detection device, and a vein detection device that are capable of improving detection accuracy. [Means for solving the problem]

[0006] A detection device of one embodiment of the present invention has a plurality of optical sensors arranged in a matrix, a plurality of switching elements, a plurality of gate lines, and a plurality of signal lines provided corresponding to the plurality of optical sensors, a detection circuit to which signals from the plurality of optical sensors are supplied via the plurality of signal lines, and a signal line selection circuit that switches a connection state between the plurality of signal lines and the detection circuit, wherein a drive signal is supplied to the gate line for each row, and a plurality of the switching elements belonging to a predetermined row are connected, and during a readout period of the predetermined row, the signal line selection circuit connects the plurality of signal lines to the detection circuit in a predetermined order for each column, and after the readout period of the predetermined row is completed and before the readout period of the next row of the predetermined row begins, a reset potential is supplied to the plurality of optical sensors and the plurality of signal lines belonging to the predetermined row.

[0007] A fingerprint detection device according to one aspect of the present invention includes the above detection device and at least one light source.

[0008] A vein detection device according to one aspect of the present invention includes the detection device described above and at least one light source. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a detection device according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram showing the detection device. [Figure 4] FIG. 4 is a circuit diagram showing a plurality of partial detection areas. [Figure 5A] FIG. 5A is a cross-sectional view showing a schematic cross-sectional configuration of a sensor unit. [Figure 5B] FIG. 5B is a cross-sectional view showing a schematic cross-sectional configuration of a sensor unit of a detection device according to a first modified example. [Figure 6] FIG. 6 is a timing waveform diagram illustrating an example of the operation of the detection device of the comparative example. [Figure 7]FIG. 7 is a timing waveform diagram illustrating an example of operation during the reset period in FIG. [Figure 8] FIG. 8 is a timing waveform diagram showing an example of operation during the readout period in FIG. [Figure 9] FIG. 9 is a timing waveform diagram showing an example of operation during a driving period of one gate line included in the readout period in FIG. [Figure 10] FIG. 10 is an explanatory diagram for explaining the relationship between the driving of the sensor unit of the detection device of the comparative example and the lighting operation of the light source. [Figure 11] FIG. 11 is an explanatory diagram for explaining an operation example of the detection device according to the first embodiment. [Figure 12] FIG. 12 is a timing waveform diagram illustrating an example of the operation of the detection device according to the first embodiment. [Figure 13] FIG. 13 is an image that illustrates the detection result of the detection device of the comparative example. [Figure 14] FIG. 14 is an image that shows a schematic representation of the detection result of the detection device of the embodiment. [Figure 15] FIG. 15 is an explanatory diagram for explaining the relationship between the driving of the sensor unit of the detection device of the second modified example and the lighting operation of the light source. [Figure 16] FIG. 16 is an explanatory diagram that illustrates a schematic relationship between the detection device of the second modified example and a light source. [Figure 17] FIG. 17 is a flowchart showing an operation example of the detection device according to the second embodiment. [Figure 18] FIG. 18 is a table showing the order of signal line connections for each detection of one frame. [Figure 19] FIG. 19 is a timing waveform diagram illustrating an example of the operation of the detection device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The form (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiment. In addition, the components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0011] (First embodiment) Fig. 1 is a plan view showing a detection device according to a first embodiment. As shown in Fig. 1, the detection device 1 has a sensor substrate 21, a sensor unit 10, a gate line driving circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 122, a power supply circuit 123, a first light source substrate 51, a second light source substrate 52, a first light source 61, and a second light source 62. A plurality of first light sources 61 are provided on the first light source substrate 51. A plurality of second light sources 62 are provided on the second light source substrate 52.

[0012] The control board 121 is electrically connected to the sensor base material 21 via a flexible printed circuit board 71. The flexible printed circuit board 71 is provided with a detection circuit 48. The control board 121 is provided with a control circuit 122 and a power supply circuit 123. The control circuit 122 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 122 supplies control signals to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The control circuit 122 also supplies control signals to the first light source 61 and the second light source 62 to control the lighting or non-lighting of the first light source 61 and the second light source 62. The power supply circuit 123 supplies voltage signals such as a sensor power supply signal VDDSNS (see FIG. 4) to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16. The power supply circuit 123 also supplies a power supply voltage to the first light source 61 and the second light source 62.

[0013] The sensor substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area in which a plurality of optical sensors PD (see FIG. 4) of the sensor unit 10 are provided. The peripheral area GA is an area between the outer periphery of the detection area AA and an end of the sensor substrate 21, in which the optical sensors PD are not provided.

[0014] The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0015] The first direction Dx is a direction in a plane parallel to the sensor substrate 21. The second direction Dy is a direction in a plane parallel to the sensor substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction of the sensor substrate 21.

[0016] The multiple first light sources 61 are provided on the first light source substrate 51 and arranged along the second direction Dy. The multiple second light sources 62 are provided on the second light source substrate 52 and arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123 via terminal portions 124 and 125 provided on the control board 121, respectively.

[0017] The first light sources 61 and the second light sources 62 are, for example, inorganic light emitting diodes (LEDs) or organic light emitting diodes (OLEDs). The first light sources 61 and the second light sources 62 emit first light and second light of different wavelengths, respectively.

[0018] The first light emitted from the first light source 61 is mainly reflected by the surface of the object to be detected such as the finger Fg and enters the sensor unit 10. As a result, the sensor unit 10 can detect a fingerprint by detecting the shape of the projections and recesses on the surface of the finger Fg. The second light emitted from the second light source 62 is mainly reflected inside the finger Fg or passes through the finger Fg and enters the sensor unit 10. As a result, the sensor unit 10 can detect information about a living body inside the finger Fg. The information about a living body is, for example, a pulse wave, a pulse, a blood vessel image, etc. of the finger Fg or the palm. That is, the detection device 1 may be configured as a fingerprint detection device that detects a fingerprint, or a vein detection device that detects a blood vessel pattern such as a vein.

[0019] The first light may have a wavelength of 500 nm or more and 600 nm or less, for example, about 550 nm, and the second light may have a wavelength of 780 nm or more and 950 nm or less, for example, about 850 nm. In this case, the first light is blue or green visible light, and the second light is infrared light. The sensor unit 10 can detect a fingerprint based on the first light emitted from the first light source 61. The second light emitted from the second light source 62 is reflected inside the detection object such as a finger Fg or transmitted / absorbed by the finger Fg or the like and enters the sensor unit 10. As a result, the sensor unit 10 can detect a pulse wave or a blood vessel image (blood vessel pattern) as information about the living body inside the finger Fg or the like.

[0020] Alternatively, the first light may have a wavelength of 600 nm or more and 700 nm or less, for example, about 660 nm, and the second light may have a wavelength of 780 nm or more and 900 nm or less, for example, about 850 nm. In this case, based on the first light emitted from the first light source 61 and the second light emitted from the second light source 62, the sensor unit 10 can detect information about the living body, such as a pulse wave, a pulse rate, and a blood vessel image, as well as blood oxygen saturation. In this way, since the detection device 1 has the first light source 61 and a plurality of second light sources 62, it can detect various information about the living body by performing detection based on the first light and detection based on the second light.

[0021] The arrangement of the first light source 61 and the second light source 62 shown in FIG. 1 is merely an example and can be changed as appropriate. The detection device 1 is provided with a plurality of types of light sources (the first light source 61 and the second light source 62) as the light source. However, this is not limited to this, and the light source may be of one type. For example, a plurality of first light sources 61 and a plurality of second light sources 62 may be arranged on each of the first light source substrate 51 and the second light source substrate 52. Furthermore, the number of light source substrates on which the first light source 61 and the second light source 62 are arranged may be one or three or more. Alternatively, it is sufficient that at least one or more light sources are arranged.

[0022] Fig. 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. As shown in Fig. 2, the detection device 1 further includes a detection control unit 11 and a detection unit 40. A part or all of the functions of the detection control unit 11 are included in a control circuit 122. In addition, a part or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 122.

[0023] The sensor unit 10 has a plurality of optical sensors PD. The optical sensors PD of the sensor unit 10 are photodiodes, and output an electrical signal corresponding to irradiated light as a detection signal Vdet to the signal line selection circuit 16. The sensor unit 10 also performs detection according to a gate drive signal Vgcl supplied from the gate line drive circuit 15.

[0024] The detection control unit 11 is a circuit that supplies control signals to the gate line driving circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control unit 11 supplies various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, to the gate line driving circuit 15. The detection control unit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16. The detection control unit 11 also supplies various control signals to the first light source 61 and the second light source 62, and controls the lighting and non-lighting of each of them.

[0025] The gate line driving circuit 15 is a circuit that drives a plurality of gate lines GCL (see FIG. 3) based on various control signals. The gate line driving circuit 15 sequentially or simultaneously selects the plurality of gate lines GCL, and supplies a gate driving signal Vgcl to the selected gate lines GCL. In this way, the gate line driving circuit 15 selects a plurality of photosensors PD connected to the gate lines GCL.

[0026] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL (see FIG. 3). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected signal line SGL to the detection circuit 48 based on a selection signal ASW supplied from the detection control unit 11. As a result, the signal line selection circuit 16 outputs a detection signal Vdet of the optical sensor PD to the detection unit 40.

[0027] The detection unit 40 includes a detection circuit 48, a signal processing unit 44, a coordinate extraction unit 45, a storage unit 46, a detection timing control unit 47, an image processing unit 49, and an output processing unit 50. Based on a control signal supplied from the detection control unit 11, the detection timing control unit 47 controls the detection circuit 48, the signal processing unit 44, the coordinate extraction unit 45, and the image processing unit 49 so that they operate in synchronization with each other.

[0028] The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier 42 and an A / D converter 43. The detection signal amplifier 42 amplifies the detection signal Vdet. The A / D converter 43 converts the analog signal output from the detection signal amplifier 42 into a digital signal.

[0029] The signal processing unit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on an output signal from the detection circuit 48. When the finger Fg is in contact with or close to the detection surface, the signal processing unit 44 can detect unevenness on the surface of the finger Fg or the palm based on a signal from the detection circuit 48. The signal processing unit 44 can also detect information about the living body based on a signal from the detection circuit 48. The information about the living body is, for example, a blood vessel image of the finger Fg or the palm, a pulse wave, a pulse rate, a blood oxygen concentration, etc.

[0030] Furthermore, the signal processing unit 44 may acquire detection signals Vdet (information about the living body) simultaneously detected by a plurality of optical sensors PD and execute a process of averaging these signals. In this case, the detection unit 40 can suppress measurement errors caused by noise and relative positional deviation between the detection object such as a finger Fg and the sensor unit 10, enabling stable detection.

[0031] The storage unit 46 temporarily stores the signal calculated by the signal processing unit 44. The storage unit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0032] The coordinate extraction unit 45 is a logic circuit that determines the detection coordinates of the unevenness of the surface of the finger or the like when the contact or proximity of the finger is detected in the signal processing unit 44. The coordinate extraction unit 45 is also a logic circuit that determines the detection coordinates of the blood vessels of the finger Fg or the palm. The image processing unit 49 combines the detection signals Vdet output from each optical sensor PD of the sensor unit 10 to generate two-dimensional information indicating the shape of the unevenness of the surface of the finger Fg or the like and two-dimensional information indicating the shape of the blood vessels of the finger Fg or the palm. The coordinate extraction unit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates. The coordinate extraction unit 45 and the image processing unit 49 may not be included in the detection unit 40.

[0033] The output processing unit 50 functions as a processing unit that performs processing based on the outputs from the multiple optical sensors PD. Specifically, the output processing unit 50 of the embodiment outputs a sensor output Vo including at least pulse wave data based on at least the detection signal Vdet acquired via the signal processing unit 44. In the embodiment, the signal processing unit 44 outputs data indicating the change (amplitude) of the output of the detection signal Vdet of each optical sensor PD described later, and the output processing unit 50 determines which output is adopted as the sensor output Vo, but both of these may be performed by the signal processing unit 44 or the output processing unit 50. Note that the output processing unit 50 may include the detection coordinates obtained by the coordinate extraction unit 45, the two-dimensional information generated by the image processing unit 49, and the like in the sensor output Vo. In addition, the function of the output processing unit 50 may be integrated into another configuration (for example, the image processing unit 49, etc.).

[0034] Next, an example of the circuit configuration of the detection device 1 will be described. Fig. 3 is a circuit diagram showing the detection device. As shown in Fig. 3, the sensor unit 10 has a plurality of partial detection areas PAA arranged in a matrix. Each of the partial detection areas PAA is provided with an optical sensor PD.

[0035] The gate lines GCL extend in a first direction Dx and are connected to a plurality of partial detection areas PAA arranged in the first direction Dx. The plurality of gate lines GCL(1), GCL(2), ..., GCL(8) are arranged in a second direction Dy and are each connected to a gate line driving circuit 15. In the following description, when there is no need to distinguish between the plurality of gate lines GCL(1), GCL(2), ..., GCL(8), they are simply referred to as gate lines GCL. In addition, in FIG. 3, eight gate lines GCL are shown for ease of explanation, but this is merely an example, and M gate lines GCL (M is 8 or more, for example, M=256) may be arranged.

[0036] The signal line SGL extends in the second direction Dy and is connected to the photosensors PD of the partial detection areas PAA arranged in the second direction Dy. The signal lines SGL(1), SGL(2), ..., SGL(12) are arranged in the first direction Dx and are each connected to the signal line selection circuit 16 and the reset circuit 17. In the following description, when there is no need to distinguish between the signal lines SGL(1), SGL(2), ..., SGL(12), they will simply be referred to as signal lines SGL.

[0037] For ease of understanding, 12 signal lines SGL are shown, but this is merely an example, and N signal lines SGL (N is 12 or more, for example, N=252) may be arranged. In FIG. 3, the sensor unit 10 is provided between the signal line selection circuit 16 and the reset circuit 17. This is not limiting, and the signal line selection circuit 16 and the reset circuit 17 may be connected to ends of the signal lines SGL in the same direction. The effective area of ​​one sensor is, for example, substantially 50×50 um. 2 The resolution of the detection area AA is, for example, substantially 508 ppi, the number of sensors arranged in the detection area AA is, for example, 252 cells × 256 cells, and the area of ​​the detection area AA is, for example, 12.6 × 12.8 mm 2 It is said.

[0038] The gate line driving circuit 15 receives various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, from the control circuit 122 (see FIG. 1). The gate line driving circuit 15 sequentially selects the multiple gate lines GCL(1), GCL(2), ..., GCL(8) in a time-division manner based on the various control signals. The gate line driving circuit 15 supplies a gate driving signal Vgcl to the selected gate line GCL. As a result, the gate driving signal Vgcl is supplied to the multiple first switching elements Tr connected to the gate line GCL, and the multiple partial detection areas PAA arranged in the first direction Dx are selected as detection targets.

[0039] The gate line driving circuit 15 may perform different driving for each detection mode of the fingerprint detection and a plurality of different pieces of biometric information (pulse wave, pulse, blood vessel image, blood oxygen concentration, etc.) For example, the gate line driving circuit 15 may drive a plurality of gate lines GCL in a bundle.

[0040] The signal line selection circuit 16 has a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and a third switching element TrS. The plurality of third switching elements TrS are provided corresponding to the plurality of signal lines SGL, respectively. The six signal lines SGL(1), SGL(2), ..., SGL(6) are connected to a common output signal line Lout1. The six signal lines SGL(7), SGL(8), ..., SGL(12) are connected to a common output signal line Lout2. The output signal lines Lout1, Lout2 are each connected to a detection circuit 48.

[0041] Here, the signal lines SGL(1), SGL(2), ..., SGL(6) are defined as a first signal line block, and the signal lines SGL(7), SGL(8), ..., SGL(12) are defined as a second signal line block. The multiple selection signal lines Lsel are each connected to the gate of the third switching element TrS included in one signal line block. Furthermore, one selection signal line Lsel is connected to the gate of the third switching element TrS of multiple signal line blocks.

[0042] The control circuit 122 (see FIG. 1) sequentially supplies the selection signal ASW to the selection signal line Lsel. As a result, the signal line selection circuit 16 sequentially selects the signal lines SGL in one signal line block in a time-division manner by the operation of the third switching element TrS. The signal line selection circuit 16 also selects one signal line SGL from each of the multiple signal line blocks. With this configuration, the detection device 1 can reduce the number of ICs (Integrated Circuits) including the detection circuit 48 or the number of IC terminals. The signal line selection circuit 16 may also bundle multiple signal lines SGL together and connect them to the detection circuit 48.

[0043] As shown in Fig. 3, the reset circuit 17 has a reference signal line Lvr, a reset signal line Lrst, and a fourth switching element TrR. The fourth switching element TrR is provided corresponding to the multiple signal lines SGL. The reference signal line Lvr is connected to one of the sources or drains of the multiple fourth switching elements TrR. The reset signal line Lrst is connected to the gates of the multiple fourth switching elements TrR.

[0044] The control circuit 122 supplies a reset signal RST2 to the reset signal line Lrst. This turns on the multiple fourth switching elements TrR, and the multiple signal lines SGL are electrically connected to the reference signal line Lvr. The power supply circuit 123 supplies a reference signal COM to the reference signal line Lvr. This causes the reference signal COM to be supplied to the capacitive elements Ca (see FIG. 4) included in the multiple partial detection areas PAA.

[0045] FIG. 4 is a circuit diagram showing a plurality of partial detection areas. Note that FIG. 4 also shows the circuit configuration of a detection circuit 48. As shown in FIG. 4, the partial detection area PAA includes a light sensor PD, a capacitance element Ca, and a first switching element Tr. The capacitance element Ca is a capacitance (sensor capacitance) formed in the light sensor PD, and is equivalently connected in parallel with the light sensor PD. Furthermore, the signal line capacitance Cc is a parasitic capacitance formed in the signal line SGL, and is equivalently formed between the signal line SGL and the anode of the light sensor PD and one end side of the capacitance element Ca.

[0046] 4 shows two gate lines GCL(m) and GCL(m+1) arranged in the second direction Dy among the multiple gate lines GCL. Also, two signal lines SGL(n) and SGL(n+1) arranged in the first direction Dx among the multiple signal lines SGL. The partial detection area PAA is an area surrounded by the gate lines GCL and the signal lines SGL.

[0047] The first switching element Tr is provided corresponding to the photosensor PD. The first switching element Tr is configured of a thin film transistor, and in this example, is configured of an n-channel MOS (Metal Oxide Semiconductor) type TFT (Thin Film Transistor).

[0048] The gates of the first switching elements Tr belonging to the partial detection areas PAA aligned in the first direction Dx are connected to the gate line GCL. The sources of the first switching elements Tr belonging to the partial detection areas PAA aligned in the second direction Dy are connected to the signal line SGL. The drains of the first switching elements Tr are connected to the cathodes of the photosensors PD and the capacitive elements Ca.

[0049] A sensor power supply signal VDDSNS is supplied to the anode of the photosensor PD from the power supply circuit 123. In addition, a reference signal COM, which becomes the initial potential of the signal line SGL and the capacitive element Ca, is supplied from the power supply circuit 123 to the signal line SGL and the capacitive element Ca.

[0050] When light is irradiated onto the partial detection area PAA, a current corresponding to the amount of light flows through the photosensor PD, causing charge to accumulate in the capacitance element Ca. When the first switching element Tr is turned on, a current flows through the signal line SGL corresponding to the charge accumulated in the capacitance element Ca. The signal line SGL is connected to the detection circuit 48 via the third switching element TrS of the signal line selection circuit 16. This allows the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the photosensor PD for each partial detection area PAA or for each block unit PAG.

[0051] In the readout period Pdet (see FIG. 6), the switch SSW of the detection circuit 48 is turned on and connected to the signal line SGL. The detection signal amplifier 42 of the detection circuit 48 converts the fluctuation in current supplied from the signal line SGL into a fluctuation in voltage and amplifies it. A reference potential (Vref) having a fixed potential is input to the non-inverting input terminal (+) of the detection signal amplifier 42, and the signal line SGL is connected to the inverting input terminal (-). In the embodiment, a signal that is the same as the reference signal COM is input as the reference potential (Vref) voltage. The detection signal amplifier 42 also has a capacitance element Cb and a reset switch RSW. In the reset period Prst (see FIG. 6), the reset switch RSW is turned on and the charge of the capacitance element Cb is reset.

[0052] Next, the configuration of the optical sensor PD will be described. FIG. 5A is a cross-sectional view showing a schematic cross-sectional configuration of the sensor unit. As shown in FIG. 5A, the sensor unit 10 includes a sensor substrate 21, a TFT layer 22, an insulating layer 23, an optical sensor PD, and insulating layers 24a, 24b, 24c, and 25. The sensor substrate 21 is an insulating substrate, and for example, glass or a resin material is used. The sensor substrate 21 is not limited to a flat plate shape, and may have a curved surface. In this case, the sensor substrate 21 may be a film-like resin. The sensor substrate 21 has a first surface and a second surface opposite to the first surface. The TFT layer 22, the insulating layer 23, the optical sensor PD, and the insulating layers 24 and 25 are laminated in this order on the first surface.

[0053] The TFT layer 22 is provided with circuits such as the gate line driving circuit 15 and the signal line selection circuit 16 described above. The TFT layer 22 is also provided with TFTs (Thin Film Transistors) such as the first switching element Tr, and various wirings such as the gate line GCL and the signal line SGL. The sensor substrate 21 and the TFT layer 22 are a driving circuit board that drives a sensor for each predetermined detection area, and are also called a backplane or array substrate.

[0054] The insulating layer 23 is an organic insulating layer, and is provided on the TFT layer 22. The insulating layer 23 is a planarizing layer that planarizes unevenness formed by the first switching element Tr formed in the TFT layer 22 and various conductive layers.

[0055] The photosensor PD is provided on the insulating layer 23. The photosensor PD has a lower electrode 35, a semiconductor layer 31, and an upper electrode 34, which are laminated in this order.

[0056] The lower electrode 35 is provided on the insulating layer 23 and is electrically connected to the first switching element Tr of the TFT layer 22 through a contact hole H1. The lower electrode 35 is a cathode of the photosensor PD and is an electrode for reading out the detection signal Vdet. The lower electrode 35 is made of a metal material such as molybdenum (Mo) or aluminum (Al). Alternatively, the lower electrode 35 may be a laminated film in which a plurality of these metal materials are laminated. The lower electrode 35 may be made of a conductive material having translucency such as ITO (Indium Tin Oxide).

[0057] The semiconductor layer 31 is amorphous silicon (a-Si). The semiconductor layer 31 includes an i-type semiconductor layer 32a, a p-type semiconductor layer 32b, and an n-type semiconductor layer 32c. The i-type semiconductor layer 32a, the p-type semiconductor layer 32b, and the n-type semiconductor layer 32c are a specific example of a photoelectric conversion element. In FIG. 5A, the n-type semiconductor layer 32c, the i-type semiconductor layer 32a, and the p-type semiconductor layer 32b are stacked in this order in the direction perpendicular to the surface of the sensor substrate 21. However, the opposite configuration, that is, the p-type semiconductor layer 32b, the i-type semiconductor layer 32a, and the n-type semiconductor layer 32c may be used. The semiconductor layer 31 may also be a photoelectric conversion element made of an organic semiconductor.

[0058] The n-type semiconductor layer 32c is an n+ region formed by doping impurities into a-Si. The p-type semiconductor layer 32b is a p+ region formed by doping impurities into a-Si. The i-type semiconductor layer 32a is, for example, a non-doped intrinsic semiconductor and has lower conductivity than the p-type semiconductor layer 32b and the n-type semiconductor layer 32c.

[0059] The upper electrode 34 is an anode of the photosensor PD and is an electrode for supplying a power supply signal VDDSNS to the photoelectric conversion layer. The upper electrode 34 is a light-transmitting conductive layer such as ITO, and a plurality of upper electrodes are provided for each photosensor PD.

[0060] An insulating layer 24a and an insulating layer 24b are provided on the insulating layer 23. The insulating layer 24a covers the periphery of the upper electrode 34, and an opening is provided at a position where the insulating layer 24a overlaps with the upper electrode 34. The connection wiring 36 is connected to the upper electrode 34 at a portion of the upper electrode 34 where the insulating layer 24a is not provided. The insulating layer 24b is provided on the insulating layer 24a, covering the upper electrode 34 and the connection wiring 36. An insulating layer 24c, which is a planarizing layer, is provided on the insulating layer 24b. An insulating layer 25 is provided on the insulating layer 24c. However, the insulating layer 25 may be omitted.

[0061] 5B is a cross-sectional view showing a schematic cross-sectional configuration of a sensor unit of a detection device according to a first modification. As shown in FIG. 5B, in a detection device 1A of the first modification, an optical sensor PDA is provided on an insulating layer 23a. The insulating layer 23a is an inorganic insulating layer provided to cover the insulating layer 23, and is formed of, for example, silicon nitride (SiN). The optical sensor PDA has a photoelectric conversion layer 31A, a lower electrode 35 (cathode electrode), and an upper electrode 34 (anode electrode). In a direction perpendicular to the first surface S1 of the sensor substrate 21, the lower electrode 35, the photoelectric conversion layer 31A, and the upper electrode 34 are laminated in this order.

[0062] The photoelectric conversion layer 31A changes its characteristics (for example, voltage-current characteristics and resistance value) depending on the light irradiated thereto. An organic material is used as the material of the photoelectric conversion layer 31A. Specifically, the photoelectric conversion layer 31A is made of, for example, a low molecular weight organic material, C 60 (fullerene), PCBM (phenyl C61-butyric acid methyl ester), CuPc (copper phthalocyanine), F 16CuPc (fluorinated copper phthalocyanine), rubrene (5,6,11,12-tetraphenyltetracene), PDI (perylene derivative), etc. can be used.

[0063] The photoelectric conversion layer 31A can be formed by a vapor deposition (dry process) using these low molecular weight organic materials. In this case, the photoelectric conversion layer 31A is, for example, a laminated film of CuPc and F16CuPc, or a laminated film of rubrene and C 60 The photoelectric conversion layer 31A may be a laminated film of the above-mentioned low molecular weight organic material and the above-mentioned polymer organic material. In this case, the photoelectric conversion layer 31A is made of a material obtained by combining the above-mentioned low molecular weight organic material and the polymer organic material. As the polymer organic material, for example, P3HT (poly(3-hexylthiophene)), F8BT (F8-alt-benzothiadiazole), etc. may be used. The photoelectric conversion layer 31A may be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed.

[0064] The lower electrode 35 and the upper electrode 34 face each other with the photoelectric conversion layer 31A interposed therebetween. The upper electrode 34 is made of a conductive material having light transmission properties, such as indium tin oxide (ITO). The lower electrode 35 is made of a metal material, such as silver (Ag) or aluminum (Al). Alternatively, the lower electrode 35 may be made of an alloy material containing at least one of these metal materials.

[0065] By controlling the film thickness of the lower electrode 35, the lower electrode 35 can be formed as a semi-transparent electrode having translucency. For example, the lower electrode 35 has a translucency of about 60% by forming it from a thin Ag film having a film thickness of 10 nm. In this case, the optical sensor PDA can detect light irradiated from both sides of the sensor substrate 21, for example, light L1 irradiated from the first surface S1 side and light irradiated from the second surface S2 side.

[0066] 5B, a protective film 24 may be provided to cover the upper electrode 34. The protective film is a passivation film, and is provided to protect the photosensor PDA.

[0067] 5B, a first switching element Tr electrically connected to the photosensor PDA is provided in the TFT layer 22. The first switching element Tr has a semiconductor layer 81, a source electrode 82, a drain electrode 83, and gate electrodes 84 and 85. The lower electrode 35 of the photosensor PDA is electrically connected to the drain electrode 83 of the first switching element Tr through a contact hole H11 provided in the insulating layers 23 and 23a.

[0068] The first switching element Tr has a so-called dual gate structure in which gate electrodes 84, 85 are provided on both the upper and lower sides of a semiconductor layer 81. However, the first switching element Tr is not limited to this, and may have a top gate structure or a bottom gate structure.

[0069] FIG. 5B shows a schematic diagram of the second switching element TrA and the terminal portion 72 provided in the peripheral area GA. The second switching element TrA is, for example, a switching element provided in the gate line driving circuit 15 (see FIG. 1). The second switching element TrA has a semiconductor layer 86, a source electrode 87, a drain electrode 88, and a gate electrode 89. The second switching element TrA has a so-called top gate structure in which the gate electrode 89 is provided on the upper side of the semiconductor layer 86. A light-shielding layer 90 is provided below the semiconductor layer 86 between the semiconductor layer 86 and the sensor substrate 21. However, the present invention is not limited to this, and the second switching element TrA may have a bottom gate structure or a dual gate structure.

[0070] The semiconductor layer 81 of the first switching element Tr and the semiconductor layer 86 of the second switching element TrA are provided in different layers. The semiconductor layer 81 of the first switching element Tr is, for example, an oxide semiconductor. The semiconductor layer 86 of the second switching element TrA is, for example, polysilicon.

[0071] Next, to facilitate understanding of an example of the operation of the detection device 1 of this embodiment, an example of the operation of a detection device of a comparative example will be described. FIG. 6 is a timing waveform diagram showing an example of the operation of the detection device of the comparative example. FIG. 7 is a timing waveform diagram showing an example of the operation of the reset period in FIG. 6. FIG. 8 is a timing waveform diagram showing an example of the operation of the readout period in FIG. 6. FIG. 9 is a timing waveform diagram showing an example of the operation of a drive period of one gate line included in the row readout period VR in FIG. 6. FIG. 10 is an explanatory diagram for explaining the relationship between the drive of the sensor unit of the detection device of the comparative example and the lighting operation of the light source.

[0072] As shown in FIG. 6, the detection device of the comparative example has a reset period Prst, an exposure period Pex, and a readout period Pdet. The power supply circuit 123 supplies a sensor power supply signal VDDSNS to the anode of the optical sensor PD throughout the reset period Prst, the exposure period Pex, and the readout period Pdet. The sensor power supply signal VDDSNS is a signal that applies a reverse bias between the anode and the cathode of the optical sensor PD. For example, the reference signal COM of substantially 0.75V is applied to the cathode of the optical sensor PD, but by applying a sensor power supply signal VDDSNS of substantially -1.25V to the anode, the anode and the cathode are reverse biased at substantially 2.0V. The control circuit 122 sets the reset signal RST2 to "H" and then supplies a start signal STV and a clock signal CK to the gate line driving circuit 15, and the reset period Prst begins. In the reset period Prst, the control circuit 122 supplies the reference signal COM to the reset circuit 17, and turns on the fourth switching element TrR for supplying a reset voltage by the reset signal RST2. As a result, the reference signal COM is supplied to each signal line SGL as a reset voltage. The reference signal COM is set to, for example, 0.75 V.

[0073] In the reset period Prst, the gate line driving circuit 15 sequentially selects the gate lines GCL based on the start signal STV, the clock signal CK, and the reset signal RST1. The gate line driving circuit 15 sequentially supplies the gate lines GCL with the gate driving signals Vgcl {Vgcl(1) to Vgcl(M)}. The gate driving signal Vgcl has a pulse-like waveform having a power supply voltage VDD, which is a high-level voltage, and a power supply voltage VSS, which is a low-level voltage. In FIG. 6, M (for example, M=256) gate lines GCL are provided, and the gate driving signals Vgcl(1), ..., Vgcl(M) are sequentially supplied to each gate line GCL, and the first switching elements Tr are sequentially turned on for each row, and a reset voltage is supplied. For example, the voltage of 0.75V of the reference signal COM is supplied as the reset voltage.

[0074] Specifically, as shown in Fig. 7, the gate line driving circuit 15 supplies a gate driving signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1) during a period V(1). The control circuit 122 supplies one of the selection signals ASW1, ..., ASW6 (selection signal ASW1 in Fig. 7) to the signal line selection circuit 16 during the period when the gate driving signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). As a result, the signal line SGL of the partial detection area PAA selected by the gate driving signal Vgcl(1) is connected to the detection circuit 48. As a result, a reset voltage (reference signal COM) is also supplied to the connection wiring between the third switching element TrS and the detection circuit 48.

[0075] Similarly, the gate line driving circuit 15 supplies high-level voltage gate driving signals Vgcl(2), ..., Vgcl(M-1), Vgcl(M) to the gate lines GCL(2), ..., GCL(M-1), GCL(M), respectively, during periods V(2), ..., V(M-1), V(M).

[0076] As a result, in the reset period Prst, the capacitance elements Ca in all the partial detection areas PAA are sequentially electrically connected to the signal line SGL and the reference signal COM is supplied. As a result, the capacitance of the capacitance elements Ca is reset. It is also possible to reset the capacitance of some of the capacitance elements Ca in the partial detection area PAA by partially selecting the gate lines and the signal lines SGL.

[0077] Examples of exposure timing include a gate line non-selection exposure control method and a constant exposure control method. In the gate line non-selection exposure control method, gate drive signals {Vgcl(1) to (M)} are sequentially supplied to all gate lines GCL connected to the optical sensor PD to be detected, and a reset voltage is supplied to all optical sensors PD to be detected. After that, when all gate lines GCL connected to the optical sensor PD to be detected are at a low voltage (the first switching element Tr is off), exposure starts, and exposure is performed during the exposure period Pex. When exposure ends, as described above, gate drive signals {Vgcl(1) to (M)} are sequentially supplied to the gate lines GCL connected to the optical sensor PD to be detected, and reading is performed during the readout period Pdet. In the constant exposure control method, it is also possible to control exposure to be performed during the reset period Prst and the readout period Pdet (constant exposure control). In this case, the exposure period Pex(1) starts after the gate drive signal Vgcl(1) is supplied to the gate lines GCL during the reset period Prst. Here, the exposure period Pex{(1)...(M)} is a period during which the capacitance element Ca is charged from the photosensor PD. The charge charged in the capacitance element Ca during the reset period Prst flows in the photosensor PD as a reverse current (from the cathode to the anode) due to light irradiation, and the potential difference of the capacitance element Ca decreases. Note that the actual exposure periods Pex(1), ..., Pex(M) in the partial detection areas PAA corresponding to each gate line GCL have different start and end timings. The exposure periods Pex(1), ..., Pex(M) each start at the timing when the gate drive signal Vgcl changes from the high-level voltage of the power supply voltage VDD to the low-level voltage of the power supply voltage VSS during the reset period Prst. Also, the exposure periods Pex(1), ..., Pex(M) each end at the timing when the gate drive signal Vgcl changes from the power supply voltage VSS to the power supply voltage VDD during the readout period Pdet. The exposure time lengths of the exposure periods Pex(1), . . . , Pex(M) are equal.

[0078] In the gate line non-selection exposure control method, in the exposure periods Pex{(1)...(M)}, a current flows in each partial detection area PAA according to the light irradiated to the photosensor PD. As a result, a charge is accumulated in each capacitance element Ca.

[0079] Before the readout period Pdet starts, the control circuit 122 sets the reset signal RST2 to a low-level voltage. This stops the operation of the reset circuit 17. The reset signal may be set to a high-level voltage only during the reset period Prst. During the readout period Pdet, as in the reset period Prst, the gate line drive circuit 15 sequentially supplies gate drive signals Vgcl(1), ..., Vgcl(M) to the gate lines GCL.

[0080] 8, the gate line driving circuit 15 supplies a gate driving signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1) during a row readout period VR(1). The control circuit 122 sequentially supplies selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 during the period when the gate driving signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). As a result, the signal lines SGL of the partial detection area PAA selected by the gate driving signal Vgcl(1) are sequentially or simultaneously connected to the detection circuit 48. As a result, the detection signal Vdet is supplied to the detection circuit 48 for each partial detection area PAA.

[0081] Similarly, the gate line driving circuit 15 supplies high-level voltage gate driving signals Vgcl(2), ..., Vgcl(M-1), Vgcl(M) to the gate lines GCL(2), ..., GCL(M-1), GCL(M) during row readout periods VR(2), ..., VR(M-1), VR(M). That is, the gate line driving circuit 15 supplies the gate driving signal Vgcl to the gate line GCL during each row readout period VR(1), VR(2), ..., VR(M-1), VR(M). During each period in which each gate driving signal Vgcl is at a high level voltage, the signal line selection circuit 16 sequentially selects the signal lines SGL based on the selection signal ASW. The signal line selection circuit 16 sequentially connects each signal line SGL to one detection circuit 48. As a result, during the readout period Pdet, the detection device 1 can output the detection signals Vdet of all partial detection areas PAA to the detection circuit 48.

[0082] An example of operation during a row readout period VR, which is a supply period of one gate drive signal Vgcl(j) in Fig. 6, will be described below with reference to Fig. 9. In Fig. 6, the first gate drive signal Vgcl(1) is given the symbol of the row readout period VR, but the same is true for the other gate drive signals Vgcl(2), ..., Vgcl(M). j is a natural number from 1 to M.

[0083] As shown in FIG. 9 and FIG. 4, the output of the third switching element TrS (V out ) is reset to a reference potential (Vref) voltage in advance. The reference potential (Vref) voltage is a reset voltage, for example 0.75V. Next, the gate drive signal Vgcl(j) goes high, turning on the first switching element Tr of the row, and the signal line SGL of each row goes to a voltage according to the charge stored in the capacitance (capacitor element Ca) of the partial detection area PAA. After a period t1 has elapsed since the rising edge of the gate drive signal Vgcl(j), a period t2 occurs during which the selection signal ASW(k) goes high. When the selection signal ASW(k) goes high and the third switching element TrS goes on, the output (Vout ) (see FIG. 4) changes to a voltage according to the charge accumulated in the capacitance (capacitor element Ca) of the partial detection area PAA (period t3). In the example of FIG. 9, this voltage drops from the reset voltage as in period t3. After that, when the switch SSW is turned on (period t4 when the SSW signal is at a high level), the charge accumulated in the capacitance (capacitor element Ca) of the partial detection area PAA moves to the capacitance (capacitor element Cb) of the detection signal amplifier 42 of the detection circuit 48, and the output voltage of the detection signal amplifier 42 becomes a voltage according to the charge accumulated in the capacitor element Cb. At this time, the inverting input section of the detection signal amplifier 42 becomes the imaginary short potential of the operational amplifier, so that it has returned to the reference potential (Vref). The output voltage of the detection signal amplifier 42 is read out by the A / D converter 43. In the example of Fig. 9, the waveforms of the selection signals ASW(k), ASW(k+1), ... corresponding to the signal lines SGL of each column become high to sequentially turn on the third switching elements TrS, and similar operations are sequentially performed to sequentially read out the charges accumulated in the capacitances (capacitive elements Ca) of the partial detection areas PAA connected to the gate lines GCL. Note that ASW(k), ASW(k+1), ... in Fig. 9 are, for example, any of ASW1 to ASW6 in Fig. 9.

[0084] Specifically, when a period t4 occurs during which the switch SSW is on, charge moves from the capacitance (capacitor Ca) of the partial detection area PAA to the capacitance (capacitor Cb) of the detection signal amplifier 42 of the detection circuit 48. At this time, the non-inverting input (+) of the detection signal amplifier 42 is biased to a reference potential (Vref) voltage (for example, 0.75 [V]). For this reason, an imaginary short between the inputs of the detection signal amplifier 42 causes the output (V out ) also becomes the reference potential (Vref) voltage. The voltage of the capacitance element Cb becomes a voltage according to the charge accumulated in the capacitance (capacitance element Ca) of the partial detection area PAA where the third switching element TrS is turned on in response to the selection signal ASW(k). The output of the detection signal amplifier 42 becomes the output (V out) becomes the reference potential (Vref) voltage, then becomes a voltage according to the capacitance of the capacitive element Cb, and this output voltage is read by the A / D conversion unit 43. Note that the voltage of the capacitive element Cb is, for example, the voltage between two electrodes provided in the capacitor that constitutes the capacitive element Cb.

[0085] The period t1 is, for example, 20 [μs], the period t2 is, for example, 60 [μs], the period t3 is, for example, 44.7 [μs], and the period t4 is, for example, 0.98 [μs].

[0086] 10, in each of the periods t(1) and t(2), the detection device 1 executes the above-mentioned reset period Prst, exposure period Pex{(1)...(M)}, and readout period Pdet. In the reset period Prst and readout period Pdet, the gate line driving circuit 15 sequentially scans the gate lines GCL(1) to GCL(M). In the following description, detection in each period t, that is, detection in which the gate lines GCL(1) to GCL(M) are scanned in the reset period Prst and readout period Pdet and the detection signal Vdet is obtained from the signal line SGL of each column, is referred to as detection of one frame.

[0087] The light source (the first light source 61 or the second light source 62) is turned on continuously during the period t(1) and the period t(2). The control circuit 122 can control the turning on and off of the light source depending on the detection target. For example, the control circuit 122 may switch the turning on and off of the first light source 61 and the second light source 62 for each period, or may turn on one of them continuously.

[0088] 6 to 10 show an example in which the gate line driving circuit 15 selects the gate lines GCL individually, but the present invention is not limited to this. The gate line driving circuit 15 may simultaneously select a predetermined number of gate lines GCL (two or more) and sequentially supply the gate driving signal Vgcl to each of the predetermined number of gate lines GCL. The signal line selection circuit 16 may also simultaneously connect a predetermined number of signal lines SGL (two or more) to one detection circuit 48. Furthermore, the gate line driving circuit 15 may scan a plurality of gate lines GCL by thinning them out.

[0089] 8, in the comparative example, during a row readout period VR(1), while the gate drive signal Vgcl(1) is at a high-level voltage (power supply voltage VDD), the selection signals ASW1, ..., ASW6 are sequentially supplied to the signal line selection circuit 16. That is, even after the selection signal ASW1 becomes a low-level voltage at time t11, exposure continues during an exposure period Pex-1 until the gate drive signal Vgcl(1) becomes a low-level voltage at time t13. Charges corresponding to the exposure period Pex-1 are charged from the photosensor PD to the signal line SGL(1) corresponding to the selection signal ASW1.

[0090] Similarly, electric charges are stored in each signal line SGL during exposure periods Pex-1, ..., Pex-6 corresponding to each selection signal ASW1, ..., ASW6. For example, the exposure period Pex-6 is the period from when the selection signal ASW6 becomes a low-level voltage at time t12 until when the gate drive signal Vgcl(1) becomes a low-level voltage at time t13, and the exposure period Pex differs for each column.

[0091] Then, in the next row readout period VR(2), a signal obtained by adding up the charges accumulated during the exposure periods Pex-1(SGL(1)), Pex-6(SGL(6)) of the previous row readout period VR(1) to the detection signal Vdet for the second row is supplied to the detection circuit 48. In this way, the detection signal Vdet for each row readout period VR changes depending on the detection result of the previous row readout period VR, which may result in a decrease in detection accuracy.

[0092] FIG. 11 is an explanatory diagram for explaining an operation example of the detection device according to the first embodiment. FIG. 12 is a timing waveform diagram showing an operation example of the detection device according to the first embodiment. In the comparative example, in detection of one frame, the readout period Pdet of one frame is executed after the reset period Prst of one frame. In contrast, in the detection device 1 according to the first embodiment, as shown in FIG. 11, the readout period Pdet of one frame (1F) and the reset period Prst of one frame (1F) are executed in parallel.

[0093] In this embodiment, a driving signal Vgcl is supplied to the gate line GCL for each row, and a plurality of first switching elements Tr belonging to a predetermined row are brought into a connected state. Specifically, as shown in Fig. 12, at time t21, the gate line driving circuit 15 supplies a gate driving signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1). The row readout period VR(1) starts at the timing when the gate driving signal Vgcl(1) becomes a high-level voltage at time t21.

[0094] Specifically, the control circuit 122 sequentially supplies the selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 during a period in which the gate drive signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). The third switching elements TrS are sequentially switched to a connected state in response to the selection signals ASW1, ..., ASW6. That is, during a row-by-row readout period (row readout period VR(1)), a plurality of first switching elements Tr in a predetermined row are in a connected state, and the signal line selection circuit 16 connects a plurality of signal lines SGL to the detection circuit 48 in a predetermined order for each column. As a result, the detection signal Vdet is supplied to the detection circuit 48 for each partial detection area PAA.

[0095] 12, the selection signals ASW1, ..., ASW6 are supplied in a time-division manner in the order of periods T11, ..., T16. At time t22, the control circuit 122 sets the selection signal ASW6 to a low-level voltage, and the readout of the last column is completed. That is, in this embodiment, the row readout period VR(1) ends at the timing when the gate drive signal Vgcl(1) is at a high-level voltage and the selection signal ASW6 is changed to a low-level voltage.

[0096] After the readout period of a given row (row readout period VR(1)) is completed and before the readout period of the next row (row readout period VR(2)) of the given row starts, a reset potential (reference signal COM) is supplied to the photosensors PD and signal lines SGL belonging to the given row. Specifically, the control circuit 122 supplies a reset signal RST2 to the reset signal line Lrst at time t22. This turns on the fourth switching elements TrR, and the reference signal COM is supplied to the photosensors PD and signal lines SGL corresponding to the gate line GCL(1).

[0097] 12, the timing when the reset signal RST2 becomes a high-level voltage and the timing when the selection signal ASW6 becomes a low-level voltage coincide with each other at time t22. However, this is not limited thereto, and the reset signal RST2 may be set to a high-level voltage after a predetermined period has elapsed after the selection signal ASW6 becomes a low-level voltage.

[0098] After that, at time t23, the gate line driving circuit 15 sets the gate driving signal Vgcl(1) to a low-level voltage. This causes the first switching elements Tr in a predetermined row to be in a non-connected state. At time t24, the control circuit 122 sets the reset signal RST2 to a low-level voltage. This ends the readout period Pdet and reset period Prst of the first row.

[0099] After that, at time t25, the gate line driving circuit 15 supplies a gate driving signal Vgcl(2) of a high-level voltage (power supply voltage VDD) to the gate line GCL(2) of the second row. Thereafter, similar to the first row, the readout period Pdet and reset period Prst of the second row are executed from time t26 to time t28. This operation is repeated until the final row (gate line GCL(256)) is scanned, whereby one frame can be detected.

[0100] In this embodiment, since a reset period Prst is provided for each row readout period VR, even if the signal line SGL is charged after a specific column (e.g., SGL(1)) is read out, the signal line SGL is reset before the row readout period VR for the next row. Therefore, the detection device 1 can suppress fluctuations in the detection signal Vdet due to the detection result in the previous row, and can improve detection accuracy.

[0101] In this embodiment, a reset potential is supplied to each row after the row readout period VR. For this reason, as shown in FIG. 11, it is preferable to provide a reset period Prst as a start-up sequence when starting up the detection device 1. In the start-up sequence, no readout is performed, and a reset potential is supplied to the photosensors PD and signal lines SGL for one frame (1F) to perform resetting. This makes it possible to suppress detection variations in the first readout period Pdet after start-up. The start-up sequence is performed when the power supply of the detection device 1 is turned on for startup, or when the detection device 1 returns from a sleep mode in which detection is not performed for a predetermined period.

[0102] Fig. 13 is an image showing the detection result of the detection device of the comparative example. Fig. 14 is an image showing the detection result of the detection device of the embodiment. Fig. 13 and Fig. 14 are image data showing the same test pattern TP, and both are test patterns TP in which square black patterns are arranged in a staggered pattern.

[0103] In the detection pattern DP of the comparative example shown in Fig. 13, the boundary (contrast) between the black pattern and the white pattern is blurred between adjacent rows, whereas in the detection pattern DP of the embodiment shown in Fig. 14, the boundary (contrast) between the black pattern and the white pattern is clear between adjacent rows. This shows that the detection accuracy can be improved by supplying a reset potential to the photosensor PD and the signal line SGL for each row readout period VR as described above.

[0104] (Second Modification) In the first embodiment described above, although interference between detection signals between rows can be suppressed, as shown in Fig. 12, a time difference occurs in the readout timing of each column from the timing (e.g., time t21) when the gate drive signal Vgcl(1) becomes a high-level voltage. Compared to the exposure period Pex-1 of the photosensor PD connected to the signal line SGL(1), the exposure period Pex-6 of the photosensor PD connected to the signal line SGL(6) is longer. As a result, there is a possibility that detection variations in the column direction will occur periodically.

[0105] Fig. 15 is an explanatory diagram for explaining the relationship between the driving of the sensor unit of the detection device of the second modified example and the lighting operation of the light source. Fig. 16 is an explanatory diagram that typically shows the relationship between the detection device of the second modified example and the light source.

[0106] 15, the control circuit 122 turns off the light source (the first light source 61 or the second light source 62) during the reset period Prst and the readout period Pdet of one frame (1F), and turns on the light source during the period T2 between frames. During the period T2, none of the gate lines GCL are selected (the gate drive signal Vgcl is at a low-level voltage). That is, the light source is turned off during the row readout period VR when the first switching element Tr of a predetermined row is in the connected state, and the light source is turned on during the period T2 when all the first switching elements Tr are in the disconnected state.

[0107] As a result, light L1 (see Figure 16) from the light source is not irradiated during the row readout period VR when the gate drive signal Vgcl is at a high-level voltage, thereby suppressing detection variations from column to column caused by variations in the exposure periods Pex-1, ..., Pex-6.

[0108] Second embodiment In the second embodiment, a driving is performed to further improve the detection accuracy. For example, depending on the usage conditions of the detection device 1, external light L2 may be irradiated in addition to light L1 from the light source, as shown in FIG. 16. In this case, the sensor is irradiated with light even when the light source is not lit, and the influence of irradiation with external light L2 differs for each column due to the difference in readout time for each column. Therefore, if external light L2 is irradiated during the row readout period VR, there is a possibility that detection variation will occur for each column.

[0109] Fig. 17 is a flowchart showing an example of the operation of the detection device according to the second embodiment Fig. 18 is a table showing the order of connection of signal lines for each detection of one frame.

[0110] 17, the control circuit 122 executes a start-up sequence (see FIG. 11) of the detection device 1 (step ST1). The control circuit 122 sets driving parameters of the detection device 1 (step ST2). The driving parameters include, for example, the sensor resolution, the number of selected signal lines SGL, the brightness of the light source, and the like.

[0111] The control circuit 122 starts detection (step ST3). As in the first embodiment described above, the control circuit 122 supplies a reset potential to the photosensors PD and the signal lines SGL for each row readout period VR.

[0112] The control circuit 122 scans the gate lines GCL and the signal lines SGL, and acquires sensor data (detection signal Vdet) for each block unit PAG (see FIG. 3) (step ST4).

[0113] If one frame (1F) worth of data has not been acquired (step ST5, No), the control circuit 122 continues scanning the gate lines GCL and the signal lines SGL. If one frame (1F) worth of data has been acquired (step ST5, Yes), the control circuit 122 executes detection of the next frame.

[0114] 18 shows the order of the selection signal ASW in the periods T11 to T16 for each frame for the detection of frames 1 to 6. As shown in FIG 18, the control circuit 122 changes the order of the selection signal ASW for each frame. That is, the signal line selection circuit 16 changes the order of connection between the multiple signal lines SGL and the detection circuit 48 in the readout period Pdet for each detection of one frame based on the selection signal ASW from the control circuit 122.

[0115] In other words, the length of the exposure period Pex of each column differs for each frame. For example, when focusing on the selection signal ASW1, the period during which the selection signal ASW1 is supplied (period T11 to period T16) differs between frames 1 to 6. That is, in the example shown in Fig. 18, the exposure period Pex-1 (see Fig. 12) corresponding to the selection signal ASW1 is shortest in frame 1 and longest in frame 2. Then, the exposure period Pex-1 (selection signal ASW1) becomes shorter in sequence from frame 3 to frame 6.

[0116] 18, the order of the selection signal ASW (from period T11 to period T16) is shifted by one from frame 1 to frame 6. However, this is not limited to this, and the order of the selection signal ASW may be changed randomly in each frame.

[0117] Next, if data for N frames (e.g., N=6) has not been acquired (step ST6, No), the control circuit 122 repeatedly executes steps ST4 and ST5. If data for N frames has been acquired (step ST6, Yes), the control circuit 122 performs frame averaging processing (step ST7).

[0118] The frame averaging process is a signal process that averages data (detection signal Vdet) acquired for each column in each frame, for example, from frame 1 to frame 6 shown in FIG. 18. For example, averaging process is performed on six signals detected from the signal line SGL(1) based on the selection signal ASW1 from frame 1 to frame 6. Similarly, averaging process is performed on signals detected for each column (each signal line SGL). This makes it possible to suppress variations in the exposure period Pex for each column.

[0119] The control circuit 122 rearranges the averaged data in the order of the columns (signal lines SGL) (step ST8). The control circuit 122 displays an image as two-dimensional information based on the information averaged over multiple frames (step ST9).

[0120] When the control circuit 122 continues the detection (step ST10, No), it repeatedly executes steps 4 to 9. When the control circuit 122 ends the detection (step ST10, Yes), it executes a shutdown sequence (step ST11) and ends the process.

[0121] In this embodiment, the order of connection between the multiple signal lines SGL and the detection circuit 48 is changed for each detection of one frame, and the detection signals Vdet for multiple frames are averaged in each column. As a result, in this embodiment, the variation in exposure time of each column is averaged, so that the detection variation for each column can be suppressed. In addition, in this embodiment, the variation for each column can be suppressed by applying the driving in the first embodiment shown in FIG. 11 and FIG. 12 other than the driving in the first modified example of the first embodiment shown in FIG. 15.

[0122] Third embodiment 19 is a timing waveform diagram showing an example of the operation of the detection device according to the third embodiment. The third embodiment is different from the first and second embodiments in that the control circuit 122 sequentially supplies selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 during the row readout period VR when the gate drive signal Vgcl is at a low level voltage.

[0123] 19, at time t31, the gate line driving circuit 15 supplies a gate driving signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1). The row readout period VR(1) starts at the timing when the gate driving signal Vgcl(1) becomes a high-level voltage.

[0124] After a predetermined period has elapsed, at time t32 before the selection signal ASW is supplied, the gate line drive circuit 15 sets the gate drive signal Vgcl(1) to a low-level voltage. That is, in the readout period of a predetermined row (row readout period VR(1)), the first switching elements Tr of the predetermined row are connected at time t31, and after a predetermined period has elapsed, are disconnected at time t32.

[0125] During the period when the first switching element Tr is in the connected state (from time t31 to time t32), the selection signal ASW is not supplied and the third switching element TrS is in the disconnected state. Therefore, a part of the charge stored in the capacitance element Ca in response to the light irradiated to the photosensor PD is also charged in the signal line capacitance Cc in accordance with the ratio of the capacitance element Ca to the signal line capacitance Cc.

[0126] Next, the control circuit 122 sequentially supplies the selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 while the gate drive signal Vgcl(1) is at a low-level voltage. The third switching elements TrS are sequentially switched to a connected state in response to the selection signals ASW1, ..., ASW6. That is, during the row-by-row readout period (row readout period VR(1)), the multiple first switching elements Tr of a predetermined row are in a non-connected state, and the signal line selection circuit 16 connects the multiple signal lines SGL to the detection circuit 48 in a predetermined order. As a result, the detection signal Vdet is supplied to the detection circuit 48 for each partial detection area PAA.

[0127] In this embodiment, in periods T11, . . . , T16, the first switching element Tr is in a disconnected state, and therefore the detection circuit 48 is not connected to the capacitance element Ca. Therefore, in periods T11, . . . , T16, a signal corresponding to the charge charged in the signal line capacitance Cc during the period in which the first switching element Tr is in a connected state is output as the detection signal Vdet.

[0128] When the capacitance value of the capacitive element Ca is C1 and the capacitance value of the signal line capacitance Cc is C2, the control circuit 122 corrects the sensor output based on the ratio of the capacitances C1 and C2 shown in the following formula (1). This makes it possible to correct the sensor output to a signal equivalent to the detection signal Vdet read out when the first switching element Tr shown in the first embodiment is in a connected state. As an example of the correction, the detection value read out by the A / D conversion unit 43 in FIG. 4 is multiplied by the value of the following formula (1).

[0129] (C1+C2) / C2 (1)

[0130] 19, the selection signals ASW1, ..., ASW6 are supplied in a time-division manner in the order of periods T11, ..., T16. At time t33, the control circuit 122 sets the selection signal ASW6 to a low-level voltage, and the readout of the last column is completed. That is, in this embodiment, the row readout period VR(1) starts at time t31 when the gate drive signal Vgcl(1) becomes a high-level voltage, and after the gate drive signal Vgcl(1) becomes a low-level voltage, the selection signals ASW1, ..., ASW6 are supplied. Then, the row readout period VR(1) ends at the timing when the gate drive signal Vgcl(1) is at a low-level voltage and the selection signal ASW6 of the last column is changed to a low-level voltage.

[0131] At time t34, the gate line drive circuit 15 supplies a gate drive signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1). That is, after the completion of the readout period VR(1) and before the start of the readout period VR(2) of the next row (second row) of the predetermined row (first row), the multiple first switching elements Tr of the predetermined row (first row) are brought into a connected state.

[0132] At time t35, the control circuit 122 supplies a reset signal RST2 to the reset signal line Lrst, which turns on the multiple fourth switching elements TrR and supplies the reference signal COM to the photosensor PD corresponding to the gate line GCL(1) and the multiple signal lines SGL.

[0133] After that, at time t36, the gate line driving circuit 15 sets the gate driving signal Vgcl(1) to a low-level voltage. At time t37, the control circuit 122 sets the reset signal RST2 to a low-level voltage. This ends the readout period Pdet and reset period Prst of the first row.

[0134] After that, at time t38, the gate line driving circuit 15 supplies a gate driving signal Vgcl(2) of a high-level voltage (power supply voltage VDD) to the gate line GCL(2) of the second row. Thereafter, similar to the first row, the readout period Pdet and reset period Prst of the second row are executed from time t39 to time t43. This operation is repeated until the final row (gate line GCL(256)) is scanned, whereby one frame can be detected.

[0135] As described above, in the third embodiment, during the period when the first switching element Tr of a given row is in the disconnected state (the period from time t32 to time t34), the selection signals ASW1, ..., ASW6 are sequentially supplied to read out each column. This makes it possible to suppress the fluctuation of the detection signal Vdet due to the variation in the exposure period of each column. In other words, in the third embodiment, it is possible to suppress the periodic contrast difference in the row direction as shown in Figs. 13 and 14.

[0136] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present invention. Appropriate modifications made within the scope of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-mentioned embodiments and each modified example. [Explanation of symbols]

[0137] 1. Detection device 10 Sensor section 11 Detection control section 15 Gate line driving circuit 16 Signal line selection circuit 21 Sensor substrate 40 Detection unit 48 Detection Circuit 61 1st light source 62 Second light source 122 Control circuit 123 Power supply circuit AA detection area GA Peripheral Areas GCL Gate line PD Light Sensor SGL signal line Tr 1st switching element Vgcl Gate drive signal

Claims

1. A plurality of optical sensors arranged in a matrix; A plurality of switching elements, a plurality of gate lines, and a plurality of signal lines provided corresponding to the plurality of photosensors; a detection circuit to which signals from the plurality of photosensors are supplied via the plurality of signal lines in a predetermined order for each column during a readout period for a predetermined row; A drive signal is supplied to the gate line for each row, and a plurality of the switching elements belonging to a specific row are brought into a connected state, a reset potential is supplied to the plurality of photosensors and the plurality of signal lines belonging to the predetermined row after the completion of the readout period of the predetermined row and before the start of the readout period of the next row of the predetermined row; The order of connection between the plurality of signal lines and the detection circuit during the readout period is different for each frame detection. Detection device.

2. during the readout period of the predetermined row, the plurality of switching elements of the predetermined row are in the connected state, and the plurality of signal lines are connected to the detection circuit in a predetermined order for each column; After the readout period of the predetermined row is completed, the switching elements of the predetermined row are in a non-connected state. The detection device according to claim 1 .

3. A plurality of optical sensors arranged in a matrix; A plurality of switching elements, a plurality of gate lines, and a plurality of signal lines provided corresponding to the plurality of photosensors; a detection circuit to which signals from the plurality of photosensors are supplied via the plurality of signal lines in a predetermined order for each column during a readout period for a predetermined row; A drive signal is supplied to the gate line for each row, and a plurality of the switching elements belonging to a specific row are brought into a connected state, a reset potential is supplied to the plurality of photosensors and the plurality of signal lines belonging to the predetermined row after the completion of the readout period of the predetermined row and before the start of the readout period of the next row of the predetermined row; During the readout period of the predetermined row, the switching elements of the predetermined row are brought into the connected state, and after a predetermined period, are brought into a non-connected state; the plurality of switching elements in the predetermined row are in a non-connected state, and the plurality of signal lines are connected to the detection circuit in a predetermined order for each column; After the readout period is completed and before the readout period of the next row of the predetermined row starts, the switching elements of the predetermined row are brought into the connected state, and a reset potential is supplied to the photosensors and the signal lines belonging to the predetermined row. Detection device.

4. The signals from the plurality of optical sensors are corrected based on a ratio between a sensor capacitance formed in the optical sensor and a signal line capacitance formed in the signal line.

4. The detection device according to claim 3.

5. The order of connection between the plurality of signal lines and the detection circuit during the readout period is different for each frame detection.

5. The detection device according to claim 3 or 4.

6. A detection device according to any one of claims 1 to 5; At least one light source; Fingerprint detection device.

7. A detection device according to any one of claims 1 to 5; At least one light source; Vein detection device.

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