Display device

Abstract

To provide a display device that can, when plural lines are used to supply different signals to plural pixels at the same timing, reduce difference in load capacity between the lines and reduce a gap in display gradation and / or signal delay.SOLUTION: A display device comprises a first data line to an N-th (N is a natural number of 3 or more) data line for supplying different video signals, and a pixel including a selection transistor connected to any one of the first data line to the N-th data line. One of the first data line to the N-th data line is connected to one terminal of the selection transistor by disposing the one of the first data line to the N-th data line at a place closest to the one terminal of the selection transistor in a manner that the first data line to the N-th data line cross each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a display device. Or, the present invention relates to a driving method for a display device. The present invention also relates to an electronic device equipped with the display device. [Background technology]

[0002] Display devices, such as liquid crystal display devices using liquid crystal elements, are used in large applications such as television sets. They are becoming more and more popular, from large-format displays to small displays such as mobile phones. There is a demand for products with higher added value, and their development is underway.

[0003] In the future, in order to achieve even higher added value, the scanning lines that supply signals to each pixel of the display device will be Alternatively, the number of wiring lines such as data lines may be increased to improve the functionality of pixel driving. For example, Patent Document 1 discloses a display device having a plurality of data lines. The present invention discloses a configuration for connecting each of a plurality of data lines to a pixel transistor. do. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-186451 A Summary of the Invention [Problem to be solved by the invention]

[0005] As in the above-mentioned Patent Document 1, a scanning line or a data line that supplies a signal to each pixel of the display device is When increasing the number of wirings, etc., the wiring is extended from the pixel transistor to supply signals to the pixel. This is a configuration in which the wiring is connected to the scanning line or data line, etc. In this configuration, the load capacity of each wiring is There is a problem that the amount of the load varies, causing display problems. The following description will be given with reference to the drawings.

[0006] FIG. 15A shows a circuit configuration of a pixel in a display device. N (N is a natural number greater than or equal to 3) of data lines (also called signal lines) are This figure shows a circuit configuration when different video signals are supplied to three different pixels via a line. The pixel 1501A includes a transistor 1504A (also called a selection transistor) and a display The transistor 1504A of the pixel 1501A has a gate terminal is connected to the scanning line 1503A, and one of the terminals (the first The other terminal is connected to the display element section 150 5A. Pixel 1501B is connected to transistor 1504B (selection transistor The pixel 1501B includes a transistor 150 and a display element portion 1505B. 4B has a gate terminal connected to the scanning line 1503B and serves as a source terminal or a drain terminal. One terminal (also called the first terminal) of the pixel is connected to the second data line 1502B, and the other terminal is connected to the display element portion 1505B. The pixel 1501C includes a transistor 1504C. The pixel 1501C has a display element portion 1505C (also called a selection transistor). The transistor 1504C has a gate terminal connected to the scanning line 1503C and a source terminal The drain terminal (also called the first terminal) is connected to the third data line 1502C. The other terminal is connected to the display element unit 1505C. The circuit configuration shown in FIG. 15 is, for example, a circuit diagram of a scanning line 1503A to a scanning line 1503C. The transistors 1504A to 1504C are simultaneously turned on (also called turned on). As a result, the first data line 1502 is connected to the display element portion 1505A to the display element portion 1505C. This is an effective configuration when supplying separate video signals from the A to the third data lines 1502C. be.

[0007] Regarding the display element units 1505A to 1505C, a specific display element will be described. Although not shown, in the case of a liquid crystal display device, a liquid crystal element and a capacitive element are provided, and in the case of an EL element, If necessary, a light emitting element and a transistor for driving the light emitting element may be provided. stomach.

[0008] When pixels are arranged in a matrix, the first data line 1502A to the third data line 1502B are The line 1502C is set in a direction substantially perpendicular to the scanning lines 1503A to 1503C. The transistors are arranged along the first data line 1502A to the third data line 1502C. Pixels 1501A to 1501C having transistors 1504A to 1504C Therefore, the first data line 1502A to the third data line 1502 are provided. When C is provided in parallel, one terminal of the transistor 1504B and the second data line 1502 When connecting to B, an intersection 1506 shown in FIG. When one terminal of the transistor 1504C is connected to the third data line 1502C, The intersection 1507 shown in FIG. 15(A) is formed. In 1507, an electrical short circuit is formed between the first data line 1502A to the third data line 1502C. To avoid short circuits, a conductive layer is formed on a separate layer, and the transistor is connected through this conductive layer. A connection between one terminal of the transistor 1504B and the second data line 1502B, and One terminal of data line 1504C is connected to the third data line 1502C.

[0009] However, one terminal of the transistor 1504B is connected to the second data line 1 through a conductive layer. 502B, and one terminal of the transistor 1504C and the third data line 1502 By connecting the crossing point 1506 to the crossing point 1507, as shown in the circuit diagram of FIG. load capacitance 1516 due to the crossing 1507, load capacitance 1517A due to the crossing 1507, and load capacitance 151 Specifically, the load capacitance 1516 and the load capacitance 1517B are formed. The first data line 1502A and the load capacitance 1517B are connected to the conductive layer and the first data line 1502A to the third data line 1502B. The difference occurs depending on the area of ​​the intersection with the data line 1502C. A difference in load capacitance occurs between the first data line 1502A and the second data line 1502B. It becomes difficult to supply the desired potential signal to each pixel, which causes the display grayscale deviation. and / or signal delays.

[0010] In view of this, one embodiment of the present invention is to transmit different signals to multiple pixels at the same timing using multiple wirings. When supplying power at 100V, the difference in the load capacitance formed on each wiring is reduced, and the display gray scale deviation and / or The present invention aims to provide a display device capable of reducing a signal delay. [Means for solving the problem]

[0011] According to one aspect of the present invention, first to Nth data lines (N is 3 or more) for supplying different video signals are provided. A data line (above natural number) is connected to any one of the first data line to the Nth data line. A pixel having a selection transistor for selecting a first data line to an Nth data line. The first data line and one terminal of the selection transistor are connected to the first data line through the Nth data line. By connecting the first data line to the Nth data line, one of the first data line to the Nth data line is selected as one of the selection transistors. The display device is disposed and connected in the closest proximity to one of the terminals.

[0012] In one embodiment of the present invention, the other terminal of the selection transistor is connected to a display element having a liquid crystal element. It may also be a display device to which a child is connected.

[0013] In one embodiment of the present invention, the other terminal of the selection transistor is connected to a light-emitting element and It may also be a display device to which a display element having a driving transistor for driving is connected.

[0014] In one embodiment of the present invention, a display device has scan lines, a first data line, a second data line, and an Nth data line. The display device may be one in which the intersections are provided using the same conductive layer as the scanning lines.

[0015] In one embodiment of the present invention, a conductor at an intersection of the first data line to the Nth data line is The resistors formed by the conductive layer are uniformly formed on the first data line to the Nth data line. It may be a display device.

[0016] According to one aspect of the present invention, first to Nth scan lines (N is 3 or more) for supplying different scan signals are provided. A selection transistor connected to any one of the first to Nth scanning lines (a natural number of which is a scanning line of the first scanning line to the Nth scanning line) A pixel having a transistor, and any one of the first scanning line to the Nth scanning line and a selection The gate terminal of the selection transistor is connected to the first scanning line through the Nth scanning line by crossing the first scanning line through the Nth scanning line. Any one of the first data line to the Nth scan line is located closest to the gate terminal of the selection transistor. The display device is arranged and connected.

[0017] In one embodiment of the present invention, one terminal of the selection transistor is connected to the first data line to the Nth data line. The other terminal of the selection transistor is connected to one of the data lines. The display device may be a display device to which a display element is connected.

[0018] In one embodiment of the present invention, one terminal of the selection transistor is connected to the first data line to the Nth data line. The other terminal of the selection transistor is connected to a light emitting element and In a display device to which a display element having a driving transistor for driving a light emitting element is connected, good. Effect of the Invention

[0019] According to one aspect of the present invention, the difference in load capacitance formed in each wiring is reduced, and the deviation of the displayed gray scale is prevented. And / or signal delay can be reduced. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a top view of one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 7] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 8] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 9] 1A and 1B are a circuit diagram and a timing chart according to one embodiment of the present invention. [Figure 10] 1A and 1B are a circuit diagram and a block diagram according to one embodiment of the present invention. [Figure 11] FIG. 1 is a timing chart according to one embodiment of the present invention. [Figure 12] 1A and 1B are a top view and a cross-sectional view of one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view of one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 15] FIG. 1 is a circuit diagram for explaining inversion driving. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the above-mentioned embodiments, and may be practiced in various different ways without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the form and details of the present invention may be modified in various ways. The present invention should not be construed as being limited to the description of the present embodiment. In the structure of the invention, reference numerals indicating the same objects are common among different drawings.

[0022] In addition, the size, layer thickness, signal waveform, or Areas may be exaggerated for clarity. This is not limited to rules.

[0023] In this specification, the terms first, second, third, through n-th (n is a natural number) refer to configurations. It is noted that this is added to avoid confusion of elements and is not intended to limit the number. do.

[0024] (Embodiment 1) In this embodiment mode, a circuit configuration of a pixel included in a display device will be described. In the circuit diagram, multiple wiring is used to supply different signals to multiple pixels at the same time. N data lines (also called signal lines) (N is a natural number greater than or equal to 3) are used as the scanning signal for the scanning lines. An example in which different video signals are supplied to a plurality of pixels will be described.

[0025] FIG. 1A shows a circuit configuration of a pixel in a display device. N is a natural number of 3 or more) as data lines (also called signal lines), specifically, three data lines 1 shows a circuit configuration in which three different video signals are supplied to three different pixels. The pixel 101A includes a transistor 104A (also called a selection transistor) and a display element portion 1 The transistor 104A of the pixel 101A has a gate terminal connected to the scanning line 103. A is connected to the source or drain terminal (also called the first terminal). The other terminal is connected to the first data line 102A, and the other terminal is connected to the display element section 105A. The pixel 101B includes a transistor 104B (also called a selection transistor) and a display element portion The transistor 104B of the pixel 101B has a gate terminal connected to the scan line 10 3B is connected to one terminal that serves as either the source terminal or the drain terminal (also called the first terminal) The first terminal is connected to the second data line 102B, and the other terminal is connected to the display element section 105B. The pixel 101C includes a transistor 104C (also called a selection transistor) and a display element The transistor 104C of the pixel 101C has a gate terminal connected to the scan line 1 One terminal (also called the first terminal) that is connected to 03C and serves as either the source terminal or the drain terminal ) is connected to the third data line 102C, and the other terminal is connected to the display element section 105C. The circuit configuration shown in FIG. 1A described above is, for example, a circuit configuration including the scanning lines 103A to 103C. In step 03C, the transistors 104A to 104C are simultaneously turned on (turned on). The first data line 102A is connected to the display element section 105A to the display element section 105C as a pixel. This is an effective configuration when separate video signals are supplied from the first to third data lines 102C.

[0026] When pixels are arranged in a matrix, the first data line 102A to the third data line 102C is provided in a direction substantially perpendicular to the scanning lines 103A to 103C, The transistors 104A are connected along the first data line 102A to the third data line 102C. Pixels 101A to 101C each having a transistor 104A to 104C are provided. The circuit configuration shown in FIG. 1A differs from the circuit configuration shown in FIG. 15A in that In the region where the first data line 102A to the third data line 102C are arranged, By providing the intersections of the lines 102A to 102C, the first data line 102 A to the third data lines 102C are connected to the corresponding pixels 101A to 101C, respectively. The first step is to place the transistor in the vicinity of one terminal of the transistor. One terminal of the capacitor is connected to the data line disposed in the closest vicinity.

[0027] A pixel is a pixel that has one color component (e.g., one of R (red), G (green), and B (blue)). This corresponds to a display unit that can control the brightness. Therefore, in the case of a color display device, The smallest display unit of a color image is made up of three pixels: an R pixel, a G pixel, and a B pixel. However, the color elements for displaying a color image are not limited to three colors, and may be more than three colors. You can also use the above, or colors other than RGB.

[0028] A transistor has at least three terminals including a gate, a drain, and a source. A channel region is provided between a drain region and a source region. A current can be passed through the source region, the channel region, and the source region. Which is the source and which is the drain depends on the transistor structure and operating conditions. It is difficult to determine whether the source is a drain or a drain. The regions that function as a source and a drain are not always called a source or a drain. In that case, for example, they may be referred to as one terminal and the other terminal, respectively. Alternatively, they may be referred to as a first electrode (terminal) and a second electrode (terminal), respectively. Alternatively, they may be written as source region and drain region. It may be written as a rain terminal.

[0029] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. "Connected to" means that there is an object between A and B that has some electrical effect. In this case, the part between A and B that contains the object is the node. A and B are connected via a switching element such as a transistor. When the switching element is conductive, A and B may be at roughly the same potential, or A and B may be at the same potential through a resistive element. B is connected, and the potential difference generated across the resistor element affects the operation of the circuit including A and B. When considering the circuit operation, for example, if the part between A and B is the same, This indicates a state in which it is acceptable to regard the node as such.

[0030] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0031] The structure of the transistor provided in the pixel may be an inverted staggered structure or a forward staggered structure. Alternatively, the channel region may be divided into a plurality of regions and connected in series. Alternatively, the gate electrode may be provided above and below the channel region. A dual-gate structure may be used. Also, the semiconductor layer constituting the transistor may be divided into a plurality of islands. The transistor element may be formed from a semiconductor layer and capable of performing a switching operation.

[0032] In FIG. 1A, the intersection 106 is between the second data line 102B and the third data line 102C. The intersection 107 is an area where the first data line 102A and the second data line The intersection 108 is an area where the first data line 102A and the third data line 102B intersect. The intersection 109 is the area where the second data line 102B intersects with the second data line 102C. The intersection 110 is an area where the first data line 102C intersects with the third data line 102C. The intersection 111 is an area where the first data line 102A and the second data line 102B intersect. This is the area where the first data line 102A and the third data line 102C intersect. The data line 102A is disposed in the closest vicinity to one terminal of the transistor 104A. One terminal of 04A is connected without crossing with other wiring. The second data line 102B is disposed adjacent to one terminal of the transistor 104B. One terminal of the resistor 104B is connected without crossing with other wiring. The third data line 102C is disposed closest to one terminal of the transistor 104C. One terminal of the transistor 104C is connected without crossing over any other wiring. This results in:

[0033] The intersections 106 to 111 shown in FIG. 1A are the first data line 102A to the third data line 102B. In order to avoid electrical shorts between the data lines 102C, The intersection 106 using the conductive layer is formed on the other side. At 111, a load capacitance is formed between the crossing data lines. Forming the overlapping areas of the lines, i.e., the first data line 102A to the third data line 102C A conductive layer is formed in the area where one conductive layer overlaps another conductive layer at the intersection.

[0034] FIG. 1B shows the first data line 102A to the third data line 102 shown in FIG. FIG. 1(B) is a circuit diagram showing the crossings 106 to 111 of C as load capacitances. 1A, the first data line 102A is connected to the first pixel 101A. , the second data line 102B is connected to the second pixel 101B, and the third data line 102C is 1B, the crossing 106 shown in FIG. The load capacitance due to the crossing point 107 shown in FIG. The load capacitance is represented by a capacitance element 192, and the load capacitance caused by the intersection 108 shown in FIG. The load capacitance due to the intersection 109 shown in FIG. 1A is represented by a capacitance element 193. 94, and the load capacitance due to the intersection 110 shown in FIG. 1(A) is represented by a capacitance element 195. The load capacitance caused by the intersection 111 shown in FIG.

[0035] As shown in FIG. 1B, the first data line 102A and the second data line 102B form a capacitance A load capacitance is formed by the element 192 and the capacitive element 195. In addition, the second data line 10 2B and the third data line 102C, a load capacitance of the capacitance element 191 and the capacitance element 194 In addition, the first data line 102A and the third data line 102C form a capacitive element. A load capacitance is formed by the first capacitance element 193 and the capacitance element 196. As described above, the load capacitance is The conductive layer forming the first data line 102A to the third data line 102C and another conductive layer at the intersection Therefore, in the configuration of this embodiment, the first The first data line 102A to the third data line 102C are data lines having the same wiring width. Thus, a load capacitance can be formed uniformly on each of the data lines.

[0036] Therefore, in the configuration of this embodiment, the first data line 102A to the third data line 102C Since the area of ​​the intersection formed by the As a result, the first data line 102A to the third data line 102B can be formed with a load capacitance. The load capacitances between the lines 102C can be made uniform, and a signal of a desired potential can be supplied to each pixel. The display device is also susceptible to a shift in the displayed gray scale caused by a difference in the load capacitance between the wirings and / or The signal delay can be reduced.

[0037] Next, in FIG. 2(A) and (B), the display element unit 105A to the display element unit 105B shown in FIG. A specific example of the display element 105C will be described. In FIG. 1A, the display element units 105A to 105C are not overlapped with the other components. The explanation of the relevant points will be omitted.

[0038] The circuit diagram shown in FIG. 2A is a circuit diagram of the display element portion 105A to the display element portion 105B shown in FIG. FIG. 2(A) shows an example of a configuration in which the liquid crystal element is included. The display element section 105A serves as the source terminal or drain terminal of the transistor 104A. A liquid crystal element 121A and a capacitor element 122A are connected to one terminal (also referred to as a second terminal). In the display element portion 105B shown in FIG. The liquid crystal element 121B and the liquid crystal element 121C connected to the other terminal (also called the second terminal) which is the drain terminal The display element portion 105C shown in FIG. The other terminal (also called the second terminal) of the 04C is connected to the source or drain terminal of the The liquid crystal element 121C and the capacitor 122C are connected to the liquid crystal element 121A. The transistor 121C has one electrode (also called a pixel electrode or a first electrode) connected to the transistor 104A. The other electrode (opposite electrode, second electrode) is connected to the other terminal of the transistor 104C. The capacitors 122A to 122C are connected to a common potential line (also referred to as a common line). The capacitor 122C has one electrode (also referred to as a first electrode) of the transistors 104A to 104C. The other electrode (also called the second electrode) of the transistor 104C is connected to the other terminal of the transistor 104C. Note that the capacitors 122A to 122C may be provided as necessary. It is also possible to omit it.

[0039] The circuit diagram shown in FIG. 2B is a circuit diagram of the display element portion 105A to the display element portion 10 5C has a light-emitting element such as an EL (Electro Luminescence) element. The display element section 105A shown in FIG. A transistor 124A (drive transistor) for driving the optical element 123A and the light emitting element 123A. The display element portion 105B shown in FIG. B and a transistor 124B (also called a driving transistor) for driving the light-emitting element 123B. The display element portion 105C shown in FIG. 2B includes a light-emitting element 123C and a light-emitting element A transistor 124C (also called a drive transistor) for driving the transistor 123C. Note that the gate terminals of the transistors 124A to 124C are transistors 104A to 104C are connected to the other terminals, and the source terminal or drain terminal One terminal (also called a first terminal) is connected to the light emitting elements 123A to 123C. It is connected to a current supply line (also called a power supply line) to pass current, and is called the source terminal or drain terminal. The other terminal (also called the second terminal) is the terminal of the light emitting element 123A to the light emitting element 123C. The light-emitting elements 123A to 123B are connected to one electrode (also referred to as a first electrode). The other electrode (also called the second electrode) of C is connected to the ground line (also called the common potential line). Between the gate terminals and the first terminals of the transistors 124A to 124C A capacitor may be provided in the transistor.

[0040] Next, the display element portions 105A to 105C shown in FIG. 2A are each provided with a liquid crystal element. FIG. 1 is a top view of a circuit diagram showing a first embodiment of the present invention; The areas of the intersections formed by the data lines 102A to 102C are made equal to each other, The advantage of being able to form a uniform load capacitance on each line will now be described.

[0041] The top view shown in FIG. 3 corresponds to the top view of the circuit diagram shown in FIG. The capacitor elements 122A to 122C described in 2(A) are omitted in the description. As components corresponding to the liquid crystal elements 121A to 121C, the liquid crystal elements 121A to 121C are 21C (pixel electrodes) are shown. The first data line 102A to the third data line 102C shown in FIG. In addition to the conductive layer (first conductive layer 141) disposed in a direction perpendicular to the scan line 103C, At the intersections 106 to 111, the same conductive layer (second The conductive layer 142 is made of a conductive material.

[0042] In the top view shown in FIG. 3, the first conductive layer 141 and the second conductive layer 142 are formed at the intersections 106 to 111. A load capacitance is formed in the region where the second conductive layer 142 overlaps. The first conductive layer 141 of the third data line 102C and the second conductive layer 142 of the second data line 102B are A load capacitance is formed at the intersection 106 between the first data line 102 and the conductive layer 142. 2A includes a first conductive layer 141 and a second conductive layer 142 of the second data line 102B. A load capacitance is formed at an intersection 107 between the first data line 102A and the first The intersection 108 between the conductive layer 141 of the third data line 102C and the second conductive layer 142 of the third data line 102C. A load capacitance is formed. In addition, the first conductive layer 141 of the second data line 102B and A load capacitance is formed at an intersection 109 between the third data line 102C and the second conductive layer 142. In addition, the first conductive layer 141 of the second data line 102B and the first data line 1 A load capacitance is formed at an intersection 110 between the first conductive layer 142 and the second conductive layer 142 of the first conductive layer 142. The first conductive layer 141 of the third data line 102C and the second conductive layer 142 of the first data line 102A A load capacitance is formed at the intersection 111 between the first data line 10 and the conductive layer 142 of the second data line 10. Between the data lines 2A to 102C, the first conductive layer 141 and the second conductive layer 142 are used. The number of intersections (intersections 106 to 111) formed by the above-mentioned steps can be made equal. Therefore, the first data line 102A to the third data line 102C are arranged to have the same wiring width. By using thin data lines, it is possible to form a load capacitance evenly on each of the data lines. Cut.

[0043] Therefore, in the configuration of this embodiment, the first data line 102A to the third data line 102C Since the area of ​​the intersection formed by the As a result, the first data line 102A to the third data line 102B can be formed with a load capacitance. The load capacitances between the lines 102C can be made uniform, and a signal of a desired potential can be supplied to each pixel. The display device is also susceptible to a shift in the displayed gray scale caused by a difference in the load capacitance between the wirings and / or The signal delay can be reduced.

[0044] In the first data line 102A to the third data line 102C shown in FIG. The first data layer 141 and the second conductive layer 142 are formed by using conductive layers having different electrical conductivities. The wiring resistances of the line 102A to the third data line 102C may differ from each other. In FIG. 4A, the second conductive layer 142 in the top view shown in FIG. 3 is used as a resistor element. FIG.

[0045] As shown in FIG. 4A, the second conductive layer 142 constituting the intersection 106 in FIG. The data line 102B is represented as a first resistor element 151B. The second conductive layer 142 constituting the difference portion 107 is a second resistor of the second data line 102B. 3. The second conductive layer 152B constituting the intersection 108 in FIG. 42 is represented as a first resistive element 151C included in the third data line 102C. 3, the second conductive layer 142 constituting the intersection 109 in FIG. 3 is connected to the third data line 102C. 3. The second resistor element 152C is also shown as the second resistor element 152C which constitutes the intersection 110 in FIG. The second conductive layer 142 is represented as a first resistor element 151A of the first data line 102A. In addition, the second conductive layer 142 constituting the intersection 111 in FIG. 102A is represented as a second resistive element 152A.

[0046] As shown in FIG. 4A, in the configuration of this embodiment, the first data line 102A is a first resistor The second data line 102B has a first resistor element 151A and a second resistor element 152A. The third data line 102C has a first resistor element 151B and a second resistor element 152B. The first resistor element 151C and the second resistor element 152C may be configured as follows. In the configuration of this embodiment, each of the first data line 102A to the third data line 102C Therefore, the second conductive layer 142 can be formed of the same conductor. The first data line 102A to the third data line 10 The wiring resistance of 2C can be made uniform.

[0047] The first resistance elements 151 in the first data line 102A to the third data line 102C A to the first resistance element 151C and the second resistance element 152A to the second resistance element 152C The data line 102 may be located at any one of the first data line 102A to the third data line 102C. For example, as shown in FIG. 4B, a second conductive layer 142 that will become a resistor element is provided. This may also be configured.

[0048] In the configuration of this embodiment, different signals are supplied to a plurality of pixels at the same timing. The display device has a first data line to a third data line as a plurality of wirings for However, other wiring may be used. For example, the wiring shown in FIG. In a configuration having light-emitting elements, in order to pass a current through the light-emitting elements 123A to 123C, As shown in FIG. 5, the current supply lines for the first and second current supply lines 125A and 125B are 5B, the third current supply line 125C is divided into intersections 161 to 166. The first current supply line 125A, the second current supply line 125B, and the third current supply line By providing intersections 161 to 166 in 125C, the first current supply The third current supply line 125A through the third current supply line 125C are connected to the transistors 124A through 124C. 24C, and the transistors 124A to 124C are disposed adjacent to one terminal of the transistors 124A to 124C. One terminal of the first current supply line 125A to the third current supply line 125C is connected to the first current supply line 125A to the third current supply line 125C without crossing with other wiring. 125C.

[0049] Therefore, in the configuration of this embodiment, the first data line 102A to the third data line 102C Similarly, it is possible to form a load capacitance evenly on each of the current supply lines. The load capacitances of the first current supply line 125A to the third current supply line 125C are made uniform, and the A signal of a desired potential can be supplied. The display device can also reduce the difference in load capacitance between the wirings. It is possible to reduce the deviation in the display gray scale and / or the signal delay caused by the above.

[0050] As described above, by reducing the difference in load capacitance between data lines or current supply lines, As a result, the display gray scale shift and / or signal delay caused by the difference in load capacitance can be eliminated. can be reduced.

[0051] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0052] (Embodiment 2) In this embodiment, a configuration different from that of the above-mentioned embodiment 1 will be described with reference to FIG. 6 and FIG. The configuration shown in this embodiment is different from the configuration shown in FIGS. 1 and 2 described in the above embodiment 1. The advantage of this embodiment is that a plurality of scanning lines are provided as a plurality of wirings. In the circuit diagram shown in FIG. 1, multiple wirings are used to supply different signals to multiple pixels at the same time. With N scanning lines (N is a natural number greater than or equal to 3), different scanning signals are supplied to multiple pixels. An example will be described.

[0053] FIG. 6A shows a circuit configuration of a pixel included in a display device. In FIG. Specifically, three scanning lines are used to supply different scanning signals to three different pixels. The pixel 201A has a transistor 204A (selection transistor The pixel 201A has a transistor (also called a transistor) and a display element portion 205A. 204A has a gate terminal connected to the first scanning line 203A and a source terminal or drain terminal One terminal (also called a first terminal) is connected to the data line 202A, and the other terminal is connected to the display element portion 205A. The pixel 201B includes a transistor 204B (selection The pixel 201B has a transistor (also called a transistor) and a display element portion 205B. The gate terminal of the second scanning line 203B is connected to the second scanning line 203B, and the source terminal or drain terminal of the second scanning line 204B is connected to the second scanning line 203B. One terminal (also called a first terminal) serving as a pin terminal is connected to the data line 202B, and the other terminal The pixel 201C includes a transistor 204C (selection The pixel 201C has a display element portion 205C. The gate terminal of the gate electrode 204C is connected to the third scanning line 203C, and the source terminal or drain terminal of the gate electrode 204C is connected to the third scanning line 203C. One terminal (also called a first terminal) serving as an IN terminal is connected to the data line 202C, and the other The terminal is connected to the display element portion 205C. The circuit configuration shown in FIG. For example, the transistors are driven by scanning signals of the first scanning line 203A to the third scanning line 203C. The transistors 204A to 204C are individually turned on (also referred to as on state). The data lines 202A to 202C are connected to the display element sections 205A to 205C. This is an effective configuration when supplying a video signal.

[0054] When pixels are arranged in a matrix, the first scanning line 203A to the third scanning line 20 3C is provided in a direction substantially perpendicular to the data lines 202A to 202C, Transistors 204A to 204C are arranged along the first to third scanning lines 203A to 203C. Thus, pixels 201A to 201C each having a transistor 204C are provided. The circuit configuration shown in FIG. 6A is a crossing of the first scanning line 203A to the third scanning line 203C. By providing the first scanning line 203A to the third scanning line 203C, The pixel 201A to the pixel 201C are arranged in the vicinity of the gate terminals of the transistors included in the pixel 201A to the pixel 201C. Then, the gate terminal of the transistor is connected to the scanning line disposed in the closest vicinity.

[0055] In FIG. 6A, the intersection 206 is where the second scanning line 203B and the third scanning line 203C intersect. The intersection 207 is an area where the first scanning line 203A and the second scanning line 203B intersect. The intersection 208 is an area where the first scanning line 203A and the third scanning line 20 3C. Also, the intersection 209 is the area where the second scanning line 203B and the third scanning line 203C intersect. The intersection 210 is the area where the first scanning line 203A and the second scanning line 203C intersect. The intersection 211 is an area where the first scanning line 203A and the third scanning line 203B intersect. The first scanning line 203A is a region where the second scanning line 203C intersects with the transistor The gate terminal of the transistor 204A is disposed in the closest proximity to the gate terminal of the transistor 204A. The second scanning line 203B is connected to the transistor without crossing the other scanning lines. The gate terminal of the transistor 204B is disposed closest to the gate terminal of the transistor 204B. The third scanning line 203C is connected without crossing with other wirings. The gate terminal of the transistor 204C is disposed closest to the gate terminal of the transistor 204C. The terminals are connected without crossing other wirings.

[0056] The intersections 206 to 211 shown in FIG. 6A correspond to the first scanning line 203A to the third scanning line 203B. In order to avoid electrical shorts between the scan lines 203C, one of the intersecting scan lines is The conductive layer is used to form the intersections 206 to 211. In this case, a load capacitance is formed between the intersecting scanning lines. The load capacitance is generated when the intersecting scanning lines overlap. a conductive layer forming a region where the first scanning line 203A to the third scanning line 203C are formed, Another conductive layer is formed in the area of ​​overlap at the intersection.

[0057] FIG. 6B shows the first scanning line 203A to the third scanning line 203C shown in FIG. FIG. 6B is a circuit diagram showing the crossing points 206 to 211 as load capacitances. In the same manner as in FIG. 6A, the first scanning line 203A is connected to the first pixel 201A, and the second The first scanning line 203B is connected to the second pixel 201B, and the third scanning line 203C is connected to the third pixel 6B, the crossover caused by the crossover 206 shown in FIG. The load capacitance is represented by a capacitance element 291, and the load capacitance caused by the intersection 207 shown in FIG. The load capacitance due to the intersection 208 shown in FIG. 6A is represented by a capacitance element 292. 93, and the load capacitance caused by the intersection 209 shown in FIG. 6(A) is represented by a capacitance element 294. The load capacitance caused by the intersection 210 shown in FIG. 6(A) is represented by a capacitance element 295. ) caused by intersection 211 is represented by capacitive element 296.

[0058] As shown in FIG. 6B, the first scanning line 203A and the second scanning line 203B form a capacitive element. A load capacitance is formed by the second scanning line 203B and the capacitance element 295. A load capacitance is formed by the capacitance elements 291 and 294 together with the third scanning line 203C. In addition, the first scanning line 203A and the third scanning line 203C form a capacitance element 293 and a capacitance As described above, the load capacitance is formed by the capacitance element 296. The conductive layer forming the third scanning lines 203A to 203C overlaps with another conductive layer at the intersection. Therefore, in the configuration of this embodiment, the first scanning line 203A By making the first to third scan lines 203C into scan lines having the same wiring width, A load capacitance can be formed equally between them.

[0059] Therefore, in the configuration of this embodiment, the intersections with the first scanning line 203A to the third scanning line 203C are Since the area of ​​the difference part can be made equal, the load capacitance is formed equally on each scanning line. As a result, the load is reduced between the first scanning line 203A to the third scanning line 203C. By making the capacitance uniform, it is possible to supply a scanning signal to each pixel at a desired timing. The display device can reduce delays in scanning signals caused by differences in load capacitance between lines. .

[0060] 7A and 7B, the display element unit 205A to the display element unit 205B shown in FIG. A specific example of the display element 205C will be described. In FIG. 6A, the display element units 205A to 205C are not overlapped with the display element units 205A to 205C. The explanation of the relevant points will be omitted.

[0061] The circuit diagram shown in FIG. 7A is a circuit diagram of the display element unit 205A to the display element unit 20 FIG. 7(A) shows an example of a configuration in which the liquid crystal element is included. The display element section 205A serves as the source terminal or drain terminal of the transistor 204A. A liquid crystal element 221A and a capacitor element 222A are connected to one terminal (also referred to as a second terminal). In the display element portion 205B shown in FIG. The liquid crystal element 221B and the liquid crystal element 221C connected to the other terminal (also called the second terminal) which is the drain terminal The display element portion 205C shown in FIG. The other terminal (also called the second terminal) of the 04C is connected to the source or drain terminal of the The liquid crystal element 221C and the capacitor 222C are connected to the liquid crystal element 221A. The transistor 221C has one electrode (also called a pixel electrode or a first electrode) connected to the transistor 204A. The other electrode (opposite electrode, second electrode) is connected to the other terminal of the transistor 204C. The capacitor elements 222A to 222C are connected to a common potential line (also referred to as a common line). The capacitor 222C has one electrode (also referred to as a first electrode) of the transistors 204A to 204C. The other electrode (also called the second electrode) of the transistor 204C is connected to the other terminal of the transistor 204C. Note that the capacitors 222A to 222C may be provided as necessary. It is also possible to omit it.

[0062] The circuit diagram shown in FIG. 7B is a circuit diagram of the display element unit 205A to the display element unit 20 5C has a light-emitting element such as an EL (Electro Luminescence) element. The display element section 205A shown in FIG. A transistor 224A (drive transistor) for driving the optical element 223A and the light emitting element 223A. The display element portion 205B shown in FIG. B and a transistor 224B (also called a driving transistor) for driving the light emitting element 223B. The display element portion 205C shown in FIG. 7B includes a light-emitting element 223C and a light-emitting element A transistor 224C (also called a drive transistor) for driving the transistor 223C. Note that the gate terminals of the transistors 224A to 224C are transistors 204A to 204C are connected to the other terminals, and the source terminals or drain terminals One terminal (also called a first terminal) is connected to the light emitting elements 223A to 223C. It is connected to a current supply line (also called a power supply line) to pass current, and is called the source terminal or drain terminal. The other terminal (also called the second terminal) is the terminal of the light emitting element 223A to the light emitting element 223C. The light-emitting elements 223A to 223B are connected to one electrode (also referred to as a first electrode). The other electrode (also called the second electrode) of C is connected to the ground line (also called the common potential line). Between the gate terminals and the first terminals of the transistors 224A to 224C A capacitor may be provided in the transistor.

[0063] As a result, the difference in the load capacitance of the scanning lines can be reduced. Therefore, the delay in the scanning signal caused by the difference can be reduced.

[0064] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0065] (Embodiment 3) In this embodiment, the circuit configuration described in the first embodiment is a field sequential type. An example of a display device that performs display will be described with reference to FIGS. In the display device of this embodiment, a liquid crystal display device using liquid crystal elements as display elements will be described.

[0066] <Configuration example of liquid crystal display device> FIG. 8(A) is a diagram showing a configuration example of a liquid crystal display device. The liquid crystal display device shown in FIG. A pixel section 30, a scanning line driving circuit 31, and a data line driving circuit 32 (also called a signal line driving circuit) are provided. The scanning lines are arranged parallel or approximately parallel to each other, and the potentials of the scanning lines are controlled by a scanning line driving circuit 31. 3n (n is a natural number of 2 or more) scanning lines 33 are arranged parallel or approximately parallel to each other. The potential of each of the m data lines (m is a natural number equal to or greater than 2) is controlled by the data line driving circuit 32. ) first data lines 341, m second data lines 342, and m third data lines 343. 43 and,

[0067] Furthermore, the pixel section 30 is divided into three regions (regions 301 to 303), The image sensor has a plurality of pixels arranged in a matrix (n rows and m columns). Among the multiple pixels arranged in a matrix (3n rows and m columns) in the element portion 30, Each of the first data lines 341 is connected to m pixels arranged in a row of the region 30. Among the multiple pixels 351 arranged in a matrix (n rows and m columns) in 1, Each of the second data lines 342 is connected to n pixels arranged in a column. Among the multiple pixels 352 arranged in a matrix (n rows and m columns) in Each of the third data lines 343 is connected to n pixels arranged in the region 303. In the example shown in FIG. 1, a plurality of pixels 353 are arranged in a matrix (n rows and m columns). The first data line 341 to the third data line 342 are connected to n pixels arranged in the pixel array. As described in the first embodiment, the crossing portion 361 is provided in the first data. The first data line 341 to the second data line 343 are connected to the transistors of the pixels in the regions 301 to 303. Therefore, the first data line 341 to the third data line 342 are arranged in the vicinity of one of the terminals. As a result, the load capacitance can be uniformly formed on each of the data lines 343. It is possible to supply a video signal of the desired potential to the pixel, and the difference in load capacitance between the data lines This can reduce the deviation in the displayed gray scale and / or the signal delay.

[0068] The scanning line driving circuit 31 receives a scanning line driving circuit start signal (GSP), a scanning line driving circuit start signal (GSP), and a scanning line driving circuit start signal (SSP) from the outside. Clock signal (GCK) for the scan line driver circuit, and power supplies for driving high and low power potentials The data line driving circuit 32 is also supplied with a data line driving circuit start signal from the outside. signal (SSP), clock signal for data line driver circuit (SCK), image signal (data1~ Data3) and driving power sources such as a high power supply potential and a low power supply potential are input.

[0069] 8B to 8D are diagrams showing examples of the circuit configuration of a pixel. 8(C) is a diagram showing an example of a circuit configuration of a pixel 351 arranged in the region 301. FIG. 8(D) is a diagram showing an example of a circuit configuration of a pixel 352 arranged in the region 302. 8B is a diagram showing an example of a circuit configuration of the pixel 353 disposed in the pixel 351 shown in FIG. The gate terminal is connected to the scanning line 33, and one of the source and drain terminals is connected to the first data line 34. A transistor 3511 is connected to the data line 341, and one electrode of the transistor 3511 is A capacitance element connected to the other of the source and drain terminals and having the other electrode connected to a capacitance line 3512, one electrode (pixel electrode) is the source and drain of the transistor 3511, The other electrode (opposite electrode) is connected to the terminal of the capacitor 3512 and one electrode of the capacitor 3512. and a liquid crystal element 3514 connected to a wiring for supplying a forward potential.

[0070] The pixel 352 shown in FIG. 8C and the pixel 353 shown in FIG. 8D also have the circuit configuration itself shown in FIG. 8B). However, in the pixel 352 shown in FIG. 8C, One of the source and drain of the transistor 3521 is connected to the second data line 341 instead of the first data line 341. The pixel 351 shown in FIG. 8(B) is connected to the data line 342 at a point different from that of the pixel 351 shown in FIG. 8(D). In the element 353, one of the source and drain of the transistor 3531 is connected to the first data line 34. 8B in that it is connected to the third data line 343 instead of the first data line. .

[0071] <Configuration Example of Scanning Line Driving Circuit 31> FIG. 9A shows an example of the configuration of the scanning line driving circuit 31 included in the liquid crystal display device shown in FIG. 8A. The scanning line driving circuit 31 shown in FIG. 9(A) is a shift register having n output terminals. The shift register 311 has a shift register 312. Each of the output terminals is connected to one of the n scanning lines 33 arranged in the area 301. The output terminals of the shift register 312 are connected to n input terminals of the n-th input terminals of the shift register 312 arranged in the region 302. The output terminals of the shift register 313 are connected to any one of the scanning lines 33. , is connected to any one of n scanning lines 33 arranged in the region 303. The register 311 is a shift register that supplies a scanning signal to the area 301. The shift register 312 is a shift register that supplies scanning signals in the area 302. The shift register 313 is a shift register that provides the scanning signals in the area 303 . Specifically, the shift register 311 receives a start pulse for a scanning line driving circuit input from the outside. The pulse signal (GSP) is used as a trigger, and the scanning line 33 arranged in the first row is used as a starting point. Shift the scanning signal (scanning line 33 every 1 / 2 cycle of the clock signal (GCK) for the scanning line driving circuit) The shift register 312 has a function of sequentially selecting the scanning line driving signals input from the outside. The circuit start pulse signal (GSP) triggers the scanning line arranged in the n+1th row. The shift register 313 has a function of shifting the scanning signal sequentially starting from the external The start pulse signal (GSP) for the scanning line driver circuit input from It has a function of sequentially shifting the scanning signal starting from the scanning line 33 arranged in the +1st row.

[0072] <Example of Operation of Scanning Line Driving Circuit 31> An example of the operation of the scanning line driving circuit 31 will be described with reference to FIG. 9(B) shows a clock signal (GCK) for the scanning line driving circuit, The signal (SR311out) output from the n output terminals is a shift register 312. The signals (SR312out) output from the n output terminals and the shift register 31 3 shows signals (SR313out) output from n output terminals of the SR313.

[0073] In the sampling period (T1), the shift register 311 is Starting from the scanning line 33, the high level potential is 1 / 2 clockwise from the scanning line 33 arranged in the nth row. The shift register 312 shifts the data sequentially every clock period (horizontal scanning period) to the n+1th row. Starting from the scanning line 33 arranged in the row 2n, a high-level voltage is applied to the scanning line 33 arranged in the row 2n. The position is shifted sequentially every 1 / 2 clock period (horizontal scanning period), and in the shift register 313 , starting from the scanning line 33 arranged in the 2n+1th row, to the scanning line 33 arranged in the 3nth row. The high-level potential is shifted sequentially every 1 / 2 clock period (horizontal scanning period). Therefore, the scanning line driving circuit 31 detects m pixels 351 arranged in the first row via the scanning lines 33. m pixels 351 arranged in rows 1 to n are sequentially selected, and m pixels 351 arranged in rows n+1 are sequentially selected. m pixels 352 arranged in the 2nth row are sequentially selected from the m pixels 352 arranged in the 2nth row, and 2n+ The m pixels 353 arranged in the 1st row to the m pixels 353 arranged in the 3nth row are sequentially That is, the scanning line driving circuit 31 selects three different rows for each horizontal scanning period. It is possible to supply scanning signals to the arranged 3m pixels.

[0074] In the sampling period (T2) and the sampling period (T3), the shift register 31 The operation of the shift register 313 from 1 is the same as that in the sampling period (T1). That is, the scanning line driving circuit 31 performs a specific scanning operation for each horizontal scanning period, similar to the sampling period (T1). It is possible to supply scanning signals to 3m pixels arranged in three rows.

[0075] <Configuration Example of Data Line Driving Circuit 32> FIG. 10A shows an example of the configuration of the data line driving circuit 32 of the liquid crystal display device shown in FIG. 8A. The data line driving circuit 32 shown in FIG. A shift register 320, m transistors 321, and m transistors 322, The gate terminal of the transistor 321 is connected to the The jth (j is a natural number between 1 and m) output terminal of the soft register 320 is connected to the jth One of the source and drain terminals is connected to a wiring that supplies a first image signal (data1). The other of the source and drain terminals is connected to the j-th column of the pixel section 30. The gate terminal of the transistor 322 is connected to the data line 341 of the shift register 321. The jth (j is a natural number between 1 and m) output terminal of the register 320 is connected to the One of the source and drain terminals is connected to a wiring that supplies a second image signal (data2). The other of the source and drain terminals is connected to a second diode arranged in the j-th column in the pixel section 30. The gate terminal of the transistor 323 is connected to the data line 342. 320, the jth (j is a natural number from 1 to m) output terminal of the One of the drain terminals is connected to a wiring that supplies a third image signal (data3), The other terminal of the source and drain is a third data line arranged in the j-th column in the pixel section 30. Connected to 343.

[0076] In this case, the first image signal (data1) is , red (R) image signal (retained in the pixel when the backlight is turned on red (R) In the sampling period (T2), a green image signal is supplied to the first data line 341. The image signal (G) is supplied to the first data line 341, and during the sampling period (T3), A blue (B) image signal is supplied to the first data line 341. The signal (data2) is the second image signal of blue (B) during the sampling period (T1). data line 342, and in the sampling period (T2), a red (R) image signal is A green (G) image signal is supplied to the second data line 342 during the sampling period (T3). A third image signal (data3) is supplied to the second data line 342. In the sampling period (T1), a green (G) image signal is input to the third data line 343. During the sampling period (T2), a blue (B) image signal is supplied to the third data line 34. 3, and in the sampling period (T3), a red (R) image signal is supplied to the third data line 343.

[0077] <Backlight configuration example> FIG. 10B shows a back panel provided behind the pixel section 30 of the liquid crystal display device shown in FIG. 8A. A diagram showing an example of the configuration of a light. The backlight shown in FIG. 10(B) has red (R), green (G), and The backlight unit 36 ​​has a plurality of light sources each having three colors: blue (A), red (B), and blue (C). The backlight units 36 are arranged in a matrix and are illuminated in a specific area. In this example, the lighting of multiple pixels arranged in 3n rows and m columns can be controlled individually. As a backlight for the corresponding LEDs, at least every k rows and m columns (here, k is n / 4) A backlight unit 36 ​​is provided, and the lighting of the backlight unit 36 ​​is independently controlled. That is, the backlight is capable of illuminating at least the pixels in the first to kth rows. Backlight unit for pixels in rows 2n+3k+1 to 3n The backlight unit will have a built-in LED and will be able to control the lighting of each backlight unit independently.

[0078] <Example of operation of liquid crystal display device> FIG. 11 shows the timing of scanning of the scanning signal and lighting of the backlight in the above-mentioned liquid crystal display device. The liquid crystal display device is a diagram showing a sampling period (T1) for one row. m pixels 351 arranged in the first row to m pixels 351 arranged in the nth row are sequentially selected. , and m pixels 352 arranged in the n+1th row to m pixels 353 arranged in the 2nth row 52 are sequentially selected, and m pixels 353 arranged in the 2n+1th row to m pixels 354 arranged in the 3nth row are sequentially selected. By sequentially selecting the m pixels 353, an image signal can be input to each pixel. It is.

[0079] Also, the timing of scanning the scanning signal and turning on the backlight in the liquid crystal display device shown in FIG. The area (1st row to nth row, n+1st row to 2nth row, and 2n+1st row to 3nth row) For each eye, a scanning signal is scanned and a backlight unit that displays a specific color (red (R), green (G) It is possible to set the timing to turn on the blue (B) or green (C) in parallel. In the liquid crystal display device of the present embodiment, the sampling period (T1) to the sampling period (T3 ) an image is formed in the pixel section 30. In the liquid crystal display device, the sampling period (T1) to the sampling period (T3) are 1 This corresponds to a frame period.

[0080] <Liquid Crystal Display Device of the Present Embodiment> The liquid crystal display device of the present embodiment has a first data line to which the configuration of the first embodiment can be applied. The third data line 341 to the third data line 343 form a load capacitance evenly on each wiring. As a result, a video signal with a desired potential can be supplied to each pixel, and This can reduce the display gray scale deviation and / or signal delay caused by the difference in load capacitance. do.

[0081] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0082] (Embodiment 4) In this embodiment mode, a plan view and a cross-sectional view of a pixel included in a display device, here a liquid crystal display device, are shown. An example will be described with reference to the drawings.

[0083] FIG. 12(A) shows a plan view of one of a plurality of pixels included in a display panel. 12(A) is a cross-sectional view taken along dashed line AB in FIG.

[0084] In FIG. 12A, the wiring layer (the source electrode layer) that will become the first data line to the third data line 1201A to 1201C, and the drain electrode layer 1202) are shown in the upper and lower parts of the figure. The gate electrode layer 1 is arranged so as to extend in the direction (column direction). 203) is approximately perpendicular to the source electrode layers 1201A to 1201C. The capacitance wiring layer 1204 is arranged to extend in the left-right direction (row direction in the figure). is approximately parallel to the gate electrode layer 1203 and is adjacent to the source electrode layer 1201A. The source electrode layer 1201C extends in a direction substantially perpendicular to the source electrode layer 1201C (the left-right direction (row direction) in the figure). The intersection 1209 is formed by the gate electrode layer 1203 and the capacitance wiring layer 1204. The source electrode layers 1201B and 1201C are crossed by a wiring layer formed of the same layer as 04. This shows how it works.

[0085] In FIG. 12A, a pixel of a display panel includes a transistor having a gate electrode layer 1203. A transistor 1205 is provided over the insulating film 1227. 1228 and an interlayer film 1229 are provided.

[0086] The pixels of the display panel shown in FIG. 12(A) and FIG. 12(B) are connected to a transistor 1205. The transistor 1205 has a transparent electrode layer 1208 as a first electrode layer. An opening (contact hole) is formed in the insulating film 1227, the insulating film 1228, and the interlayer film 1229. In the opening (contact hole), the transparent electrode layer 1208 and the transistor 1 205 is connected.

[0087] The transistor 1205 shown in FIG. 12A and FIG. 12B has a gate insulating layer 1212 interposed therebetween. The semiconductor layer 1206 is disposed on the gate electrode layer 1203. A source electrode layer 1201A and a drain electrode layer 1202 are provided in contact with each other. 1204, a gate insulating layer 1212, and a drain electrode layer 1202 are stacked to form a capacitor element 1 It forms 207.

[0088] The first substrate 1218 on which the transistor 1205 is formed has a liquid crystal layer 1217 therebetween. It is disposed so as to overlap with the second substrate 1219, sandwiching it therebetween.

[0089] In FIG. 12B, a bottom-gate inverted staggered transistor is used as the transistor 1205. However, any other transistors can be used in the liquid crystal display device disclosed in this specification. The structure of the gate electrode is not particularly limited. For example, the gate electrode is a semiconductor layer. A top-gate transistor is disposed on the upper side of the gate insulating layer. A staggered type transistor and a planar type transistor having a bottom gate structure in which an electrode layer is arranged under a semiconductor layer A rain type transistor or the like can be used.

[0090] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0091] (Embodiment 5) In this embodiment, an example of a transistor that can be applied to the liquid crystal display device disclosed in this specification will be described. The structure of a transistor that can be applied to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a gate electrode is disposed above the semiconductor layer via a gate insulating layer. A bottom structure in which a gate electrode is disposed below a semiconductor layer via a gate insulating layer. The gate structure may be a staggered type or a planar type. In the single-gate structure, where one channel formation region is formed, and in the double-gate structure, where two channel formation regions are formed, The channel region may be a gate structure or a triple gate structure. A dual gate semiconductor device having two gate electrode layers arranged above and below the gate insulating layer. Examples of cross-sectional structures of transistors are shown in FIGS. vinegar.

[0092] Note that the transistors shown in FIGS. 13A to 13D each include an oxide semiconductor as a semiconductor layer. The advantage of using an oxide semiconductor is that the on-state of a transistor is High field effect mobility (maximum 5cm 2 / Vsec or more, preferably a maximum of 1 0cm 2 / Vsec~150cm 2 / Vsec), and low in the off state of the transistor. Off-current per unit channel width (for example, the off-current per unit channel width is 1aA / μm, more preferably less than 10zA / μm, and less than 100zA / μm at 85° C. The aim is to obtain a satisfactory result.

[0093] The transistor 410 shown in FIG. 13A is a bottom-gate transistor. It is also called an inverted staggered transistor.

[0094] The transistor 410 includes a gate electrode layer 401, a gate The insulating layer 402, the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 40 In addition, an insulating film that covers the transistor 410 and is stacked on the oxide semiconductor layer 403 A protective insulating layer 409 is further formed on the insulating film 407. .

[0095] The transistor 420 shown in FIG. 13B is a channel protection type (also called a channel stop type). This is one of the bottom-gate structures known as inverted staggered transistors.

[0096] The transistor 420 includes a gate electrode layer 401, a gate The insulating layer 402, the oxide semiconductor layer 403, and the oxide semiconductor layer 403 are provided so as to cover a channel formation region thereof. The insulating layer 427 functioning as a channel protective layer, the source electrode layer 405a, and the drain electrode A protective insulating layer 409 is formed to cover the transistor 420. do.

[0097] The transistor 430 shown in FIG. 13C is a bottom-gate transistor. A gate electrode layer 401, a gate insulating layer 402, a source electrode layer 404, and a gate insulating layer 405 are formed on a substrate 400 having a surface. 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403. An insulating film 407 is provided to cover the capacitor 430 and to be in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is further formed on 407 .

[0098] In the transistor 430, the gate insulating layer 402 is connected to the substrate 400 and the gate electrode layer 400. 1, a source electrode layer 405a and a drain electrode layer 405b are provided on the gate insulating layer 402. The gate insulating layer 402 and the source electrode layer 405b are provided in contact with each other. In FIG. 5a, an oxide semiconductor layer 403 is provided over a drain electrode layer 405b.

[0099] The transistor 440 shown in FIG. 13D is a top-gate transistor. The transistor 440 is formed on a substrate 400 having an insulating surface, an insulating layer 437, an oxide semiconductor A conductor layer 403, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating layer 402, and a gate electrode layer 401, and a source electrode layer 405a and a drain electrode layer 405b. The wiring layers 436a and 436b are provided adjacent to each other and connected to each other.

[0100] In this embodiment, as described above, the oxide semiconductor layer 403 is used as the semiconductor layer. The oxide semiconductor used for the oxide semiconductor layer 403 is a quaternary metal oxide, In-Sn- Ga-Zn-O oxide semiconductors and In-Ga-Zn-O oxides, which are ternary metal oxides Semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors , Sn-Ga-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, Sn- Al-Zn-O oxide semiconductors and In-Zn-O oxide semiconductors, which are binary metal oxides, body, Sn-Zn-O oxide semiconductor, Al-Zn-O oxide semiconductor, Zn-Mg-O Oxide semiconductors, Sn-Mg-O oxide semiconductors, In-Mg-O oxide semiconductors, In -O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, In-Ga- In addition, the oxide semiconductor may contain SiO2. Here, for example, the In-Ga-Zn-O-based oxide semiconductor is an indium (I n), gallium (Ga), and zinc (Zn), and its chemical The stoichiometric ratio is not particularly important. Also, elements other than In, Ga, and Zn may be included.

[0101] The oxide semiconductor layer 403 is formed of a material represented by the chemical formula InMO3(ZnO). m (m>0) A thin film can be used. Here, M is one selected from Ga, Al, Mn, and Co. Or it represents multiple metal elements. For example, M can be Ga, Ga and Al, Ga and Mn, or or Ga and Co.

[0102] A transistor 410 and a transistor 420 each including an oxide semiconductor layer 403 430, the transistor 440 reduces the current value in the off state (off current value). Therefore, in the pixel, the capacitance element for holding the electric signal such as the video signal can be made small. Therefore, the aperture ratio of the pixel can be improved, and This has the effect of reducing power consumption.

[0103] In addition, a transistor 410, a transistor 420, and a transistor The off-state current of the transistor 430 and the transistor 440 can be reduced. In the device, the retention time of electrical signals such as video signals can be extended, and the writing interval can also be extended. Therefore, the cycle of one frame period can be extended, and the still image display period can be set This reduces the frequency of refresh operations, resulting in greater power consumption savings. In addition, the transistors can be formed separately in a driver circuit portion and a pixel portion on the same substrate. Since the liquid crystal display device can be manufactured by using only one of the above components, the number of components required can be reduced.

[0104] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. A glass substrate such as borosilicate glass or aluminoborosilicate glass is used.

[0105] In the bottom-gate transistors 410, 420, and 430, In the above case, an insulating film serving as a base film may be provided between the substrate and the gate electrode layer. It has the function of preventing the diffusion of impurity elements such as silicon nitride, silicon oxide, and oxynitride. A laminated structure of one or more films selected from a silicon oxide film, a silicon oxynitride film, and a silicon oxide nitride film. It can be formed.

[0106] The material of the gate electrode layer 401 is molybdenum, titanium, chromium, tantalum, tungsten, Metallic materials such as aluminum, copper, neodymium, and scandium, or alloys containing these as the main components It can be formed of a gold material in a single layer or in a multilayer structure.

[0107] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. silicon layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer , an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or an aluminum oxide layer. The aluminum layer can be formed as a single layer or a stacked layer. For example, the first gate insulating layer and Then, a silicon nitride layer (SiN y (y>0)) was formed on the first gate insulating layer as a second gate insulating layer having a thickness of 5 nm. A silicon oxide layer of 300 nm or more (SiO x (x>0)) to a total thickness of 20 The gate insulating layer is set to 0 nm.

[0108] The conductive film used for the source electrode layer 405a and the drain electrode layer 405b is, for example, Al a metal film containing an element selected from the group consisting of Cr, Cu, Ta, Ti, Mo, and W, or Metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) In addition, the lower or upper side of a metal film such as Al or Cu may be used. Both are made of high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film A laminate of a nitride film, a molybdenum nitride film, and a tungsten nitride film may be used.

[0109] The wiring layer 436a and the wiring layer 436b are connected to the source electrode layer 405a and the drain electrode layer 405b, respectively. The conductive film such as 6b is also made of the same material as the source electrode layer 405a and the drain electrode layer 405b. It can be used.

[0110] In addition, the source electrode layer 405a, the drain electrode layer 405b (wiring formed in the same layer as this The conductive film (including the layer) may be formed of a conductive metal oxide. The oxides are indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide Indium zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide Containing kon can be used.

[0111] Insulating films 407 and 427 are provided above the oxide semiconductor layer, and an insulating layer 43 is provided below the oxide semiconductor layer. 7 is typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an oxide An inorganic insulating film such as an aluminum nitride film can be used.

[0112] The protective insulating layer 409 provided above the oxide semiconductor layer is formed of a silicon nitride film, an alumina film, or the like. Inorganic insulating films such as aluminum film, silicon nitride oxide film, and aluminum nitride oxide film are used. It is possible.

[0113] In addition, a planarizing insulating film is formed on the protective insulating layer 409 in order to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (low In addition, multiple insulating films made of these materials can be stacked. A planarizing insulating film may be formed by performing the above-mentioned process.

[0114] The transistor including the oxide semiconductor layer manufactured in accordance with this embodiment can remove hydrogen and moisture. By removing the impurities, the off-state current can be reduced. The oxide semiconductor layer can be formed without a process such as laser irradiation, and can be used for a large-area substrate. This is advantageous because it allows the formation of transistors on the substrate.

[0115] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0116] (Embodiment 6) The display device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (a television or a television receiver). (also called "transmitting devices"), computer monitors, digital cameras, digital video cameras Cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) , portable game machines, personal digital assistants, audio playback devices, pachinko machines and other large game machines. Examples of electronic devices including the display device described in the above embodiment will be described. do.

[0117] FIG. 14(A) shows an example of an electronic book. The electronic book shown in FIG. 14(A) has a housing 1 The device is made up of two housings, housing 700 and housing 1701. The doors are connected together by a hinge 1704 and can be opened and closed. This configuration allows the device to operate like a book.

[0118] A display unit 1702 is incorporated in the housing 1700, and a display unit 1703 is incorporated in the housing 1701. The display unit 1702 and the display unit 1703 can also be used to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 1702 in FIG. 14A) and An image can be displayed on a display unit (display unit 1703 in FIG. 14A).

[0119] FIG. 14A shows an example in which an operation unit and the like are provided in a housing 1700. The body 1700 includes a power input terminal 1705, operation keys 1706, a speaker 1707, etc. The operation keys 1706 can be used to turn pages. The device may be configured to include a keyboard, a pointing device, etc. On the sides, there are external connection terminals (earphone terminal, USB terminal, USB cable, etc.) The device may be configured to include a terminal for connecting to a cable, a recording medium insertion section, etc. The electronic book shown in 14(A) may be configured to have the function of an electronic dictionary.

[0120] FIG. 14B shows an example of a digital photo frame using a display device. For example, The digital photo frame shown in FIG. 14B has a display unit 1712 built in a housing 1711. The display unit 1712 is capable of displaying various images, such as digital images. By displaying image data taken with a digital camera, etc., it functions like a normal photo frame. It is possible to do so.

[0121] The digital photo frame shown in FIG. 14(B) has an operation unit, an external connection terminal (USB terminals that can be connected to various cables such as USB cables, etc.), and a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a display on the surface of a digital photo frame to improve the design. Insert a memory that stores image data taken with a digital camera into the recording medium insertion section to record images. Data can be imported and the imported image data can be displayed on the display unit 1712.

[0122] FIG. 14C shows an example of a television set using the display device. The television device shown in FIG. 17 has a display unit 1722 built into a housing 1721. 1722 allows the display of images. The display unit 1722 is the same as that in the above embodiment. The display device shown in FIG.

[0123] The television device shown in FIG. 14C can be operated using an operation switch provided on the housing 1721, This can be done using a separate remote control. The channel and volume can be controlled, and the image displayed on the display unit 1722 can be controlled. In addition, the information output from the remote control device can be displayed on the remote control device. A display unit for indicating the position of the object may be provided.

[0124] FIG. 14(D) shows an example of a mobile phone using the display device. The mobile phone has a display unit 1732 built into a housing 1731, as well as operation buttons 1733, An operation button 1737, an external connection port 1734, a speaker 1735, and a microphone 1736 It is equipped with the following:

[0125] In the mobile phone shown in FIG. 14D, the display portion 1732 is a touch panel. By touching the screen, the display contents of the display unit 1732 can be operated. Or, creation of an e-mail or the like can be performed by touching the display portion 1732 with a finger or the like.

[0126] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0127] 101A Pixel 101B pixels 101C Pixel 102A First Data Line 102B Second Data Line 102C 3rd data line 103A Scan Line 103B Scan Line 103C Scan Line 104A Transistor 104B Transistor 104C Transistor 105A Display element section 105B Display element section 105C Display element section 106 Intersection 107 Intersection 108 Intersection 109 Intersection 110 Intersection 111 Intersection 121A Liquid crystal element 121B Liquid crystal element 121C Liquid crystal element 122A Capacitive Element 122B Capacitive element 122C Capacitive element 123A Light emitting element 123B Light emitting element 123C Light-emitting element 124A Transistor 124B Transistor 124C Transistor 125A First Current Supply Line 125B Second current supply line 125C 3rd current supply line 131A One electrode 131B One electrode 131C One electrode 141 First conductive layer 142 Second conductive layer 161 Intersection 162 Intersection 163 Intersection 164 Intersection 165 Intersection 166 Intersection 191 Capacitive element 192 Capacitive element 193 Capacitive element 194 Capacitive element 195 Capacitive element 196 Capacitive element 201A Pixel 201B pixels 201C Pixel 202A Data Line 202B Data line 202C Data line 203A 1st scan line 203B 2nd scan line 203C 3rd scan line 204A Transistor 204B Transistor 204C Transistor 205A Display element section 205B Display element section 205C Display element section 206 Intersection 207 Intersection 208 Intersection 209 Intersection 210 Intersection 211 Intersection 221A Liquid crystal element 221B Liquid crystal element 221C Liquid crystal element 222A Capacitive element 222B Capacitive element 222C Capacitive element 223A Light emitting element 223B Light emitting element 223C Light-emitting element 224A Transistor 224B Transistor 224C Transistor 291 Capacitive element 292 Capacitive element 293 Capacitive Element 294 Capacitive element 295 Capacitive Element 296 Capacitive Element 30 Pixel section 31 Scanning line driving circuit 32 Data line driving circuit 33 Scan Lines 301 area 302 areas 303 areas 311 Shift Register 312 Shift Register 313 Shift Register 320 Shift Register 321 Transistor 322 Transistor 323 Transistor 341 First Data Line 342 Second Data Line 343 Third Data Line 351 pixels 352 pixels 353 pixels 3511 Transistor 3512 Capacitor 3514 Liquid crystal element 3521 Transistor 3531 Transistor 36 Backlight unit 361 Intersection 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating Film 409 Protective Insulation Layer 410 Transistor 420 Transistor 427 Insulating Layer 430 Transistor 436a Wiring layer 436b wiring layer 437 Insulating Layer 440 Transistor 1201A Source electrode layer 1201B Source electrode layer 1201C Source electrode layer 1202 Drain electrode layer 1203 Gate electrode layer 1204 Capacitive wiring layer 1205 Transistor 1206 Semiconductor layer 1207 Capacitive element 1208 Transparent electrode layer 1209 Intersection 1212 Gate insulation layer 1217 Liquid crystal layer 1218 First Board 1219 Second Board 1227 Insulating film 1228 Insulating film 1229 Interlayer film 1501A Pixel 1501B pixels 1501C Pixels 1502A First Data Line 1502B Second Data Line 1502C 3rd Data Line 1503A Scan Line 1503B Scan Line 1503C Scan Line 1504A Transistor 1504B Transistor 1504C Transistor 1505A Display element section 1505B Display element section 1505C Display element section 1506 Intersection 1507 Intersection 1516 Load capacity 1517A load capacity 1517B load capacity 151A Resistance element 151B Resistance element 151C Resistance element 152A Resistance element 152B Resistance element 152C Resistance element 1700 Case 1701 Case 1702 Display section 1703 Display section 1704 Hinge 1705 Power input terminal 1706 Operation key 1707 Speaker 1711 Case 1712 Display section 1721 Case 1722 Display section 1723 Stand 1731 Case 1732 Display section 1733 Operation button 1734 External connection port 1735 Speaker 1736 Mike 1737 Operation button

Claims

1. The pixel array includes first to third pixels arranged in sequence along one direction, The first pixel has a first transistor whose gate is always electrically connected to a first scan line; the second pixel has a second transistor whose gate is always electrically connected to a second scan line; the third pixel is a display device having a third transistor whose gate is always electrically connected to a third scan line, a first conductive film that functions as the second scan line and overlaps with a channel region of the second transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to one of the source and the drain of the second transistor; a third conductive film having a region disposed below the second conductive film via the first insulating film and always electrically connected to the second conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to the second conductive film via the third conductive film; a fifth conductive film having a region disposed below the fourth conductive film via the first insulating film and always electrically connected to the third conductive film via the fourth conductive film; a sixth conductive film that functions as the first scan line and overlaps with a channel region of the first transistor; a seventh conductive film that functions as the third scan line and overlaps with a channel region of the third transistor; an eighth conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and a region intersecting with the seventh conductive film, and always electrically connected to one of a source or a drain of the first transistor; the third conductive film, the fourth conductive film, and the fifth conductive film are disposed in a region between the seventh conductive film and the sixth conductive film in a plan view; the eighth conductive film has a region intersecting with the third conductive film; Display device.

2. The pixel array includes first to third pixels arranged in sequence along one direction, The first pixel has a first transistor whose gate is always electrically connected to a first scan line; the second pixel has a second transistor whose gate is always electrically connected to a second scan line; the third pixel is a display device having a third transistor whose gate is always electrically connected to a third scan line, a first conductive film that functions as the second scan line and overlaps with a channel region of the second transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to one of the source and the drain of the second transistor; a third conductive film having a region disposed below the second conductive film via the first insulating film and always electrically connected to the second conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to the second conductive film via the third conductive film; a fifth conductive film having a region disposed below the fourth conductive film via the first insulating film and always electrically connected to the third conductive film via the fourth conductive film; a sixth conductive film that functions as the first scan line and overlaps with a channel region of the first transistor; a seventh conductive film that functions as the third scan line and overlaps with a channel region of the third transistor; an eighth conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and a region intersecting with the seventh conductive film, and always electrically connected to one of a source or a drain of the first transistor; each of the first conductive film, the third conductive film, the fifth conductive film, the sixth conductive film, and the seventh conductive film has a region in contact with an insulating surface; the third conductive film, the fourth conductive film, and the fifth conductive film are disposed in a region between the seventh conductive film and the sixth conductive film in a plan view; the eighth conductive film has a region intersecting with the third conductive film; Display device.

3. The pixel array includes first to third pixels arranged in sequence along one direction, The first pixel has a first transistor whose gate is always electrically connected to a first scan line; the second pixel has a second transistor whose gate is always electrically connected to a second scan line; the third pixel is a display device having a third transistor whose gate is always electrically connected to a third scan line, a first conductive film that functions as the second scan line and overlaps with a channel region of the second transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to one of the source and the drain of the second transistor; a third conductive film having a region disposed below the second conductive film via the first insulating film and always electrically connected to the second conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to the second conductive film via the third conductive film; a fifth conductive film having a region disposed below the fourth conductive film via the first insulating film and always electrically connected to the third conductive film via the fourth conductive film; a sixth conductive film that functions as the first scan line and overlaps with a channel region of the first transistor; a seventh conductive film that functions as the third scan line and overlaps with a channel region of the third transistor; an eighth conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and a region intersecting with the seventh conductive film, and always electrically connected to one of a source or a drain of the first transistor; the third conductive film, the fourth conductive film, and the fifth conductive film are disposed in a region between the seventh conductive film and the sixth conductive film in a plan view; the fifth conductive film is disposed in a region between the first conductive film and the sixth conductive film in a plan view; the eighth conductive film has a region intersecting with the third conductive film; Display device.

4. The pixel array includes first to third pixels arranged in sequence along one direction, The first pixel has a first transistor whose gate is always electrically connected to a first scan line; the second pixel has a second transistor whose gate is always electrically connected to a second scan line; the third pixel is a display device having a third transistor whose gate is always electrically connected to a third scan line, a first conductive film that functions as the second scan line and overlaps with a channel region of the second transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to one of the source and the drain of the second transistor; a third conductive film having a region disposed below the second conductive film via the first insulating film and always electrically connected to the second conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and always electrically connected to the second conductive film via the third conductive film; a fifth conductive film having a region disposed below the fourth conductive film via the first insulating film and always electrically connected to the third conductive film via the fourth conductive film; a sixth conductive film that functions as the first scan line and overlaps with a channel region of the first transistor; a seventh conductive film that functions as the third scan line and overlaps with a channel region of the third transistor; an eighth conductive film having a region intersecting with the first conductive film, a region intersecting with the sixth conductive film, and a region intersecting with the seventh conductive film, and always electrically connected to one of a source or a drain of the first transistor; each of the first conductive film, the third conductive film, the fifth conductive film, the sixth conductive film, and the seventh conductive film has a region in contact with an insulating surface; the third conductive film, the fourth conductive film, and the fifth conductive film are disposed in a region between the seventh conductive film and the sixth conductive film in a plan view; the fifth conductive film is disposed in a region between the first conductive film and the sixth conductive film in a plan view; the eighth conductive film has a region intersecting with the third conductive film; Display device.

Images