Method, system and program for identifying dependencies in control sequences

Abstract

A method, system, and program for identifying dependencies in a control sequence includes receiving a control block having a first error dependency (EDEP) level, retaining the first EDEP level and determining whether the received control block executed successfully, receiving a subsequent control block having a second EDEP level, comparing the first EDEP level with the second EDEP level, and providing the subsequent control block for execution based at least in part on the successful execution of the received control block and the second EDEP level being less than or equal to the first EDEP level.

Description

[Technical field]

[0001] The present invention relates to computer hardware, and more particularly to identifying dependencies in control sequences for execution on a hardware accelerator. [Background technology]

[0002] Various acceleration techniques can be used to increase the efficiency of performing various computing tasks. Hardware acceleration achieves this increase in efficiency by offloading various tasks to highly specialized hardware such as graphics processing units (GPUs) and application-specific integrated circuits (ASICs). Software acceleration techniques are designed to maximize system functionality performed in software before offloading other functions to external hardware. Summary of the Invention

[0003] Embodiments of the invention are directed to a computer-implemented method for identifying dependencies in a control sequence for execution on a hardware accelerator. A non-limiting example of the computer-implemented method includes receiving a control block including a first error dependency (EDEP) level, retaining the first EDEP level, and determining whether the received control block successfully executed. The computer-implemented method also includes receiving a subsequent control block including a second EDEP level, comparing the first EDEP level to the second EDEP level, and providing the subsequent control block for execution based at least in part on the successful execution of the received control block and the second EDEP level being less than or equal to the first EDEP level. Also provided are embodiments of the invention directed to systems and computer program products for identifying dependencies in a control sequence for execution on a hardware accelerator.

[0004] Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference should be made to the detailed description and drawings.

[0005] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the end of this specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a system in accordance with one or more embodiments of the present invention. [Figure 2A] FIG. 2 illustrates an example control sequence having dependencies in accordance with one or more embodiments of the present invention. [Figure 2B]FIG. 2 illustrates an example control sequence having dependencies in accordance with one or more embodiments of the present invention. [Diagram 3] 1 is a flowchart of a method for identifying dependencies in a control sequence in accordance with one or more embodiments of the present invention. [Figure 4] FIG. 1 is a block diagram of a computer system in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The diagrams shown herein are exemplary. There may be many variations in the diagrams or operations described herein without departing from the scope of the invention. For example, actions may be performed in a different order, or actions may be added, removed, or modified. Additionally, the term "coupled" and variations thereof indicate that there is a communication path between two elements, and do not imply a direct connection between the elements without an intervening element / connection between them. All of these variations are considered part of this specification.

[0008] In the accompanying figures and the following detailed description of the disclosed embodiments, various elements shown in the figures are given two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number corresponds to the figure in which the element is first shown.

[0009] One or more embodiments of the present invention provide a hardware accelerator that queues multiple control block (CB) instructions that are intended to be executed in a predetermined sequence. The control blocks may indicate relationships to preceding and succeeding control blocks. If an error occurs during execution of a control block, one or more control blocks may need to be reprocessed in order to properly complete a job or task.

[0010] Current systems do not provide a mechanism for tracking dependencies between control blocks that must be executed in a given sequence or control blocks of another independent sequence. If a control block that one or more subsequent control blocks depend on fails, the subsequent dependent control blocks continue to be processed. Because the sequence of control blocks has been executed including the failing control block, the entire sequence of control blocks must be requeued in the control block store queue and reexecuted. This can degrade system performance. Also, if another independent sequence of control blocks is queued after the sequence of control blocks that includes the failing control block, that independent sequence of control blocks must still wait for completion of processing of the control blocks that depend on the failing control block, which also introduces delays.

[0011] One or more embodiments of the present invention address one or more of the above-mentioned deficiencies of the prior art by providing a mechanism that can identify dependencies between a stream of sequential control blocks such that, if one control block fails, an execution unit can automatically abort processing of subsequent control blocks depending on the failing control block, and then automatically resume execution when the dependency on that control block is no longer present.

[0012] Referring now to FIG. 1, a block diagram of a system 100 for identifying dependencies in a control sequence is shown, in accordance with one or more embodiments of the present invention. In some embodiments of the present invention, the system 100 may be implemented in a computer system / server 12 in a computing node 10 as shown in FIG. 4. The system 100 includes a host processor 102. The host processor 102 is configured to assign an error dependency (EDEP) level to each control block (CB), and the host processor 102 is configured to provide the control block to a control block store queue 104. In some embodiments, the host processor 102 may include one or more hardware and / or software instructions for configuration. The hardware may include one or more elements of the computing node 10 shown in FIG. 1. Each control block is programmed with an EDEP level assigned by the host processor 102. The EDEP level may be two bits long and indicates a hierarchical dependency between the control blocks in the control sequence. The EDEP level determines whether a subsequent control block should be executed if a previous control block in the hierarchy fails to execute.

[0013] In accordance with one or more embodiments of the present invention, control block store queue 104 is configured to store one or more control blocks. The control blocks are provided to EDEP processor 108 upon reaching the head of the store queue. In accordance with one or more embodiments of the present invention, EDEP processor 108 is configured to perform several functions, including, but not limited to, receiving control blocks from control block store queue 104, providing control blocks to execution units 110, processing responses from execution units 110, providing response words to response word handler 112, receiving reset signals from host processor 102, and others.

[0014] The EDEP processor 108 may be further configured to detect whether a fault occurs during execution of the control block in the execution unit 110. Errors may occur for a variety of reasons. For example, an error may occur during execution when a "divide by zero" operation or parity occurs. If an error is detected, the execution unit 110 may provide notification of such error to the EDEP processor 108. If an error is detected, each subsequent control block that depends on the faulty control block indicated by the EDEP level is not executed by the execution unit 110. As such, when subsequent control blocks that depend on the faulty control block are received and identified from the control block store queue 104, they are abended (abnormal ending). The control block is not executed and a response word (RspW) is generated indicating that the control block was not executed.

[0015] EDEP processor 108 is configured to analyze the EDEP level of received control blocks and to maintain a current EDEP level, where the EDEP level indicates dependencies between control blocks. In response to determining that an error has occurred, EDEP processor 108 subsequently analyzes the EDEP level of each received control block to determine whether the control block should be passed to execution unit 110 for execution.

[0016] For example, if EDEP processor 108 determines that a fault has occurred in a control block having EDEP level=0, then all subsequent CBs having EDEP level=0 received by EDEP processor 108 having EDEP level=0 do not need to be processed. Thus, upon receipt, those control blocks are aborted in EDEP processor 108 and are not passed to execution unit 110 for execution. By not executing those control blocks in execution unit 110, processing delays are improved because subsequent control blocks that depend on the faulty control block are not processed.

[0017] In a scenario where the control block at EDEP level n fails to execute, all subsequent CBs with an EDEP level less than n (<n) are not executed in execution unit 110. This continues until a CB with an EDEP level (≧) n is found. In this scenario, the execution of the control block is resumed until a control block in which another failure has occurred is detected.

[0018] The EDEP processor 108 is configured to receive a response word (RspW) from the execution unit 110 and provide it to the response word handler 112 to inform the host processor 102 of the status of the control block. The RspW can indicate success, error, or abandonment of the execution of the control block. It should be understood that the RspW can indicate additional information to the host processor 102.

[0019] In one or more embodiments of the present invention, the host processor 102 of the system 100 can adjust the EDEP level held in the EDEP processor 108 by sending a NULL CB. In a non-limiting example, a NULL CB with EDEP = 3 is sent to the EDEP processor and, when received, the EDEP processor 108 is set to 3. It should be understood that the NULL CB is executed without error. Alternatively, the host processor 102 can directly provide a CB with EDEP = 3 to the EDEP processor 108 to reset the dependency chain. In one example, when a NULL CB or a reset CB is received by the EDEP processor 108, the EDEP level held in the EDEP processor 108 can be initialized to the highest EDEP level and reset to the highest level when a new dependency chain is identified.

[0020] As shown in Figures 2A and 2B, an example of an error dependency for identifying dependencies between multiple control blocks in a control sequence is provided. Multiple control blocks are shown, and one or more control blocks may be used to define a job. Each of the control blocks is queued in the control block storage queue 104 in a specific sequence before execution. Each control block may include a job number and an EDEP level. As shown in the non-limiting error dependency example of Figure 2A, two jobs (job 1, job 2) are represented by multiple control blocks. Job 1 is the first job queued in the control block storage queue 104 and provided to the EDEP processor 108, followed by job 2, which is the second job. Each of the jobs (job 1, job 2) includes multiple control blocks, and as shown, the right-most control block includes the highest EDEP level (EDEP level 2), and each subsequent control block includes an EDEP level equal to or less than the EDEP level of the right-most control block. As control blocks reach the head of the control block store queue 104, each control block is sent to the EDEP processor 108 and, if a fault is detected, the EDEP level of the control block is compared to the EDEP level held by the EDEP processor 108.

[0021] In a scenario where the EDEP processor 108 determines that the right-most control block has failed, each of the subsequent control blocks is aborted. Consider an example where the second control block (job 1, layer 1) with EDEP level=1 fails, all subsequent jobs / control blocks with EDEP level=0 will not execute because they have a lower EDEP level. In another example, if a control block (job 1, layer 2) fails, all subsequent control blocks / jobs with EDEP level=0 will not execute on the execution unit 110. If the control block (job 2, layer 1) executes successfully (no errors), the remaining jobs / control blocks are executed until the failed control block is detected.

[0022] In another example of error dependency as shown in FIG. 2B, four different jobs (J1, J2, J3, J4) are depicted. The first job (J1) is queued in the control block storage queue 104, followed by the subsequent jobs (J2, J3, J4). The first control block of J1 to be processed is "Clear Spad" EDEP3, and control block J4 MB1, EDEP1 is processed last. In a scenario where the rightmost job "Clear Spad" with EDEP level=3 fails, each control block up to the next "Clear Spad" VF:2, EDEP3 is not executed. That is, the control blocks (J1 Pre-load, J1 MB1, J1 MB2, J2 Preload, J2 MB1, J2 MB2, J2 MB3, J2 MB4) are not executed by the execution unit 110 because the rightmost control block "Clear Spad" fails.

[0023] However, if only the control block (J1 MB1) fails, the next job (J2, MB2) can still be executed. If the control block corresponding to the J1 preload step fails, both control blocks (J1 MB1, J1 MB2) will not be executed, but jobs (J2, J3, J4) can still be processed.

[0024] Referring now to Figure 3, a flow chart of a method 300 for identifying dependencies in a control sequence is shown, according to one or more embodiments. The method 300 may be performed in a system, such as the system 100 shown in Figure 1. It should be understood that the method 300 may be performed in other systems and is not limited to that shown in Figure 1. The method 300 begins at block 302 and proceeds to block 304, which provides for receiving a control block at an error dependency (EDEP) processor 108, the control block including a first EDEP level. The EDEP level indicates dependencies between the control blocks.

[0025] Block 306 maintains the first EDEP level in EDEP processor 108. EDEP processor 108 maintains the EDEP level of the most recent control block, which allows EDEP processor 108 to determine dependencies between control blocks in a control sequence.

[0026] Block 308 determines whether the received control block was successfully executed. In response to receiving a notification or response from execution unit 110, EDEP processor 108 determines whether the control block was successfully executed at execution unit 110. Block 310 receives a subsequent control block including a second EDEP level. EDEP processor 108 receives the subsequent control block having an EDEP level from control block store queue 104.

[0027] The first EDEP level and the second EDEP level are compared in block 312. In one or more embodiments of the invention, if the EDEP level of the received control block is higher than the EDEP level held in the EDEP processor 108, the EDEP level is updated. Receiving an EDEP level higher than the held EDEP level may indicate that a new sequence of control blocks has been received that is independent of previous control blocks.

[0028] Block 314 provides a subsequent control block for execution based at least in part on successful execution of the received control block and the second EDEP level being less than or equal to the first EDEP level. If no faults or errors are detected in the execution of the control block, the subsequent control block may be provided to and executed by execution unit 110. However, if a fault is detected in the control block, the subsequent control block that depends on the faulty control block is not provided to and executed by execution unit 110. The control block identified as depending on the faulty control block based on the EDEP level is not processed, and the next control block that does not depend on the faulty control block, also indicated by the EDEP level, may be processed. Thus, the processing of other control blocks is not delayed by the processing of a control block that depends on the faulty control block.

[0029] Method 300 ends at block 316. It should be understood that method 300 is not intended to be limited by the steps illustrated in Figure 3 and may include additional steps and / or a different sequence of steps to identify dependencies in a control sequence in accordance with one or more embodiments of the present invention.

[0030] 4, a schematic diagram of an example computing node is shown. Computing node 10 is merely one example of a suitable computing node and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the invention described herein. In any event, computing node 10 is capable of implementing and / or executing any of the functionality described above.

[0031] Computing node 10 includes computer system / server 12, which is operable in many other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0032] The computer system / server 12 may be described in the general context of computer system executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 12 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0033] 4, computer system / server 12 within computing node 10 is shown in the form of a general purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components, including system memory 28, to processor 16.

[0034] Bus 18 represents any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example and not limitation, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnects (PCI) bus.

[0035] Computer system / server 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system / server 12 and includes both volatile and nonvolatile media, removable and non-removable media.

[0036] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may further include other removable / non-removable volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive may be provided for reading from and writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical medium. In such an example, each may be connected to the bus 18 by one or more data media interfaces. As further illustrated and described below, the memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of an embodiment of the present invention.

[0037] A program / utility 40 having a set (at least one) of program modules 42 may be stored in memory 28, as well as, by way of example and not limitation, an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may comprise an implementation of a networking environment. The program modules 42 generally perform the functions and / or methodologies of embodiments of the invention described herein.

[0038] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, one or more devices that allow a user to interact with the computer system / server 12, or any device that allows the computer system / server 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.), or combinations thereof. Such communication may occur via an input / output (I / O) interface 22. Furthermore, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or combinations thereof, via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. It is understood that other hardware and / or software components, not shown, may be used with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0039] The techniques described herein improve upon the prior art by reducing the delay in processing non-dependent control blocks and increasing the processing speed of control blocks in a control sequence. The EDEP level allows the system to discard control blocks that are dependent on a failed control block. Control blocks that are not dependent on a failed control block can be processed without being delayed by the processing of control blocks that are dependent on the failed control block.

[0040] The present invention may be a system, method, or computer program product, or combination thereof, at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to carry out aspects of the present invention.

[0041] A computer readable storage medium may be any tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or groove ridge structures having instructions recorded thereon, and any suitable combination thereof. A computer-readable storage medium, as used herein, should not be construed to be a transitory signal per se, such as, for example, radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over a wire.

[0042] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to the respective computing / processing device or to an external computer or storage device over a network, such as, for example, the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface of each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0043] The computer readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the last scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or a connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing state information of the computer-readable program instructions to execute the computer-readable program instructions to perform aspects of the invention.

[0044] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0045] These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that, when the instructions are executed by the processor of the computer or other programmable data processing apparatus, means are generated for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored constitutes an article of manufacture including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0046] Furthermore, computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps, thereby generating a computer-implemented process that, when executed on the computer, other programmable apparatus, or other device, implements the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0047] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions described in the blocks may occur out of the order shown. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may possibly be executed in the reverse order. It will also be noted that each block in the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or executes a combination of dedicated hardware and computer instructions.

[0048] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments described in this specification.

[0049] Various embodiments of the invention are described herein with reference to the associated drawings. Alternative embodiments of the invention may be devised without departing from the scope of the invention. In the following description and drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the invention is not limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. Also, various tasks and process steps described herein may be combined into a more comprehensive procedure or process having additional steps or functions not specifically described herein.

[0050] The following definitions and abbreviations will be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variations thereof, are intended to include a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and can include other elements not expressly listed or pertaining to such composition, mixture, process, method, article, or device.

[0051] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The term "a plurality" may be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" may include both indirect and direct "connections."

[0052] The terms "about," "substantially," and "approximately," as well as variations thereof, are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time of this application. For example, "about" can include a range of ±8% or 5% or 2% from a given value.

[0053] For the sake of brevity, prior art related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and particular computer programs for implementing various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are mentioned only briefly herein or omitted entirely, and details of well-known systems and / or processes are not provided.

Claims

1. A method for identifying dependencies in a control sequence by computer information processing, comprising the steps of: receiving at a processor a control block including a first error dependency (EDEP) level; maintaining the first EDEP level in the processor; determining whether the received control block was successfully executed; receiving a subsequent control block including a second EDEP level; comparing the first EDEP level with the second EDEP level; providing the subsequent control block for execution based at least in part on the successful execution of the received control block and the second EDEP level being less than or equal to the first EDEP level; A method comprising:

2. The method of claim 1 , wherein the EDEP levels define hierarchical dependencies between sequences of control blocks.

3. The method of claim 1 , wherein the determining comprises receiving a notification of successful execution of the control block from an execution unit.

4. 4. The method of claim 3, further comprising sending a response word from said processor to a host processor, said response word indicating whether said control block was successfully executed by said execution unit.

5. 2. The method of claim 1, further comprising: in response to receiving a reset command from a host processor, resetting the EDEP level held in the processor.

6. 2. The method of claim 1, further comprising initializing the EDEP level maintained in the processor to a starting value.

7. 2. The method of claim 1, further comprising: in the processor, aborting additional subsequent control blocks based at least in part on the EDEP level of a failing control block.

8. 4. The method of claim 3, further comprising providing the additional subsequent control block to the execution unit if the EDEP level of the additional subsequent control block exceeds the retained EDEP level.

9. 1. A system for identifying dependencies in a control sequence for execution on a hardware accelerator, comprising: a host processor configured to assign an error dependency (EDEP) level to a control block; a control block store queue configured to store the control blocks; an EDEP processor; The EDEP processor comprises: receiving a control block including a first error dependency level; maintaining the first EDEP level; determining whether the received control block was successfully executed; receiving a subsequent control block including a second EDEP level; comparing the first EDEP level with the second EDEP level; providing the subsequent control block for execution based at least in part on the successful execution of the received control block and the second EDEP level being less than or equal to the first EDEP level; A system configured to run

10. The system of claim 9 , wherein the EDEP levels define hierarchical dependencies between sequences of control blocks.

11. The system of claim 9 , further comprising an execution unit configured to provide notification of successful execution of the control block to the EDEP processor.

12. 12. The system of claim 11, wherein the EDEP processor is further configured to send a response word to the host processor, the response word indicating whether the control block was successfully executed by the execution unit.

13. 10. The system of claim 9, wherein the host processor is further configured to reset the EDEP level held in the EDEP processor in response to receiving a reset command from the host processor.

14. 10. The system of claim 9, wherein the host processor is further configured to initialize the EDEP level maintained in the EDEP processor to a starting value.

15. 10. The system of claim 9, wherein the EDEP processor is further configured to abort additional subsequent control blocks based at least in part on the EDEP level of a failing control block.

16. 12. The system of claim 11, wherein the EDEP processor is further configured to provide the additional subsequent control block to the execution unit if the EDEP level of the additional subsequent control block exceeds the retained EDEP level.

17. A computer program causing a computer to execute a method according to any one of claims 1 to 8.

18. A storage medium having the computer program described in claim 17 stored in a computer-readable storage medium.

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