Encoding device, encoding method, decoding device, decoding method, and program

Abstract

The present technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program which enable encoding in which running disparity is controlled and transmission efficiency is high. The present technology is provided with: a scrambling unit that scrambles an input data sequence; a calculation unit that calculates a first running disparity for the data sequence scrambled by the scrambling unit; a determination unit that determines whether to invert the data sequence scrambled by the scrambling unit, on the basis of the first running disparity calculated by the calculation unit and a second running disparity calculated at a time point before the first running disparity; and an addition unit that, on the basis of the determination result by the determination unit, inverts or does not invert the data sequence scrambled by the scrambling unit, and outputs the data sequence with a flag indicating the determination result added thereto. The present technology can be applied to a device that performs communication according to SLVC-EC specifications.

Description

[Technical field]

[0001] The present technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program, for example, an encoding device, an encoding method, a decoding device, a decoding method, and a program that enable DC-free encoding and decoding. [Background technology]

[0002] As image sensors achieve higher image quality and higher frame rates, the data transmission capacity required for the interface between the image sensor and a DSP (Digital Signal Processor) that processes the images captured by the image sensor is increasing.

[0003] Interface standards for data transmission between chips, such as between an image sensor and a DSP, include the Mobile Industry Processor Interface (MIPI) standard and the Scalable Low Voltage Signaling-Embedded Clock (SLVS-EC) standard.

[0004] Patent Document 1 describes a transmission method in which packets that store image data are distributed to multiple lanes and the data is transmitted from an image sensor to a DSP via the multiple lanes. In this transmission method, image data constituting each line of one frame is stored in each packet in the image sensor and transmitted to the DSP. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-120159 A Summary of the Invention [Problem to be solved by the invention]

[0006] In data transmission between chips, encoding methods such as 8b / 10b, 64b / 66b, and 64b / 67b were used, and decoding was performed using a decoding method corresponding to the encoding method. The 8b / 10b encoding method could reduce transmission efficiency. Also, the 64b / 66b encoding method could not be DC-free. The 64b / 67b encoding method could deteriorate the run length, making accurate decoding impossible on the receiving side.

[0007] The present technology has been made in view of such circumstances, and makes it possible to perform encoding and decoding with controlled running disparity and run length without deteriorating transmission efficiency. [Means for solving the problem]

[0008] According to one aspect of the present technology, an encoding device includes a scrambling unit that scrambles an input data sequence; a calculation unit that calculates a first running disparity of the data sequence scrambled by the scrambling unit; a determination unit that determines whether to invert the data sequence scrambled by the scrambling unit based on the first running disparity calculated by the calculation unit and a second running disparity calculated at an earlier point in time than the first running disparity; and an addition unit that inverts or does not invert the data sequence scrambled by the scrambling unit based on a determination result by the determination unit, and adds a flag indicating the determination result to output the data sequence. a parity section for treating a plurality of the data strings as one block, generating a calculation result using the flag added to each of the data strings, and adding the calculation result to the end of the one block; .

[0009] According to one aspect of the present technology, there is provided an encoding method, in which an encoding device scrambles an input data sequence, calculates a first running disparity of the scrambled data sequence, determines whether to invert the scrambled data sequence based on the calculated first running disparity and a second running disparity calculated at a point in time before the first running disparity, inverts or does not invert the scrambled data sequence based on a result of the determination, and outputs the scrambled data sequence with a flag indicating the result of the determination added thereto. A plurality of the data strings are treated as one block, a calculation result is generated using the flag added to each of the data strings, and the calculation result is added to the end of the one block.do.

[0010] A first program according to one aspect of the present technology includes a program for causing a computer that controls an encoding device to scramble an input data sequence, calculate a first running disparity of the scrambled data sequence, determine whether or not to invert the scrambled data sequence based on the calculated first running disparity and a second running disparity calculated at an earlier point in time than the first running disparity, invert or not invert the scrambled data sequence based on a result of the determination, and output the scrambled data sequence with a flag added that indicates the result of the determination. A plurality of the data strings are treated as one block, a calculation result is generated using the flag added to each of the data strings, and the calculation result is added to the end of the one block. The process includes the step of:

[0011] A decoding device according to one aspect of the present technology includes a determination unit that references a flag added to an input data sequence and determines whether the data sequence is inverted or not; an output unit that inverts and outputs the input data sequence when the determination unit determines that the data sequence is inverted, and outputs the input data sequence without inverting it when the determination unit determines that the data sequence is not inverted; and a descrambling unit that descrambles the data sequence output by the output unit. and an error determination unit that determines whether or not there is an error in the flag based on a calculation result using the flag that is added to each of the data strings that is added to the end of the block, the data strings being grouped into one block. .

[0012] In a decoding method according to one aspect of the present technology, a decoding device refers to a flag added to an input data sequence, determines whether the data sequence is inverted, and if it is determined that the data sequence is inverted, inverts and outputs the input data sequence, and if it is determined that the data sequence is not inverted, outputs the input data sequence without inverting it, and descrambles the output data sequence. A plurality of the data strings are regarded as one block, and it is determined whether or not there is an error in the flag from a calculation result using the flag added to each of the data strings added to the end of the block. do.

[0013] A second program according to one aspect of the present technology includes a program for causing a computer that controls a decoding device to refer to a flag added to an input data sequence, determine whether the data sequence has been inverted, invert the input data sequence and output it when it has been determined that the data sequence has been inverted, and output the input data sequence without inverting it when it has been determined that the data sequence has not been inverted, and descramble the output data sequence. A plurality of the data strings are regarded as one block, and it is determined whether or not there is an error in the flag from a calculation result using the flag added to each of the data strings added to the end of the block. The process includes the step of:

[0014] In an encoding device, an encoding method, and a first program according to one aspect of the present technology, an input data sequence is scrambled, a first running disparity of the scrambled data sequence is calculated, and based on the calculated first running disparity and a second running disparity calculated at a point in time before the first running disparity, it is determined whether or not to invert the data sequence, and based on a result of the determination, the data sequence is inverted or not inverted, and a flag indicating the result of the determination is added and output. A number of data strings are treated as one block, and a calculation result is generated using a flag added to each data string, and the calculation result is added to the end of the block. do.

[0015] In a decoding device, a decoding method, and a second program according to one aspect of the present technology, a flag added to an input data sequence is referenced to determine whether or not the data sequence is inverted, and if it is determined that the data sequence is inverted, the input data sequence is inverted and output, and if it is determined that the data sequence is not inverted, the input data sequence is output without being inverted, and the output data sequence is descrambled. A plurality of data strings are treated as one block, and a flag is added to each data string at the end of each block. The result of the calculation using the flag is used to determine whether or not there is an error in the flag. do.

[0016] The encoding device or the decoding device may be an independent device or an internal block constituting a single device.

[0017] The program can also be provided by transmitting it via a transmission medium or by recording it on a recording medium. [Brief description of the drawings]

[0018] [Figure 1] 1 is a diagram showing a configuration of an embodiment of a data processing system to which the present technology is applied; [Diagram 2] FIG. 13 is a diagram for explaining the number of bits to be divided. [Diagram 3] FIG. 2 illustrates an example of the configuration of an encoder. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of a decoder. [Diagram 5] FIG. 13 is a diagram for explaining control of running disparity. [Figure 6] FIG. 13 is a diagram for explaining a flag. [Figure 7] FIG. 13 is a diagram for explaining the relationship between a running disparity and a flag. [Figure 8] FIG. 13 is a diagram for explaining run length control. [Figure 9] 11 is a flowchart illustrating an encoding process. [Figure 10] 13 is a flowchart illustrating a decoding process. [Figure 11] FIG. 13 is a diagram for explaining the configuration of a decoder that performs error detection. [Figure 12] FIG. 13 is a diagram for explaining flag settings when performing error detection. [Figure 13] FIG. 13 is a diagram for explaining flag settings when performing error detection. [Figure 14] FIG. 11 is a diagram showing the configuration of another embodiment of a data processing system to which the present technology is applied. [Figure 15] FIG. 1 illustrates an example of the configuration of a transmission system. [Figure 16] FIG. 2 is a diagram illustrating an example of a frame format. [Figure 17] FIG. 2 is a diagram illustrating an example of the configuration of a transmitting unit and a receiving unit. [Figure 18] FIG. 13 is a diagram showing a header structure. [Figure 19] 11A and 11B are diagrams showing the contents and amount of information of header information. [Figure 20]FIG. 13 is a diagram illustrating an example of a bit array. [Figure 21] FIG. 13 is a diagram illustrating an example of pixel-to-byte conversion when the pixel value of each pixel is represented by 8 bits. [Figure 22] FIG. 13 is a diagram showing an example of pixel-to-byte conversion when the pixel value of each pixel is represented by 10 bits. [Diagram 23] FIG. 13 is a diagram showing an example of pixel-to-byte conversion when the pixel value of each pixel is represented by 12 bits. [Figure 24] FIG. 13 is a diagram showing an example of pixel-to-byte conversion when the pixel value of each pixel is represented by 14 bits. [Diagram 25] FIG. 13 is a diagram showing an example of pixel-to-byte conversion when the pixel value of each pixel is represented by 16 bits. [Figure 26] FIG. 11 is a diagram illustrating an example of payload data. [Figure 27] FIG. 13 is a diagram showing another example of payload data. [Figure 28] FIG. 13 is a diagram showing an example of payload data into which parity has been inserted. [Figure 29] FIG. 13 is a diagram showing a state in which a header is added to payload data. [Diagram 30] FIG. 13 is a diagram showing a state in which a header and a footer are added to payload data. [Diagram 31] FIG. 13 is a diagram showing a state in which a header is added to payload data into which parity has been inserted. [Diagram 32] FIG. 13 is a diagram illustrating an example of packet data allocation. [Diagram 33] FIG. 11 is a diagram illustrating an example of a control code. [Diagram 34] FIG. 13 is a diagram showing the value of K Character. [Diagram 35] FIG. 13 is a diagram showing an example of inserting a Pad Code. [Diagram 36] FIG. 13 is a diagram showing an example of packet data after a control code is inserted. [Figure 37] FIG. 13 is a diagram illustrating an example of data skew correction. [Figure 38]10 is a flowchart illustrating processing of the imaging device. [Figure 39] 39 is a flowchart illustrating a data transmission process performed in step S102 of FIG. 38. [Diagram 40] 39 is a flowchart illustrating a data reception process performed in step S103 of FIG. 38. [Diagram 41] FIG. 11 is a diagram showing a control sequence when switching the number of lanes. [Diagram 42] FIG. 13 is a diagram illustrating another example of the configuration of a transmission system. [Diagram 43] FIG. 1 is a diagram illustrating an example of the configuration of an encoder including a pre-encoder. [Diagram 44] FIG. 13 is a diagram for explaining conversion in case 1. [Diagram 45] FIG. 13 is a diagram for explaining conversion in case 2. [Diagram 46] FIG. 13 is a diagram illustrating an example of a conversion table. [Figure 47] FIG. 13 is a diagram for explaining conversion in case 3. [Figure 48] FIG. 13 is a diagram for explaining conversion in Case 4. [Figure 49] FIG. 11 is a diagram for explaining a data conversion method. [Figure 50] FIG. 11 is a diagram for explaining a data conversion method. [Figure 51] 11 is a flowchart illustrating an encoding process. [Figure 52] 13 is a flowchart illustrating a decoding process. [Figure 53] FIG. 13 is a diagram for explaining a control code when an error occurs. [Figure 54] FIG. 13 is a diagram for explaining a data string that is prohibited from being inverted. [Figure 55] FIG. 2 is a diagram illustrating an example of a configuration related to an encoder. [Figure 56] FIG. 13 is a diagram illustrating another example of the configuration related to an encoder. [Figure 57] FIG. 13 is a diagram illustrating an example of a configuration related to a decoder. [Figure 58] FIG. 13 is a diagram illustrating another example of the configuration of an encoder. [Figure 59] FIG. 13 is a diagram illustrating another example of the configuration of a decoder. [Figure 60] 13 is a flowchart illustrating another process of the encoder. [Figure 61] 13 is a flowchart illustrating another process of the decoder. [Figure 62] 13 is a flowchart illustrating another process of the encoder. [Figure 63] 13 is a flowchart illustrating another process of the decoder. [Figure 64] FIG. 2 is a block diagram showing an example of the configuration of a computer. [Figure 65] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 66] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described.

[0020] <System configuration example> 1 is a diagram showing an example of the configuration of a data processing system to which the present technology is applied. The data processing system 1 includes an encoder (encoding device) 11 that encodes data, and a decoder (decoding device) 12 that decodes the encoded data.

[0021] Before explaining the encoding and decoding methods to which this technology is applied, an example of a conventional encoding method will be explained. One conventional encoding method is the 8b / 10b encoding method. The 8b / 10b encoding method is a method for encoding 8-bit data into 10-bit data, and transfers data and clocks over the same wiring by embedding a clock in the serial data.

[0022] However, converting 8 bits to 10 bits results in a loss of 20% of the bandwidth. Therefore, the 64b / 66b encoding method has also been proposed. The 64b / 66b encoding method achieves the same effect as the 8b / 10b encoding method, but in a different way. The 64b / 66b encoding method uses a technique called scrambling instead of the code table used in the 8b / 10b encoding method.

[0023] By scrambling, the pattern of 0s and 1s in the coded data is randomized by frequent shifts, and controlled so that there is a high probability that 0s and 1s will not occur consecutively. Even if the coded data is randomized in this way, it is configured so that it can be restored to its original state on the receiving side. This type of scrambling randomizes the output data and balances the DC balance.

[0024] 64b / 66b does not guarantee complete DC-free because the running disparity, which is the cumulative value of 0 or 1, is not controlled. The 64b / 67b encoding method has also been proposed as an encoding method in which the running disparity is controlled. With the 64b / 67b encoding method, the running disparity is controlled, but the run length caused by successive 0s or 1s may not be controlled.

[0025] For these reasons, in both the 64b / 66b and 64b / 67b encoding methods, depending on the data sequence being transmitted, the running disparity and run length may deteriorate, which may have a negative effect on the clock recovery performance of the receiving side (decoder side).In addition, with the 64b / 67b encoding method, 3 bits of control data are required for every 64 bits of transmitted data, which reduces transmission efficiency.

[0026] Therefore, the following describes an encoding method that applies the present technology, is DC-free, controls running disparity, and also controls run length, and suppresses deterioration of transmission efficiency. In addition, a decoding method for decoding data encoded by such an encoding method will be described as appropriate.

[0027] The encoder 11 to which this technology is applied converts an input data string into a data string as shown in Fig. 2. As shown in A of Fig. 2, the encoder 11 divides the input data string into N-bit data strings and adds a 1-bit flag to the beginning of each N bits.

[0028] Alternatively, as shown in FIG. 2B, the encoder 11 divides the input data into N-bit and M-bit data strings, adds a 1-bit flag to the beginning of the N-bit data string, and adds a 1-bit flag to the beginning of the M-bit data string.

[0029] In the following description, an N-bit or M-bit data string is referred to as one block. In addition, an (N+1)-bit data string obtained by adding a one-bit flag to an N-bit data string is also referred to as one block, where appropriate. Similarly, an (M+1)-bit data string obtained by adding a one-bit flag to an M-bit data string is also referred to as one block, where appropriate.

[0030] The encoder 11 may encode the input data by dividing it into pieces of the same number of bits as shown in FIG. 2A, or may encode it by dividing it into pieces of different numbers of bits as shown in FIG. 2B.

[0031] N and M are odd numbers. Because a 1-bit flag is added to N bits, (N+1) bits are an even number. Also, (M+1) bits are an even number. In this way, N or M is set so that one block including the flag has an even number of bits.

[0032] In the following explanation, an example in which an input data string is divided into N bits and M bits as shown in B of Fig. 2 will be mainly explained as an example, but the present embodiment described below can also be applied to a case in which an input data string is divided into N bits as shown in A of Fig. 2. In other words, even when N=M, the present embodiment can be applied.

[0033] <Encoder configuration> 3 is a diagram showing the configuration of the encoder 11. The encoder 11 includes an inversion unit 31, a selection unit 32, an addition unit 33, a bit check unit 34, an RD check unit 35, an RL check unit 36, and a flag determination unit 37.

[0034] The data input to the encoder 11 is supplied to each of an inverter 31, a selection unit 32, and a bit check unit 34. The inverter 31 inverts the supplied data. If the input data is "1", the inverter 31 converts it to "0", and if the input data is "0", the inverter 31 converts it to "1". The data inverted by the inverter 31 (n-bit data string) is supplied to the selection unit 32.

[0035] The data string itself input to the encoder 11 is also input to the selection unit 32. That is, an inverted data string and a non-inverted data string are input to the selection unit 32. Depending on the determination result from the flag determination unit 37, the selection unit 32 supplies either the inverted data string or the non-determined data string to the addition unit 33.

[0036] The adding unit 33 adds the flag supplied from the flag determining unit 37 to the data string output from the selecting unit 32. For example, when an N-bit data string is output from the selecting unit 32, a 1-bit flag is added and a (N+1)-bit data string is output. The flag indicates whether or not the data is inverted. In the following description, the flag is set to "1" when the data is inverted and the flag is set to "0" when the data is not inverted, but it is within the scope of the present technology even if other flags are set.

[0037] The bit check unit 34 checks the input data string. The bit check unit 34 monitors the running disparity (hereinafter, abbreviated as RD) and run length (hereinafter, abbreviated as RL) of the input data string.

[0038] The bit check unit 34 assigns "1" when the input data is "1", and assigns "-1" when the input data is "0", and the cumulative sum of the assigned values ​​is the cumulative value RD. The bit check unit 34 also manages the number of times RL that the input data has consecutive "1s" and the number of times RL that the input data has consecutive "0s".

[0039] The bit check unit 34 functions as a calculation unit that calculates the running disparity and run length of the input data.

[0040] The RD check unit 35 checks the past accumulated value RD. The RL check unit 36 ​​checks the past number of times RL. The RD check unit 35 and the RL check unit 36 ​​respectively check the accumulated value RD and the number of times RL in a data string prior to the data string being checked by the bit check unit 34.

[0041] The flag determination unit 37 determines whether or not to invert the data string, using the check results from the bit check unit 34, the RD check unit 35, and the RL check unit 36, and generates a corresponding flag. Although details will be described later, the flag determination unit 37 determines whether or not to invert the data string, using the accumulated value RD and the number of times RL of the data string currently being processed, and the accumulated value RD and the number of times RL of past data strings.

[0042] If the flag determination unit 37 determines that the data should be inverted, it generates data “1” as the flag, and if it determines that the data should not be inverted, it generates data “0” as the flag and supplies it to the selection unit 32 and the addition unit 33.

[0043] When the selection unit 32 receives a flag of "1", it outputs the data string supplied from the inversion unit 31 to the addition unit 33, and the addition unit 33 adds a flag of "1" to the data string. When the selection unit 32 receives a flag of "0", it outputs the non-inverted data string input to the encoder 11 to the addition unit 33, and the addition unit 33 adds a flag of "0" to the data string.

[0044] <Decoder configuration> 4 is a diagram showing the configuration of the decoder 12. The decoder 12 includes an inversion unit 41, a selection unit 42, and a flag determination unit 43.

[0045] The data input to the decoder 12 is supplied to each of an inversion unit 41, a selection unit 42, and a flag determination unit 43. The inversion unit 41 inverts the supplied data and supplies it to the selection unit 42. The selection unit 42 also receives the non-inverted data string input to the decoder 12.

[0046] The flag determination unit 43 refers to a 1-bit flag included in the data string input to the decoder 12, and if the flag indicates inversion, in this case "1", instructs the selection unit 42 to select and output the data string from the inversion unit 41. The flag determination unit 43 also refers to a 1-bit flag included in the data string input to the decoder 12, and if the flag indicates non-inversion, in this case "0", instructs the selection unit 42 to select and output the data string input without going through the inversion unit 41.

[0047] In this way, the encoder 11 adds a 1-bit flag to the data string, and the decoder 12 performs a process of determining whether the data string is inverted or not by referring to the flag. On the encoder 11 side, when the data to be encoded is N bits, a 1-bit flag is added and the data string is converted to an (N+1)-bit data string. However, since only 1 bit is added, it is possible to perform encoding with reduced deterioration in transmission efficiency.

[0048] In addition, the encoder 11 monitors the running disparity (RD) and run length (RL) and performs encoding based on the monitored running disparity and run length, thereby enabling encoding with controlled running disparity and run length.

[0049] Moreover, the decoder 12 can perform decoding according to the encoding performed on the encoder 11 side. The decoder 12 can also decode the encoded data based on the running disparity and run length, and perform decoding with reduced deterioration in transmission efficiency.

[0050] <Running disparity control> In the encoder 11, the running disparity (RD) is monitored in the bit check unit 34 and the RD check unit 35, and a flag corresponding to the running disparity is set. Here, the control of the running disparity will be explained.

[0051] 5 is a diagram for explaining the control of running disparity. Time Tc represents the current (processing) time, time Tp represents a time before time Tc, and time Tn represents a time after time Tc.

[0052] The bit check unit 34 (FIG. 3) calculates the cumulative value RD of the data string being processed at time Tc. The RD check unit 35 (FIG. 3) refers to the cumulative value RD of the data string processed up to the time before time Tc, in this case at time Tp. The cumulative value RD is a value that has been calculated since the start of processing in the encoder 11, taking "1" when the data is "1" and "-1" when the data is "0".

[0053] An example will be described in which an N-bit data string is processed at time Tc. In other words, as shown in A of Fig. 2, the encoder 11 divides input data into N-bit chunks, adds a 1-bit flag, and generates a data string with one block being (N+1) bits.

[0054] 5, the thin line graph L1 represents the change in the accumulated value RD at time Tp. Assume that the accumulated value RD at the end of time Tp (the start of time Tc) is RD=(-5).

[0055] Assume that the N-bit data string processed at time Tc is all "1". When the N-bit data string processed at time Tc is all "1", the cumulative value RD will rise in a straight line starting from (-5), as shown by the thick line in graph L2 in FIG. 5. In this case, the data is not inverted, so the flag is "0". Therefore, the cumulative value RDnext(A) at the end of time Tc (the start of time Tn) is the sum of the cumulative value RD at the end of time Tp and the cumulative value RD calculated at time Tc.

[0056] The value obtained by adding the cumulative value RD calculated at time Tc is N because all N bits are “1”. Since the flag “0” is included in the cumulative value RDnext(A) as “-1”, the cumulative value RDnext(A) becomes the following value. Accumulation value RDnext(A)=(-5)+(-1)+N

[0057] The running disparity of the N-bit data string being processed is N. The above-mentioned cumulative value RDnext(A) is a value obtained by adding the running disparity calculated up to the previous point in time to the running disparity calculated at the current point in time.

[0058] If the N-bit data string processed at time Tc is all "1" and the data is all inverted, it will all become "0", and the cumulative value RD will start at (-5) and fall in a straight line, as shown by dotted line graph L3 in Figure 5. In this case, since the data has been inverted, the flag becomes "1". The "1" flag is set to "1" when calculating the cumulative value RD, and this value is also included in the cumulative value RDnext (R).

[0059] The cumulative value RDnext(R) is as follows: Accumulation value RDnext=(-5)+1+(-N)

[0060] When the N-bit data string being processed is inverted, the running disparity of the N-bit data string becomes −N. The above-mentioned cumulative value RDnext(R) is a value obtained by subtracting the running disparity calculated at the current point in time from the running disparity calculated up to the previous point in time.

[0061] The ideal running disparity is 0 (RD = 0). A running disparity of 0 means that the number of occurrences of "0" and "1" in the data is the same, and DC balance is achieved.

[0062] In order to control the running disparity to a value close to 0, the encoder 11 is configured to compare the accumulated value RD when the data is inverted with the accumulated value RD when the data is not inverted, and to adopt the accumulated value RD that is closer to RD=0.

[0063] That is, in this case, the absolute value of the accumulated value RDnext(A) is compared with the absolute value of the accumulated value RDnext(R), and the one closer to 0 is adopted. In the example shown in Fig. 5, the accumulated value RDnext(A) is closer to RD = 0 than the accumulated value RDnext(R), so the accumulated value RDnext(A) is adopted. The accumulated value RDnext(A) is a case where the data is not inverted, so in this case, "0" is set as the flag.

[0064] The bit check unit 34 (FIG. 3) of the encoder 11 executes a process at time Tc. That is, the bit check unit 34 calculates a cumulative value RD of the input N-bit data string. For example, the bit check unit 34 executes a process of creating the graph L2 in FIG. 5.

[0065] The RD check unit 35 (FIG. 3) of the encoder 11 executes processing at time Tp. As shown in FIG. 3, the RD check unit 35 receives a data string including a flag output from the addition unit 33. The data string output from the addition unit 33 is an inverted data string or a non-inverted data string. In other words, the data string transmitted to the decoder 12 side is input to the RD check unit 35.

[0066] The RD check unit 35 calculates the cumulative value RD of the input data string in the same manner as the bit check unit 34. For example, the RD check unit 35 executes a process of creating the graph L1 in FIG.

[0067] As described with reference to Fig. 5, the flag determination unit 37 (Fig. 3) compares the accumulated value RDnext(A) with the accumulated value RDnext(R), determines which accumulated value is closer to 0, and generates a flag according to the accumulated value. For example, the flag determination unit 37 performs determination based on the determination table shown in Fig. 6 and generates a flag.

[0068] Referring to the judgment table in FIG. 6, the judgment table is a table in which the accumulated value RD at time Tc (present time) (hereinafter referred to as accumulated value RDc), the accumulated value at time Tp (past) (hereinafter referred to as accumulated value RDp), and a flag are associated with each other.

[0069] The determination table in Fig. 6 is a table for determining whether or not to invert data at time Tc (the present time). Therefore, the cumulative value RDp is a cumulative value including a flag at time Tp (past), in other words, at the time when time Tp switches to time Tc. The cumulative value RDc is a cumulative value at the end of time Tc, and does not include a flag.

[0070] The accumulated value RDc is classified into a positive case (accumulated value RDc>0), a zero case (accumulated value RDc=0), and a negative case (accumulated value RDc<0). That is, whether the accumulated value RDc supplied from the bit check unit 34 is positive, zero, or negative is set as one of the factors for setting the flag.

[0071] 6, the accumulated value RDp is also classified into a case where the accumulated value RDp is positive (accumulated value RDp>0), a case where the accumulated value RDp is zero (accumulated value RDp=0), and a case where the accumulated value RDp is negative (accumulated value RDp<0). In other words, whether the accumulated value RDp supplied from the RD check unit 35 is positive, zero, or negative is set as one of the factors for setting the flag.

[0072] If the accumulated value RDc>0 and the accumulated value RDp>0, the flag is set to "1". That is, in this case, the data is inverted. If the accumulated value RDc>0 and the accumulated value RDp=0, the flag is set to "1". That is, in this case, the data is inverted. If the accumulated value RDc>0 and the accumulated value RDp<0, the flag is set to "0". That is, in this case, the data is not inverted.

[0073] Note that, when the accumulated value RDc>0 and the accumulated value RDp=0, the flag may be set to "0" and the data may be set to be non-inverted.

[0074] The case where the accumulated value RDc>0 is described below with reference to A of Fig. 7. In Fig. 7, as in Fig. 6, the accumulated value RDp is an accumulated value including the flag of time Tp, and the accumulated value RDc is a value not including the flag of time Tc.

[0075] 7A, a graph in which the accumulated value RDc>0 and the accumulated value RDp>0 is shown as graph L11, a graph in which the accumulated value RDc>0 and the accumulated value RDp=0 is shown as graph L12, and a graph in which the accumulated value RDc>0 and the accumulated value RDp<0 is shown as graph L13. Note that the accumulated value RDp and the accumulated value RDc are two points, and a straight line passes through the two points (connects the two points), and this straight line is described as a graph.

[0076] When the accumulated value RDc>0, the graphs L11 to L13 starting from the accumulated value RDp are increasing graphs (graphs sloping upwards to the right). That is, referring to the graph L11, when the accumulated value RDp>0 is the starting point, the accumulated value RDc>0 is greater than the accumulated value RDp, and the graphs move in a direction away from 0. Therefore, in such a case, in order to bring the accumulated value RD closer to 0, the flag determination unit 37 determines that the data should be inverted, and sets the flag to "1". When the data is inverted, it can be seen that the graph L11 becomes a graph sloping downwards to the right, approaching 0.

[0077] Referring to graph L12, when the cumulative value RDp=0 is used as the starting point, the cumulative value RDc>0, so the value is greater than the cumulative value RDp (=0), and the graph progresses in a direction away from 0. Therefore, in such a case, in order to bring the cumulative value RD closer to 0, the flag determination unit 37 determines that the data is to be inverted and sets the flag to "1". Alternatively, in order to bring the cumulative value RD closer to 0, the flag determination unit 37 may determine that the data is not to be inverted and set the flag to "0". In the case of cumulative value RDp=0, the distance from 0 is the same whether it is inverted or not, so it may be set to determine that it is inverted or not to be inverted.

[0078] When the accumulated value RDc>0, that is, when the accumulated value RD of the data string being processed is positive, the data string being processed is a data string that contains many "1's." Since the value of the flag is also included in the accumulated value RD, when the data string being processed is a data string that contains many "1's," the accumulated value RD can be brought closer to 0 by setting the flag to "0." Taking this into consideration, when the accumulated value RDp=0 and the accumulated value RDc>0, the flag may be set to "0."

[0079] Referring to graph L13, when the cumulative value RDp<0 is used as the starting point, the cumulative value RDc>0, so the value becomes larger than the cumulative value RDp, and the graph progresses in a direction approaching 0 (from the negative region to the positive region). Therefore, in such a case, in order to bring the cumulative value RD closer to 0, the flag determination unit 37 determines that the data is not inverted, and sets the flag to "0."

[0080] Returning to the explanation with reference to FIG. 6, if the accumulated value RDc=0 and the accumulated value RDp>0, the flag is set to "0". That is, in this case, the data is not inverted. If the accumulated value RDc=0 and the accumulated value RDp=0, the flag is set to "0". That is, in this case, the data is not inverted. If the accumulated value RDc=0 and the accumulated value RDp<0, the flag is set to "1". That is, in this case, the data is not inverted.

[0081] When the accumulated value RDc=0 and the accumulated value RDp=0, the flag may be set to "1" and the data may be set to be inverted.

[0082] The case where the accumulated value RDc=0 will be described with reference to B of Fig. 7. In B of Fig. 7, a graph where the accumulated value RDc=0 and the accumulated value RDp>0 is shown as graph L21, a graph where the accumulated value RDc=0 and the accumulated value RDp=0 is shown as graph L22, and a graph where the accumulated value RDc=0 and the accumulated value RDp<0 is shown as graph L23.

[0083] When the accumulated value RDc=0, the graphs L21 to L23 starting from the accumulated value RDp are graphs in which the values ​​do not change. That is, referring to the graph L21, when the accumulated value RDp>0 is the starting point, the accumulated value RDc=0, so the accumulated value RDp remains the same, and the distance from 0 is constant. Therefore, in such a case, the distance from 0 does not change whether the data is inverted or not, so the flag determination unit 37 may determine not to invert the data and set the flag to "0", or may determine to invert the data and set the flag to "1".

[0084] By setting "0" as the flag, "-1" is used as the value when calculating the accumulated value RD, so that when the accumulated value RDp>0, it approaches 0 by -1. Here, the explanation will be continued assuming that "0" is set as the flag.

[0085] Referring to graph L22, when the cumulative value RDp=0 is used as the starting point, the cumulative value RDc=0, so the cumulative value RDp (=0) is maintained on the graph. Therefore, in such a case, since the state is good and it does not matter whether the data is inverted or not, the flag determination unit 37 may determine that the data is to be inverted and set the flag to "1", or may determine that the data is not to be inverted and set the flag to "0".

[0086] Referring to graph L23, when the cumulative value RDp<0 is used as the starting point, the cumulative value RDc=0, so the value of the cumulative value RDp remains the same, resulting in a graph with a constant distance from 0. In this case, therefore, since the distance from 0 does not change whether the data is inverted or not, the flag determination unit 37 may determine not to invert the data and set the flag to "0", or may determine to invert the data and set the flag to "1".

[0087] By setting the flag to "1", "1" is used as the value when calculating the accumulated value RD, so that when the accumulated value RDp<0, it approaches 0 by 1. Here, the explanation will be continued assuming that the flag is set to "1".

[0088] Returning to the explanation with reference to FIG. 6, if the accumulated value RDc<0 and the accumulated value RDp>0, the flag is set to "0". That is, in this case, the data is not inverted. If the accumulated value RDc<0 and the accumulated value RDp=0, the flag is set to "0". That is, in this case, the data is not inverted. If the accumulated value RDc<0 and the accumulated value RDp<0, the flag is set to "1". That is, in this case, the data is inverted.

[0089] When the accumulated value RDc<0 and the accumulated value RDp=0, the flag may be set to "1" and the data may be set to be inverted.

[0090] The case where the accumulated value RDc<0 will be described with reference to C of Fig. 7. In C of Fig. 7, a graph where the accumulated value RDc<0 and the accumulated value RDp>0 is shown as graph L31, a graph where the accumulated value RDc<0 and the accumulated value RDp=0 is shown as graph L32, and a graph where the accumulated value RDc<0 and the accumulated value RDp<0 is shown as graph L33.

[0091] When the accumulated value RDc<0, the graphs L31 to L33 starting from the accumulated value RDp are decreasing graphs (graphs sloping downward to the right). That is, referring to the graph L31, when the accumulated value RDp>0 is the starting point, the accumulated value RDc<0, so the value becomes smaller than the accumulated value RDp, and the graph progresses in a direction approaching 0. Therefore, in such a case, in order to bring the accumulated value RD closer to 0, the flag determination unit 37 determines not to invert the data, and sets the flag to "0".

[0092] Referring to graph L32, when the cumulative value RDp=0 is used as the starting point, the cumulative value RDc is smaller than the cumulative value RDp (=0) because RDc<0, and the graph progresses in a direction away from 0. Therefore, in such a case, in order to bring the cumulative value RD closer to 0, the flag determination unit 37 may determine that the data is not to be inverted and set the flag to "0", or may determine that the data is to be inverted and set the flag to "1". When the cumulative value RDp=0, the distance from 0 is the same whether it is inverted or not, so it may be set to determine that it is inverted, or may be set to determine that it is not inverted.

[0093] When the accumulated value RDc<0, that is, when the accumulated value RD of the data string being processed is negative, the data string being processed is a data string that contains many "0's." Since the value of the flag is also included in the accumulated value RD, when the data string being processed is a data string that contains many "0's," the accumulated value RD can be brought closer to 0 by setting the flag to "1." Taking this into consideration, when the accumulated value RDp=0 and the accumulated value RDc<0, the flag may be set to "1."

[0094] Referring to graph L33, when the cumulative value RDp<0 is used as the starting point, the cumulative value RDc<0, so the value is smaller than the cumulative value RDp, and the graph progresses in a direction away from 0. Therefore, in such a case, in order to bring the cumulative value RD closer to 0, the flag determination unit 37 determines that the data should be inverted, and sets the flag to "1." When the data is inverted, the graph of L33 becomes an upward sloping graph, and it can be seen that it approaches 0.

[0095] In this manner, the flag determination unit 37 sets a flag based on the past accumulated value RD and the currently processed accumulated value RD.

[0096] In this way, the running disparity (RD) is monitored, and data can be inverted as necessary to make the cumulative value RD closer to 0, thereby making it possible to control the data to be DC-free. Furthermore, by controlling the so-called run length, which is the number of consecutive 0s or 1s in a data string, more suitable encoding and decoding can be performed.

[0097] <Run length control> In the encoder 11, the run length (RL) is monitored in the bit check unit 34 and the RL check unit 36, and a flag according to the run length is set (changed). Here, the control of the run length will be explained.

[0098] The graph shown in Fig. 8 is a diagram for explaining the control of run length. In the graph shown in Fig. 8, as in the graph shown in Fig. 5, time Tc represents the current (processing) time, time Tp represents the time before time Tc, and time Tn represents the time after time Tc.

[0099] The accumulated value RD at time Tpc when time Tp switches to time Tc is the accumulated value RDpc, and in the example shown in Fig. 8, it is assumed that the accumulated value RDpc is greater than 0. It is also assumed that the accumulated value RD at time Tp changes as shown in graph L51 in Fig. 8.

[0100] As shown in graph L52 of FIG. 8, the cumulative value RD of the data string being processed at time Tc is a series of 1s, so that the cumulative value RD rises from the cumulative value RDpc, drops once near the end of time Tc, and finally becomes the cumulative value RDcn at the time Tc switching from time Tc to time Tn.

[0101] Graph L53 shows the result when the data string processed at time Tc is inverted. Graph L53 is an inverted version of graph L52, so the data shows continuous 0s, drops from the cumulative value RDpc, rises once near the end of time Tc, and finally reaches the cumulative value RDcn' at time Tcn when time Tc switches to time Tn.

[0102] When the accumulated value RD changes as shown in Fig. 8, the accumulated value RDcn' when the data is inverted is closer to the accumulated value RD=0 than the accumulated value RDcn when the data is not inverted. Therefore, when the running disparity RD is taken into consideration, the data at time Tc is determined to be inverted, and the flag is set to "1". In other words, referring again to Fig. 6, in the case of a data string that changes from graph L51 to graph L52 shown in Fig. 8, RDc>0 and RDp>0 are satisfied, and therefore, it can be seen from the table shown in Fig. 6 that the flag is set to "1".

[0103] Now consider the run length. As described above, when the data is inverted, taking into account the running disparity RD, the cumulative value RD changes from graph L51 to graph L53 shown in FIG. 8. When the data string is inverted, there is a section from graph L51 to graph L53 that falls in a straight line. In other words, there is a section where 0s continue.

[0104] 8, 0's continue from a specific time (time Tp1) of time Tp to time Tpc. Also, by inverting the data string of time Tc, 0's continue from time Tpc to a specific time (time Tc1) of time Tc. That is, in this case, the data from time Tp1 to time Tc1 is 0. In other words, several bits of data from time Tp1 to time Tc1 are 0's.

[0105] Inverting the data in this way may result in a worsening of the run length. For example, if a maximum value for the run length (maximum value RLmax) is set, and the run length becomes equal to or greater than the maximum value RLmax (larger), the decision to invert the data in order to control the running disparity RD is overturned and changed to a decision not to invert the data.

[0106] In the example shown in FIG. 8, if the number of consecutive 0 bits (run length RL) from time Tp1 to time Tc1 is equal to or greater than the maximum value RLmax, the determination is changed to no inversion, and as a result, the accumulated value RD (data string) changes from graph L51 to graph L52.

[0107] Therefore, since the graph changes from L51 to L52, the succession of 0s is interrupted at time Tpc, and deterioration of the run length is prevented. In this way, when a determination is made once as to whether or not to invert the data using the running disparity RD and the data is processed based on the result of that determination, a determination is made as to whether or not the run length RL will deteriorate, and if the run length RL will deteriorate, the determination based on the running disparity RD is changed.

[0108] Referring again to Figure 8, in the above explanation, it has been explained that the graph L52 is a graph of the cumulative value RD of the data string currently being processed. Next, a description will be given of the case where the graph L53 is a graph of the cumulative value RD of the data string currently being processed.

[0109] If the graph L53 is a graph of the cumulative value RD when the data is not inverted, the cumulative value RD at time Tcn when the data is not inverted is the cumulative value RDcn'. Also, since the graph of the cumulative value RD when the data is inverted is the graph L52, the cumulative value RD at time Tcn when the data is inverted is the cumulative value RDcn.

[0110] When comparing the accumulated value RDcn' with the accumulated value RDcn, the value closest to the accumulated value RD=0 is the accumulated value RDcn'. Therefore, when the running disparity RD is taken into consideration, it is determined that the data at time Tc is not inverted, and the flag is set to "0." In other words, referring again to FIG. 6, in the case of the data string from graph L51 to graph L53 shown in FIG. 8, RDc<0 and RDp>0 are satisfied, so it can be seen from the table shown in FIG. 6 that the flag is set to "0."

[0111] When the data string is not inverted, there is a section from graph L51 to graph L53 that descends in a straight line. That is, there is a section with continuous 0s. As in the above case, there is continuous 0s from time Tp1 to time Tpc. Also, because the data string for time Tc is not inverted, there is continuous 0s from time Tpc to time Tc1. That is, in this case, the data from time Tp1 to time Tc1 is 0. In other words, several bits of data from time Tp1 to time Tc1 are continuous 0s.

[0112] Even if the data is not inverted in this way, there is a possibility that the run length may deteriorate. In such a case, the maximum run length RLmax is set, and when the run length becomes equal to or greater than the maximum value RLmax, the decision to not invert the data is overturned and changed to a decision to invert the data in order to control the running disparity RD.

[0113] In the example shown in FIG. 8, if the number of consecutive 0 bits (run length RL) from time Tp1 to time Tc1 is equal to or greater than the maximum value RLmax, the determination is changed to one of inversion, and as a result, the accumulated value RD (data string) changes from graph L51 to graph L52.

[0114] Therefore, since the graph changes from L51 to L52, the succession of 0s is interrupted at time Tpc, and deterioration of the run length is prevented. In this way, when a determination is made once as to whether or not to invert the data using the running disparity RD and the data is processed based on the result of that determination, a determination is made as to whether or not the run length RL will deteriorate, and if the run length RL will deteriorate, the determination based on the running disparity RD is changed.

[0115] Such control may deteriorate the running disparity RD because the run length RL is prioritized. The degree to which the run length RL is prioritized, in other words, the value of the maximum value RLmax, can be set depending on the system. For example, when the decoding capability of the decoder 12 is high, for example, when decoding is possible even if the run length RL is large, the value of the maximum value RLmax can be increased and the priority of the run length RL can be decreased.

[0116] Here, the case where there are successive 0s has been explained as an example, but the case where there are successive 1s is also processed in the same manner.

[0117] <About the encoder process> The process of the encoder 11 will now be described with reference to the flowchart of FIG.

[0118] In step S11, the encoder 11 divides the input data into N bits, and executes the process from step S12 onward for each N bits. Here, the case of N bits will be described as an example, but the process is similar when dividing into M bits.

[0119] In step S12, the bit check unit 34 calculates a cumulative value RD of the N-bit data string being processed.

[0120] In step S13, the flag determination unit 37 performs a determination based on the running disparity RD. This determination is performed as described with reference to Figs. 5 to 7, and therefore a detailed description thereof will be omitted.

[0121] In step S14, it is determined whether or not the determination result in step S13 was to invert the data string. If it is determined in step S14 that the data string is to be inverted, the process proceeds to step S15.

[0122] In step S15, the flag is set to 1. In step S16, the data string is inverted due to the flag being set to 1, and the process proceeds to step S18.

[0123] On the other hand, if it is determined in step S14 that the data string is not to be inverted, the process proceeds to step S17, where the flag is set to 1, and the process proceeds to step S18.

[0124] In step S18, a determination is made based on the run length RL. This determination is made as described with reference to Fig. 8, and therefore a detailed description thereof will be omitted.

[0125] In step S19, it is determined whether the result of the determination in step S18 was to change the flag (to overturn the determination based on the running disparity RD). That is, after the determination based on the running disparity is made, a determination based on the run length is made again, and the determination based on the running disparity is either maintained or a different determination result is produced.

[0126] If it is determined in step S18 that the flag is to be changed, the process proceeds to step S20. In step S20, the flag is changed. For example, if the flag was set to 1, it is changed to 0, and if the flag was set to 0, it is changed to 1. In step S21, the data string is inverted due to the flag being changed, and the process proceeds to step S22.

[0127] On the other hand, if it is determined in step S18 that the flag is not to be changed, the process proceeds to step S22.

[0128] In step S22, the running disparity RD and run length RL in one block of the data string including the set flag are calculated. The running disparity RD and run length RL calculated in step S22 are used as the running disparity RD and run length RL at the above-mentioned time Tp.

[0129] In step S23, the data string (one block) including the flag is output from the encoder 11 as output data (encoded data).

[0130] In this manner, encoding processing is performed in the encoder 11. In the flowchart shown in Fig. 9, an example is shown in which input data is processed in units of N-bit data, but when encoding is performed with different numbers of bits, N bits and M bits, as shown in Fig. 2B, the processing performed with N bits in Fig. 9 can be performed by appropriately performing it with M bits.

[0131] <Decoder processing> The process of the decoder 12 will be described with reference to the flowchart of FIG.

[0132] In step S31, the decoder 12 processes (N+1) bits of the input encoded data. In the case where the number of data bits in one block is a mixture of (N+1) bits and (M+1) bits as shown in B of Fig. 2, the decoder 12 may process either (N+1) bits or (M+1) bits.

[0133] In step S32, the flag determination unit 43 refers to a 1-bit flag included in one block of (N+1) bits, and determines whether or not the flag is 1, that is, whether or not the data is inverted.

[0134] If it is determined in step S32 that the flag is 1, the process proceeds to step S33. In step S33, the selection unit 42 selects the inverted data input via the inversion unit 41, and outputs it as the decoded result.

[0135] On the other hand, if it is determined in step S32 that the flag is not 1, in other words, that the flag is 0 and the data is not inverted, the process proceeds to step S34. In step S34, the selection unit 42 selects the data input without passing through the inversion unit 41, and outputs it as the decoded result.

[0136] In this way, the decoder 12 performs a decoding process that corresponds to the encoding process performed by the encoder 11 .

[0137] <Error detection in decoders> As described above, the encoder 11 performs control so that the running disparity RD approaches 0. By utilizing this, the decoder 12 can detect an error.

[0138] Even if the encoder 11 controls the running disparity RD to be small, for example, if an error occurs on the transmission path between the encoder 11 and the decoder 12, the running disparity RD of the data received by the decoder 12 may become large. The decoder 12 decodes the received data, calculates the running disparity RD of the decoded data, and if the calculated value becomes large (tends to increase), it can be determined that the received data contains an error.

[0139] As shown in Fig. 11, an error detection unit 61 that receives the output from the decoder 12, calculates the running disparity RD, and detects errors can be provided on the decoder 12 side. The internal configuration of the decoder 12 shown in Fig. 11 is the same as the configuration of the decoder 12 shown in Fig. 4. Decoded data is output from the decoder 12.

[0140] The error detection unit 61 calculates the running disparity RD of the decoded data supplied from the decoder 12. If the calculated running disparity RD is large, it determines that an error has occurred, and supplies information to the upper layer that there is a possibility of an error.

[0141] The upper layer is a layer that receives data output from the decoder 12 and performs a predetermined process. When such an upper layer acquires information from the error detection unit 61 that there may be an error, it processes the supplied data on the assumption that there may be an error. For example, the upper layer may perform a process that strengthens the error correction process or discard data that may contain an error.

[0142] The error detection unit 61 determines that an error has occurred when the running disparity RD becomes large, but for example, a predetermined threshold value may be set and, when the running disparity RD becomes larger than the threshold value, it may determine that an error has occurred. Also, the running disparity RD of the data being processed may be compared with the running disparity RD of data processed before that data, and, when the difference between the running disparity RD and the running disparity RD becomes larger than a predetermined threshold value, it may determine that an error has occurred.

[0143] In this way, the decoding side can also determine whether or not there is a possibility that an error is included in the received data by monitoring the running disparity RD. Also, by configuring the decoding side to be able to detect errors and to deal with the occurrence of an error, the reliability of the received data decoded by the decoder 12 can be improved.

[0144] <Improving the reliability of flags> As described above, the encoder 11 side inverts or does not invert the data, and adds a flag so that the decoder 12 side can determine whether the data has been inverted or not. If an error occurs when the data is supplied from the encoder 11 to the decoder 12, causing the flag to change, the decoder 12 side will not be able to decode the data correctly.

[0145] Therefore, a mechanism for enabling the decoder 12 to determine whether or not an error has occurred in the flag will be described below.

[0146] The explanation with reference to Figures 12 and 13 will be given by taking as an example a case where data to be coded is divided into an N-bit block and an M-bit block for processing, as shown in B of Figure 2. With reference to Figure 12, the flag of N-bit block 81-1 is FLG1, the flag of M-bit block 81-2 is FLG2, and the flag of N-bit block 81-3 is FLG3.

[0147] The flag of the M-bit block 81-4 is FLG4, but this FLG4 is not used as a flag indicating whether the data of the block 81-4 is inverted or not. Also, the data of the block 81-4 is a block that does not undergo inversion processing. In other words, the data of the block 81-4 is not subject to the control of the running disparity RD or the run length RL, and is non-inverted data.

[0148] FLG4 is the result (parity) of the exclusive OR (EXOR) of FLG1, FLG2, and FLG3. FLG4 differs from FLG1, FLG2, and FLG3 and is added to block 81-4 as the parity of these flags. FLG4=FLG1xorFLG2xorFLG3

[0149] On the receiving side, the exclusive OR of FLG1 to FLG4 is calculated, and if the value is 0, it is determined that there is no error, and if the value is 1, it is determined that there is an error. FLG1xorFLG2xorFLG3xorFLG4=0 No error detected FLG1xorFLG2xorFLG3xorFLG4=1 Error detected

[0150] In this way, the decoder 12 (receiving side) can determine whether all of FLG1, FLG2, FLG3, and FLG4 are correct or any of them are incorrect. If it is determined that the flags contain an error, information that there may be an error is provided to a layer higher than the decoder 12. When the higher layer receives the information on whether or not there is an error output from the decoder 12, it processes the provided data on the assumption that there may be an error. For example, it performs processing such as performing enhanced error correction processing or discarding data that may contain an error.

[0151] 12 is an example in which one parity flag (FLG4) is included for every four blocks 81. The number of blocks for which parity is included may be set depending on the system, or may be changed as appropriate depending on the state of the transmission line by monitoring the state of the transmission line.

[0152] If more parity is added, there is a possibility that the number of blocks whose running disparity RD is not controlled (blocks corresponding to block 81-4 in the example shown in Figure 12), in other words, blocks whose data is determined to be inverted to prevent deterioration of the running disparity RD, will increase as the blocks are treated as non-inverted.

[0153] If less parity is used, there will be more indeterminate flags when an error occurs. If a flag is indeterminate, the data in the block to which that flag is added will also be indeterminate, and the amount of data that is treated as an error may increase.

[0154] Taking this into consideration, the number of blocks in which parity is stored may be set.

[0155] When encoding is performed by dividing into N-bit blocks and M-bit blocks, a total of two blocks, one N-bit block and one M-bit block, are treated as one processing unit, and the flag of the last block of the several processing units is set as parity for each several processing units. The example shown in Figure 12 is for two processing units. Also, as shown in A of Figure 2, when encoding is performed only with N-bit blocks, at least two blocks or more are treated as one processing unit, and the flag of the last block of the processing unit is set as parity.

[0156] The number of blocks in which parity is to be stored is set with the processing unit taken into consideration.

[0157] In the example shown in Figure 12, we have taken the case where the data to be encoded is divided into N-bit blocks and M-bit blocks for processing, as shown in Figure 2B, but the present invention can also be applied to the case where the data to be encoded is divided into N-bit blocks for processing, as shown in Figure 2A.

[0158] Fig. 13 is a diagram showing another structure of data for determining whether or not there is an error in the flag. As in the case shown in Fig. 12, Fig. 13 also shows an example in which data for detecting an error is inserted every four blocks of blocks 81-1 to 81-4.

[0159] In the example shown in FIG. 13, the flag of N-bit block 81-1 is FLG1, the flag of M-bit block 81-2 is FLG2, the flag of N-bit block 81-3 is FLG3, and the flag of M-bit block 81-4 is FLG4.

[0160] Blocks 81-1 to 81-4 are coded in sequence, and FLG4 is added. Then, FLG1 to FLG4 are subjected to a Hamming coding process to calculate a parity bit (a Hamming result). This calculated parity bit 82 is added to the end of block 81-4 and transmitted.

[0161] 13, when parity bits 82 are added to each of four blocks 81-1 to 81-4, three parity bits 82 are generated and added to the four bits of FLG1, FLG2, FLG3, and FLG4. In this case, a (7,4,3) Hamming code can be used as the Hamming code.

[0162] The Hamming code given here is an example, and other Hamming codes can be applied. For example, a (8,4,4) Hamming code in which 4 parity bits 82 are generated for the 4 bits of FLG1, FLG2, FLG3, and FLG4 can be applied, and can be calculated based on the following formula, for example. P[3]=F[0] ^ F[1] ^ F[2] ^ F[3] ^ P[2] ^ P[1] ^ P[0] P[2]=F[1] ^ F[2] ^ F[3] P[1]=F[0] ^ F[2] ^ F[3] P[0]=F[0] ^ F[1] ^ F[3]

[0163] The receiving side (decoder 12) can detect whether there is an error in FLG1, FLG2, FLG3, and FLG4 by performing Hamming decoding after receiving blocks 81-1 to 81-4 and parity bit 82. In this case, by performing Hamming decoding, it is possible to detect and correct an error in any one bit (one flag) of FLG1, FLG2, FLG3, and FLG4.

[0164] Here, the case where Hamming code and decoding are used is explained as an example, but error correction code and decoding other than Hamming code and decoding can also be applied. Also, here, the case where coding is performed by dividing into N-bit blocks and M-bit blocks is explained as an example, but it can also be applied to the case where coding is performed by dividing into only N-bit blocks.

[0165] When encoding is performed by dividing into N-bit blocks and M-bit blocks, one N-bit block and one M-bit block, a total of two blocks, are considered to be one processing unit, and a parity bit 82 is added after the last block of the processing unit for every two or more processing units (four or more blocks). The example shown in Fig. 12 is for a two-processing unit. Also, as shown in A of Fig. 2, when encoding is performed only using N-bit blocks, at least two blocks or more are considered to be one processing unit, and a parity bit 82 is added after the last block of the processing unit.

[0166] If a large number of parity bits 82 using the Hamming code are inserted, the tolerance to errors can be increased. However, since three parity bits 82 are required in the above example, the more parity bits are inserted, the more likely it is that transmission efficiency will deteriorate. Taking this into consideration, the number of blocks (number of processing units) into which the parity bits 82 are inserted can be set depending on the system.

[0167] In the example shown in Figure 13, the case where the data to be encoded is divided into N-bit blocks and M-bit blocks and processed as shown in Figure 2B is taken as an example. However, the present invention can also be applied to the case where the data to be encoded is divided into N-bit blocks and processed as shown in Figure 2A.

[0168] Furthermore, N bits can be, for example, 32 bits. When N=32 bits and processing is performed every 4 blocks as shown in FIG. 13, a 128-bit data string is processed. If a 1-bit flag is added to the 128-bit data string every 4 blocks and the parity bit 82 is set to 4 bits, the data string becomes 136 bits. That is, in this case, the 128-bit data string is converted into 136-bit data.

[0169] In this way, the 128b / 136b encoding method can also be applied to this technology.

[0170] In this way, by making it possible for the receiving side to determine whether or not there is an error in the flag, it is possible to increase the reliability of encoding and decoding.

[0171] <Other system configuration examples> Fig. 14 is a diagram showing another example of the configuration of a data processing system. The data processing system 1 shown in Fig. 14 differs from the data processing system 1 shown in Fig. 1 in that an encoder 13 and a selector 14 are added, but the other parts are the same.

[0172] 14 includes an encoder 11 that performs the above-mentioned encoding for inverting data (hereinafter, appropriately referred to as inversion encoding), and an encoder 13 that performs encoding other than inversion encoding. Also, the data processing system 1 includes a selector 14 that selects whether to transmit a data string encoded by the encoder 11 or a data string encoded by the encoder 13.

[0173] The encoder 13 performs encoding using an encoding method such as 8b / 10b encoding, 64b / 66b encoding, 64b / 67b encoding, etc. Although only one encoder 13 is shown in Fig. 14, a plurality of encoders may be provided corresponding to these encoding methods.

[0174] The selector 14 switches between the output from the encoder 11 and the output from the encoder 13. The selector 14 switches the output according to a control signal supplied from an external circuit. The control signal may be a signal indicating an encoding method selected (set) by the user.

[0175] 14 shows an example in which the selector 14 is provided at a position where the encoded data from the encoder 11 or 13 is selected, in other words, an example in which the selector 14 is provided after the encoder 11 and the encoder 13, but it is also possible to configure the selector 14 to be provided before the encoder 11 and the encoder 13. In other words, the selector 14 may be provided as a selection unit that selects the encoder 11 or the encoder 13 as the supply destination of the input data.

[0176] Alternatively, a configuration may be adopted in which selectors 14 are provided in the upstream and downstream of the encoders 11 and 13. The selectors 14 provided in the upstream of the encoders 11 and 13 supply input data to the encoders 11 or 13 based on a control signal from the outside.

[0177] A selector 14 provided after the encoder 11 and the encoder 13 functions as a selector 14 that selects the output from the encoder 11 or the encoder 13 that is set as the supply destination of the input data.

[0178] Also, it is possible to configure so that power is not supplied to the encoder 11 or the encoder 13 that is not performing encoding, thereby reducing power consumption.

[0179] The encoder 11 and the decoder 12 may each be provided with an adjustment unit that adds or deletes data according to the amount of effective data of the input data. The added data may be, for example, a Pad Code. Note that the Pad Code is a group of symbols that are inserted into the payload data to fill the difference between the pixel data band and the PHY transmission band when, for example, the system shown in Fig. 14 is applied to the SLVS-EC standard described later, and such data can be used as the added data.

[0180] With this configuration, it is possible to perform encoding using an encoding method corresponding to a decoding method supported by the side receiving the encoded data, generate encoded data, and supply the encoded data.

[0181] 14, the decoder 12 side is shown with only one decoder, but like the encoder side, the decoder 12 may be configured to include a plurality of decoders 12, such as a decoder 12 corresponding to the encoding method of the encoder 11 and a decoder 12 corresponding to the encoding method of the encoder 13. Also, the decoder 12 may be configured to include a selector that supplies encoded data to one of the plurality of decoders 12, or a selector that selects decoded data from one of the plurality of decoders 12.

[0182] Similarly, on the decoding side, when the configuration includes a plurality of decoders 12 and selectors, the control signal for the selector may be input from an external circuit or may be input according to user settings. Also, on the encoding side, when performing encoding, an identifier indicating the encoding method may be added to the encoded data so that the identifier is supplied to the selector.

[0183] <Regarding the SLVS-EC Standard> The above encoding, decoding, in other words, the system shown in FIG. 1 can be applied to the parts that perform encoding and decoding in the SLVS-EC (Scalable Low Voltage Signaling-Embedded Clock) standard described below. Therefore, the SLVS-EC standard will be described below.

[0184] There is the SLVS-EC standard as a standard for the interface of the image sensor. The transmission method of the SLVS-EC standard is a method in which data is transmitted in a form with a clock superimposed on the transmission side, and the clock is regenerated on the reception side to demodulate and decode the data.

[0185] <Configuration Example of Transmission System> FIG. 15 is a diagram showing a configuration example of a transmission system. The transmission system 100 in FIG. 15 is composed of an image sensor 111 and a DSP 112. The image sensor 111 and the DSP 112 are each composed of different LSIs (Large Scale Integrated Circuits) and are provided in the same imaging device having an imaging function, such as a digital camera or a mobile phone. The image sensor 111 is provided with an imaging unit 121 and one transmission unit 122, and the DSP 112 is provided with one reception unit 131 and an image processing unit 132.

[0186] The imaging unit 121 of the image sensor 111 is made up of an imaging element such as a CMOS (Complementary Metal Oxide Semiconductor) and performs photoelectric conversion of light received through a lens. The imaging unit 121 also performs A / D conversion of the signal obtained by the photoelectric conversion, and outputs pixel data constituting one frame of an image to the transmission unit 122, one pixel at a time.

[0187] The transmission unit 122 assigns the data of each pixel supplied from the imaging unit 121 to a plurality of transmission paths, for example, in the order in which the data is supplied from the imaging unit 121, and transmits the data to the DSP 112 in parallel via the plurality of transmission paths. In the example of FIG. 15, the pixel data is transmitted using eight transmission paths. The transmission paths between the image sensor 111 and the DSP 112 may be wired transmission paths or wireless transmission paths. Hereinafter, the transmission paths between the image sensor 111 and the DSP 112 are appropriately referred to as lanes.

[0188] The receiving unit 131 of the DSP 112 receives the pixel data transmitted from the transmitting unit 122 via the eight lanes, and outputs the data for each pixel to the image processing unit 132 in sequence.

[0189] The image processing unit 132 generates an image of one frame based on the pixel data supplied from the receiving unit 131, and performs various image processing using the generated image. The image data transmitted from the image sensor 111 to the DSP 112 is RAW data, and the image processing unit 132 performs various processes such as compressing the image data, displaying the image, and recording the image data on a recording medium.

[0190] <Frame format> FIG. 16 is a diagram showing an example of a format used for transmitting one frame of image data between the image sensor 111 and the DSP 112. In FIG.

[0191] The effective pixel area A1 is an area of ​​effective pixels in one frame of an image captured by the imaging section 121. A margin area A2, whose vertical number of pixels is the same as that of the effective pixel area A1, is set to the left of the effective pixel area A1.

[0192] A front dummy area A3 is set above the effective pixel area A1, and the number of pixels in the horizontal direction is the same as the number of pixels in the effective pixel area A1 and the entire margin area A2 in the horizontal direction. In the example of Fig. 16, Embedded Data is inserted into the front dummy area A3. The Embedded Data includes information on setting values ​​related to imaging by the imaging unit 121, such as shutter speed, aperture value, and gain. Embedded Data may also be inserted into the rear dummy area A4.

[0193] Below the effective pixel area A1, a rear dummy area A4 is set, the number of pixels in the horizontal direction of which is the same as the number of pixels in the effective pixel area A1 and the entire margin area A2 in the horizontal direction.

[0194] The effective pixel area A1, the margin area A2, the front dummy area A3, and the rear dummy area A4 constitute an image data area A11.

[0195] A header is added before each line that constitutes the image data area A11, and a start code is added before the header. In addition, a footer is optionally added after each line that constitutes the image data area A11, and a control code such as an end code (described later) is added after the footer. If a footer is not added, a control code such as an end code is added after each line that constitutes the image data area A11.

[0196] Every time one frame of an image captured by the imaging unit 121 is transmitted from the image sensor 111 to the DSP 112, the entire data in the format shown in FIG. 16 is transmitted as transmission data.

[0197] The upper band in Fig. 16 shows the structure of packets used to transmit the transmission data shown below. If the horizontal row of pixels is considered to be a line, the payload of a packet stores data of the pixels that make up one line of the image data area A11. The transmission of the entire image data of one frame is performed using packets whose number is equal to or greater than the number of pixels in the vertical direction of the image data area A11.

[0198] A packet is constructed by adding a header and footer to a payload that stores one line of pixel data. As will be described in detail later, the header contains additional information about the pixel data stored in the payload, such as Frame Start, Frame End, Line Valid, Line Number, and ECC. At least the Start Code and End Code, which are control codes, are added to each packet.

[0199] In this way, by adopting a format in which the pixel data that constitutes one frame of an image is transmitted line by line, it becomes possible to transmit additional information such as a header and control codes such as a start code and end code during the blanking period for each line.

[0200] <Configuration of the Transmitter 122 and the Receiver 131> FIG. 17 is a diagram showing an example of the configuration of the transmission unit 122 and the reception unit 131. As shown in FIG.

[0201] 17, the configuration enclosed by a dashed line on the left side is the configuration of the transmission unit 122, and the configuration enclosed by a dashed line on the right side is the configuration of the reception unit 131. The transmission unit 122 and the reception unit 131 each have a link layer configuration and a physical layer configuration. The configuration shown above the solid line L201 is the link layer configuration, and the configuration shown below the solid line L201 is the physical layer configuration.

[0202] The configuration shown above the solid line L101 is the configuration of the application layer. The system control unit 151, the frame data input unit 152, and the register 153 are realized in the imaging unit 121. The system control unit 151 communicates with the LINK-TX protocol management unit 161 of the transmission unit 122, and controls the transmission of image data by providing information on the frame format. The frame data input unit 152 captures an image in response to an instruction from a user, and supplies data of each pixel constituting the image obtained by capturing the image to the Pixel to Byte conversion unit 162 of the transmission unit 122. The register 153 stores information such as the number of bits for Pixel to Byte conversion and the number of Lanes. The image data is transmitted according to the information stored in the register 153.

[0203] Also, the frame data output unit 241, the register 242, and the system control unit 243 in the configuration of the application layer are realized in the image processing unit 132. The frame data output unit 241 generates and outputs one frame of image based on pixel data of each line supplied from the receiving unit 131. Various processes are performed using the image output from the frame data output unit 241. The register 242 stores various setting values ​​related to reception of image data, such as the number of bits for Byte to Pixel conversion and the number of Lanes. Reception processing of image data is performed according to the information stored in the register 242. The system control unit 243 communicates with the LINK-RX protocol management unit 221 and controls sequences such as mode changes.

[0204] <Link Layer Configuration of Transmitter 122> First, the configuration of the link layer of the transmission unit 122 will be described.

[0205] The transmitter 122 is provided with, as link layer components, a LINK-TX protocol management unit 161, a Pixel to Byte conversion unit 162, a payload ECC insertion unit 163, a packet generation unit 164, and a lane distribution unit 165. The LINK-TX protocol management unit 161 is composed of a state control unit 171, a header generation unit 172, a data insertion unit 173, and a footer generation unit 174.

[0206] The state control unit 171 of the LINK-TX protocol management unit 161 manages the state of the link layer of the transmission unit 122 .

[0207] The header generation unit 172 generates a header to be added to a payload in which one line's worth of pixel data is stored, and outputs the header to the packet generation unit 164 .

[0208] FIG. 18 is a diagram showing the structure of the header generated by the header generating unit 172. As shown in FIG.

[0209] As mentioned above, one packet consists of a header and payload data, which is one line of pixel data. A footer may be added to the packet. The header consists of header information and Header ECC.

[0210] The header information includes Frame Start, Frame End, Line Valid, Line Number, and Reserved. The content and amount of each information is shown in Figure 19.

[0211] Frame Start is 1-bit information indicating the beginning of a frame. A value of 1 is set to Frame Start in the header of a packet used to transmit pixel data of the first line in the image data area A11 in Fig. 16, and a value of 0 is set to Frame Start in the header of a packet used to transmit pixel data of other lines.

[0212] Frame End is 1-bit information indicating the end of a frame. The Frame End of the header of a packet that contains in its payload the pixel data of the last line of the effective pixel area A1 is set to a value of 1, and the Frame End of the header of a packet used to transmit pixel data of other lines is set to a value of 0.

[0213] Frame Start and Frame End constitute frame information, which is information relating to a frame.

[0214] "Line Valid" is 1-bit information that indicates whether the line of pixel data stored in the payload is a line of valid pixels. A value of 1 is set to "Line Valid" in the header of a packet used to transmit pixel data of a line within the valid pixel area A1, and a value of 0 is set to "Line Valid" in the header of a packet used to transmit pixel data of other lines.

[0215] The Line Number is 13-bit information that indicates the line number of the line composed of the pixel data stored in the payload.

[0216] Line Valid and Line Number constitute line information, which is information about the line.

[0217] Reserved is a 32-bit area for expansion. The total data size of the header information is 6 bytes.

[0218] 18, the Header ECC placed following the header information includes a CRC (Cyclic Redundancy Check) code, which is a 2-byte error detection code calculated based on the 6-byte header information. In addition, the Header ECC includes two pieces of information following the CRC code, which are the same as the 8-byte information that is a combination of the header information and the CRC code.

[0219] In other words, one packet header contains three sets of the same header information and CRC code. The total data size of the header is 24 bytes, consisting of the first 8-byte set of header information and CRC code, the second 8-byte set of header information and CRC code, and the third 8-byte set of header information and CRC code.

[0220] FIG. 20 is a diagram showing an example of an 8-byte bit array that constitutes one set of header information and a CRC code.

[0221] The first byte H7 of the eight bytes that make up the header contains, in order from bit 1, one each of Frame Start, Frame End, and Line Valid, as well as bits 1 to 5 of the 13-bit Line Number. Additionally, the second byte H6 contains bits 6 to 13 of the 13-bit Line Number.

[0222] The third byte H5 to the sixth byte H2 are reserved. The seventh byte H1 and the eighth byte H0 contain the bits of the CRC code.

[0223] 17, the header generation unit 172 generates header information under the control of the system control unit 151. For example, the system control unit 151 supplies information indicating the line number of the pixel data output by the frame data input unit 152 and information indicating the beginning and end of the frame.

[0224] Furthermore, the header generating unit 172 applies the header information to a generating polynomial to calculate a CRC code. The generating polynomial of the CRC code added to the header information is expressed by, for example, the following equation (1).

number

[0225] The header generating unit 172 generates a pair of the header information and the CRC code by adding a CRC code to the header information, and generates a header by repeatedly arranging the same pair of the header information and the CRC code three times. The header generating unit 172 outputs the generated header to the packet generating unit 164.

[0226] The data insertion unit 173 generates data used for stuffing, and outputs it to the Pixel to Byte conversion unit 162 and the lane distribution unit 165. The stuffing data supplied to the Pixel to Byte conversion unit 162, that is, payload stuffing data, is added to pixel data after Pixel to Byte conversion, and is used to adjust the amount of pixel data stored in the payload. Also, the stuffing data supplied to the lane distribution unit 165, that is, lane stuffing data, is added to data after lane allocation, and is used to adjust the amount of data between lanes.

[0227] The footer generating unit 174, under the control of the system control unit 151, appropriately applies the payload data to a generating polynomial to calculate a 32-bit CRC code, and outputs the calculated CRC code as a footer to the packet generating unit 164. The generating polynomial for the CRC code added as the footer is expressed by, for example, the following equation (2).

number

[0228] The pixel to byte conversion unit 162 acquires the pixel data supplied from the frame data input unit 152, and performs pixel to byte conversion to convert the data of each pixel into data in units of one byte. For example, the pixel value (RGB) of each pixel of the image captured by the imaging unit 121 is represented by any one of 8 bits, 10 bits, 12 bits, 14 bits, and 16 bits.

[0229] FIG. 21 is a diagram showing an example of pixel-to-byte conversion in the case where the pixel value of each pixel is represented by 8 bits.

[0230] Data[0] represents the LSB, and Data[7], the largest number, represents the MSB. As indicated by the white arrow, in this case, the 8 bits of Data[7]~[0] representing the pixel value of pixel N are converted to Byte N consisting of Data[7]~[0]. When the pixel value of each pixel is represented by 8 bits, the number of bytes of data after pixel to byte conversion will be the same as the number of pixels.

[0231] FIG. 22 is a diagram showing an example of pixel-to-byte conversion in the case where the pixel value of each pixel is represented by 10 bits.

[0232] In this case, the 10 bits of Data[9] to [0] that represent the pixel value of pixel N are converted into Byte 1.25*N consisting of Data[9] to [2].

[0233] Similarly, for pixels N+1 to N+3, the 10 bits Data[9] to [0] representing each pixel value are converted to Bytes 1.25*N+1 to 1.25*N+3 consisting of Data[9] to [2]. Additionally, the lowest bits Data[1] and Data[0] of pixels N to N+3 are collected and converted to Byte 1.25*N+4. When the pixel value of each pixel is represented by 10 bits, the number of bytes of data after Pixel to Byte conversion will be 1.25 times the number of pixels.

[0234] FIG. 23 is a diagram showing an example of pixel-to-byte conversion in the case where the pixel value of each pixel is represented by 12 bits.

[0235] In this case, the 12 bits of Data

[11] to [0] that represent the pixel value of pixel N are converted into Byte 1.5*N consisting of Data

[11] to [4].

[0236] Similarly, for pixel N+1, the 12 bits Data

[11] to [0] representing the pixel value of pixel N+1 are converted into Byte 1.5*N+1 consisting of Data

[11] to [4]. Additionally, the lowest bits Data[3] to [0] of pixels N and N+1 are collected and converted into Byte 1.5*N+2. When the pixel value of each pixel is represented by 12 bits, the number of data bytes after Pixel to Byte conversion will be 1.5 times the number of pixels.

[0237] FIG. 24 is a diagram showing an example of pixel-to-byte conversion in the case where the pixel value of each pixel is represented by 14 bits.

[0238] In this case, the 14 bits of Data

[13] to [0] that represent the pixel value of pixel N are converted into Byte 1.75*N consisting of Data

[13] to [6].

[0239] Similarly, for pixels N+1 to N+3, the 14 bits Data

[13] to [0] representing the pixel values ​​are converted to Bytes 1.75*N+1 to 1.75*N+3 consisting of Data

[13] to [6]. The remaining bits of pixels N to N+3 are collected in order from the least significant bit, and for example, the bits of pixel N, Data[5] to [0], and the bits of pixel N+1, Data[5], [4], are converted to Byte 1.75*N+4.

[0240] Similarly, Data[3] to [0], which are the bits of pixel N+1, and Data[5] to [2], which are the bits of pixel N+2, are converted to Byte 1.75*N+5, and Data[1], [0], which are the bits of pixel N+2, and Data[5] to [0], which are the bits of pixel N+3, are converted to Byte 1.75*N+6. If the pixel value of each pixel is represented by 14 bits, the number of data bytes after Pixel to Byte conversion will be 1.75 times the number of pixels.

[0241] FIG. 25 is a diagram showing an example of pixel-to-byte conversion in the case where the pixel value of each pixel is represented by 16 bits.

[0242] In this case, the 16 bits of Data

[15] to [0] that represent the pixel value of pixel N are converted to Byte 2*N consisting of Data

[15] to [8] and Byte 2*N+1 consisting of Data[7] to [0]. When the pixel value of each pixel is represented by 16 bits, the number of bytes of data after Pixel to Byte conversion will be twice the number of pixels.

[0243] 17 performs such pixel to byte conversion on each pixel in sequence starting from the pixel at the left end of the line. The pixel to byte conversion unit 162 also generates payload data by adding payload stuffing data supplied from the data insertion unit 173 to the pixel data in units of bytes obtained by the pixel to byte conversion, and outputs the payload data to the payload ECC insertion unit 163.

[0244] FIG. 26 is a diagram illustrating an example of payload data.

[0245] 26 shows payload data including pixel data obtained by pixel to byte conversion when the pixel value of each pixel is represented by 10 bits. One uncolored block represents pixel data in units of bytes after pixel to byte conversion. One colored block represents payload stuffing data generated by the data insertion unit 173.

[0246] The pixel data after pixel to byte conversion is grouped into a predetermined number of groups in the order obtained by the conversion. In the example of Fig. 26, the pixel data are grouped into 16 groups, groups 0 to 15, where the pixel data including the MSB of pixel P0 is assigned to group 0, and the pixel data including the MSB of pixel P1 is assigned to group 1. The pixel data including the MSB of pixel P2 is assigned to group 2, the pixel data including the MSB of pixel P3 is assigned to group 3, and the pixel data including the LSBs of pixels P0 to P3 is assigned to group 4.

[0247] The pixel data after the pixel data containing the MSB of pixel P4 is also assigned in order to each group from group 5 onwards. When certain pixel data is assigned to group 15, the subsequent pixel data is assigned in order to each group from group 0 onwards. Of the blocks representing pixel data, a block with three dashed lines inside represents pixel data in bytes that is generated during pixel to byte conversion so as to include the LSBs of pixels N to N+3.

[0248] In the link layer of the transmitter 122, after grouping in this manner, pixel data at the same position in each group is processed in parallel for each period defined by the clock signal. That is, when pixel data is assigned to 16 groups as shown in Fig. 26, the pixel data is processed such that the 16 pixel data arranged in each column are processed within the same period.

[0249] As described above, the payload of one packet contains one line of pixel data. The entire pixel data shown in Fig. 26 is pixel data that constitutes one line. Here, the processing of pixel data in the effective pixel area A1 in Fig. 16 is described, but pixel data in other areas such as the margin area A2 are also processed together with the pixel data in the effective pixel area A1.

[0250] After one line of pixel data is grouped, payload stuffing data is added to make the data length of each group the same. The payload stuffing data is 1 byte of data.

[0251] 26, no payload stuffing data is added to the pixel data of group 0, and one piece of payload stuffing data is added to the end of each pixel data of groups 1 to 15, as shown by the dashed lines. The data length (bytes) of the payload data consisting of pixel data and stuffing data is expressed by the following formula (3).

number

[0252] In equation (3), LineLength represents the number of pixels in a line, BitPix represents the number of bits that represent the pixel value of one pixel, and PayloadStuffing represents the number of payload stuffing data.

[0253] When pixel data is allocated to 16 groups as shown in Fig. 26, the number of payload stuffing data is expressed by the following formula (4): In formula (4), % represents a remainder.

number

[0254] FIG. 27 is a diagram illustrating another example of the payload data.

[0255] FIG. 27 shows payload data including pixel data obtained by pixel to byte conversion when the pixel value of each pixel is represented by 12 bits.

[0256] 27, pixel data including the MSB of pixel P0 is assigned to group 0, pixel data including the MSB of pixel P1 is assigned to group 1, and pixel data including the LSBs of pixels P0 and P1 is assigned to group 2. The pixel data including the MSB of pixel P2 and subsequent pixel data are also assigned in order to each group from group 3 onwards. Of the blocks representing pixel data, a block with a single dashed line inside represents pixel data in bytes that was generated during pixel to byte conversion so as to include the LSBs of pixel N and pixel N+1.

[0257] In the example of FIG. 27, no payload stuffing data is added to the pixel data of groups 0 and 1, and one piece of payload stuffing data is added to the end of each of the pixel data of groups 2 to 15.

[0258] Payload data having such a structure is supplied from the Pixel to Byte conversion unit 162 to the payload ECC insertion unit 163 .

[0259] The payload ECC insertion unit 163 calculates an error correction code used for error correction of the payload data based on the payload data supplied from the Pixel to Byte conversion unit 162, and inserts the parity, which is the error correction code obtained by calculation, into the payload data. For example, a Reed-Solomon code is used as the error correction code. Note that the insertion of the error correction code is optional, and for example, only one of the insertion of the parity by the payload ECC insertion unit 163 and the addition of the footer by the footer generation unit 174 can be performed.

[0260] FIG. 28 is a diagram showing an example of payload data in which parity is inserted.

[0261] The payload data shown in Fig. 28 is payload data including pixel data obtained by pixel to byte conversion in the case where the pixel value of each pixel is represented by 12 bits, as described with reference to Fig. 27. The shaded blocks represent parity.

[0262] 28, 14 pixel data are selected in order from the top of each group from groups 0 to 15, and 2 bytes of parity are calculated based on the selected 224 pixel data (224 bytes). The 2 bytes of parity are inserted as the 15th data of groups 0 and 1 following the 224 pixel data used in the calculation, and the first Basic Block is formed from the 224 pixel data and the 2 bytes of parity.

[0263] In this way, in the payload ECC insertion unit 163, basically, 2 bytes of parity are generated based on 224 pieces of pixel data, and inserted consecutively to the 224 pieces of pixel data.

[0264] 28, 224 pixel data following the first Basic Block are selected in order from each group, and 2 bytes of parity are calculated based on the selected 224 pixel data. The 2 bytes of parity are inserted as the 29th data of groups 2 and 3 following the 224 pixel data used in the calculation, and the second Basic Block is formed from the 224 pixel data and the 2 bytes of parity.

[0265] If the number of pixel data and payload stuffing data following a Basic Block, 16×M, is less than 224, 2 bytes of parity are calculated based on the remaining 16×M blocks (pixel data and payload stuffing data). The calculated 2 bytes of parity are inserted following the payload stuffing data, and an Extra Block is formed from the 16×M blocks and 2 bytes of parity.

[0266] The payload ECC insertion unit 163 outputs the payload data with the parity inserted therein to the packet generation unit 164. When parity insertion is not performed, the payload data supplied from the Pixel to Byte conversion unit 162 to the payload ECC insertion unit 163 is output to the packet generation unit 164 as is.

[0267] The packet generator 164 generates a packet by adding a header generated by the header generator 172 to the payload data supplied from the payload ECC inserter 163. When a footer is generated by the footer generator 174, the packet generator 164 also adds the footer to the payload data.

[0268] FIG. 29 is a diagram showing a state in which a header is added to payload data.

[0269] The 24 blocks labeled H7 to H0 represent header data in bytes, which is header information or a CRC code of the header information. As described with reference to Fig. 18, the header of one packet includes three pairs of header information and a CRC code.

[0270] For example, the header data H7 to H2 are header information (6 bytes), and the header data H1 and H0 are CRC codes (2 bytes).

[0271] In the example of Fig. 29, one header data H7 is added to the payload data of group 0, and one header data H6 is added to the payload data of group 1. One header data H5 is added to the payload data of group 2, and one header data H4 is added to the payload data of group 3. One header data H3 is added to the payload data of group 4, and one header data H2 is added to the payload data of group 5. One header data H1 is added to the payload data of group 6, and one header data H0 is added to the payload data of group 7.

[0272] 29, two pieces of header data H7 are added to the payload data of group 8, and two pieces of header data H6 are added to the payload data of group 9. Two pieces of header data H5 are added to the payload data of group 10, and two pieces of header data H4 are added to the payload data of group 11. Two pieces of header data H3 are added to the payload data of group 12, and two pieces of header data H2 are added to the payload data of group 13. Two pieces of header data H1 are added to the payload data of group 14, and two pieces of header data H0 are added to the payload data of group 15.

[0273] FIG. 30 is a diagram showing a state in which a header and a footer are added to payload data.

[0274] The four blocks labeled F3 to F0 represent footer data, which is a 4-byte CRC code generated as a footer. In the example of Fig. 30, the footer data F3 to F0 are added to the payload data of each of groups 0 to 3.

[0275] FIG. 31 is a diagram showing a state in which a header is added to payload data into which parity has been inserted.

[0276] In the example of FIG. 31, header data H7 to H0 are added to the payload data of FIG. 28 into which parity has been inserted, in the same manner as in the cases of FIG. 29 and FIG.

[0277] The packet generator 164 outputs packet data, which is data constituting one packet generated in this manner, to the lane distributor 165. Packet data consisting of header data and payload data, packet data consisting of header data, payload data, and footer data, or packet data consisting of header data and payload data into which parity has been inserted, is supplied to the lane distributor 165. The packet structure in Fig. 18 is a logical one, and in the link layer and physical layer, the data of a packet having the structure in Fig. 18 is processed in units of bytes.

[0278] The lane distributor 165 allocates the packet data supplied from the packet generator 164 to each of the lanes 0 to 7 used for data transmission, in order from the leading data.

[0279] FIG. 32 is a diagram illustrating an example of packet data allocation.

[0280] Here, allocation of packet data (FIG. 30) consisting of header data, payload data, and footer data will be described. An example of packet data allocation when data transmission is performed using eight lanes from Lanes 0 to 7 is shown at the end of the white arrow #1.

[0281] In this case, each of the header data constituting the three repetitions of header data H7 to H0 is assigned to Lanes 0 to 7 in order starting from the first header data. When a certain header data is assigned to Lane 7, the subsequent header data is assigned to each lane from Lane 0 onwards in order. The same header data is assigned three times to each of Lanes 0 to 7.

[0282] Furthermore, payload data is allocated in order from the leading payload data to Lanes 0 to 7. When some payload data is allocated to Lane 7, the subsequent payload data is allocated in order to each of the lanes from Lane 0 onwards.

[0283] The footer data F3 to F0 are assigned to each lane in order from the first footer data. In the example of Fig. 32, the last payload stuffing data constituting the payload data is assigned to Lane 7, and the footer data F3 to F0 are assigned to Lanes 0 to 3 one by one.

[0284] Blocks shown in black represent lane stuffing data generated by the data insertion unit 173. After one packet of packet data is assigned to each lane, the lane stuffing data is assigned to a lane with a smaller amount of data so that the data length assigned to each lane is the same. The lane stuffing data is 1 byte of data. In the example of FIG. 32, one piece of lane stuffing data is assigned to each of Lanes 4 to 7, which are lanes with a smaller amount of data assigned.

[0285] When packet data consists of header data, payload data, and footer data, the number of lane stuffing data is expressed by the following equation (5).

number

[0286] In formula (5), LaneNum represents the number of lanes, PayloadLength represents the payload data length (bytes), and FooterLength represents the footer length (bytes).

[0287] Furthermore, when packet data consists of header data and payload data with parity inserted, the number of lane stuffing data is expressed by the following formula (6): ParityLength in formula (6) represents the total number of bytes of parity included in the payload.

number

[0288] An example of packet data allocation when data transmission is performed using six lanes, Lanes 0 to 5, is shown at the end of the white arrow #2.

[0289] In this case, each of the header data constituting the three repetitions of header data H7 to H0 is assigned to Lanes 0 to 5 in order starting from the first header data. When a certain header data is assigned to Lane 5, the subsequent header data is assigned to each of the lanes from Lane 0 onwards in order. Four pieces of header data are assigned to each of Lanes 0 to 5.

[0290] Furthermore, payload data is allocated in order from the leading payload data to Lanes 0 to 5. When some payload data is allocated to Lane 5, the subsequent payload data is allocated in order to each of the lanes from Lane 0 onwards.

[0291] The footer data F3 to F0 are assigned to each lane in order from the first footer data. In the example of Fig. 32, the last payload stuffing data constituting the payload data is assigned to Lane 1, and the footer data F3 to F0 are assigned one each to Lanes 2 to 5. Since the number of packet data in Lanes 0 to 5 is the same, in this case, the lane stuffing data is not used.

[0292] An example of packet data allocation when data transmission is performed using four lanes, Lanes 0 to 3, is shown at the end of the white arrow #3.

[0293] In this case, each of the header data constituting the three repetitions of header data H7 to H0 is assigned to Lanes 0 to 3 in order starting from the first header data. When a certain header data is assigned to Lane 3, the subsequent header data is assigned to each lane from Lane 0 onwards in order. Six pieces of header data are assigned to each of Lanes 0 to 3.

[0294] Furthermore, the payload data is allocated in order from the leading payload data to Lanes 0 to 3. When some payload data is allocated to Lane 3, the subsequent payload data is allocated in order to each of the lanes from Lane 0 onwards.

[0295] The footer data F3 to F0 are assigned to each lane in order from the first footer data. In the example of Fig. 32, the last payload stuffing data constituting the payload data is assigned to Lane 3, and the footer data F3 to F0 are assigned one each to Lanes 0 to 3. Since the number of packet data in Lanes 0 to 3 is the same, in this case, the lane stuffing data is not used.

[0296] The lane distributor 165 outputs the packet data thus allocated to each lane to the physical layer. The following mainly describes a case where data is transmitted using eight lanes, Lanes 0 to 7, but similar processing is performed even when the number of lanes used for data transmission is other than the above.

[0297] <Physical Layer Configuration of Transmitter 122> Next, the configuration of the physical layer of the transmitting unit 122 will be described.

[0298] The transmitting unit 122 is provided with a PHY-TX state control unit 181, a clock generating unit 182, and signal processing units 183-0 to 183-N as components of the physical layer. The signal processing unit 183-0 is composed of a control code inserting unit 191, an 8B10B symbol encoder 192, a synchronizing unit 193, and a transmitting unit 194.

[0299] The encoder 11 that performs the encoding described with reference to Figures 1 to 13 can be used in place of the 8B10B symbol encoder 192. The case where the encoder 11 is used in place of the 8B10B symbol encoder 192 will be described first, and the case where the encoder 11 is used in place of the 8B10B symbol encoder 192 will be described with reference to Figures 42 onwards.

[0300] Packet data assigned to Lane 0, output from the lane distributor 165, is input to a signal processor 183-0, and packet data assigned to Lane 1 is input to a signal processor 183-1. Also, packet data assigned to Lane N is input to a signal processor 183-N.

[0301] In this way, the physical layer of the transmitter 122 is provided with signal processing units 183-0 to 183-N in the same number as the number of lanes, and processing of packet data to be transmitted using each lane is performed in parallel in each of the signal processing units 183-0 to 183-N. The configuration of the signal processing unit 183-0 will be described, but the signal processing units 183-1 to 183-N also have the same configuration.

[0302] The PHY-TX state control unit 181 controls each unit of the signal processing units 183-0 to 183-N. For example, the PHY-TX state control unit 181 controls the timing of each process performed by the signal processing units 183-0 to 183-N.

[0303] The clock generating unit 182 generates a clock signal and outputs it to the synchronization units 193 of each of the signal processing units 183-0 to 183-N.

[0304] The control code insertion unit 191 of the signal processing unit 183-0 adds a control code to the packet data supplied from the lane distribution unit 165. The control code is a code represented by one symbol selected from a plurality of types of symbols prepared in advance, or a combination of a plurality of types of symbols. Each symbol inserted by the control code insertion unit 191 is 8-bit data. By performing 8B10B conversion in a subsequent circuit, one symbol inserted by the control code insertion unit 191 becomes 10-bit data. On the other hand, in the receiving unit 131, 10B8B conversion is performed on the received data as described later, but each symbol before the 10B8B conversion included in the received data is 10-bit data, and each symbol after the 10B8B conversion becomes 8-bit data.

[0305] FIG. 33 is a diagram showing an example of the control code added by the control code insertion unit 191. As shown in FIG.

[0306] Control codes include Idle Code, Start Code, End Code, Pad Code, Sync Code, Deskew Code, and Standby Code.

[0307] The idle code is a group of symbols that are repeatedly transmitted during periods other than when packet data is being transmitted. The idle code is represented by the D character D00.0 (00000000), which is an 8B10B code.

[0308] The Start Code is a group of symbols that indicates the start of a packet. As mentioned above, the Start Code is added to the beginning of a packet. The Start Code is represented by four symbols, K28.5, K27.7, K28.2, and K27.7, which are combinations of three types of K Characters. The values ​​of each K Character are shown in Figure 34.

[0309] End Code is a group of symbols that indicates the end of a packet. As mentioned above, End Code is added to the end of a packet. End Code is represented by four symbols, K28.5, K29.7, K30.7, and K29.7, which are combinations of three types of K Characters.

[0310] The Pad Code is a group of symbols inserted into the payload data to fill the difference between the pixel data bandwidth and the PHY transmission bandwidth. The pixel data bandwidth is the transmission rate of the pixel data output from the imaging unit 121 and input to the transmission unit 122, and the PHY transmission bandwidth is the transmission rate of the pixel data transmitted from the transmission unit 122 and input to the reception unit 131. The Pad Code is represented by four symbols, K23.7, K28.4, K28.6, and K28.3, which are combinations of four types of K Characters.

[0311] FIG. 35 is a diagram showing an example of inserting a Pad Code.

[0312] The upper part of Fig. 35 shows the payload data assigned to each lane before the Pad Code is inserted, and the lower part shows the payload data after the Pad Code is inserted. In the example of Fig. 35, the Pad Code is inserted between the third and fourth pixel data from the top, between the sixth and seventh pixel data, and between the twelfth and thirteenth pixel data. In this way, the Pad Code is inserted at the same position in the payload data of each lane, Lanes 0 to 7.

[0313] The insertion of Pad Codes into the payload data assigned to Lane 0 is performed by the control code insertion unit 191 of the signal processing unit 183-0. Similarly, the insertion of Pad Codes into the payload data assigned to the other lanes is performed at the same timing in each of the signal processing units 183-1 to 183-N. The number of Pad Codes is determined based on the difference between the pixel data band and the PHY transmission band, the frequency of the clock signal generated by the clock generation unit 182, and the like.

[0314] In this way, when the pixel data band is narrow and the PHY transmission band is wide, the Pad Code is inserted to adjust the difference between the two bands. For example, the Pad Code is inserted to adjust the difference between the pixel data band and the PHY transmission band to fall within a certain range.

[0315] Returning to the explanation of Fig. 33, the Sync Code is a group of symbols used to ensure bit synchronization and symbol synchronization between the transmitter 122 and the receiver 131. The Sync Code is represented by two symbols, K28.5 and Any**. Any** indicates that any type of symbol may be used. The Sync Code is repeatedly transmitted, for example, during a training mode before the start of transmission of packet data between the transmitter 122 and the receiver 131.

[0316] The deskew code is a group of symbols used to correct data skew between lanes, that is, a difference in reception timing of data received at each lane of the receiver 131. The deskew code is represented by two symbols, K28.5 and Any**. The correction of data skew between lanes using the deskew code will be described later.

[0317] The Standby Code is a group of symbols used to notify the receiving unit 131 that the output of the transmitting unit 122 will be in a state such as High-Z (high impedance) and data transmission will no longer be performed. That is, the Standby Code is transmitted to the receiving unit 131 when the transmission of packet data ends and the unit goes into a Standby state. The Standby Code is represented by two symbols, K28.5 and Any**.

[0318] The control code insertion unit 191 outputs the packet data to which such a control code has been added to the 8B10B symbol encoder 192.

[0319] FIG. 36 is a diagram showing an example of packet data after the control code is inserted.

[0320] As shown in Fig. 36, in each of the signal processing units 183-0 to 183-N, a start code is added before the packet data, and a pad code is inserted into the payload data. An end code is added after the packet data, and a deskew code is added after the end code. In the example of Fig. 36, an idle code is added after the deskew code.

[0321] The 8B10B symbol encoder 192 performs 8B10B conversion on the packet data (packet data to which a control code has been added) supplied from the control code insertion unit 191, and outputs the packet data converted into data in 10-bit units to the synchronization unit 193.

[0322] Synchronization unit 193 outputs each bit of the packet data supplied from 8B10B symbol encoder 192 to transmission unit 194 in accordance with the clock signal generated by clock generation unit 182. Note that transmission unit 122 may not be provided with synchronization unit 193. In this case, the packet data output from 8B10B symbol encoder 192 is supplied to transmission unit 194 as is.

[0323] The transmitting unit 194 transmits the packet data supplied from the synchronizing unit 193 to the receiving unit 131 via the transmission path constituting Lane 0. When data transmission is performed using 8 lanes, the packet data is transmitted to the receiving unit 131 also using the transmission paths constituting Lanes 1 to 7.

[0324] <Physical Layer Configuration of Receiving Unit 131> Next, the configuration of the physical layer of the receiving unit 131 will be described.

[0325] The receiving unit 131 is provided with a PHY-RX state control unit 201 and signal processing units 202-0 to 202-N as a physical layer configuration. The signal processing unit 202-0 is made up of a receiving unit 211, a clock generating unit 212, a synchronizing unit 213, a symbol synchronizing unit 214, a 10B8B symbol decoder 215, a skew correcting unit 216, and a control code removing unit 217.

[0326] The decoder 12 that performs the decoding described with reference to Figures 1 to 13 can be used in place of the 10B8B symbol decoder 215. The case where the decoder 12 is used in place of the 10B8B symbol decoder 215 will be described first, and the case where the decoder 12 is used in place of the 10B8B symbol decoder 215 will be described with reference to Figures 42 onwards.

[0327] Packet data transmitted via the transmission path constituting Lane0 is input to the signal processing unit 202-0, and packet data transmitted via the transmission path constituting Lane1 is input to the signal processing unit 202-1. Also, packet data transmitted via the transmission path constituting LaneN is input to the signal processing unit 202-N.

[0328] In this way, the physical layer of the receiver 131 is provided with signal processing units 202-0 to 202-N in the same number as the number of lanes, and the packet data transmitted using each lane is processed in parallel in each of the signal processing units 202-0 to 202-N. The configuration of the signal processing unit 202-0 will be described, but the signal processing units 202-1 to 202-N also have the same configuration.

[0329] The receiving unit 211 receives a signal representing packet data transmitted from the transmitting unit 122 via the transmission path that constitutes Lane 0 , and outputs the signal to the clock generating unit 212 .

[0330] The clock generating unit 212 performs bit synchronization by detecting edges of the signal supplied from the receiving unit 211, and generates a clock signal based on the edge detection period. The clock generating unit 212 outputs the signal supplied from the receiving unit 211 to the synchronizing unit 213 together with the clock signal.

[0331] The synchronization unit 213 samples the signal received by the receiving unit 211 in accordance with the clock signal generated by the clock generation unit 212, and outputs packet data obtained by the sampling to the symbol synchronization unit 214. The clock generation unit 212 and the synchronization unit 213 realize a CDR (Clock Data Recovery) function.

[0332] The symbol synchronization unit 214 performs symbol synchronization by detecting a control code included in the packet data or by detecting a part of a symbol included in the control code. For example, the symbol synchronization unit 214 detects a K28.5 symbol included in the Start Code, End Code, and Deskew Code to perform symbol synchronization. The symbol synchronization unit 214 outputs packet data in 10-bit units representing each symbol to the 10B8B symbol decoder 215.

[0333] Furthermore, the symbol synchronization unit 214 performs symbol synchronization by detecting the boundaries of symbols included in the Sync Code repeatedly transmitted from the transmission unit 122 during the training mode before the start of packet data transmission.

[0334] The 10B8B symbol decoder 215 performs 10B8B conversion on the 10-bit packet data supplied from the symbol synchronizer 214 , and outputs the packet data converted into 8-bit data to the skew corrector 216 .

[0335] The skew correction unit 216 detects a deskew code from the packet data supplied from the 10B8B symbol decoder 215. Information on the timing at which the skew code is detected by the skew correction unit 216 is supplied to the PHY-RX state control unit 201.

[0336] The skew correction unit 216 also corrects data skew between lanes by adjusting the timing of the deskew code to the timing represented by the information supplied from the PHY-RX state control unit 201. The PHY-RX state control unit 201 supplies information representing the latest timing of the deskew codes detected in each of the signal processing units 202-0 to 202-N.

[0337] FIG. 37 is a diagram illustrating an example of correcting data skew between lanes using Deskew Code.

[0338] 37, in each of Lanes 0 to 7, Sync Code, Sync Code, ..., Idle Code, Deskew Code, Idle Code, ..., Idle Code, Deskew Code are transmitted, and each control code is received by the receiving unit 131. The timing of receiving the same control code differs for each lane, resulting in data skew between the lanes.

[0339] In this case, the skew correction unit 216 detects Deskew Code C1 which is the first Deskew Code, and corrects the timing of the beginning of Deskew Code C1 to coincide with time t1 indicated by the information supplied from the PHY-RX state control unit 201. The PHY-RX state control unit 201 supplies information on time t1 at which Deskew Code C1 was detected in Lane 7, which is the latest timing among the timings at which Deskew Code C1 was detected in each of Lanes 0 to 7.

[0340] The skew correction unit 216 also detects the second Deskew Code, Deskew Code C2, and corrects the timing of the beginning of Deskew Code C2 to coincide with time t2 indicated by the information supplied from the PHY-RX state control unit 201. The PHY-RX state control unit 201 supplies information on time t2 when Deskew Code C2 is detected in Lane 7, which is the latest timing among the timings when Deskew Code C2 is detected in each of Lanes 0 to 7.

[0341] Similar processing is performed in each of the signal processing units 202-1 to 202-N, whereby data skew between the lanes is corrected as indicated by the tip of the arrow #1 in FIG.

[0342] The skew correction unit 216 outputs the packet data with the data skew corrected to the control code removal unit 217 .

[0343] The control code removal unit 217 removes the control code added to the packet data, and outputs the data between the Start Code and the End Code to the link layer as packet data.

[0344] The PHY-RX state control unit 201 controls each unit of the signal processing units 202-0 to 202-N to correct data skew between lanes, etc. When a transmission error occurs in a specific lane and a control code is lost, the PHY-RX state control unit 201 performs error correction of the control code by adding a control code transmitted in another lane in place of the lost control code.

[0345] <Link Layer Configuration of Receiving Unit 131> Next, the configuration of the link layer of the receiving unit 131 will be described.

[0346] The receiving unit 131 is provided with a LINK-RX protocol management unit 221, a lane integration unit 222, a packet separation unit 223, a payload error correction unit 224, and a Byte to Pixel conversion unit 225 as link layer configurations. The LINK-RX protocol management unit 221 is made up of a state control unit 231, a header error correction unit 232, a data removal unit 233, and a footer error detection unit 234.

[0347] The lane integration unit 222 integrates the packet data supplied from the physical layer signal processing units 202-0 to 202-N by rearranging the data in the reverse order to the order in which the data was distributed to the lanes by the lane distribution unit 165 of the transmission unit 122.

[0348] For example, when the lane distribution unit 165 distributes packet data as shown by the tip of arrow #1 in Fig. 32, the packet data of each lane is integrated to obtain the packet data on the left side of Fig. 32. When the packet data of each lane is integrated, the lane stuffing data is removed by the lane integration unit 222 under the control of the data removal unit 233. The lane integration unit 222 outputs the integrated packet data to the packet separation unit 223.

[0349] The packet separation unit 223 separates one packet's worth of packet data integrated by the lane integration unit 222 into packet data constituting header data and packet data constituting payload data. The packet separation unit 223 outputs the header data to the header error correction unit 232 and outputs the payload data to the payload error correction unit 224.

[0350] Furthermore, when a footer is included in a packet, the packet separation unit 223 separates one packet's worth of data into packet data constituting header data, packet data constituting payload data, and packet data constituting footer data. The packet separation unit 223 outputs the header data to the header error correction unit 232, and outputs the payload data to the payload error correction unit 224. Furthermore, the packet separation unit 223 outputs the footer data to the footer error detection unit 234.

[0351] When parity is inserted in the payload data supplied from the packet separation unit 223, the payload error correction unit 224 detects an error in the payload data by performing an error correction calculation based on the parity and corrects the detected error. For example, when parity is inserted as shown in Fig. 28, the payload error correction unit 224 uses the two parities inserted at the end of the first basic block to perform error correction on the 224 pixel data preceding the parity.

[0352] The payload error correction unit 224 performs error correction on each Basic Block and Extra Block, and outputs the error-corrected pixel data obtained by the error correction to the Byte to Pixel conversion unit 225. If parity is not inserted in the payload data supplied from the packet separation unit 223, the payload data supplied from the packet separation unit 223 is output to the Byte to Pixel conversion unit 225 as is.

[0353] The byte to pixel conversion unit 225 removes the payload stuffing data contained in the payload data supplied from the payload error correction unit 224 under the control of the data removal unit 233 .

[0354] In addition, the Byte to Pixel conversion unit 225 performs Byte to Pixel conversion to convert the data of each pixel in bytes obtained by removing the payload stuffing data into pixel data in units of 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits. The Byte to Pixel conversion unit 225 performs a conversion that is the reverse of the Pixel to Byte conversion performed by the Pixel to Byte conversion unit 162 of the transmission unit 122 described with reference to Figs. 21 to 25.

[0355] The Byte to Pixel conversion unit 225 outputs pixel data in 8-bit, 10-bit, 12-bit, 14-bit, or 16-bit units obtained by the Byte to Pixel conversion to the frame data output unit 241. In the frame data output unit 241, for example, each line of valid pixels specified by Line Valid in the header information is generated based on the pixel data obtained by the Byte to Pixel conversion unit 225, and one frame of an image is generated by arranging each line according to the Line Number in the header information.

[0356] The state control unit 231 of the LINK-RX protocol management unit 221 manages the state of the link layer of the receiving unit 131 .

[0357] The header error correction unit 232 obtains three pairs of header information and CRC codes based on the header data supplied from the packet separation unit 223. The header error correction unit 232 performs an error detection calculation, which is a calculation for detecting an error in the header information, for each pair of header information and CRC codes, using the CRC code of the same pair as the header information.

[0358] The header error correction unit 232 infers correct header information based on at least one of the error detection result of the header information of each set and the comparison result of the data obtained by the error detection calculation, and outputs the header information inferred to be correct and the decoded result. The data obtained by the error detection calculation is a value obtained by applying a generating polynomial of the CRC to the header information. The decoded result is information indicating whether the decoding is successful or unsuccessful.

[0359] The three sets of header information and CRC codes are set 1, set 2, and set 3, respectively. In this case, the header error correction unit 232 performs an error detection calculation on set 1 to determine whether or not there is an error in the header information of set 1 (error detection result) and obtains data 1, which is the data obtained by the error detection calculation. Furthermore, the header error correction unit 232 performs an error detection calculation on set 2 to determine whether or not there is an error in the header information of set 2 and obtains data 2, which is the data obtained by the error detection calculation. The header error correction unit 232 performs an error detection calculation on set 3 to determine whether or not there is an error in the header information of set 3 and obtains data 3, which is the data obtained by the error detection calculation.

[0360] Furthermore, the header error correction unit 232 determines whether or not data 1 and data 2 match, whether or not data 2 and data 3 match, and whether or not data 3 and data 1 match, respectively.

[0361] For example, if no error is detected by any of the error detection calculations for set 1, set 2, and set 3, and all comparison results of the data obtained by the error detection calculations match, the header error correction unit 232 selects information indicating successful decoding as the decoding result. Also, the header error correction unit 232 assumes that all header information is correct, and selects one of the header information of set 1, the header information of set 2, and the header information of set 3 as output information.

[0362] On the other hand, if no error is detected only in the error detection calculation targeted at set 1, the header error correction unit 232 selects information indicating successful decoding as the decoding result, and infers that the header information of set 1 is correct, and selects the header information of set 1 as output information.

[0363] In addition, if no error is detected only in the error detection calculation targeting set 2, the header error correction unit 232 selects information indicating successful decoding as the decoding result, and infers that the header information of set 2 is correct, and selects the header information of set 2 as output information.

[0364] If no error is detected only in the error detection calculation targeting set 3, the header error correction unit 232 selects information indicating successful decoding as the decoding result, and infers that the header information of set 3 is correct, and selects the header information of set 3 as output information.

[0365] The header error correction unit 232 outputs the decoded result and output information selected as described above to and stores them in the register 242. In this manner, the header error correction unit 232 corrects errors in the header information by detecting error-free header information from among a plurality of pieces of header information using a CRC code, and outputting the detected header information.

[0366] The data removal unit 233 controls the lane integration unit 222 to remove the lane stuffing data, and controls the Byte to Pixel conversion unit 225 to remove the payload stuffing data.

[0367] The footer error detection unit 234 acquires the CRC code stored in the footer based on the footer data supplied from the packet separation unit 223. The footer error detection unit 234 performs an error detection calculation using the acquired CRC code to detect an error in the payload data. The footer error detection unit 234 outputs the error detection result and stores it in the register 242.

[0368] <Operation of image sensor 111 and DSP 112> Next, a series of processes performed by the transmitting unit 122 and the receiving unit 131 having the above configuration will be described.

[0369] First, the operation of an imaging device having the transmission system 100 will be described with reference to the flowchart of Fig. 38. The process of Fig. 38 is started when an instruction to start imaging is issued, for example, by pressing a shutter button provided on the imaging device.

[0370] In step S101, the imaging unit 121 of the image sensor 111 captures an image. The frame data input unit 152 (FIG. 17) of the imaging unit 121 sequentially outputs pixel data constituting one frame of an image obtained by imaging, one pixel at a time.

[0371] In step S102, data transmission processing is performed by the transmitting unit 122. By the data transmission processing, a packet having one line's worth of pixel data stored in its payload is generated, and the packet data constituting the packet is transmitted to the receiving unit 131. The data transmission processing will be described later with reference to the flowchart in FIG.

[0372] In step S103, data reception processing is performed by the receiving unit 131. By the data reception processing, packet data transmitted from the transmitting unit 122 is received, and pixel data stored in the payload is output to the image processing unit 132. The data reception processing will be described later with reference to the flowchart of FIG.

[0373] The data transmission process performed by the transmitter 122 in step S102 and the data reception process performed by the receiver 131 in step S103 are alternately performed for one line of pixel data. That is, when a certain line of pixel data is transmitted by the data transmission process, the data reception process is performed, and when a line of pixel data is received by the data reception process, the data transmission process is performed for the next line of pixel data. The data transmission process by the transmitter 122 and the data reception process by the receiver 131 may be performed in parallel in time as appropriate. In step S104, the frame data output unit 241 of the image processor 132 determines whether or not transmission and reception of pixel data for all lines constituting one frame of image has been completed, and if it is determined that transmission and reception have not been completed, the frame data output unit 241 causes the processes from step S102 onwards to be repeated.

[0374] If it is determined in step S104 that the transmission and reception of pixel data for all lines constituting one frame of an image has been completed, in step S105, the frame data output unit 241 of the image processing unit 132 generates one frame of an image based on the pixel data supplied from the receiving unit 131.

[0375] In step S106, the image processing unit 132 performs image processing using one frame of image, and then ends the processing.

[0376] Next, the data transmission process performed in step S102 in FIG. 38 will be described with reference to the flowchart in FIG.

[0377] In step S111, the header generation unit 172 generates header information including a Frame Start, a Frame End, a Line Valid, a Line Number, and a Reserved.

[0378] In step S112, the header generating unit 172 applies the header information to the generating polynomial to calculate a CRC code.

[0379] In step S113, the header generating unit 172 generates a pair of the header information and the CRC code by adding a CRC code to the header information, and generates a header by repeatedly arranging the same pair of the header information and the CRC code three times.

[0380] In step S114, the Pixel to Byte conversion unit 162 obtains the pixel data supplied from the frame data input unit 152 and performs Pixel to Byte conversion. The Pixel to Byte conversion unit 162 outputs payload data generated by grouping the pixel data in byte units obtained by the Pixel to Byte conversion, adding payload stuffing data, etc. Parity is appropriately inserted into the payload data by the payload ECC insertion unit 163.

[0381] In step S115, the packet generator 164 generates a packet based on the payload data including one line's worth of pixel data and the header generated by the header generator 172, and outputs the packet data constituting one packet.

[0382] In step S116, the lane allocation unit 165 allocates the packet data supplied from the packet generation unit 164 to a plurality of lanes used for data transmission.

[0383] In step S117 , the control code insertion unit 191 adds a control code to the packet data supplied from the lane distribution unit 165 .

[0384] In step S118, 8B10B symbol encoder 192 performs 8B10B conversion on the packet data to which the control code has been added, and outputs the packet data converted into data in 10-bit units.

[0385] In step S119, synchronization unit 193 outputs the packet data supplied from 8B10B symbol encoder 192 in accordance with the clock signal generated by clock generation unit 182, and transmits it from transmission unit 194. The processes of steps S117 to S119 are performed in parallel by signal processing units 183-0 to 183-N. When transmission of one line's worth of pixel data is completed, the process returns to step S102 in Fig. 38 and the subsequent processes are performed.

[0386] Next, the data reception process performed in step S103 in FIG. 38 will be described with reference to the flowchart in FIG.

[0387] In step S131, the receiving unit 211 receives a signal representing packet data transmitted from the transmitting unit 122. The processes of steps S131 to S136 are performed in parallel by the signal processing units 202-0 to 202-N.

[0388] In step S132, the clock generating unit 212 performs bit synchronization by detecting an edge of the signal supplied from the receiving unit 211. The synchronizing unit 213 samples the signal received by the receiving unit 211 and outputs packet data to the symbol synchronizing unit 214.

[0389] In step S133, the symbol synchronization unit 214 performs symbol synchronization by detecting a control code included in the packet data.

[0390] In step S134, the 10B8B symbol decoder 215 performs 10B8B conversion on the packet data after symbol synchronization, and outputs the packet data converted into data in 8-bit units.

[0391] In step S135, the skew correction unit 216 detects the deskew code, and corrects the data skew between the lanes by matching the timing of the deskew code to the timing represented by the information supplied from the PHY-RX state control unit 201, as described above.

[0392] In step S136, the control code removal unit 217 removes the control code added to the packet data.

[0393] In step S137, the lane integrating unit 222 integrates the packet data supplied from the signal processing units 202-0 to 202-N.

[0394] In step S138, the packet separator 223 separates the packet data integrated by the lane integrater 222 into packet data constituting header data and packet data constituting payload data.

[0395] In step S139, the header error correction unit 232 performs an error detection calculation using the CRC code on each pair of header information and CRC code included in the header data separated by the packet separation unit 223. The header error correction unit 232 also selects and outputs error-free header information based on the error detection result of each pair and the comparison result of the data obtained by the error detection calculation.

[0396] In step S140, the Byte to Pixel conversion unit 225 performs Byte to Pixel conversion on the payload data, and outputs pixel data in units of 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits. The payload error correction unit 224 appropriately performs error correction using parity on the payload data that is the subject of the Byte to Pixel conversion.

[0397] When the processing of one line's worth of pixel data is completed, the process returns to step S103 in FIG. 38 and the subsequent processing is carried out.

[0398] As described above, data transmission between the image sensor 111 and the DSP 112 is performed using a packet format in which one line of one frame corresponds to one packet.

[0399] The packet format used for data transmission between the image sensor 111 and the DSP 112 is a format that minimizes the transmission of header information and control codes indicating packet boundaries such as Start Code and End Code, making it possible to prevent a decrease in transmission efficiency. If a packet format in which pixel data stored in the payload of one packet is less than one line is adopted, more packets would need to be transmitted to transmit the pixel data of an entire frame, and the transmission efficiency would decrease as the number of header information and control codes to be transmitted increases.

[0400] In addition, by preventing a decrease in transmission efficiency, it is possible to reduce transmission latency, thereby realizing an interface with high pixel count and high frame rate that requires the high-speed transmission of large amounts of image data.

[0401] It is possible to ensure measures against transmission errors in header information by adopting a packet format that increases the reliability / redundancy of transmission and assumes that error correction will be performed on the receiving unit 131 side. Since transmission of Frame / Line (V / H) synchronization information and the like is performed using header information, if the header information is lost due to a transmission error, this can cause a major malfunction in the system, but this can be prevented.

[0402] It is also possible to suppress increases in implementation costs and power consumption required to ensure measures against header information transmission errors. That is, the packet format used for data transmission between the image sensor 111 and the DSP 112 has a CRC code added thereto, so that the presence or absence of a header information transmission error can be detected by the DSP 112. In addition, by transmitting three pairs of header information and CRC code, if a header information transmission error occurs, the DSP 112 can correct the header information to the correct one.

[0403] If an error correction code is used as a measure against transmission errors in the header information, a circuit for calculating the error correction code must be provided in the transmitting unit 122, and a circuit for performing error correction calculations must be provided in the receiving unit 131. Since a CRC code, which is an error detection code, is added to the header information, the circuit scale and power consumption can be reduced compared to the case where a circuit for performing calculations related to error correction is provided. Furthermore, since the receiving unit 131 does not request the transmitting unit 122 to resend the header information when an error in the header information is detected, there is no need to provide a transmission path in the reverse direction for a resend request.

[0404] By increasing the redundancy and combining multiple K characters of the 8B10B code to construct a control code, the probability of an error in the control code can be reduced, making it possible to ensure protection against transmission errors in the control code using relatively simple circuits.

[0405] Specifically, the Start Code uses a combination of three types of K Characters for four symbols, but if it can detect at least a symbol other than K28.5, it can identify the Start Code in the receiver 131, and it can be said to have high resistance to transmission errors. The same applies to the End Code.

[0406] In addition, four types of K Characters are combined and used for the Pad Code, and by assigning more types of K Characters than other control codes, it is possible to increase the error resistance compared to other control codes. In other words, if one type of symbol out of the four types can be detected, the Pad Code can be identified in the receiver 131. The Pad Code is transmitted more frequently than the Start Code, End Code, etc., and therefore has a structure that can increase the error resistance.

[0407] Furthermore, by transmitting the same control code at the same time on each lane, even if a transmission error occurs on one lane and the control code is lost, the erroneous control code can be reproduced using the control code on the other lanes.

[0408] In addition, because the number of K characters is limited, each control code is composed of a minimum number of K characters. For example, for the Sync Code, Deskew Code, and Standby Code, which are transmitted repeatedly and relatively tolerant of transmission errors, a data structure is used that does not require the allocation of additional K characters.

[0409] Since the control code required for resynchronization is assigned to each packet (each line), resynchronization can be quickly achieved if bit synchronization is lost due to disturbances such as static electricity or noise. In addition, the impact of transmission errors caused by out-of-synchronization can be minimized.

[0410] Specifically, bit synchronization can be achieved by detecting transitions / edges of bit data after 8B10B conversion in the CDR realized by the clock generating unit 212 and the synchronizing unit 213. If the transmitting unit 122 continues to send data, bit synchronization can be achieved within a period assumed as the CDR lock time.

[0411] Even if symbol synchronization is lost, resynchronization can be quickly achieved by detecting a specific K character (K28.5) in the symbol synchronization unit 214. Since K28.5 is used as the start code, end code, and deskew code, it becomes possible to achieve symbol synchronization at three points during the transmission period of one packet of packet data.

[0412] In addition, by making it possible to correct data skew between lanes using the deskew code, it is also possible to synchronize the lanes.

[0413] In the link layer, by processing each packet data in parallel in groups of 16 or the like (in the example of FIG. 26, in units of 16 bytes), it is possible to reduce the circuit scale and memory amount compared to processing one packet data per clock cycle. In terms of implementation, processing packet data one by one can reduce the circuit scale, etc., by processing them collectively in a predetermined unit. Reducing the circuit scale also makes it possible to reduce power consumption.

[0414] In addition, when allocating lanes, error tolerance can be improved by allocating consecutive packet data to different lanes. Even if an error occurs across a number of consecutive packet data in a certain lane that exceeds the error correction capability of the parity, lane combination is performed in the receiver 131, and the positions of the packet data in which the error occurred are dispersed, which may enable error correction using the parity. The error correction capability of the parity is determined by the parity length.

[0415] Furthermore, by treating the side closer to the physical layer as the lower layer and performing ECC processing at a higher level than lane distribution and lane integration, it is possible to reduce the circuit scale of the transmitter 122 and the receiver 131. For example, if ECC parity is inserted into the payload after packet data is assigned to each lane in the transmitter 122, it is necessary to prepare a payload ECC insertion unit 163 for each lane, which would increase the circuit scale, but this can be prevented.

[0416] In the physical layer, parallel processing of packet data is performed by multiple circuits, but by standardizing the PHY-TX state control unit 181 and clock generation unit 182, the circuits can be simplified compared to when those circuits are provided for each lane. Also, by using a protocol that does not transmit different control codes for each lane, the circuits that process packet data for each lane can be simplified.

[0417] <Switching the number of lanes> The same control code is transmitted at the same time in each lane not only during normal data transmission, but also when, for example, the number of lanes is changed. Even when the number of lanes is changed, the state of all active lanes (lanes used for data transmission) is the same.

[0418] FIG. 41 is a diagram showing a control sequence when the number of lanes is changed.

[0419] The timing of the vertical sync signal (XVS) and horizontal sync signal (XHS) is shown on the right side of Figure 41. The pixel data of each line constituting one frame of image is transmitted in accordance with the horizontal sync signal until time t1 when the vertical sync signal is detected, and the active lanes are changed from 4 to 2 at time t1. Data transmission is performed using 4 lanes until time t1.

[0420] The status of each lane is shown vertically in the center of Figure 41. "PIX DATA" indicates that pixel data is being transmitted in the lane to which it is attached. "E", "BLK", and "S" following "PIX DATA" represent Frame End, blanking period, and Frame Start, respectively.

[0421] When the transmission of pixel data of a frame to be transmitted in one frame period up to time t1 is completed, in step S181, the image processing unit 132 instructs the receiving unit 131 to switch the number of lanes from 4 to 2. The instruction from the image processing unit 132 is received by the receiving unit 131 in step S171.

[0422] At time t1, in step S182, the image processing unit 132 requests a mode change from the imaging unit 121 of the image sensor 111. The request for mode change transmitted to the imaging unit 121 also includes information indicating that the number of lanes is to be switched from 4 to 2. Although not shown in FIG. 1 etc., a transmission path is provided between the imaging unit 121 and the image processing unit 132 for the image processing unit 132 to transmit information on setting values ​​related to imaging, such as shutter speed and gain, to the imaging unit 121. The request for mode change is also transmitted to the imaging unit 121 via this transmission path.

[0423] In step S151, the imaging unit 121 receives a mode change request from the image processing unit 132, and in step S152 instructs the transmission unit 122 to switch the number of lanes from 4 to 2. The instruction from the imaging unit 121 is received by the transmission unit 122 in step S161.

[0424] A Standby Sequence is performed between the transmitting unit 122 and the receiving unit 131, and a Standby Code is repeatedly transmitted from the transmitting unit 122 to the receiving unit 131 using Lanes 0 to 3. When the Standby Sequence ends, in step S172, the receiving unit 131 outputs a state detection result, which is received by the image processing unit 132 in step S183. Furthermore, Lanes 0 and 1 that maintain an active state go into a Low state, and Lanes 2 and 3 that end data transmission go into a High-Z state.

[0425] A training sequence is performed between the transmitter 122 and the receiver 131, and a Sync Code is repeatedly transmitted from the transmitter 122 to the receiver 131 using Lanes 0 and 1. Bit synchronization is ensured in the receiver 131, and symbol synchronization is ensured by detecting the Sync Code.

[0426] When the training sequence ends, in step S173, the receiving unit 131 notifies the image processing unit 132 that preparation is complete. The notification from the receiving unit 131 is received by the image processing unit 132 in step S184, and the series of control sequences for switching the number of lanes ends.

[0427] In this way, in the control sequence for switching the number of lanes, the standby code is transmitted during the standby sequence for lanes 2 and 3 that end data transmission so that they are in the same state as lanes 0 and 1 that will be used for subsequent data transmission. For example, it is possible to leave lanes 2 and 3 in a High-Z state without transmitting the standby code, but this would result in a state different from that of the lanes that will be used for subsequent data transmission, making the control complicated.

[0428] <Other configurations of the transmitting unit 122 and the receiving unit 131> Fig. 42 is a diagram showing another example of the configuration of the transmission unit 122 and the reception unit 131. In order to distinguish it from the transmission unit 122 shown in Fig. 17, the transmission unit shown in Fig. 42 is described as a transmission unit 122a. Similarly, in order to distinguish it from the reception unit 131 shown in Fig. 17, the transmission unit shown in Fig. 42 is described as a reception unit 131a.

[0429] Comparing the transmitting unit 122 shown in Fig. 17 with the transmitting unit 122a shown in Fig. 42, the difference is that the 8B10B symbol encoder 192 of the transmitting unit 122 is replaced by the encoder 11, and the other parts are configured in the same manner. Comparing the receiving unit 131 shown in Fig. 17 with the receiving unit 131a shown in Fig. 42, the difference is that the 10B8B symbol decoder 215 of the receiving unit 131 is replaced by the decoder 12, and the other parts are configured in the same manner. Similar parts are denoted by similar reference numerals, and their explanations will be omitted.

[0430] The encoder 11 and the decoder 12 described with reference to Fig. 1 to Fig. 13 can be applied to a transmission system 100 that transmits and receives data according to the SLVS-EC standard. Specifically, as shown in Fig. 42, the encoder 11 can be applied to a portion that encodes data included in a signal processing unit 183 in a transmission unit 122a. Also, as shown in Fig. 42, the decoder 12 can be applied to a portion that decodes data included in a signal processing unit 202 in a reception unit 131a.

[0431] When the encoder 11 and the decoder 12 are applied to the transmission system 100 that transmits and receives data according to the SLVS-EC standard, the encoding and decoding are performed as described with reference to Fig. 1 to Fig. 13, and therefore the description thereof will be omitted. Here, a more specific description will be given of the processing of the encoder 11 and the decoder 12 when transmitting and receiving data according to the SLVS-EC standard.

[0432] When transmitting and receiving data according to the SLVS-EC standard, the data is divided into an N-bit block and an M-bit block, and processing is performed with one N-bit block and one M-bit block as one processing unit, as shown in B of Fig. 2. Also, as described with reference to Fig. 33 and Fig. 34, a control code is also input to the encoder 11 (8B10B symbol encoder 192 in Fig. 17) in addition to the data to be transmitted.

[0433] Unlike the data to be transmitted (hereinafter, referred to as information transmission data as appropriate to distinguish it from the control code), the control code is a code that has a special role of controlling communications, and therefore, when encoded by the encoder 11, it is processed separately from the information transmission data.

[0434] As shown in Fig. 43, a pre-encoder 301 that performs pre-encoding to distinguish between control codes and information transmission data and to divide the data into N or M bits is added before the encoder 11. Note that, although the pre-encoder 301 and the encoder 11 are shown as separate entities in Fig. 43, it is also possible to configure the encoder 11 to include the pre-encoder 301 as part of the encoder 11.

[0435] The pre-encoder 301 is supplied with information transmission data (referred to as Data in the drawing) from the lane distribution unit 165 (FIG. 42), and is supplied with a control code (referred to as Code in the drawing) from the control code insertion unit 191. The pre-encoder 301 divides (converts) the input information transmission data or control code into N bits or M bits, and supplies the data to the encoder 11. The pre-encoder 301 also supplies to the encoder 11 a flag (hereinafter referred to as a DC flag) indicating whether the supplied data is information transmission data or a control code.

[0436] Here, reference is made again to Figure 33. For example, looking at the Start Code as a control code, the Start Code is expressed as four symbols, K28.5, K27.7, K28.2, and K27.7, which are a combination of three types of K Characters. Since one symbol is 8 bits, the Start Code is a 32-bit code. Other control codes are also similarly composed of 32 bits.

[0437] The N and M bits used when encoding can be set according to the number of bits in the control code. If the control code is 32 bits, N bits are set to 31 bits and M bits are set to 33 bits. In this way, (N+M) bits become 64 bits. Also, because a 1-bit flag is added to the N bits, one block of N bits becomes 32 bits, and because a 1-bit flag is added to the M bits, one block of M bits becomes 34 bits.

[0438] In the following description, an example will be given where N=31 and M=33, but the present technology can be applied to other numbers of bits. In the following description, (N+M)=64 bits will be used as one processing unit. Of the 64 bits in one processing unit, the first 32 bits input to the pre-encoder 301 will be referred to as the first half block, and the second 32 bits will be referred to as the second half block.

[0439] The data string that is reduced to N bits (31 bits) by pre-encoder 301 and output to encoder 11 is described as a first block, and the data string that is reduced to M bits (33 bits) and output to encoder 11 is described as a second block.

[0440] Here, the explanation will be given assuming that the pre-encoder 301 divides the input data of one processing unit into a first block of N bits (31 bits) and then into a second block of M bits (33 bits), but it may also be configured to first divide the data into M-bit blocks and then into N-bit blocks.

[0441] The 64-bit data of the first half block and the second half block are supplied to the pre-encoder 301. Since the first half block and the second half block are information transmission data or control codes, there are the following four combinations. Case 1: The first half block is information transmission data + the second half block is information transmission data Case 2: The first half of the block is information transmission data + the second half of the block is control code Case 3: The first half of the block is control code and the second half is information transmission data Case 4: First half block is control code + second half block is control code The processing of the pre-encoder 301 and the encoder 11 will be explained for each of the cases 1 to 4.

[0442] <About encoding in case 1> 44, a further explanation will be given on pre-encoding and encoding in case 1. Case 1 is a case where all 64-bit data input to the pre-encoder 301 is signaling data, and is divided into a first block of signaling data and a second block of signaling data.

[0443] That is, in case 1, the pre-encoder 301 receives the first signaling data [31:0] as the first half block of 32 bits and the second signaling data [31:0] as the second half block of 32 bits.

[0444] The pre-encoder 301 takes the 31-bit signaling data [31:1] of the input 32-bit first signaling data [31:0] of the first half block as a first block, and outputs it to the encoder 11.

[0445] The pre-encoder 301 assigns the last bit of the input 32-bit first signaling data [31:0], that is, the first signaling data [0], to the second block, and outputs 33 bits, which are the latter half block of 32-bit second signaling data [31:0], to the encoder 11 as the second block.

[0446] In other words, the pre-encoder 301 divides the input 64-bit data string into two parts: first information-transmitting data [31:1] constituting the first 31 bits of the input 64 bits, and 33 bits consisting of the remaining first information-transmitting data [0] and second information-transmitting data [31:0] constituting the last 32 bits of the input 64 bits.

[0447] When the pre-encoder 301 outputs the first block, which is signaling data, to the encoder 11, it also supplies to the encoder 11 a DC flag indicating that the first block is signaling data.

[0448] When the supplied DC flag indicates that the data is information transmission data, the encoder 11 performs encoding on the supplied first block of data by controlling the running disparity RD and run length RL as described with reference to Fig. 1 to Fig. 13. That is, the encoder 11 executes processing to invert the data of the first block and add a flag indicating that the data has been inverted, or to not invert the data and add a flag indicating that the data has not been inverted, using the running disparity RD and run length RL.

[0449] Since the encoder 11 processes the first block of 31 bits and adds a 1-bit flag, the data output from the encoder 11 is 32-bit data.

[0450] Similarly, when the pre-encoder 301 outputs the second block, which is signaling data, to the encoder 11, it also supplies to the encoder 11 a DC flag indicating that the second block is signaling data.

[0451] When the supplied DC flag indicates that the data is information transmission data, the encoder 11 performs encoding on the supplied second block data by controlling the running disparity RD and run length RL as described with reference to Fig. 1 to Fig. 13. That is, the encoder 11 executes processing to invert the data of the second block and add a flag indicating that the data has been inverted, or to not invert the data and add a flag indicating that the data has not been inverted, using the running disparity RD and run length RL.

[0452] Since the encoder 11 processes the second block of 33 bits and adds a 1-bit flag, the data output from the encoder 11 is 34-bit data.

[0453] <About encoding in case 2> 45, a further explanation will be given on pre-encoding and encoding in case 2. Case 2 is a case where the first half block of the 64-bit data input to the pre-encoder 301 is signaling data and the second half block is a control code, and the data is divided into a first block of signaling data and a second block of control code.

[0454] That is, in case 2, the pre-encoder 301 receives the first signaling data [31:0] as the first half block of 32 bits and the second control code [31:0] as the second half block of 32 bits.

[0455] The pre-encoder 301 takes the 31-bit signaling data [31:1] of the input 32-bit first signaling data [31:0] of the first half block as a first block, and outputs it to the encoder 11.

[0456] The pre-encoder 301 assigns the first signaling data [0], which is the last bit of the input 32-bit first signaling data [31:0], to the second block. The pre-encoder 301 also adds the second conversion control code "30:0" obtained by converting the 32-bit second control code [31:0] of the latter block to 31 bits, to the end of the first signaling data [0] to make a 32-bit data string, and further adds one bit of "0" or "1" data to generate a 33-bit second block and outputs it to the encoder 11.

[0457] In other words, the pre-encoder 301 divides the input 64-bit data string into two parts: first signaling data [31:1] constituting the first 31 bits of the input 64 bits, and a second block of 33 bits. The second block of 33 bits is a data string composed of first signaling data [0], which is the remaining bit of the first signaling data [31:0], a second converted control code [30:0] obtained by converting the second control code [31:0] constituting the latter 32 bits of the input 64 bits into a 31-bit control code, and a bit obtained by inverting the first signaling data [0].

[0458] The running disparity RD of the second block is set to 0 by adding a bit of the first information transmitting data [0] and an inverted bit of the first information transmitting data [0] before and after the second block.

[0459] Furthermore, the input 32-bit control code is converted to a 31-bit control code. The input 32-bit control code is, for example, a control code corresponding to the above-mentioned 8B10B encoding, and has, for example, the symbol configuration described with reference to Fig. 33. The input 32-bit control code and the converted 31-bit control code will be described with reference to Fig. 46.

[0460] In the following description, in order to distinguish between the 8B10B coding and the coding described with reference to FIGS. 1 to 13, the coding described with reference to FIGS. 1 to 13 will be referred to as inverted coding.

[0461] As described with reference to FIG. 33, the control codes in 8B10B encoding (referred to as 8b codes in FIG. 46) include Idle Code, Start Code, End Code, Pad Code, Sync Code, Deskew Code, and Standby Code.

[0462] The idle code is represented by the D character D00.0 (00000000), which is an 8B10B code. In 8b code, the idle code is a data string of 32 bits, all of which are "0". The running disparity RD of the idle code is "-32". Inversion coding of the idle code (shown as INV in the diagram) means that the 1st symbol and 2nd symbol are all "0", and the 3rd symbol and 4th symbol are all "1" except for the last bit.

[0463] In inversion coding, the last bit of the fourth symbol in the 8b code is not used, resulting in a 31-bit control code. In the case of a control code, the encoder 11 assigns a flag of "1". A flag of "1" indicates that the data has been inverted, but even in the case of a control code, the flag is set to "1" to indicate that the data is a control code. In the case of a control code, the encoder 11 sets the flag to "1", but does not invert the data.

[0464] In the case of a control code, the flag is set to "1", so the running disparity RD of the idle code in the inversion coding including this flag is 0. As will be described below, the control code in the inversion coding is set so that the running disparity RD is 0 in the 32 bits including the flag.

[0465] The data string described in the "inversion prohibited" section of the Idle Code in Fig. 46 is a data string obtained by inverting the Idle Code in inversion coding. That is, the 1st symbol and the 2nd symbol are all "1", and the 3rd symbol and the 4th symbol are all "0" except for the last bit. When such a data string is input to the pre-encoder 301 (or the encoder 11) as information transmission data, set as data to be inverted, and inverted, it becomes the same data string as the Idle Code.

[0466] A data string that becomes the same as the control code when inverted is set as an inversion-prohibited data string. Therefore, when such an inversion-prohibited data string is input, the encoder 11 sets the flag to "0" and sets it as a non-inversion data string. This data string set as inversion-prohibited is also a data string whose running disparity RD, including the flag "0", is "0".

[0467] In the 8b code, the start code is represented by four symbols, K28.5, K27.7, K28.2, and K27.7, which are combinations of three types of K characters. The running disparity RD of the start code in the 8b code is "14." In the inversion coding, the first symbol of the start code is "00111100," the second symbol is "11111010," the third symbol is "11000011," and the fourth symbol is "0000010."

[0468] The start code in the inversion coding is also a 31-bit control code because the last bit of the fourth symbol in the 8b code is not used. Also, because the start code is a control code, the encoder 11 assigns a flag of "1." Therefore, the running disparity RD of the start code in the inversion coding including the flag is 0.

[0469] A data string that prohibits inversion of the Start Code is also set, and a data string that becomes the same as the Start Code when inverted is set as a data string that does not invert. When a data string that prohibits inversion of the Start Code is input to the encoder 11 as information transmission data, a flag of "0" is set and the data string is processed as a non-inverted data string. This data string that is set to prohibit inversion is also a data string in which the running disparity RD, including the flag "0", is "0".

[0470] In the 8b code, the end code is represented by four symbols, K28.5, K29.7, K30.7, and K29.7, which are combinations of three types of K characters. The running disparity RD of the end code in the 8b code is "20." In the inversion coding, the first symbol of the end code is "00111100," the second symbol is "11111100," the third symbol is "11000011," and the fourth symbol is "0000001."

[0471] The end code in the inversion coding is also a 31-bit control code because the last bit of the fourth symbol in the 8b code is not used. Since the end code is also a control code, the encoder 11 adds a flag of "1." Therefore, the running disparity RD of the end code in the inversion coding including the flag is 0.

[0472] A data string that prohibits inversion of the End Code is also set, and a data string that becomes the same as the End Code when inverted is set as a data string that does not invert. When a data string that prohibits inversion of the End Code is input to the encoder 11 as information transmission data, a flag of "0" is set and the data string is processed as a non-inverted data string. This data string that is set to prohibit inversion is also a data string in which the running disparity RD, including the flag "0", is "0".

[0473] In the 8b code, the Pad Code is expressed by four symbols, K23.7, K28.4, K28.6, and K28.3, which are combinations of three types of K Characters. The running disparity RD of the Pad Code in the 8b code is "10". The first symbol of the Pad Code in inversion coding is "01110111", the second symbol is "10011100", the third symbol is "10001000", and the fourth symbol is "0110001".

[0474] The Pad Code in the inversion coding is also a 31-bit control code because the last bit of the fourth symbol in the 8b code is not used. Since the Pad Code is also a control code, the encoder 11 assigns a flag of "1." Therefore, the running disparity RD of the Pad Code in the inversion coding including the flag is 0.

[0475] In addition, a data string that prohibits inversion of the Pad Code is also set, and a data string that becomes the same as the Pad Code when inverted is set as a data string that does not invert. When the data string that prohibits inversion of the Pad Code is input to the encoder 11 as information transmission data, the flag "0" is set and the data string is processed as a non-inverted data string. This data string that is set to prohibit inversion is also a data string in which the running disparity RD including the flag "0" is "0".

[0476] In the 8b code, the Sync Code is expressed as four symbols consisting of a combination of the K character K28.5 and the D character D10.5. In Fig. 33, it was explained that Any** means that any type of symbol may be used, but Fig. 46 specifically shows an example in which the D character D10.5 is used.

[0477] The running disparity RD of the Sync Code in the 8b code is “2.” The first symbol of the Sync Code in the inversion coding is “00111100,” the second symbol is “10101010,” the third symbol is “11000011,” and the fourth symbol is “0101010.”

[0478] The Sync Code in the inversion coding is also a 31-bit control code because the last bit of the fourth symbol in the 8b code is not used. Since the Sync Code is also a control code, the encoder 11 assigns a flag of "1." Therefore, the running disparity RD of the Sync Code in the inversion coding including the flag is 0.

[0479] A data string that prohibits inversion of the Sync Code is also set, and a data string that becomes the same as the Sync Code when inverted is set as a data string that does not invert. When a data string that prohibits inversion of the Sync Code is input to the encoder 11 as information transmission data, the flag is set to "0" and the data string is processed as a non-inverted data string. This data string that is set to prohibit inversion is also a data string in which the running disparity RD, including the flag "0", is "0".

[0480] In the 8b code, Deskew Code is expressed as 4 symbols consisting of a combination of K character K28.5 and D character D00.3. In Fig. 33, Any** was used to indicate that any type of symbol may be used, but Fig. 46 specifically shows an example in which D character D00.3 is used.

[0481] The running disparity RD of the Deskew Code in the 8b code is "-10." The first symbol of the Deskew Code in the inversion coding is "00111100," the second symbol is "01100000," the third symbol is "11000011," and the fourth symbol is "1001111."

[0482] The deskew code in the inversion coding is also a 31-bit control code because the last bit of the fourth symbol in the 8b code is not used. Since the deskew code is also a control code, the encoder 11 assigns a flag of "1." Therefore, the running disparity RD of the deskew code in the inversion coding including the flag is 0.

[0483] In addition, a data string that prohibits inversion of the Deskew Code is also set, and a data string that becomes the same as the Deskew Code when inverted is set as a data string that does not invert. When a data string that prohibits inversion of the Deskew Code is input to the encoder 11 as information transmission data, a flag of "0" is set and the data string is processed as a non-inverted data string. This data string that is set to prohibit inversion is also a data string in which the running disparity RD, including the flag "0", is "0".

[0484] In the 8b code, the Standby Code is represented by four symbols consisting of a combination of the K character K28.5 and the D character D03.0. In Fig. 33, it is described as Any**, which indicates that any type of symbol may be used, but Fig. 46 specifically shows an example in which the D character D03.0 is used.

[0485] The running disparity RD of the Standby Code in the 8b code is −10. The first symbol of the Standby Code in the inversion coding is “00111100”, the second symbol is “00000010”, the third symbol is “11000011”, and the fourth symbol is “111110”.

[0486] The Standby Code in the inversion coding is also a 31-bit control code because the last bit of the fourth symbol in the 8b code is not used. Since the Standby Code is also a control code, the encoder 11 assigns a flag of "1". Therefore, the running disparity RD of the Standby Code in the inversion coding including the flag is 0.

[0487] A data string that prohibits inversion of the Standby Code is also set, and a data string that becomes the same as the Standby Code when inverted is set as a data string that does not invert. When the data string that prohibits inversion of the Standby Code is input to the encoder 11 as information transmission data, the flag "0" is set and the data string is processed as a non-inverted data string. This data string that is set to prohibit inversion is also a data string in which the running disparity RD, including the flag "0", is "0".

[0488] When such a control code is set, the pre-encoder 301 converts the input 8b code into a code of inversion coding. When performing this conversion, a correspondence table between the control code in the 8b code and the control code in the inversion coding shown in Fig. 46 may be stored and appropriately referred to for conversion. Here, the explanation will be continued assuming that the conversion process is included, but the control code inserting unit 191 may insert the control code in the inversion coding, and the pre-encoder 301 may be configured not to perform conversion.

[0489] Returning to the explanation with reference to FIG. 45, when the pre-encoder 301 outputs the first block, which is signaling data, to the encoder 11, it also supplies to the encoder 11 a DC flag indicating that the first block is signaling data.

[0490] When the supplied DC flag indicates that the data is information transmission data, the encoder 11 performs encoding on the supplied first block of data by controlling the running disparity RD and run length RL as described with reference to Fig. 1 to Fig. 13. That is, the encoder 11 executes processing to invert the data of the first block and add a flag indicating that the data has been inverted, or to not invert the data and add a flag indicating that the data has not been inverted, using the running disparity RD and run length RL.

[0491] If the information transmitting data is a data sequence that prohibits inversion, the pre-encoder 301 may determine whether or not the data sequence is such that inversion is prohibited, output the determination result as a DC flag, and the encoder 11 may refer to the DC flag for processing. Alternatively, if the DC flag indicates that the information transmitting data is information transmitting data, the encoder 11 may determine whether or not the information transmitting data is a data sequence that prohibits inversion, and execute processing according to the determination result.

[0492] Since the encoder 11 processes the first block of 31 bits and adds a 1-bit flag, the data output from the encoder 11 is 32-bit data.

[0493] Similarly, when the pre-encoder 301 outputs the second block including the second conversion control code to the encoder 11, the pre-encoder 301 also supplies to the encoder 11 a DC flag indicating that the second block is a control code.

[0494] If the supplied DC flag indicates that it is a control code, the encoder 11 sets the flag to "1", adds it to the supplied 33-bit second block, and outputs it as 34-bit data.

[0495] <About encoding in case 3> 47, a further explanation will be given on pre-encoding and encoding in case 3. Case 3 is a case where the first half block of the 64-bit data input to the pre-encoder 301 is a control code and the second half block is information transmission data, and the data is divided into a first block of control code and a second block of information transmission code.

[0496] That is, in case 3, the pre-encoder 301 receives the first control code [31:0] as the first half block of 32 bits and the second signaling data [31:0] as the second half block of 32 bits.

[0497] The pre-encoder 301 converts the input 32-bit first control code [31:0] of the first half block into a 31-bit first conversion control code [30:0], for example by referring to the table shown in FIG. 46, and outputs the first conversion control code [30:0] as the first block to the encoder 11.

[0498] The pre-encoder 301 allocates the input second signaling data [31:0] of the latter block of 32 bits to the second block. Since the second block is 33 bits, one bit is added to the beginning of the second block. This added bit can be the value of A of the fourth symbol of the control code in the 8b code. That is, the last bit of the first control code of the former block is assigned to the beginning bit of the second block of the second block.

[0499] For example, in the case of the Idle Code, since the value of A in the fourth symbol of the control code in the 8b code is "0", the first bit of the second block is set to "0".

[0500] The bit inserted at the beginning of the second block, in this case the first control code [0], is treated as dummy data by the decoder 12.

[0501] The pre-encoder 301 divides the input 64-bit data string into two parts: a first control code [31:0] constituting the first 31 bits of the input 64 bits, and a second block of 33 bits. The second block of 33 bits is a 33-bit data string obtained by adding the remaining one bit of the first control code [31:0], the first control code [0], to second information transmission data [31:0] constituting the latter 32 bits of the input 64 bits.

[0502] When the pre-encoder 301 outputs the first block, which is a control code, to the encoder 11, the pre-encoder 301 also supplies to the encoder 11 a DC flag indicating that the first block is a control code.

[0503] If the supplied DC flag indicates that it is a control code, the encoder 11 sets the flag to "1", adds it to the supplied first block of 31 bits, and outputs it as 32-bit data.

[0504] When the pre-encoder 301 outputs the second block, which is signaling data, to the encoder 11, it also supplies to the encoder 11 a DC flag indicating that the second block is signaling data.

[0505] When the supplied DC flag indicates that the data is information transmission data, the encoder 11 performs encoding on the supplied second block data by controlling the running disparity RD and run length RL as described with reference to Fig. 1 to Fig. 13. That is, the encoder 11 executes processing to invert the data of the second block and add a flag indicating that the data has been inverted, or to not invert the data and add a flag indicating that the data has not been inverted, using the running disparity RD and run length RL.

[0506] <About encoding in case 4> 48, a further explanation will be given on pre-encoding and encoding in case 4. Case 4 is a case where all of the 64-bit data input to the pre-encoder 301 is control code, and the data is divided into a first block of control code and a second block of control code.

[0507] That is, in case 4, the pre-encoder 301 receives the first control code [31:0] as the first half block of 32 bits and the second control code [31:0] as the second half block of 32 bits.

[0508] The pre-encoder 301 converts the input 32-bit first control code [31:0] of the first half block into a 31-bit first conversion control code [30:0], for example by referring to the table shown in FIG. 46, and outputs the first conversion control code [30:0] as the first block to the encoder 11.

[0509] The pre-encoder 301 converts the input 32-bit second control code [31:0] of the latter half block into a 31-bit second conversion control code [30:0] by referring to the table shown in Fig. 46, for example, and allocates the second conversion control code [30:0] to the second block. Since the second block is 33 bits, a total of two bits are added, one bit at the beginning of the second block and one bit at the end.

[0510] The one bit added to the beginning can be the value of A in the fourth symbol of the control code in the 8b code. That is, the last bit of the first control code in the first half block (first control code [0]) is assigned to the first bit of the second block. For example, in the case of the Idle Code, the value of A in the fourth symbol of the control code in the 8b code is "0", so the first bit of the second block is set to "0".

[0511] The last bit added is the inverted value of the first bit added. That is, since the first bit added is the first control code [0], the inverted value of this first control code [0] is the last bit added. For example, in the case of the Idle Code, the value of A in the fourth symbol of the control code in the 8b code is "0", and since this value is added to the beginning, the last bit of the second block is set to "1".

[0512] In this way, two bits of data are added to the second block, and the running disparity RD can be set to 0 by making the inverted value of one bit the same as the other bit.

[0513] The bit placed at the beginning and the end of the second block are treated as dummy data by the decoder 12.

[0514] The pre-encoder 301 divides the input 64-bit data string into two blocks by converting the first control code [31:0] constituting the first 32 bits of the input 64 bits into a first conversion control code [30:0] and converting the second control code [31:0] constituting the latter 32 bits into a second conversion control code [30:0]. The pre-encoder 301 also adds two bits to the second conversion control code [30:0] to make it a 33-bit data string and generate the second block.

[0515] When the pre-encoder 301 outputs the first block, which is a control code, to the encoder 11, it also supplies a DC flag indicating that the first block is a control code to the encoder 11. If the supplied DC flag indicates that the first block is a control code, the encoder 11 sets the flag to "1", adds it to the supplied 31-bit first block, and outputs it as 32-bit data.

[0516] Similarly, when the pre-encoder 301 outputs the second block, which is a control code, to the encoder 11, it also supplies a DC flag indicating that the second block is a control code to the encoder 11. If the supplied DC flag indicates that the second block is a control code, the encoder 11 sets the flag to "1", adds it to the supplied 33-bit second block, and outputs it as 34-bit data.

[0517] In this way, the 64-bit data input by the pre-encoder 301 is divided into 31-bit data and 33-bit data. In the above description, the control code is converted by referring to the table shown in Fig. 46, but when a control code (the above-mentioned 8b code) used in 8B10B encoding is input and the 8b code is converted, the conversion may be performed as described with reference to Figs. 49 and 50. In other words, as described with reference to Figs. 49 and 50, the conversion control code has a rule and can be generated from the 8b code based on the rule.

[0518] Fig. 49 is a diagram for explaining a conversion method when the first half of the 64-bit data input to the pre-encoder 301 is a control code. That is, the first half block of the input 64 bits described with reference to Figs. 47 and 48 is the first control code [31:0], and the first control code [31:0] is converted to the first converted control code [30:0].

[0519] In FIG. 49, the first control code of 8b code is shown at the top. The first control code [31:0] is 32-bit data. Of the first control code [31:0], the 14 bits of the first control code [30:17] are used as they are as the 14 bits 16 to 29 of the first conversion control code. That is, the first control code [30:17] is used as the first conversion control code [29:16]. This first change control code [30:17] is used as data for distinguishing the control code.

[0520] The first bit of the first conversion control code, in other words, the bit before the first conversion control code[29:16], the first conversion control code

[30] , is fixed at “0.” In addition, the first conversion control code

[15] and the first conversion control code

[14] of the first conversion control code, in other words, the two bits following the first conversion control code[29:16], are fixed at “0” and “1.”

[0521] The 14 bits of the first conversion control code [13:0] are set to the inverted value of the 14 bits of the first conversion control code [29:16]. In other words, the 14 bits of the first conversion control code [13:0] are set to the inverted data of the 14 bits of the first control code [30:17] of the input 8b code.

[0522] In this way, the conversion control code is generated from the input 8b code. In this way, the first conversion control code [30:0] is generated using 14 bits of the first control code [30:17] of the input first control code [31:0].

[0523] Set the bit that becomes the first conversion control code

[30] to 0. The 14 bits of the first control code [30:17] of the first control code [30:0] are defined as the first conversion control code [29:16]. The first conversion control code [15:14] is set to 0, 1 as the two bits following the first conversion control code [29:16]. The 14 bits obtained by inverting the 14 bits of the first control code [30:17] are set as the first converted control code [13:0]. By carrying out such processing, the first conversion control code [30:0] is generated.

[0524] Since the first conversion control code [29:16] and the first conversion control code [13:0] have an inverted data relationship, the running disparity RD for this portion is 0. In addition, the first conversion control code contains 0, 0, and 1 as fixed values, and the flag added to the control code is 1, so the running disparity RD for this portion is also 0. Therefore, the running disparity RD for the generated first conversion control code [30:0], including the flag, is always 0.

[0525] Next, a conversion method when the latter half of the 64-bit data input to the pre-encoder 301 is a control code will be described with reference to Fig. 50. That is, the latter half of the input 64-bit data described with reference to Figs. 45 and 48 is the second control code [31:0], and the second control code [31:0] is converted to the second conversion control code [30:0].

[0526] The basic conversion is the same as that shown in Figure 49, but the case shown in Figure 49 is a conversion to 31 bits, while the case shown in Figure 50 is a conversion to 33 bits. For this reason, a process is added to add two more bits. These two bits are the bit corresponding to the second conversion control code

[32] and the bit corresponding to the second conversion control code [0].

[0527] That is, in the case shown in Figure 50, the 14 bits of the second control code [30:17] of the second control code [31:0] are used as they are as the 14 bits 16 to 29 of the second conversion control code. In this case, the second control code [30:17] is used as the second conversion control code [30:17]. This second change control code [30:17] is used as data for distinguishing the control code.

[0528] The first bit of the second conversion control code, in other words, the bit before the second conversion control code[30:17],

[31] , is fixed at “0.” In addition, the second conversion control code

[16] and the second conversion control code

[15] of the second conversion control code, in other words, the two bits following the second conversion control code[30:17], are fixed at “0” and “1.”

[0529] The 14 bits of the second conversion control code [14:1] are set to the inverted value of the 14 bits of the second conversion control code [29:16]. In other words, the 14 bits of the second conversion control code [14:1] are set to the inverted data of the 14 bits of the second control code [30:17] of the input 8b code.

[0530] Furthermore, a bit corresponding to the second conversion control code

[32] is added before the second conversion control code [31:1], and a bit corresponding to the second conversion control code [0] is added before the second conversion control code [31:1].

[0531] The second conversion control code

[32] is assigned the last bit of the first half block of the input 64 bits, for example, the first signaling data [0] of the first signaling data [31:0] in the example shown in Fig. 45. Also, the inverted value of the second conversion control code

[32] is assigned to the second conversion control code [0].

[0532] In this way, the conversion control code is generated from the input 8b code. In this way, the second conversion control code [32:0] is generated using 14 bits of the second control code [30:17] of the input second control code [31:0].

[0533] The last bit of the previous block is assigned as the second conversion control code

[32] . Set bit

[31] to 0 to become the second conversion control code. The 14 bits of the second control code [30:17] are defined as the second conversion control code [30:17]. The second conversion control code [16:15] is set to 0,1 as the two bits following the second conversion control code [30:17]. The 14 bits obtained by inverting the 14 bits of the second control code [30:17] are set as the second conversion control code [14:1]. This bit is set to the second conversion control code [0], and is set to the inverted value of the second conversion control code

[32] . By carrying out such processing, the second conversion control code [32:0] is generated.

[0534] Since the second conversion control code [30:17] and the second conversion control code [14:1] have an inverted data relationship, the running disparity RD for this part is 0. Also, since the second conversion control code

[32] and the second conversion control code [0] have an inverted data relationship, the running disparity RD for this part is 0. Furthermore, the fixed values ​​contained in the second conversion control code are 0, 0, 1, and the flag added to the control code is 1, so the running disparity RD for this part is also 0. Therefore, the running disparity RD including the flag for the generated second conversion control code [32:0] is always 0.

[0535] As described with reference to FIGS. 49 and 50, the input control code may be converted to generate the control code used in the inversion encoding.

[0536] Even when the control code and information transmission data are encoded in this way, the operations of the transmitting unit 122a and the receiving unit 131a shown in Fig. 42 are based on the flowcharts shown in Fig. 38 to Fig. 40. Here, to avoid duplication of explanations, only different processing will be explained.

[0537] As part of the data transmission process of the transmission unit 122a, in step S117 (FIG. 39), the control code insertion unit 191 adds a control code to the packet data supplied from the lane distribution unit 165. This added control code is a code obtained by converting a control code in 8B10B encoding into a control code in inversion encoding.

[0538] Alternatively, instead of performing such conversion in the control code insertion unit 191, it may be configured so that it is performed in the encoder 11 (pre-encoder 301 included in the encoder 11).

[0539] In step S118, the encoder 11 performs inverse encoding on the packet data to which the control code has been added. The process in the encoder 11 will be described later with reference to FIG.

[0540] As part of the data reception process of the receiver 131a, in step S133 (FIG. 40), the symbol synchronization unit 214 performs symbol synchronization by detecting a control code included in the packet data, etc. The control code used at this time is a control code in inversion coding.

[0541] When the symbol synchronization unit 244 performs symbol synchronization using a control code in 8B10B encoding, the control code that is the data after being decoded by the decoder 12 and converted into a control code in 8B10B encoding may be used.

[0542] In step S134, the decoder 12 decodes the reverse-coded encoded data. The process in the decoder 12 will be described later with reference to FIG.

[0543] <Encoder processing including control codes> The process of the encoder 11 when encoding control codes having a special role and information-carrying data will now be described with reference to the flow chart of FIG.

[0544] In step S201, the encoder 11 inputs data and a DC flag from the pre-encoder 301. In step S202, the encoder 11 determines whether the input data is a control code by referring to the DC flag. If it is determined in step S202 that the input data is a control code, the process proceeds to step S203.

[0545] In step S203, the flag is set to 1. As described above, the control code is set as data that is not inverted and has the flag set to 1. Since the control code has been changed to an N- or M-bit control code by the pre-encoder 301 in the encoder 11, the flag is added to the control code and the control code is output.

[0546] In step S204, the running disparity RD and run length RL of the output control code are calculated. In step S205, the generated data string is transmitted to the receiving side. Steps S204 and S205 are the same processes as steps S22 and S23 (FIG. 9).

[0547] On the other hand, if it is determined in step S202 that the input data is not a control code, the process proceeds to step S206. In step S206, it is determined whether the input information transmission data is a data string that is prohibited from being inverted. As described with reference to Fig. 46, a data string that is prohibited from being inverted is a data string that becomes the same data string as a control code when inverted.

[0548] If it is determined in step S206 that the input data is a data string that is prohibited from being inverted, the process proceeds to step S207. In step S207, the flag is set to 0. Since the pre-encoder 301 has changed the data to N- or M-bit information transmission data in the encoder 11, the flag is added to the information transmission data and the data is output. Thereafter, the processes of steps S204 and S205 are executed, but the processes of steps S204 and S205 have already been described, and therefore will not be described here.

[0549] On the other hand, if it is determined in step S206 that the input information-transmitting data is not a data sequence that is prohibited from being inverted, the process proceeds to step S208. In step S208, an inversion coding process is performed on the information-transmitting data. In addition, the processes of steps S204 and S205 are performed on the information-transmitting data that has been inverted.

[0550] The inversion encoding process executed in step S208 and the processes executed in steps S204 and S205 correspond to the processes in steps S12 to S23 in the flowchart shown in FIG. 9, and therefore a description thereof will be omitted since it has already been given.

[0551] In this way, when handling codes having special data strings such as control codes in inversion coding, the process includes a step of preventing the control codes from being inverted and adding a flag indicating that the code is a control code.

[0552] <Decoder processing including control codes> The operation of the decoder 12 when decoding control codes having a special role and signalling data will now be described with reference to the flow chart of FIG.

[0553] In step S231, the decoder 12 determines whether or not the flag is 1. If it is determined in step S231 that the flag is 1, the process proceeds to step S232.

[0554] In step S232, it is determined whether the data string to be processed is a control code. If it is determined in step S232 that the data string to be processed is a control code, the process proceeds to step S233.

[0555] In step S233, the data information is set to information indicating that it is a control code. The data information is information that is referred to when processing the output from the decoder 12 in the processing at the later stage of the decoder 12, and is information (flag) indicating whether it is a control code or not.

[0556] In step S234, the decoder 12 outputs the data information and the control code.

[0557] On the other hand, if it is determined in step S232 that the data is not a control code, the process proceeds to step S235. The process proceeds to step S235 when the flag is 1 and the data is not a control code. That is, when the process proceeds to step S235, the data being processed is the inverted information transmission data.

[0558] In step S235, the data information is set to information indicating that it is signaling data. In step S236, the data string to be processed is inverted. Then, in step S237, the data information and the signaling data are output from the decoder 12.

[0559] On the other hand, if it is determined in step S231 that the flag is 0, the process proceeds to step S238. Step S238 is reached when the data being processed is non-inverted information transmission data.

[0560] In step S238, the data information is set to information indicating that it is information transmission data. In step S239, the data string to be processed is output as is without being inverted. Then, in step S237, the data information and the information transmission data are output from the decoder 12.

[0561] In this way, when decoding corresponding to inversion coding, when dealing with codes having special data strings such as control codes, the control codes are not inverted, and data strings to which flags indicating that they are control codes are added are processed by referring to the flags.

[0562] <Other encoding and decoding processes> As described above, the control code is prevented from being inverted, and a flag of 1 is added to it. Furthermore, among data other than the control code (information transmission data), data that becomes the same data string as the control code when inverted is treated as a data string that is prohibited from being inverted, and is controlled so as not to be inverted, and a flag of 0 is added to it.

[0563] Furthermore, when information transmission data is inverted, a flag of 1 is added. The flag of 1 is added in the same way as when it indicates that it is a control code. If an error occurs in the inverted information transmission data, resulting in the same data string as the control code, the decoding side will process it as a control code because the flag is 1 and the data is the same as the control code.

[0564] Furthermore, if an error occurs in the control code, the decoder may treat it as inverted information transmission data and decode it because the flag is set to 1. Therefore, we will explain encoding and decoding that allows the control code to be treated as such even when an error occurs in the control code.

[0565] Assume that a one-bit error has occurred in the control code, as shown in Figure 53. The code shown in the upper part of Figure 53 is the Pad Code in the inversion coding shown in Figure 46, and shows a code in which a flag of 1 has been added to the first bit of the Pad Code. If no error has occurred and the code is encoded and sent to the decoding side, the code shown in the upper part of Figure 53 is exchanged.

[0566] The case where, for example, a 1-bit error occurs in the Pad Code is shown in the lower part of Fig. 53. In the Pad Code represented as data 1 with a 1-bit difference, an error occurs in the last data, and data that should be 1 in a normal code becomes data 0. When this type of data with a 1-bit difference, 1, is processed on the decoder 12 side, it is processed as inverted information transmission data because the flag is 1.

[0567] Similarly, an error occurs in the penultimate data of the Pad Code, which is represented as data 2 with a 1-bit difference, and the data that should be 0 in a normal code becomes 1. When this type of data 2 with a 1-bit difference is processed by the decoder 12, it is processed as inverted information transmission data because the flag is 1.

[0568] Furthermore, in the Pad Code represented as data 31 with a 1-bit difference, an error occurs in the 31st data from the end, and data that should be 0 in a normal code becomes 1. When such data 31 with a 1-bit difference is processed by the decoder 12, it is processed as inverted information transmission data because the flag is 1.

[0569] In this way, if a one-bit error occurs in the control code, it may be decoded as information transmission data. Therefore, the decoding is made while taking into consideration the occurrence of a one-bit error. Specifically, the decoder 12 handles data 1 to 31 that differ by one bit as a control code. In this way, data 1 to 31 that differ by one bit are appropriately described as expanded control codes.

[0570] Since there are 31 patterns of data 1 to 31 that differ by 1 bit, the decoder 12 processes these 31 patterns as well as the control code. Therefore, including the control code in which no error occurs, 32 patterns will be treated as the control code. Also, here, the Pad Code has been described as an example of the control code, but as described with reference to Fig. 46, there are other control codes besides the Pad Code, such as the Idle Code, Start Code, End Code, Sync Code, Deskew Code, and Standby Code. For each of these control codes, there are 32 patterns of data strings that are treated as the control code.

[0571] In order to enable the decoder 12 to handle the data 1 to 31 with a 1-bit difference as a control code, the encoding side performs control not to invert information transmission data that corresponds to any of the data 1 to 31 with a 1-bit difference after inversion. That is, the encoding side performs processing to expand the range of data strings that are prohibited from being inverted to include not only data strings with inverted control codes but also expanded control codes.

[0572] When information transmission data is inverted and a flag of 1 is added, and the inverted data sequence has the same pattern as any one of the data sequences 1 to 31 that differ by 1 bit, the data is treated as a control code on the decoder 12 side. To prevent this from happening, information transmission data whose inverted data sequence has the same pattern as any one of the data sequences 1 to 31 that differ by 1 bit is prohibited from being inverted, and a flag of 0 is added.

[0573] Please refer to A of Fig. 54. The data (information transmission data) before inversion is shown in the upper part of A of Fig. 54. The information transmission data shown in the upper part of A of Fig. 54 is the data 1000100001100011011101111001111. This information transmission data is not a control code.

[0574] When the signaling data shown in the upper part of A in Fig. 54 is inverted, it becomes the data shown in the lower part of A in Fig. 54. The inverted signaling data becomes 0111011110011100100010000110000. This inverted signaling data is the same data string as data 1 that differs by 1 bit, out of data 1 to 31 that differ by 1 bit shown in Fig. 53.

[0575] Moreover, the data shown in the lower part of A in Fig. 54 is inverted data, so a flag of 1 is added. Therefore, when such inversion coding is performed, the flag is 1 on the decoder 12 side, and since it is the same data string as data 1 with a difference of 1 bit, it is treated as a control code. However, since the data shown in the lower part of A in Fig. 54 is inverted information transmission data and is not a control code, if it is treated as a control code on the decoder 12 side, it will be erroneously decoded.

[0576] For this reason, the encoder 11 processes the information transmission data shown in the upper part of A in Fig. 54 as data that is not inverted (a data string that is prohibited from being inverted). That is, when the encoder 11 receives the information transmission data shown in the upper part of A in Fig. 54, it treats it as a data string that is prohibited from being inverted, and executes a process of adding a flag of 0.

[0577] By encoding in this manner, the information transmission data shown in the upper part of A in Figure 54 is not inverted and a flag of 0 is added, so that the decoder 12 decodes it as non-inverted information transmission data.

[0578] That is, the encoder 11 treats information transmission data that becomes a data string that differs from the control code by only one bit when inverted as a data string that is prohibited from being inverted, and performs encoding by adding a flag of 0. As described with reference to Fig. 54, there are 31 patterns of data strings that differ from the control code by one bit, and therefore the encoder 11 treats these 31 patterns of data strings as data strings that are prohibited from being inverted.

[0579] Also, as mentioned above, there are multiple control codes, so the 31 patterns of data that differ by 1 bit for each of the multiple control codes and the information transmission data that becomes the same data string when inverted are also treated as non-inverted data.

[0580] Also, as shown in FIG. 54B, when a 2-bit error occurs, information transmission data that matches the control code may be treated as a data string that is prohibited from being inverted.

[0581] When the communication data 1000100001101011011101111001111001111 shown in the upper row of Fig. 54B is inverted, it is converted into the data string 0111011110010100100010000110000 shown in the middle row. Furthermore, if a one-bit error occurs in this inverted data string, it becomes the data string 0111011110011100100010000110000 shown in the lower row.

[0582] This inverted data string, 0111011110011100100010000110000, in which a 1-bit error has occurred, is the same data string as the inverted data string shown in the lower part of A in Fig. 54. This inverted data string shown in the lower part of A in Fig. 54 is the same data string as Data 1 shown in Fig. 53, which differs by 1 bit.

[0583] The information transmission data before inversion shown in the upper part of B in Fig. 54 becomes a data string that is the same as data 1 that differs by 1 bit when a 1-bit error occurs in the control code due to the occurrence of a 1-bit error in the inverted data string. Such information transmission data may also be treated as data that is prohibited from being inverted. Here, such information transmission data is described as data that differs by 2 bits.

[0584] In this way, the encoder 11 treats information transmission data which becomes a control code when inverted, information transmission data which becomes data that differs by 1 bit when a 1-bit error occurs in the control code when inverted, and information transmission data which becomes data that differs by 2 bits when a 2-bit error occurs in the control code when inverted, as data strings that do not permit inversion.

[0585] In this way, even when the expanded control code is treated as an inversion-prohibited data string, the process of the encoder 11 can be performed based on the flowchart shown in Fig. 51. That is, in step S206, it is determined whether the data string to be processed is an inversion-prohibited data string, but the difference is that the data string set as the inversion-prohibited data string is expanded to include not only the information transmission data that becomes a control code when inverted, but also the above-mentioned information transmission data (expanded control data), and other processes can be performed in the same way.

[0586] Moreover, the process of the decoder 12 can be performed based on the flowchart shown in Fig. 52. That is, in step S232, it is determined whether or not it is a control code, but the difference is that the control code for determining whether it is a control code is not only a control code, but also a wider range of data that differs by 1 bit and data that differs by 2 bits, and other processes can be performed in the same way.

[0587] The encoder 11 and the decoder 12 can basically be configured in the same manner as the encoder 11 shown in Fig. 3 and the decoder 12 shown in Fig. 4. However, since the range of data strings that are prohibited from being inverted is expanded on the encoder 11 side, it is necessary to add a function to execute this processing. Also, since the range of data strings that are determined as control codes is expanded on the decoder 12 side, it is necessary to add a function to execute this processing.

[0588] 55 shows a configuration diagram related to the encoder 11 when the range treated as an inversion-prohibited data string is expanded. The encoder 11 is configured to receive an inversion prohibition flag from a distance determination unit 402. The distance determination unit 402 is also configured to receive data from a data inversion unit 401.

[0589] The data inversion unit 401 and the distance determination unit 402 can be configured to be included in the pre-encoder 301. As described with reference to Fig. 43, the pre-encoder 301 distinguishes between a control code and information transmission data, and supplies a DC flag indicating whether the data is a control code or information transmission data to the encoder 11.

[0590] The explanation will be continued by taking as an example a configuration in which a data inversion unit 401 and a distance determination unit 402 are added to the pre-encoder 301 that performs such processing, but like the pre-encoder 301, it may be provided separately from the encoder 11, or may be included in the encoder 11. The pre-encoder 301 outputs a DC flag, which is a flag indicating whether the data is a control code or information transmission data. The reason for outputting such a DC flag is to prohibit inversion if the data is a control code. Therefore, the DC flag may be used as an inversion prohibition flag, and may be used as a flag indicating whether the data is data that is prohibited from being inverted or data that may be inverted.

[0591] A data inversion unit 401 included in the pre-encoder 301 inverts the input data. Since the inverted data only needs to be signaling data, when control data is input, processing in the data inversion unit 401 may not be executed. The inverted data is supplied to a distance determination unit 402. The distance determination unit 402 compares the control code with the inverted signaling data.

[0592] The distance determination unit 402 determines whether the inverted data string corresponds to a control code, a data string differing by 1 bit, or a data string differing by 2 bits. This determination is made by determining how many bits the inverted data string and the control code differ. In other words, the distance between the inverted data string and the control code is determined. For example, the number of bits that differ between the inverted data string and the control code is determined by determining the Hamming distance.

[0593] If the inverted data string and the control code match, in other words, the Hamming distance is 0, the data string is determined to be one that does not permit inversion. If the inverted data string and the control code differ by one bit, in other words, the Hamming distance is 1, the data string is determined to be one that does not permit inversion. If the inverted data string and the control code differ by two bits, in other words, the Hamming distance is 2, the data string is determined to be one that does not permit inversion.

[0594] If the inverted data string and the control code differ by 3 or more bits, in other words, if the Hamming distance is 3 or more, the distance determination unit 402 determines that the data is information transmission data.

[0595] If the distance determination unit 402 determines that the data sequence is one that prohibits inversion, a DC flag representing that the data sequence is one that prohibits inversion is supplied to the encoder 11. The DC flag is any one of a flag representing that the data sequence is a control code, a flag representing that the data sequence is information transmission data, and a flag representing that the data is information transmission data but prohibits inversion.

[0596] In this way, it may be possible to judge whether the inverted data matches the expanded control code, and to perform encoding using the result of this judgment.

[0597] In addition, although the expanded range of control codes is set here to control codes, data with 1-bit differences, and data with 2-bit differences, it is also possible to include data with 3-bit or 4-bit differences. The number of bits that an error occurs and whether to guarantee it can be set appropriately, taking into account the performance required of the system.

[0598] It is also possible to configure the data to be compared with the inverted control code without inverting the data. Fig. 56 shows another configuration diagram related to the encoder 11 when the range of data treated as a data string that is prohibited from being inverted is expanded. The encoder 11 is configured to receive a DC flag from a distance determination unit 411 included in a pre-encoder 301.

[0599] The distance determination unit 411 determines the distance between the input data and the inverted control code. If the input data string and the inverted control code match (Hamming distance=0), the distance determination unit 411 determines that the data string is prohibited from being inverted, and outputs a DC flag indicating that inversion is prohibited.

[0600] If the input data string and the inverted control code differ by one bit (Hamming distance = 1), the distance determination unit 411 determines that the data string is prohibited from being inverted, and outputs a DC flag indicating that inversion is prohibited.If the input data string and the inverted control code differ by two bits (Hamming distance = 2), the distance determination unit 411 determines that the data string is prohibited from being inverted, and outputs a DC flag indicating that inversion is prohibited.

[0601] If the input data string and the inverted control code differ by 3 or more bits (if the Hamming distance is 3 or more), the distance determination unit 411 determines that the data is information transmission data and outputs a DC flag indicating that the data may be determined.

[0602] In this way, it may be possible to judge whether the input data matches a data string obtained by inverting the enlarged control code, and to perform encoding using the result of this judgment.

[0603] In this way, in the encoder 11, the information transmission data that matches the expanded control code is treated as a data string that is prohibited from being inverted, is made non-inverted, and the flag is set to 0.

[0604] The configuration of the decoder 12 when handling such an expanded control code will be described below. Figure 57 is a diagram showing an example of the configuration of the decoder 12 when handling an expanded control code.

[0605] The decoder 12 is configured to perform decoding using the determination result from the distance determination unit 451. The distance determination unit 451 receives the same data string as the data string input to the decoder 12, and determines the distance between the input data string and the control code. Basically, the distance determination unit 451 determines the distance between the input data string and the control code, similar to the distance determination unit 402 (411) on the encoder 11 side.

[0606] If the flag of an input data string is 1, it is either a control code or inverted signaling data. In order to determine whether an expanded control code is also a control code, it is necessary to determine whether a data string with a flag of 1 is a control code, an expanded control code, or inverted signaling data.

[0607] Therefore, distance determination unit 451 determines the distance between the input data string and the control code. If the input data string matches the control code (Hamming distance=0), distance determination unit 451 determines that it is the control code.

[0608] Furthermore, when the input data string and the control code differ by one bit (Hamming distance=1), the distance determination unit 451 determines that the code is a control code. When the input data string and the control code differ by two bits (Hamming distance=2), the distance determination unit 451 determines that the code is a control code.

[0609] If the input data string and the control code differ by 3 bits or more (if the Hamming distance is 3 or more), the distance determination unit 451 determines that the data is information transmission data.

[0610] In this way, it may be possible to determine whether the input data matches the enlarged control code, and to decode the data using the result of the determination, in other words, information as to whether the data is a control code or information transmission data.

[0611] In this way, by treating the expanded control code as a control code, it is possible to treat it as a control code even if an error occurs in the control code.

[0612] <About encoding and decoding using scrambling> By treating the expanded control code as a control code during encoding and decoding, it is possible to improve the tolerance to errors that occur. On the other hand, if the expanded control code can be treated as a control code, the amount of information transmission data that is prohibited from being inverted on the encoder 11 side may increase.

[0613] As the amount of information transmission data that is prohibited from being inverted increases, the running disparity RD may increase. For example, when information transmission data that is prohibited from being inverted continues, the running disparity RD may increase. In addition, when processing a vertical stripe image (an image called a killer pattern) in which the gradation of the image changes up and down, there is a possibility that a data string that is prohibited from being inverted continues, and the running disparity RD may increase.

[0614] As described above, according to the encoding and decoding to which the present technology is applied, the running disparity RD and the run length RL can be controlled (suppressed), but when encoding and decoding that handles even the extended control code is performed, the running disparity RD may increase. Therefore, the following description will be given of encoding and decoding that can improve error resistance by controlling (suppressing) the running disparity RD and the run length RL and also handling the extended control code.

[0615] Fig. 58 is a diagram showing another example of the configuration of the encoder 11. The encoder 11b shown in Fig. 58 is different from the encoder 11 shown in Fig. 3 in that a scramble unit 501 is added, but otherwise is the same. Description of the same parts as the encoder 11 shown in Fig. 3 will be omitted.

[0616] The scrambler 501 scrambles the information transmission data input to the encoder 11b. The encoder 11b performs encoding based on inversion encoding, similar to the encoder 11 shown in Fig. 3. Before performing this inversion encoding, the data is scrambled. However, the control code is not scrambled, and is processed without being scrambled.

[0617] The encoder 11b may be configured to receive data and a DC flag from a pre-encoder 301 (FIG. 43), or may not have a pre-encoder 301. The encoder 11b can be applied to cases where the encoder performs encoding that also handles the expanded control code and performs inversion encoding that can control the running disparity RD and run length RL. The encoder 11b can also be applied to cases where the encoder does not handle the expanded control code, and can be applied to cases where the encoder performs encoding that can control the running disparity RD and run length RL.

[0618] The scrambling is performed by randomizing the pattern of 0s and 1s through frequent shifts so that there is a high probability that 0s and 1s will not occur consecutively. This scrambling can be restored to the original data string on the receiving side. The scrambling unit 501 performs scrambling using a generator polynomial, for example. As the scrambling using a generator polynomial, a pseudo-random bit sequence (PRBS) can be used.

[0619] An example of the generating polynomial is shown in the following equation (7). PayloadScramble=X 15 +X 14 +1 ···(7)

[0620] The scramble unit 501 also scrambles the data that is prohibited from being inverted, and prevents successive 0s or 1s. Therefore, even if a situation occurs in which data that is prohibited from being inverted continues, it is possible to prevent an increase in the running disparity RD.

[0621] Furthermore, since the information transmission data scrambled by the scrambler 501 is subjected to inversion coding processing, it is possible to further perform coding with controlled running disparity RD and run length RL.

[0622] Figure 59 shows an example of the configuration of a decoder 12b corresponding to the encoder 11b shown in Figure 58. The decoder 12b shown in Figure 59 is different from the decoder 12 shown in Figure 4 in that a descrambling unit 511 is added, but otherwise is the same. Explanation of the same parts as the decoder 12 shown in Figure 4 will be omitted.

[0623] The descrambling unit 511 receives the scrambled data string decoded in the decoder 12b and executes a descrambling process. On the encoding side, the scrambling is performed in a process before the inversion coding is performed. On the decoding side, the inversion coded data is subjected to an inversion decoding process to obtain the data string before the inversion coding is performed, and then a process of descrambling is performed.

[0624] <Encoder and decoder processing> The process of the encoder 11b shown in FIG. 58 will be described with reference to the flowchart in FIG.

[0625] The processing of the flowchart shown in Figure 60 differs from the processing of the flowchart shown in Figure 51 in that it adds scrambling processing by scrambling unit 501. Since the other processing is similar, a description of the similar processing will be omitted.

[0626] Steps S301 to S305 are the same as steps S201 to S205 (FIG. 51), and when a control code is input, a data string with a flag set to 1 is output without performing inversion encoding processing. Furthermore, the scrambling processing in scrambler 501 is not performed on the control code.

[0627] On the other hand, if it is determined in step S302 that the data sequence to be processed is not a control code, that is, if it is determined that the data sequence is information transmission data, the process proceeds to step S306. In step S306, the information transmission data to be processed is scrambled by the scrambler 501.

[0628] The processes of steps S307 to S309 are executed on the scrambled information-carrying data. The processes of steps S307 to S309 are similar to steps S206 to S208 (FIG. 51), and are related to inversion coding.

[0629] In this manner, the information transmission data is scrambled and then encoded by carrying out the inversion coding process.

[0630] Next, the process of the decoder 12b shown in FIG. 59 will be described with reference to the flowchart in FIG.

[0631] The processing of the flowchart shown in Figure 61 differs from the processing of the flowchart shown in Figure 52 in that it adds a process in which descrambling unit 511 performs descrambling. Since the other processes are similar, a description of the similar processes will be omitted.

[0632] Steps S331 to S339 are the same as steps S231 to S239 (FIG. 52), and inversion decoding is performed on the information transmission data. In the case of a control code, since inversion coding and scrambling are not performed, if it is determined that the data string is a control code, the data string is processed as being a control code.

[0633] On the other hand, for data that is not a control code, i.e., information transmission data, an inversion decoding process is performed, thereby obtaining the information transmission data in a scrambled state.

[0634] In step S340, the descrambling unit 511 executes a descrambling process on the scrambled information transmission data to generate a descrambled data string.

[0635] In this manner, the inverse coded information transmission data is inversely decoded, and the scrambled information transmission data is descrambled, thereby being decoded.

[0636] By performing encoding and decoding in this manner, the running disparity RD and run length RL can be better controlled (suppressed).

[0637] When scrambling is performed, a control code for resetting the scrambling may be newly defined and transmitted between the encoder 11 and the decoder 12. The control code for resetting the scrambling may be one that allows the reset timing to be set at any number of lines.

[0638] <Other processes in the encoder and decoder> Another process of the encoder 11b shown in FIG. 58 will be described with reference to the flowchart of FIG.

[0639] The process of the flowchart shown in FIG. 62 differs from the process of the flowchart shown in FIG. 60 in that it includes the process of adding parity, but other processes are similar, so a description of the similar processes will be omitted.

[0640] Steps S361 to S365 are the same processes as steps S301 to S305 in FIG. 60 (steps S201 to S205 in FIG. 51), and processing is performed for one predetermined block.

[0641] In step S370, it is determined whether or not the processing of n blocks has been completed. For example, in the case where parity is calculated and added for every 4 blocks as described with reference to Fig. 12 or 13, n blocks is set to 4 blocks (n=4), and in step S370, it is determined whether or not the processing of 4 blocks has been completed.

[0642] If it is determined in step S370 that the processing of n blocks has not been completed, the process returns to step S361, and the subsequent steps are repeated. On the other hand, if it is determined in step S370 that the processing of n blocks has been completed, the process proceeds to step S371.

[0643] In step S371, parity is generated and added to the nth block. The parity can be generated based on the method described with reference to FIG.

[0644] In step S372, the running disparity RD and run length RL of the data string to be output are calculated. This process is basically the same as the process in step S364 (the process in S204 in FIG. 51), but in step S372, the running disparity RD and run length RL for n blocks including parity are calculated.

[0645] In step S373, a data string for n blocks is output.

[0646] Next, another process of the decoder 12b shown in FIG. 59 will be described with reference to the flowchart of FIG.

[0647] The processing in the flowchart shown in Figure 61 above is processing for one received block, whereas the processing in the flowchart shown in Figure 63 described below is processing for n received blocks; the rest of the processing is similar, so a description of the similar processing is omitted.

[0648] In step S391, flag recovery is performed. Each time a data string of n blocks is processed, the flag is recovered. The flag is a flag added to each block as described with reference to Figures 12 and 13, and the parity is used to determine whether or not there is an error in the flag, and the flag is recovered.

[0649] In step S392, the data sequence of the first block (1st block data) of the received data sequence of n blocks is set as the data sequence of the block to be processed.

[0650] Steps S393 to S402 are similar to steps S331 to S340 in FIG. 61 (steps S231 to S239 in FIG. 52), and therefore description thereof will be omitted.

[0651] In step S403, it is determined whether or not the processing of n blocks has been completed. If it is determined in step S403 that the processing of n blocks has not been completed, the process returns to step S393, the next block is processed, and the processes from step S393 onwards are repeated.

[0652] On the other hand, if it is determined in step 403 that the processing of n blocks is complete, the decoding process for the data string of n blocks is terminated.

[0653] By performing encoding and decoding in this manner, the running disparity RD and run length RL can be better controlled (suppressed).

[0654] According to the encoding and decoding to which this technology is applied, it is possible to control (suppress) the running disparity RD and run length RL with a simple circuit configuration without deteriorating the transmission efficiency. Also, by making it possible to detect flag errors, it is possible to perform processing on the receiving side that improves the reliability of the received data.

[0655] In addition, it is possible to limit the running disparity RD and run length RL of a data sequence having a special data sequence such as a control code. Therefore, even when control codes are consecutive, it is possible to prevent the running disparity RD and run length RL from deteriorating. In addition, by preventing the running disparity RD and run length RL of the control code from deteriorating, it is possible to improve the accuracy of processing using a control code such as a clock on the receiving side.

[0656] <Computer configuration example> The above-mentioned series of processes can be executed by hardware or software. When the series of processes is executed by software, the program constituting the software is installed from a program recording medium into a computer incorporated in dedicated hardware or a general-purpose personal computer.

[0657] FIG. 64 is a block diagram showing an example of the hardware configuration of a computer that executes the above-mentioned series of processes by a program.

[0658] A CPU (Central Processing Unit) 1001, a ROM (Read Only Memory) 1002, and a RAM (Random Access Memory) 1003 are interconnected by a bus 1004.

[0659] An input / output interface 1005 is further connected to the bus 1004. An input unit 1006 including a keyboard, a mouse, etc., and an output unit 1007 including a display, a speaker, etc. are connected to the input / output interface 1005. In addition, a storage unit 1008 including a hard disk or non-volatile memory, a communication unit 1009 including a network interface, etc., and a drive 1010 that drives a removable medium 1011 are connected to the input / output interface 1005.

[0660] In the computer configured as above, the CPU 1001 loads a program stored in the storage unit 1008 into the RAM 1003 via the input / output interface 1005 and the bus 1004 and executes the program, thereby performing the above-mentioned series of processes.

[0661] The programs executed by the CPU 1001 are installed in the storage unit 1008, for example, by being recorded on a removable medium 1011, or provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital broadcasting.

[0662] In addition, the program executed by the computer may be a program in which processing is performed chronologically in the order described in this specification, or it may be a program in which processing is performed in parallel or at the required timing, such as when called.

[0663] The effects described herein are merely examples and are not limiting, and other effects may also be present.

[0664] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0665] For example, the present technology can be configured as cloud computing, in which a single function is shared and processed collaboratively by multiple devices via a network.

[0666] Furthermore, each step described in the above flow chart can be executed by one device, or can be shared and executed by a plurality of devices.

[0667] Furthermore, when a single step includes multiple processes, the multiple processes included in the single step can be executed by a single device, or can be shared and executed by multiple devices.

[0668] <Application example to endoscopic surgery system> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0669] FIG. 65 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0670] 65 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0671] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0672] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0673] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0674] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0675] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0676] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0677] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0678] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0679] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0680] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0681] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0682] FIG. 66 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0683] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0684] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0685] The imaging unit 11402 may include one imaging element (so-called single-plate type) or multiple imaging elements (so-called multiple-plate type). When the imaging unit 11402 is configured as a multiple-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. By performing a 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is configured as a multiple-plate type, the lens unit 11401 may also be provided in multiple systems corresponding to each imaging element.

[0686] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0687] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0688] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0689] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0690] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0691] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0692] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0693] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0694] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0695] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0696] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0697] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0698] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0699] In this specification, the term "system" refers to an entire apparatus that is made up of a plurality of devices.

[0700] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0701] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0702] The present technology can also be configured as follows. (1) a scrambling unit for scrambling an input data string; a calculation unit that calculates a first running disparity of the data string scrambled by the scrambling unit; a determination unit that determines whether or not to invert the data string scrambled by the scrambling unit, based on the first running disparity calculated by the calculation unit and a second running disparity calculated at an earlier point in time than the first running disparity; an adding unit that inverts or does not invert the data string scrambled by the scrambling unit based on the result of the determination by the determining unit, and adds a flag indicating the result of the determination and outputs the result; An encoding device comprising: (2) The scrambling unit does not scramble the input data if the input data is a control code. The encoding device according to (1) above. (3) The determination unit compares a first absolute value of a value obtained by adding the first running disparity and the second running disparity with a second absolute value of a value obtained by adding an inverted value of the first running disparity and the second running disparity, and determines that the disparity is inverted if the second absolute value is smaller than the first absolute value. The encoding device according to (1) or (2). (4) The first running disparity and the second running disparity are values ​​including the flag. The encoding device according to (3) above. (5) After the determination by the determination unit, it is determined whether or not the run length continuing from a point before the data string scrambled by the scrambling unit is equal to or greater than a predetermined threshold, and if it is equal to or greater than the predetermined threshold, processing is performed with a determination result different from that of the determination unit. An encoding device according to any one of (1) to (4). (6) When a data string of a predetermined number of bits is defined as one block and a plurality of blocks are defined as one processing unit, the flag of the last block of the processing unit is set to the result of calculation of the exclusive OR of the flags added to blocks other than the last block of the processing unit. An encoding device according to any one of (1) to (5). (7) The last block is treated as a non-inverted data string. The encoding device according to (6) above. (8) When a data string of a predetermined number of bits is regarded as one block and a plurality of blocks are regarded as one processing unit, the result of performing a Hamming code process on the flag included in the processing unit is added to the end of the last block of the processing unit. An encoding device according to any one of (1) to (7). (9) The determination unit determines that an inversion will occur when the first running disparity is greater than 0 and the second running disparity is greater than 0, and determines that an inversion will not occur when the first running disparity is greater than 0 and the second running disparity is less than 0. An encoding device according to any one of (1) to (8). (10) The determination unit determines that inversion will not occur when the first running disparity is smaller than 0 and the second running disparity is greater than 0, and determines that inversion will occur when the first running disparity is smaller than 0 and the second running disparity is greater than 0. An encoding device according to any one of (1) to (9). (11) The encoding device, Scramble the input data string, Calculating a first running disparity of the scrambled data sequence; determining whether to invert the scrambled data sequence based on the calculated first running disparity and a second running disparity calculated at an earlier point in time than the first running disparity; Based on the result of the determination, the scrambled data string is inverted or not inverted, and a flag indicating the result of the determination is added and output. Encoding method. (12) A computer that controls the encoding device includes: Scramble the input data string, Calculating a first running disparity of the scrambled data sequence; determining whether to invert the scrambled data sequence based on the calculated first running disparity and a second running disparity calculated at an earlier point in time than the first running disparity; Based on the result of the determination, the scrambled data string is inverted or not inverted, and a flag indicating the result of the determination is added and output. A program for executing a process that includes steps. (13) a determination unit that refers to a flag added to an input data string and determines whether the data string is inverted or not; an output unit that inverts and outputs the input data string when it is determined by the determination unit that the data string is inverted, and that outputs the input data string without inverting it when it is determined that the data string is not inverted; a descrambling unit that descrambles the data string output by the output unit; A decoding device comprising: (14) When the determination unit determines that the data string is a control code, the process by the descrambling unit is not executed. The decoding device according to (13) above. (15) A running disparity of the data output from the output unit is calculated, and a determination is made as to whether or not an error has occurred in the input data by determining whether or not the running disparity is on the increase. The decoding device according to (13) or (14). (16) When a data string of a predetermined number of bits is defined as one block and a plurality of blocks are defined as one processing unit, the flag of the last block of the processing unit is set to the result of calculation of the exclusive OR of the flags added to blocks other than the last block of the processing unit. When the processing unit is decoded, it is determined whether or not there is an error in the flag from the result of calculation of the exclusive OR of the flags included in the processing unit. The decoding device according to any one of (13) to (15). (17) When a data string of a predetermined number of bits is defined as one block, and a plurality of blocks are defined as one processing unit, after the last block of the processing unit, a hamming result obtained by subjecting the flag included in the processing unit to a hamming code process is added, and when the processing unit is decoded, the hamming result is decoded and it is determined whether or not there is an error in the flag. The decoding device according to any one of (13) to (16). (18) The decoding device Refer to a flag added to the input data string to determine whether the data string is inverted or not; if it is determined that the data string is inverted, the input data string is inverted and output, and if it is determined that the data string is not inverted, the input data string is output without inverting; The output data string is descrambled. Decryption method. (19) A computer that controls the decryption device Refer to a flag added to the input data string to determine whether the data string is inverted or not; if it is determined that the data string is inverted, the input data string is inverted and output, and if it is determined that the data string is not inverted, the input data string is output without inverting; The output data string is descrambled. A program for executing a process that includes steps. [Explanation of symbols]

[0703] 11 encoder, 12 decoder, 31 inversion unit, 32 selection unit, 33 addition unit, 34 bit check unit, 35 RD check unit, 36 RL check unit, 37 flag determination unit, 41 inversion unit, 42 selection unit, 43 flag determination unit, 61 error detection unit, 71 state control unit, 72 header generation unit, 73 data insertion unit, 74 footer generation unit, 81 block, 82 parity bit, 100 transmission system, 111 image sensor, 121 imaging unit, 122 transmission unit, 131 reception unit, 132 image processing unit, 151 system control unit, 152 frame data input unit, 153 register, 161 TX protocol management unit, 162 byte conversion unit, 163 payload ECC insertion unit, 164 packet generation unit, 165 Lane distribution unit, 171 State control unit, 172 Header generation unit, 173 Data insertion unit, 174 Footer generation unit, 181 TX state control unit, 182 Clock generation unit, 183 Signal processing unit, 191 Control code insertion unit, 192 8B10B symbol encoder, 193 Synchronization unit, 194 Transmitter unit, 201 RX state control unit, 202 Signal processing unit, 211 Receiver unit, 212 Clock generation unit, 213 Synchronization unit, 214 Symbol synchronization unit, 215 10B8B symbol decoder, 216 Skew correction unit, 217 Control code removal unit, 221 RX protocol management unit, 222 Lane integration unit, 223 Packet separation unit, 224 Payload error correction unit, 225 Pixel conversion unit, 231 State control unit, 232 header error correction unit, 233 data removal unit, 234 footer error detection unit, 241 frame data output unit, 242 register, 243 system control unit, 244 symbol synchronization unit, 301 pre-encoder, 401 data inversion unit, 402 distance determination unit, 451 distance determination unit, 501 scrambling unit, 511 descrambling unit

Claims

1. a scrambling unit for scrambling an input data string; a calculation unit that calculates a first running disparity of the data string scrambled by the scrambling unit; a determination unit that determines whether or not to invert the data string scrambled by the scrambling unit, based on the first running disparity calculated by the calculation unit and a second running disparity calculated at an earlier point in time than the first running disparity; an addition unit that inverts or does not invert the data string scrambled by the scrambling unit based on the result of the determination by the determination unit, and outputs the data string by adding a flag indicating the result of the determination; a parity section for generating a calculation result using the flag added to each of the data strings as one block, and adding the calculation result to the end of the one block; An encoding device comprising:

2. The scrambling unit does not scramble the input data if the input data is a control code. The encoding device according to claim 1 .

3. The determination unit compares a first absolute value of a value obtained by adding the first running disparity and the second running disparity with a second absolute value of a value obtained by adding an inverted value of the first running disparity and the second running disparity, and determines that the disparity is inverted when the second absolute value is smaller than the first absolute value. The encoding device according to claim 1 .

4. The first running disparity and the second running disparity are values ​​including the flag. The encoding device according to claim 3.

5. After the determination by the determination unit, it is determined whether or not the run length continuing from a point before the data string scrambled by the scrambling unit is equal to or greater than a predetermined threshold, and if it is equal to or greater than the predetermined threshold, processing is performed with a determination result different from that of the determination unit. The encoding device according to claim 1 .

6. When a plurality of blocks are regarded as one processing unit, the parity section sets the flag of the last block of the one processing unit to a result of calculation of an exclusive OR of the flags added to blocks other than the last block of the one processing unit. The encoding device according to claim 1 .

7. The last block is treated as a non-inverted data string. The encoding device according to claim 6.

8. When a plurality of blocks are regarded as one processing unit, the parity section adds a result of performing a Hamming code process on the flag included in the one processing unit to the end of the last block of the one processing unit. The encoding device according to claim 1 .

9. The determination unit determines that inversion will occur when the first running disparity is greater than 0 and the second running disparity is greater than 0, and determines that inversion will not occur when the first running disparity is greater than 0 and the second running disparity is less than 0. The encoding device according to claim 1 .

10. The determination unit determines that inversion will not occur when the first running disparity is smaller than 0 and the second running disparity is larger than 0, and determines that inversion will occur when the first running disparity is smaller than 0 and the second running disparity is larger than 0. The encoding device according to claim 1 .

11. The encoding device, Scramble the input data string, Calculating a first running disparity of the scrambled data sequence; determining whether to invert the scrambled data sequence based on the calculated first running disparity and a second running disparity calculated at an earlier point in time than the first running disparity; Based on the result of the determination, the scrambled data string is inverted or not inverted, and a flag indicating the result of the determination is added and output; A plurality of the data strings are treated as one block, a calculation result is generated using the flag added to each of the data strings, and the calculation result is added to the end of the one block. Encoding method.

12. A computer that controls the encoding device includes: Scramble the input data string, Calculating a first running disparity of the scrambled data sequence; determining whether to invert the scrambled data sequence based on the calculated first running disparity and a second running disparity calculated at an earlier point in time than the first running disparity; Based on the result of the determination, the scrambled data string is inverted or not inverted, and a flag indicating the result of the determination is added and output; A plurality of the data strings are treated as one block, a calculation result is generated using the flag added to each of the data strings, and the calculation result is added to the end of the one block. A program for executing a process that includes steps.

13. a determination unit that refers to a flag added to an input data string and determines whether the data string is inverted or not; an output unit that inverts and outputs the input data string when it is determined by the determination unit that the data string is inverted, and that outputs the input data string without inverting it when it is determined that the data string is not inverted; a descrambling unit that descrambles the data string output by the output unit; an error determination unit which regards a plurality of the data strings as one block and determines whether or not there is an error in the flag from a calculation result using the flag added to each of the data strings added to the end of the one block; A decoding device comprising:

14. When the determination unit determines that the data string is a control code, the process by the descrambling unit is not executed. A decoding device according to claim 13.

15. A running disparity of the data output from the output unit is calculated, and a determination is made as to whether or not an error has occurred in the input data by determining whether or not the running disparity is on the increase. A decoding device according to claim 13.

16. When a plurality of blocks are regarded as one processing unit, when the one processing unit set in the calculation result of the exclusive OR of the flags added to the blocks other than the last block of the one processing unit is decoded, the error determination unit determines whether or not there is an error in the flag from the calculation result of the exclusive OR of the flags included in the one processing unit. A decoding device according to claim 13.

17. When a plurality of blocks are regarded as one processing unit, when the one processing unit is decoded to which a Hamming result obtained by performing a Hamming code process on the flag included in the one processing unit is added, the error determination unit decodes the Hamming result and determines whether or not there is an error in the flag. A decoding device according to claim 13.

18. The decoding device, Refer to a flag added to the input data string to determine whether the data string is inverted or not; if it is determined that the data string is inverted, the input data string is inverted and output, and if it is determined that the data string is not inverted, the input data string is output without inverting; Descrambling the output data string; A plurality of the data strings are regarded as one block, and it is determined whether or not there is an error in the flag from a calculation result using the flag added to each of the data strings added to the end of the block. Decryption method.

19. A computer that controls the decryption device Refer to a flag added to the input data string to determine whether the data string is inverted or not; if it is determined that the data string is inverted, the input data string is inverted and output, and if it is determined that the data string is not inverted, the input data string is output without inverting; Descrambling the output data string; A plurality of the data strings are regarded as one block, and it is determined whether or not there is an error in the flag from a calculation result using the flag added to each of the data strings added to the end of the block. A program for executing a process that includes steps.

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