Carrier recovery circuit

Abstract

To provide a single carrier high multi-value QAM radio system, capable of realizing a high demodulation performance even under a condition that a phase noise of a carrier wave causing deterioration in performance is applied.SOLUTION: A carrier reproduction circuit includes: a phase offset application part 4 that applies phase offsets which are different from each other to a processing object signal to generate a plurality of processing object signals after the application of the phase offsets; a phase error measurement part 5 that detects a phase error in each processing object signal after the application of the phase offsets; a determination part 63 that selects any one of the processing object signals after the application of the phase offsets; and a fifth phase rotational device 8 that rotates a phase of each processing object signal by using a value obtained by subtracting the phase offset from a phase error of the selected processing object signal after the application of the phase offset. The determination part 63 selects any one of the processing object signals after the application of the phase offsets on the basis of a phase difference in regard to a known signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a carrier recovery circuit, and more particularly to a technique for recovering a carrier wave and a received wave in digital wireless transmission. [Background technology]

[0002] Due to the demand for more efficient frequency utilization in response to an increase in wireless traffic, there is an increasing demand for high-speed transmission using a high-multilevel QAM (Quadrature Amplitude Modulation) method in digital wireless transmission.

[0003] In the high-level QAM system, demodulation performance may be degraded due to phase noise (phase error) of the carrier generated in the transmitting device or the receiving device. For this reason, a carrier recovery circuit is known that improves demodulation performance (specifically, bit error rate) based on the degree of influence of phase noise and thermal noise (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-101177 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in high multi-level modulation, the phase error detection range for carrier recovery becomes significantly narrower, and when the phase jitter increases in a phase noise environment, the correction accuracy for carrier recovery is significantly degraded, which is a problem.

[0006] Therefore, an object of the present invention is to provide a carrier recovery circuit that can achieve high demodulation performance in a single-carrier high-level QAM wireless system even under conditions where carrier phase noise, which causes performance degradation, is added. [Means for solving the problem]

[0007] In order to solve the above problem, the invention described in claim 1 is a carrier recovery circuit comprising a phase offset applying unit that applies mutually different phase offsets to a signal to be processed to generate a plurality of signals to be processed after the phase offsets have been applied, a phase error measuring unit that detects a phase error of each of the signals to be processed after the phase offsets have been applied, a judgment unit that selects one of the signals to be processed after the phase offsets have been applied, and a phase rotator that rotates the phase of the signal to be processed using a value obtained by subtracting the phase offset from the phase error of the selected signal to be processed after the phase offsets have been applied, wherein the judgment unit selects one of the signals to be processed after the phase offsets have been applied based on a phase difference related to a known signal. Effect of the Invention

[0008] According to the invention of claim 1, multiple processing target signals to which a phase offset has been added in advance are generated, and the phase error is detected and phase rotation is performed while switching between them. This prevents the constellation of the processing target signal from rotating significantly, causing many of the processing target signals to fall outside the phase error detection range and making it impossible to properly measure the phase error, thereby preventing a deterioration in the correction accuracy of carrier recovery. It is possible to improve the phase error tracking performance by dealing with the constellation rotation in an adaptive manner, and ultimately to achieve high demodulation performance.

[0009] Furthermore, according to the invention described in claim 1, the signal to be processed after the phase offset is added is selected based on the phase difference with respect to the known signal. This makes it possible to appropriately switch the signal to be processed to which the phase offset is added, and thus makes it possible to more reliably deal with the rotation of the constellation, improve the performance of tracking the phase error, and ultimately more reliably realize high demodulation performance. [Brief description of the drawings]

[0010] [Figure 1]1 is a functional block diagram showing a schematic configuration of a carrier recovery circuit in accordance with an embodiment 1 of the present invention; [Diagram 2] 1A and 1B are diagrams illustrating phase errors before and after compensation for phase fluctuation, in which (A) illustrates the phase error before compensation, and (B) illustrates the phase error after compensation by the carrier recovery circuit according to the present invention. [Diagram 3] 11A and 11B are diagrams illustrating differences in bit error rate due to differences in phase fluctuation compensation methods. [Figure 4] 10 is a functional block diagram showing a schematic configuration of a carrier recovery circuit according to an embodiment 2 of the present invention. FIG. [Diagram 5] 11 is a diagram showing an image of a transmission signal including a known signal used in a carrier recovery circuit according to a second embodiment. FIG. [Figure 6] 11 is a diagram for explaining the concept of a section for calculating a cross-correlation value in a timing detection section of a carrier recovery circuit according to a second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the present invention will be described based on the illustrated embodiment.

[0012] (Embodiment 1) FIG. 1 is a functional block diagram showing a schematic configuration of a carrier recovery circuit according to a first embodiment of the present invention.

[0013] This carrier recovery circuit is a mechanism for recovering carrier waves and received waves in digital wireless transmission, and mainly comprises a first carrier recovery loop 1, a second equalizer 2, a second carrier recovery loop 3, a phase offset providing section 4, a phase error measuring section 5, a switching control section 6, a third NCO 7, a fifth phase rotator 8, and a third delay circuit 9. As the modulation method for signals related to the carrier recovery circuit, QAM (Quadrature Amplitude Modulation) is assumed.

[0014] The first carrier recovery loop 1 includes a first phase rotator 11 , a first equalizer 12 , a first detector 13 , a first LPF 14 , a first NCO 15 , a second phase rotator 16 , and a first delay circuit 17 .

[0015] First phase rotator 11 is a rotator / multiplier that rotates the phase of an input signal, and rotates the phase of the input signal based on a phase rotation control signal output from first NCO 15 .

[0016] Specifically, the first phase rotator 11 receives an in-phase component Ich baseband signal and a quadrature component Qch baseband signal that have been quadrature demodulated by a quadrature demodulator (not shown) to which an IF signal quadrature modulated on the transmitting side is input and then converted into a digital signal by an A / D converter (not shown), and performs phase rotation on each of the in-phase component Ich and quadrature component Qch baseband signals based on a sine wave and a cosine wave as phase rotation control signals output from the first NCO 15. In the figure, the in-phase component Ich and the quadrature component Qch are indicated by a single signal line.

[0017] First equalizer 12 is an adaptive equalizer that compensates for deterioration of the frequency characteristics (frequency characteristics fluctuating in the propagation path and circuits in the wireless device) of the signal (called the "phase rotated signal") output from first phase rotator 11, that is, an equalizer that eliminates linear distortion and data errors in the phase rotated signal. Specifically, first equalizer 12 is configured, for example, by a decision feedback equalizer or a linear equalizer, and has a function of updating tap coefficients based on a decision-directed algorithm or a CMA algorithm.

[0018] The first detector 13 is a phase error detector that detects and outputs a phase error contained in the phase rotated signal after compensation by the first equalizer 12. The phase error includes the phase rotation direction (i.e., whether the phase is leading or lagging) and the phase error amount (i.e., the amount of rotation).

[0019] The method for detecting a phase error by the first detector 13 is not limited to a specific method, but may be, for example, the method described in JP-A-2008-244918 or the method described in JP-A-2019-220942.

[0020] The first LPF 14 is a filter that removes high-frequency components of the phase error detected by the first detector 13 according to a predetermined bandwidth (in other words, cutoff frequency), and is specifically configured by a low-pass filter (LPF: abbreviation for Low Pass Filter).

[0021] The first NCO 15 is a device that generates a phase rotation control signal based on the phase error from which high frequency components have been removed by the first LPF 14, and is configured by a numerically controlled oscillator (NCO: abbreviation for Numerically Controlled Oscillator).

[0022] Specifically, the first NCO 15 generates anti-phase sine waves and cosine waves based on the phase error output from the first LPF 14, outputs the generated anti-phase sine waves and cosine waves to the first phase rotator 11 as phase rotation control signals to control the phase rotation by the first phase rotator 11, and also outputs the anti-phase sine waves and cosine waves to the second phase rotator 16 as phase rotation control signals.

[0023] As described above, in first phase rotator 11, the frequency component of the difference between the carrier frequency of the IF signal and the local frequency used for quadrature demodulation is removed, and carrier frequency synchronization is achieved.

[0024] The second phase rotator 16 is a rotator / multiplier that rotates the phase of the input signal, and rotates the phase of the input signal based on the phase rotation control signal output from the first NCO 15.

[0025] Specifically, the second phase rotator 16 performs phase rotation of the signal output from the first delay circuit 17 based on a sine wave and a cosine wave as a phase rotation control signal output from the first NCO 15 based on the phase error detected by the first detector 13 after the deterioration of the frequency characteristics has been compensated for by the first equalizer 12 (i.e., after linear distortion, etc. has been eliminated).

[0026] The first delay circuit 17 generates a signal by delaying the signal input to the first phase rotator 11 (specifically, the baseband signal of the in-phase component Ich and the baseband signal of the quadrature component Qch) by a time mainly corresponding to the total processing time from the first phase rotator 11 to the first NCO 15, and outputs the signal to the second phase rotator 16.

[0027] As described above, the first carrier recovery loop 1 incorporates the first equalizer 12 in the signal processing loop, and performs cancellation processing of the phase noise of the input signal based on the estimated phase error after compensating for deterioration of the frequency characteristic (i.e., after linear distortion, etc. is eliminated). As a result, since the microwave wireless system is premised on wireless transmission in a multipath fading environment, the estimation accuracy of the carrier phase noise may be significantly reduced due to phase rotation and level fluctuation of the received signal caused by fading, but by incorporating an equalizer in the signal processing loop, the estimation accuracy of the carrier phase noise in a fading environment is improved, and high carrier recovery performance / demodulation performance is achieved.

[0028] The second equalizer 2 is an equalizer that compensates for deterioration of the frequency characteristics of the signal output from the second phase rotator 16. Specifically, the second equalizer 2 is configured by, for example, a decision feedback equalizer or a linear equalizer, and has a function of updating tap coefficients based on a decision-directed algorithm or a CMA algorithm.

[0029] The second carrier recovery loop 3 includes a third phase rotator 31, a second detector 32, a second LPF 33, a second NCO 34, a fourth phase rotator 35, and a second delay circuit 36.

[0030] The third phase rotator 31 is a rotator / multiplier that rotates the phase of the input signal, and rotates the phase of the input signal based on the phase rotation control signal output from the second NCO 34.

[0031] Specifically, the third phase rotator 31 receives the in-phase component Ich signal and the quadrature component Qch signal output from the second equalizer 2, and performs phase rotation on each of the in-phase component Ich and quadrature component Qch signals based on the sine wave and cosine wave serving as phase rotation control signals output from the second NCO 34.

[0032] The second detector 32 is a phase error detector that detects and outputs a phase error contained in the signal output from the third phase rotator 31. The phase error includes the phase rotation direction (i.e., whether the phase is leading or lagging) and the phase error amount (i.e., the amount of rotation).

[0033] The second LPF 33 is a filter that removes high-frequency components of the phase error detected by the second detector 32 according to a predetermined bandwidth (in other words, a cutoff frequency), and is specifically configured by a low-pass filter (LPF).

[0034] The bandwidth of the second LPF 33 is preferably set wider than that of the first LPF 14. The relationship between the bandwidth of the second LPF 33 and that of the first LPF 14 is preferably wider than that of the first LPF 14, but is not limited to a specific relationship and is appropriately set in consideration of not diverging the processing of the carrier recovery loop. The bandwidth of the second LPF 33 may be set to about 1.5 to 2.0 times the bandwidth of the first LPF 14 when the thermal noise is small and unlikely to diverge, and may be set to about 1.0 to 1.5 times the bandwidth of the first LPF 14 when the thermal noise is large and likely to diverge.

[0035] The second NCO 34 is a device that generates a phase rotation control signal based on the phase error from which high frequency components have been removed by the second LPF 33, and is configured by a numerically controlled oscillator (NCO).

[0036] Specifically, the second NCO 34 generates anti-phase sine waves and cosine waves based on the phase error output from the second LPF 33, outputs the generated anti-phase sine waves and cosine waves to the third phase rotator 31 as phase rotation control signals to control the phase rotation by the third phase rotator 31, and also outputs the anti-phase sine waves and cosine waves to the fourth phase rotator 35 as phase rotation control signals.

[0037] The fourth phase rotator 35 is a rotator / multiplier that rotates the phase of the input signal, and rotates the phase of the input signal based on the phase rotation control signal output from the second NCO 34.

[0038] Specifically, the fourth phase rotator 35 performs phase rotation of the signal output from the second delay circuit 36 ​​based on a sine wave and a cosine wave as a phase rotation control signal output from the second NCO 34 based on the phase error detected by the second detector 32 after the deterioration of the frequency characteristics has been compensated for by the second equalizer 2 (i.e., after linear distortion, etc. has been eliminated).

[0039] The second delay circuit 36 ​​generates a signal by delaying the signal output from the second equalizer 2 and input to the third phase rotator 31 by a time equivalent to the total processing time from the third phase rotator 31 to the second NCO 34, and outputs the signal to the fourth phase rotator 35.

[0040] The signal output from the fourth phase rotator 35 is called the "signal to be processed."

[0041] As described above, the second carrier recovery loop 3 does not incorporate an equalizer in its signal processing loop, and therefore the delay amount in the signal processing loop is smaller than that of the first carrier recovery loop 1, improving the accuracy of estimating the phase error. Furthermore, by setting the bandwidth of the second LPF 33 in the second carrier recovery loop 3 wider than that of the first LPF 14, it is possible to widen the band in which phase noise can be compensated. That is, since the first stage of compensation for phase noise has already been performed by the first carrier recovery loop 1 in the preceding stage, it is possible to widen the band in which phase noise can be compensated by setting the bandwidth wider than that of the first LPF 14 for the second stage of compensation, even if attention is paid to not diverging the processing of the carrier recovery loop.

[0042] The carrier recovery circuit according to the first embodiment includes a phase offset applying unit 4 which applies mutually different phase offsets to a signal to be processed to generate a plurality of signals to be processed after the phase offsets have been applied, a phase error measuring unit 5 which detects the phase error of each of the signals to be processed after the phase offsets have been applied, a decision unit 63 which selects one of the signals to be processed after the phase offsets have been applied, and a fifth phase rotator 8 which rotates the phase of the signal to be processed using a value obtained by subtracting the phase offset from the phase error of the selected signal to be processed after the phase offset has been applied, and the decision unit 63 selects one of the signals to be processed after the phase offsets have been applied based on a phase error fluctuation accumulation value which is obtained by accumulating the absolute value of the amount of fluctuation of the phase error between successive symbols.

[0043] The phase offset adding unit 4 is a mechanism for generating multiple signals by adding mutually different phase offsets to the signal (i.e., the signal to be processed) output from the second carrier recovery loop 3 (specifically, the fourth phase rotator 35) (in other words, by changing the slope of the signal constellation), and includes a first adding unit 41A, a second adding unit 41B, and a third adding unit 41C.

[0044] That is, the phase offset applying unit 4 applies a phase offset (in other words, a phase rotation angle) to a processing target signal (in other words, a received symbol) distributed on a complex plane, which is an orthogonal coordinate system with an I-axis of an in-phase component and a Q-axis of a quadrature component. In other words, the process by the phase offset applying unit 4 is a process of changing the inclination of the constellation of the processing target signal distributed on a complex plane.

[0045] In the example shown in the figure, the phase offset application unit 4 has three application units, and the first application unit 41A applies a phase offset of α1 [deg] to the signal to be processed, the second application unit 41B applies a phase offset of α2 [deg], and the third application unit 41C applies a phase offset of α3 [deg].

[0046] The phase offset angles α1, α2, and α3 are not limited to specific values, and are appropriately set to appropriate values, taking into consideration the size of the phase error detection range that changes according to the number of multi-values ​​of the QAM system, for example. Note that the phase error detection range corresponds to the size of each of the rectangular areas centered on each ideal symbol point, which is partitioned by dividing the ideal symbol points arranged at equal intervals vertically and horizontally on the complex plane into a grid at equal intervals vertically and horizontally.

[0047] Specifically, for example, as merely one example, when the multi-level number of the QAM method is 4096, the phase offset angles α1, α2, and α3 may be set to α1 = +1.6 [deg], α2 = 0 [deg], and α3 = -1.6 [deg].

[0048] However, the number of applying sections provided in the phase offset applying section 4 is not limited to three, and may be two, or may be four or more. For example, four applying sections may be provided, and the phase offset angles β1 to β4 of each applying section may be set as follows: β1=+1.8[deg], β2=+0.6[deg], β3=-0.6[deg], and β4=-1.8[deg].

[0049] The phase error measuring unit 5 is a mechanism for detecting a phase error, that is, how much the processing target signal after the phase offset is applied is shifted in the lead or lag direction with respect to each ideal symbol point on the complex plane, for each of the processing target signals after the three types of phase offsets are applied (in the example shown in the figure) output from the phase offset applying unit 4, and includes a first measuring unit 51A, a second measuring unit 51B, and a third measuring unit 51C. The detection of the phase error by the phase error measuring unit 5 is performed for each symbol.

[0050] The first measuring unit 51A measures and outputs a phase error corresponding to the degree of deviation in the advance or delay direction from the ideal symbol point for the signal to be processed after the phase offset (i.e., α1 = +1.6 [deg] in this embodiment) is applied from the first applying unit 41A of the phase offset applying unit 4.

[0051] The second measuring unit 51B measures and outputs a phase error corresponding to the degree of deviation in the advance or delay direction from the ideal symbol point for the signal to be processed after the phase offset (i.e., α2=0[deg] in this embodiment) is applied from the second applying unit 41B of the phase offset applying unit 4.

[0052] The third measuring unit 51C measures and outputs a phase error corresponding to the degree of deviation in the advance or delay direction from the ideal symbol point for the signal to be processed after the phase offset (in this embodiment, α3 = -1.6 [deg]) is applied from the third applying unit 41C of the phase offset application unit 4.

[0053] The switching control unit 6 is a mechanism for selecting a phase error for generating a phase rotation control signal used to control the subsequent fifth phase rotator 8, and includes a first calculation unit 61A, a second calculation unit 61B, and a third calculation unit 61C, as well as a first addition unit 62A, a second addition unit 62B, and a third addition unit 62C, as well as a judgment unit 63 and a switch 64.

[0054] The first calculation unit 61A calculates the amount of phase error fluctuation between consecutive symbols (i.e., the phase error of the nth symbol--the phase error of the (n-1)th symbol) for the phase error output from the first measurement unit 51A of the phase error measurement unit 5, and outputs the absolute value. The calculation of the amount of phase error fluctuation by the first calculation unit 61A is performed for each symbol, and the absolute value of the amount of phase error fluctuation per symbol (in other words, between two consecutive symbols) when a phase offset angle α1=+1.6[deg] is applied is output.

[0055] The second calculation unit 61B calculates the amount of phase error fluctuation between consecutive symbols (i.e., the phase error of the nth symbol--the phase error of the (n-1)th symbol) for the phase error output from the second measurement unit 51B of the phase error measurement unit 5, and outputs the absolute value. The calculation of the amount of phase error fluctuation by the second calculation unit 61B is performed for each symbol, and the absolute value of the amount of phase error fluctuation per symbol (in other words, between two consecutive symbols) when a phase offset angle α2=0[deg] is applied is output.

[0056] The third calculation unit 61C calculates the amount of phase error fluctuation between consecutive symbols (i.e., the phase error of the nth symbol--the phase error of the (n-1)th symbol) for the phase error output from the third measurement unit 51C of the phase error measurement unit 5, and outputs the absolute value. The calculation of the amount of phase error fluctuation by the third calculation unit 61C is performed for each symbol, and the absolute value of the amount of phase error fluctuation per symbol (in other words, between two consecutive symbols) when a phase offset angle α3=-1.6[deg] is applied is output.

[0057] The first adding unit 62A adds the absolute value of the fluctuation amount of the phase error output from the first calculating unit 61A for each symbol for a predetermined number of consecutive symbols, and outputs the result as an integrated value of the fluctuation amount of the phase error. The number of symbols to be added is not limited to a specific value, but is appropriately set to an appropriate value, for example, by adjusting the fluctuation speed of the phase error to be processed and taking into consideration that no problem occurs in real-time signal processing in consideration of the symbol interval. Specifically, the number of symbols to be added may be set to an appropriate value within the range of about 5 to 15. The number of symbols to be added is set to the same for all of the first adding unit 62A, the second adding unit 62B, and the third adding unit 62C.

[0058] The second adding unit 62B adds up the absolute values ​​of the fluctuation amounts of the phase error outputted for each symbol from the second calculating unit 61B for the predetermined number of consecutive symbols, and outputs the sum as an integrated value of the fluctuation amounts of the phase error.

[0059] The third adding unit 62C adds up the absolute values ​​of the fluctuation amounts of the phase error outputted for each symbol from the third calculating unit 61C for the predetermined number of consecutive symbols, and outputs the sum as an integrated value of the fluctuation amounts of the phase error.

[0060] The judgment unit 63 receives the phase error fluctuation accumulation values ​​output from the first adder unit 62A, the second adder unit 62B, and the third adder unit 62C, identifies the minimum value among these phase error fluctuation accumulation values, and outputs information about the system that includes the adder unit that output the minimum value to the switch 64.

[0061] Specifically, when the integrated value of the fluctuation amount of the phase error output from the first adding unit 62A is the smallest, the determining unit 63 outputs a switching signal to the switch 64, the switching signal instructing the phase error of the first system (i.e., the system consisting of the first assigning unit 41A, the first measuring unit 51A, the first calculating unit 61A, and the first adding unit 62A) to be output to the third NCO 7, and when the integrated value of the fluctuation amount of the phase error output from the second adding unit 62B is the smallest, the determining unit 63 outputs a switching signal instructing the phase error of the second system (i.e., the system consisting of the second assigning unit 41B, the second measuring unit 51B, the , the third adding unit 62C outputs a switching signal to the switch 64 indicating that the phase error of the third system (i.e., a system consisting of the third assigning unit 41C, the third measuring unit 51C, the third calculating unit 61C, and the third adding unit 62C) should be output to the third NCO7, and further, if the integrated value of the fluctuation amount of the phase error output from the third adding unit 62C is minimum, the third adding unit 62C outputs a switching signal to the switch 64 indicating that the phase error of the third system (i.e., a system consisting of the third assigning unit 41C, the third measuring unit 51C, the third calculating unit 61C, and the third adding unit 62C) should be output to the third NCO7.

[0062] The switch 64 receives a switching signal (i.e., system selection information) output from the determination unit 63, and switches the switch according to the input switching signal. Specifically, when the first system is specified in the switching signal, the switch 64 outputs a value obtained by subtracting the angle α1 of the phase offset assigned by the first assigning unit 41A from the phase error measured by the first measurement unit 51A to the third NCO 7, when the second system is specified in the switching signal, the switch 64 outputs a value obtained by subtracting the angle α2 of the phase offset assigned by the second assigning unit 41B from the phase error measured by the second measurement unit 51B to the third NCO 7, and when the third system is specified in the switching signal, the switch 64 outputs a value obtained by subtracting the angle α3 of the phase offset assigned by the third assigning unit 41C from the phase error measured by the third measurement unit 51C to the third NCO 7.

[0063] The third NCO 7 is a device that generates a phase rotation control signal based on the phase error output from the switch 64, and is composed of a numerically controlled oscillator (NCO).

[0064] Specifically, the third NCO 7 generates a sine wave and a cosine wave of opposite phase based on the phase error output from the switch 64, and outputs the generated sine wave and cosine wave of opposite phase to the fifth phase rotator 8 as a phase rotation control signal to control the phase rotation by the fifth phase rotator 8.

[0065] The fifth phase rotator 8 is a rotator / multiplier that rotates the phase of the input signal, and rotates the phase of the input signal based on the phase rotation control signal output from the third NCO 7.

[0066] Specifically, the fifth phase rotator 8 performs phase rotation of the signal output from the third delay circuit 9 based on a sine wave and a cosine wave as a phase rotation control signal output from the third NCO 7 based on the phase error output from the switch 64.

[0067] The third delay circuit 9 generates a signal by delaying the signal (i.e., the signal to be processed) output from the second carrier recovery loop 3 (specifically, the fourth phase rotator 35) and input to the phase offset adding unit 4 by a time equivalent to the total processing time from the phase offset adding unit 4 to the third NCO 7, and outputs the signal to the fifth phase rotator 8.

[0068] As an example of verifying the effect of the above-described carrier recovery circuit, the phase error before and after compensation for phase fluctuation is shown in Fig. 2. From the results shown in Fig. 2, it can be confirmed that before compensation (i.e., the signal input to the first phase rotator 11), the phase error fluctuates significantly as shown in Fig. 2(A), whereas after compensation by the carrier recovery circuit according to the present invention, the residual phase error is significantly smaller as shown in Fig. 2(B).

[0069] As another verification example of the effect of the above-mentioned carrier recovery circuit, the difference in bit error rate (BER: abbreviation of Bit Error Rate) due to different phase fluctuation compensation methods is shown in Fig. 3. Fig. 3 shows the bit error rate of the conventional method and the bit error rate of the carrier recovery circuit of the present invention in 4096QAM. From the results shown in Fig. 3, it is confirmed that the bit error rate of the carrier recovery circuit of the present invention is improved compared to the conventional method, and that the bit error rate is greatly improved especially in the region where the carrier-to-noise ratio (CNR: abbreviation of Carrier-to-Noise Ratio) is large.

[0070] According to the above-described carrier recovery circuit, a plurality of processing target signals to which a phase offset has been added in advance are generated, and the phase error is detected while switching between the processing target signals to perform phase rotation. This prevents the constellation of the processing target signals from rotating significantly, causing many of the processing target signals to fall outside the phase error detection range and making it impossible to properly measure the phase error, thereby preventing deterioration in the correction accuracy of the carrier recovery. It is possible to improve the phase error tracking performance by adaptively dealing with the constellation rotation, and ultimately to achieve high demodulation performance.

[0071] According to the above-mentioned carrier recovery circuit, since the signal to be processed after the phase offset is added is selected based on the integrated value of the fluctuation amount of the phase error, the signal to be processed to which the phase offset is added can be appropriately switched, and the rotation of the constellation can be more reliably handled to improve the tracking performance of the phase error, and thus it is possible to more reliably realize high demodulation performance. In particular, since the phase error fluctuates greatly and the fluctuation amount of the phase error increases in the section where a burst error occurs, by using the integrated value of the fluctuation amount of the phase error, it is possible to accurately detect the section where a burst error occurs (in other words, the section where there is a residual phase error where a burst error may occur), and it is possible to appropriately recover the carrier.

[0072] (Embodiment 2) FIG. 4 is a functional block diagram showing a schematic configuration of a carrier recovery circuit according to the second embodiment of the present invention.

[0073] In this embodiment, the configuration of the switching control unit 6 is different from that of embodiment 1, but other configurations and processing contents are similar to those of embodiment 1. Therefore, the same symbols are used for configurations and processing contents equivalent to those of embodiment 1 and their explanations are omitted.

[0074] The carrier recovery circuit of the second embodiment includes a phase offset applying unit 4 that applies mutually different phase offsets to a signal to be processed to generate a plurality of signals to be processed after the phase offsets have been applied, a phase error measuring unit 5 that detects the phase error of each of the signals to be processed after the phase offsets have been applied, a decision unit 67 that selects one of the signals to be processed after the phase offsets have been applied, and a fifth phase rotator 8 that rotates the phase of the signal to be processed using a value obtained by subtracting the phase offset from the phase error of the selected signal to be processed after the phase offset has been applied, and the decision unit 67 selects one of the signals to be processed after the phase offsets have been applied based on the phase difference with respect to a known signal.

[0075] The switching control unit 6 is a mechanism for selecting a phase error for generating a phase rotation control signal used to control the subsequent fifth phase rotator 8, and includes a timing detection unit 65, a phase difference measurement unit 66, a judgment unit 67, and a switch 68.

[0076] The timing detection unit 65 receives the signal (i.e., the signal to be processed) output from the second carrier recovery loop 3 (specifically, the fourth phase rotator 35) and calculates the cross-correlation value between the signal to be processed and a known signal.

[0077] The known signal is incorporated into the transmission data and transmitted periodically. Specifically, for example, as shown in FIG. 5, the known signal is incorporated as a signal of a predetermined number of symbols (y in the example shown in FIG. 5; specifically, for example, about 5 to 10, as only one example) for each of a predetermined number of symbols (x in the example shown in FIG. 5) constituting the data portion of the transmission data on the transmitting side. The known signal is incorporated into the transmission data at a constant period as a modulated wave of a predetermined pattern shared by the transmitting side and the carrier recovery circuit on the receiving side. The predetermined pattern of the known signal is stored in advance, for example, in a storage element (not shown) provided in the switching control unit 6.

[0078] In order to detect a section in the signal to be processed where a known signal is being received (in other words, a section corresponding to a known signal), the timing detection unit 65 calculates a cross-correlation value between a portion / range of the signal to be processed and the known signal, and if the calculated cross-correlation value is equal to or greater than a predetermined threshold, it determines that the symbol group in the section where the cross-correlation value is determined to be high is a known signal, and sets the symbol group as a reference for synchronizing the timing of incorporating the known signal. The symbol group set as the reference is called the "reference symbol group." The number of symbols in the section in which the cross-correlation value is calculated is set to y in accordance with the number of symbols constituting a predetermined pattern as a known signal, and the number of symbols in the reference symbol group is y.

[0079] Specifically, as shown in Fig. 6, the timing detection unit 65 calculates cross-correlation values ​​S(n), S(n+1), S(n+2), ... for each of y symbols of the signal to be processed (received signal) while shifting the target section / range for calculating the cross-correlation value by one symbol at a time (see Fig. 6(A)) (where n is, for example, a natural number constituting an ordinal number; see Fig. 6(B)). At this time, the timing detection unit 65 calculates the cross-correlation value while simultaneously counting the number of symbols x constituting the data section, assuming that the part with a low cross-correlation value is the data section (see Fig. 5).

[0080] The timing detection unit 65 also calculates a cross-correlation value between the known signal and y symbols separated by x symbols from the end of the reference symbol group in the signal to be processed that corresponds (is considered to correspond) to the data section. If the calculated cross-correlation value is equal to or greater than a predetermined threshold, the timing detection unit 65 determines that the counted x is a fixed period of the incorporation of the known signal (in other words, the number of symbols in the data section between the known signals). On the other hand, if the calculated cross-correlation value is less than the predetermined threshold, the timing detection unit 65 resets the counted x and returns to the process of calculating the cross-correlation value between the signal to be processed and the known signal to detect the reference symbol group.

[0081] The timing detection unit 65 outputs a reception flag signal indicating that it is time to receive the known signal to the phase difference measurement unit 66 at a constant period (that is, the number of symbols x in the data section) of the known signal incorporation specified above.

[0082] Note that even after the timing detection unit 65 has once identified the fixed period of the known signal incorporation, it may continue the process of calculating the cross-correlation value with the known signal for y symbols separated by x symbols that correspond (considered to correspond) to the data portion, and if the cross-correlation value falls below a predetermined threshold a predetermined number of times (specifically, for example, three times) in succession, it may reset the once identified x and return to the process of calculating the cross-correlation value between the signal to be processed and the known signal and detecting the reference symbol group.

[0083] The phase difference measurement unit 66 receives the signal (i.e., the signal to be processed) output from the second carrier recovery loop 3 (specifically, the fourth phase rotator 35) and waits until the reception flag signal output from the timing detection unit 65 is input.

[0084] When the reception flag signal is input, the phase difference measurement unit 66 measures the phase difference on the complex plane for each symbol constituting the symbol group corresponding to the known signal, which corresponds to the degree of deviation in the lead or lag direction from the true value of the known signal, for the processing target signal corresponding to the timing at which the reception flag is input (specifically, for the symbol group corresponding to the known signal).The phase difference measurement unit 66 also calculates the average value for the symbol group corresponding to the known signal (referred to as the "known signal phase difference average value") for the phase difference for each symbol measured as described above.

[0085] Upon completing calculation of the known signal phase difference average value, the phase difference measurement unit 66 outputs to the determination unit 67 the calculated known signal phase difference average value and an update flag signal indicating that the known signal phase difference average value has been calculated and updated.

[0086] The determination unit 67 receives the known signal phase difference average value and the update flag signal output from the phase difference measurement unit 66, and holds the input known signal phase difference average value as the latest known signal phase difference average value.

[0087] The determination unit 67 further outputs to the switch 68 information on the system selected as a result of comparing the magnitude of the latest known signal phase difference average value with the phase error detection range of each system specified according to the phase offset angles α1, α2, α3 assigned by each of the phase offset assigning units 41A, 41B, 41C of the phase offset assigning unit 4.

[0088] The comparison of the magnitude of the latest known signal phase difference average value with the phase error detection range of each system is specifically performed, for example, as follows, by way of example only: The first system is a system consisting of a first assigning unit 41A and a first measuring unit 51A, the second system is a system consisting of a second assigning unit 41B and a second measuring unit 51B, and the third system is a system consisting of a third assigning unit 41C and a third measuring unit 51C.

[0089] Here, we take as an example a case where the number of multi-levels in the QAM format is 4096, and the phase offset angles are set as α1 = +1.6 [deg], α2 = 0 [deg], and α3 = -1.6 [deg]. In this case, the phase error detection ranges of each system are as follows: First system: Phase offset is +1.6° → Phase error detection range is +0.8° to +2.4° Second system: Phase offset is 0° → Phase error detection range is -0.8° to +0.8° Third system: Phase offset is -1.6° → Phase error detection range is -2.4° to -0.8°

[0090] In this case, the judgment unit 67 outputs a switching signal to the switch 68 indicating that the phase error of the first system (i.e., the system consisting of the first assigning unit 41A and the first measuring unit 51A) should be output to the third NCO 7 if the latest known signal phase difference average value is +2°, outputs a switching signal to the switch 68 indicating that the phase error of the second system (i.e., the system consisting of the second assigning unit 41B and the second measuring unit 51B) should be output to the third NCO 7 if the latest known signal phase difference average value is +0.5° or -0.5°, and further outputs a switching signal to the switch 68 indicating that the phase error of the third system (i.e., the system consisting of the third assigning unit 41C and the third measuring unit 51C) should be output to the third NCO 7 if the latest known signal phase difference average value is -2°.

[0091] The switch 68 receives a switching signal (i.e., system selection information) output from the determination unit 67 and switches the switch according to the input switching signal. Specifically, when the first system is specified in the switching signal, the switch 68 outputs a value obtained by subtracting the angle α1 of the phase offset assigned by the first assigning unit 41A from the phase error measured by the first measurement unit 51A to the third NCO 7, when the second system is specified in the switching signal, the switch 68 outputs a value obtained by subtracting the angle α2 of the phase offset assigned by the second assigning unit 41B from the phase error measured by the second measurement unit 51B to the third NCO 7, and when the third system is specified in the switching signal, the switch 68 outputs a value obtained by subtracting the angle α3 of the phase offset assigned by the third assigning unit 41C from the phase error measured by the third measurement unit 51C to the third NCO 7.

[0092] As a result, every time a known signal is received, the latest known signal phase difference average value held in the determination unit 67 is updated, and the system (specifically, the type of phase offset) selected based on the latest known signal phase difference average value is switched by the switch 68.

[0093] According to the above-described carrier recovery circuit, a plurality of processing target signals to which a phase offset has been added in advance are generated, and the phase error is detected while switching between the processing target signals to perform phase rotation. This prevents the constellation of the processing target signals from rotating significantly, causing many of the processing target signals to fall outside the phase error detection range and making it impossible to properly measure the phase error, thereby preventing deterioration in the correction accuracy of the carrier recovery. It is possible to improve the phase error tracking performance by adaptively dealing with the constellation rotation, and ultimately to achieve high demodulation performance.

[0094] According to the above-described carrier recovery circuit, the signal to be processed after the phase offset is added is selected based on the phase difference with respect to the known signal. Therefore, the signal to be processed to which the phase offset is added can be appropriately switched. This makes it possible to more reliably deal with the rotation of the constellation, improve the performance of tracking the phase error, and ultimately more reliably realize high demodulation performance.

[0095] Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above embodiment, and even if there are design changes and the like within the scope of the gist of the present invention, they are included in the present invention.

[0096] For example, in the above embodiment, in addition to the first carrier recovery loop 1, a second carrier recovery loop 3 is provided. However, the second carrier recovery loop 3 is not an essential component of the present invention, and the signal output from the second phase rotator 16 or the signal output from the second equalizer 2 may be directly input to the phase offset adding unit 4 or the third delay circuit 9 as the signal to be processed.

[0097] Furthermore, in the above embodiment, there are two carrier wave recovery loops, the first carrier wave recovery loop 1 and the second carrier wave recovery loop 3, but there may be three or more carrier wave recovery loops.

[0098] In the above-mentioned embodiment 1, a system (in the example shown in the figure, any one of the first system, the second system, and the third system) that outputs a phase error used when generating a phase rotation control signal is selected based on a phase error integration value obtained by adding the absolute value of the amount of fluctuation of the phase error as the difference between the phase errors of each consecutive symbol for a predetermined number of consecutive symbols. However, the method of selecting a system that outputs a phase error used when generating a phase rotation control signal based on the degree of phase error is not limited to the procedure or method in the above-mentioned embodiment 1, and other procedures or methods may be used as long as they can select a system in which the degree of phase error per symbol or the degree of phase error fluctuation between two consecutive symbols is small, or the degree of phase error or the degree of phase error fluctuation over a plurality of consecutive symbols is small. For example, a system in which the average value of the absolute value of the phase error over a predetermined number of consecutive symbols is the smallest may be selected, or a system in which the average value of the absolute value of the amount of fluctuation of the phase error over a predetermined number of consecutive symbols is the smallest may be selected. [Explanation of symbols]

[0099] 1 First carrier recovery loop 11 First phase rotator 12 First Equalizer 13 First Detector 14 First LPF 15 1st NCO 16 Second Phase Rotator 17 First delay circuit 2 Second Equalizer 3 Second Carrier Recovery Loop 31 Third Phase Rotator 32 Second detector 33 Second LPF 34 2nd NCO 35 Fourth Phase Rotator 36 Second Delay Circuit 4 Phase offset adding section 41A First Grant 41B Second Grant 41C Third Grant 5 Phase error measurement section 51A First measuring section 51B Second measuring section 51C Third Measuring Section 6 Switching control section 61A First calculation section 61B Second calculation section 61C Third calculation section 62A First Adder 62B Second Addition Unit 62C Third Addition Section 63 Determination unit (first embodiment) 64 Switch (embodiment 1) 65 Timing detection section 66 Phase difference measurement section 67 Judgment unit (Embodiment 2) 68 Switch (Embodiment 2) 7. Third NCO 8 Fifth Phase Rotator 9. Third Delay Circuit

Claims

[Claim 1] a phase offset applying unit that applies mutually different phase offsets to a processing target signal to generate a plurality of processing target signals after the phase offsets are applied; a phase error measuring unit for detecting a phase error of each of the processing target signals after the phase offset is applied; A determination unit that selects one of the signals to be processed after the phase offset is applied; a phase rotator that rotates the phase of the processing target signal using a value obtained by subtracting the phase offset from the phase error of the processing target signal after the selected phase offset is applied, The determination unit selects one of the processing target signals after the phase offset is applied based on a phase difference with respect to a known signal. A carrier recovery circuit comprising:

Images