Time-dependent line equalizer for data transmission systems

Abstract

Data equalization system, featuring: a data clock input configured to receive a clock signal; an input node which is to be operated in such a way that it receives a data signal of transmission symbols which change their state synchronously with the clock signal; a first branch which is connected to the input node; and a second branch configured to receive a modification of the data signal, wherein at least one of a weighting of the first branch and a weighting of the second branch is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

Description

BACKGROUND Technical area

[0001] The present invention relates generally to telecommunications systems and in particular to equalization in high data rate data transmission systems. Description of the state of the art

[0002] In modern electrical data transmission systems in network and data processing systems, equalization techniques are typically employed to reduce distortion resulting from channel-time dispersion, which leads to inter-symbol interference (ISI). In known systems, these equalization techniques usually rely on the use of feed-forward equalization (FFE) in a transmitter and / or receiver unit, combined with continuous-time equalization (CTE) at the receiver and, in some systems, decision feedback equalization (DFE). One goal of the equalization system is to remove as much ISI as possible in a data sample time at the receiver to improve the recoverable bit error rate (BER).As data rates in modern systems continuously increase to 100 Gb / s and beyond, the clock accuracy achievable in a practical implementation can begin to significantly limit system performance. At these high data rates, a complete transmission symbol period can be 20 ps or less. Known equalization systems based on the use of FFE / CTE / DFE remove ISI at a specific point in time within this 20 ps interval. Due to practical limitations on achievable clock accuracy, for any given receiver sample, the equalized signal may be sampled earlier or later than the specific point in time being equalized, resulting in a degraded BER and ultimately limiting the maximum achievable data rate.

[0003] In this context, there is already the document US 2013 / 0208779A1. It describes a feed-forward equalizer architecture. This can be used for a sample-and-hold circuit to generate n time-delayed versions of an input signal. Capacitors and integrated summing circuits are used for this purpose, handling multiple signal streams.

[0004] Despite these advances already made, there is still a need to make feed-forward equalization (FFE) available for data transmissions that will function reliably even at very high transmission rates. SUMMARY

[0005] This problem is solved by the subject matter of the independent patent claims. Further embodiments are described by the respective dependent patent claims.

[0006] According to one embodiment, a data equalization system is provided. A data clock input is configured to receive a clock signal. An input node is operated to receive a data signal of transmission symbols that change their state synchronously with the clock signal. A first branch is connected to the input node. A second branch is configured to receive a variation of the data signal. At least one of the weights of the first branch and one of the weights of the second branch is dynamically modulated by a control parameter that repeats synchronously with each transmission symbol.

[0007] In one embodiment, the modification of the data signal is a time delay of the data signal.

[0008] In one embodiment, the dynamic control parameter provides a time-dependent functional transformation of an input sequence of transmission symbols.

[0009] In one embodiment, the data equalization system is a forward equalizer (FFE).

[0010] In one embodiment, the data equalization system is part of a transmitter circuit.

[0011] In one embodiment, the data equalization system is part of a receiver circuit.

[0012] In one embodiment, the dynamic control parameter is a linear increase.

[0013] In one embodiment, the dynamic control parameter is a non-linear function.

[0014] In one embodiment, the first and second branches are part of a plurality of branches. At least one of the plurality of branches has a branch weighting that is statically controlled with each transfer symbol.

[0015] In one embodiment, the first branch is a precursor branch with a branch weight that is constant for each transmission symbol. The second branch is a first postcursor branch with a branch weight that is modulated by a dynamic control parameter.

[0016] In one embodiment, the dynamic control parameter is differential.

[0017] According to various embodiments, a method, a data processing unit, and a non-volatile, computer-readable storage medium for equalizing a signal are provided. An equalization system is provided, comprising a first branch and a second branch. A data clock is received. Data input of transmission symbols is received, which change their state synchronously with the data clock. A branch weighting of at least one from the first branch or the second branch is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol of the data clock. The weights of all branches in the equalization system are summed. Output data is provided based on the summed weights of all branches in the system.

[0018] In one embodiment, the second branch receives a time-delayed version of the data input.

[0019] In one embodiment, the dynamic control parameter provides a time-dependent functional conversion of an input time sequence of the transmission symbols.

[0020] In one embodiment, the data equalization system is a forward equalizer (FFE).

[0021] In one embodiment, the dynamic control parameter is a linear increase.

[0022] In one embodiment, the dynamic control parameter is a non-linear function.

[0023] In one embodiment, the first and second branches are part of a plurality of branches, and at least one of the plurality of branches has a branch weighting that is statically controlled with each transfer symbol.

[0024] In one embodiment, the weighting of the first branch constant is kept constant for each transfer symbol.

[0025] In one embodiment, the weighting of the second branch is modulated by the dynamic control parameter.

[0026] In one embodiment, the weighting of at least one from the first branch or the second branch is differentially controlled by the dynamic control parameter.

[0027] The features described herein provide robust 4-level data transmission at 100 Gb / s over long-distance channels (25 dB+ loss) by improving the HEYE span by up to three times. Various transmission systems, including 100 Gb / s systems, can operate more reliably with a lower bit error rate (BER). In general, the teachings presented herein increase the HEYE span by two, three, or more times compared to static equalizers. Furthermore, the jitter tolerance (JTOL) of a data exchange system is improved, while the jitter requirements on the system clocks are reduced.

[0028] These and other features will become apparent from the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings are of exemplary embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition to or instead of those shown. Details that are obvious or unnecessary may have been omitted to save space or for more effective illustration. Some embodiments may be carried out with additional components or steps and / or without all of the components or steps illustrated. Where the same reference number appears in different drawings, it refers to the same or similar components or steps. Fig. Figure 1 is a block diagram of a data transmission system according to one embodiment. Fig. Figure 2 illustrates a channel bit impulse response in the context of time-variable equalization of at least one of the branches of the Fig. 1. Fig. Figure 3 shows waveforms of branch values ​​for different branches for different data symbols. Fig. Figure 4A illustrates an example of a forward equalizer circuit that uses current-mode logic. Fig. Figure 4B shows a hardware implementation of the dynamic branch weight generator using a CMOS circuit system according to one embodiment. Fig. 4C illustrates exemplary waveforms of the branch weighting generator circuit of the Fig. 4B. Fig. Figure 5 shows waveforms of branch values ​​for different branches for different symbols. Fig. Figures 6A to 6D illustrate the branching weights for the precursor (i.e., Fig. 6A), the postcursor (i.e. Fig. 6B), the second postcursor (i.e. Fig. 6C) and the third postcursor (i.e. Fig. 6D) of a branch FFE of example 5. Fig. Figure 7A illustrates the HEYE span, where the branch weights are fixed. Fig. Figure 7B illustrates an improved HEYE span achieved with one embodiment. Fig. Figure 8A is an eye diagram of an exemplary time-variable forward line equalizer, where the branch weights are fixed. Fig. Figure 8B is an eye diagram of an exemplary time-variable forward line equalizer, wherein the branch weights are modulated, according to one embodiment. Fig. Figure 9A is an eye diagram of another exemplary time-variable forward line equalizer, where the branch weights are fixed. Fig. 9B is an eye diagram of the in Fig. 9A used forward line equalizer, wherein the branch weights are modulated, according to one embodiment. Fig. Figure 10A is an eye diagram of another exemplary time-variable forward line equalizer, where the branch weights are fixed. Fig. 10B is an eye diagram of the in Fig. 10A used forward line equalizer, wherein the branch weights are modulated, according to an exemplary embodiment. Fig. Figure 11 shows a method for performing an equalization of a data signal according to one embodiment. Fig. Figure 12 is a block diagram of a computer hardware platform that can exchange data with various networked components. DESCRIPTION Overview

[0030] The following detailed description uses examples to illustrate numerous specific details in order to ensure a thorough understanding of the teachings in question. However, it should be evident to those skilled in the art that the teachings presented here can also be implemented without such details. In other cases, well-known methods, procedures, components, and / or circuits have been described in relatively broad terms without going into detail, in order to avoid making aspects of the teachings presented here unnecessarily unclear.

[0031] As used herein, equalization refers to the removal of distortion caused by a signal transmitted through a channel. The teachings herein provide improved equalization systems and procedures based on time-dependent equalization, wherein the time dependence of the equalization is synchronized with the data transmission interval such that the equalizer can apply a change in equalization during the transmission interval of each transmitted symbol. The equalization architecture described herein reduces the ISI over a wider time span within the symbol transmission period than known forward equalization (FFE) techniques, which employ branch weights that are nominally constant for the duration of a symbol transmission period.This, in turn, allows a data transmission system to operate with a lower BER in the presence of system clock jitter, which is typically unavoidable. To simplify the present discussion, a forward equalization architecture (FFE architecture) is described only as an example, without being restrictive. Exemplary architecture

[0032] Referring to Fig. Figure 1, a data transmission system 100, comprises a data source 102, an equalizer 103, a transmission channel 116, and a data receiver 120. In one embodiment, the equalizer 103 is a transverse FFE that generates a weighted sum of time-delayed values ​​of a transmission symbol sequence. The equalizer 103 comprises a plurality of branches 106(0) to 106(n) connected to different stages of a data signal provided by the data source 102. For example, the data source 102 is operated to provide transmission symbols that change their state synchronously with a clock signal (not shown). This signal is conditioned at different stages by signal conditioning elements 104(0) to 104(n). In one embodiment, the signal conditioning elements are delay elements which are operated in such a way that they delay the received signal by their respective time period.

[0033] The data from data source 102 can be encoded into transmission symbols using various techniques, e.g., (but not limited to) NRZ (Non-Return to Zero), 4-PAM (Pulse Amplitude Modulation), 8-PAM, or 32-QAM (Quadrature Amplitude Modulation), etc., where the number indicates the different number of constellation points used to carry the information. The summing node 110 is operated such that it receives all branches 106(0) to 106(n) and provides an output to a buffer 112. In one embodiment, current-mode logic is used to summe a current at the output of the various branches 106(0) to 106(n). Alternatively, other known summing circuits can be used to perform the summation of the different paths.

[0034] In particular, one or more of the weights of the weighted sum generated by the transverse equalizer 103 can be varied within a symbol transfer interval to achieve improved equalization over a wider time span. Conceptually, it can be found that varying the weights derives branching weights from the end-to-end channel response, as shown in Fig. Figure 1 illustrates this. In other words, unlike conventional FFEs, which have branch weights that are constant (i.e., do not vary during a symbol transmission interval), at least one of the branches 106(0) to 106(n) is modulated by a dynamic control parameter that repeats synchronously with the respective transmission symbol. Thus, in known FFE branch weight determination methods, FFE branch weights are found at time t0 of an end-to-end channel response, whereas the teachings presented here provide at least one branch weight that can dynamically vary over time during a clock cycle. This concept will be better understood by considering the discussion below.

[0035] It will now be on Fig. 2 Reference is made to the channel bit impulse response 200 in the context of a time-dependent equalization of at least one of the branches 160(0) to 160(n) of the Fig. Figure 1 illustrates this. To determine the appropriate branch weight variation to achieve equalization over a wider time interval, instead of setting the branch weight to a specific branch weight, a range of times around the nominal equalization point t0 (t) can be used. 0-2Δ t, t 0-Δt , t0, t 0+Δt , t 0+2Δt) can be considered, where Δt is a (e.g., arbitrary) small time step within the period of the symbol transmission interval. At each of these times, a new set of FFE equalization coefficients ci can be found. Improved equalization is then achieved by applying time-dependent coefficient weights to the FFE, which cycle through the calculated branching weights over time. In one embodiment, to simplify the practical implementation of the time-dependent equalizer, the change in the coefficient branching weight can be approximated as a function of time with a linear increase that cycles through the optimal values, as shown in Bit Impulse Response 200.In such an embodiment, one or more branches of an FFE can be configured with two parameters: (i) a branch weight and (ii) a branch slope value or rate of change, or alternatively, (i) a branch start weight and (ii) a branch end weight. The concept of modulating the branch weight, which repeats synchronously with each transfer symbol, is better understood by considering exemplary waveforms of timing diagrams, as described below. Example time diagrams

[0036] It will now be on Fig. 3. Reference is made to which waveforms of branch values ​​are shown for different branches of different data symbols. This is merely an example and is not intended to be limiting. Fig. 3. How the branch weights of an FFE with 5 branches change over time, for an example channel where the x-axis of the branch weight plots is given in units corresponding to time steps of 1 / 32 of a symbol transfer interval. To simplify the present discussion, the example of Fig. 3 uses a linear approximation of the rate of change of the branching weights, although it is understood that the teachings herein support any other function equally well. Waveform 302 shows the transferred symbol intervals. The branching values, herein sometimes referred to as branching weights, are synchronous with the transferred symbol intervals. For example, the waveform 310 of the precursor branching value has a coefficient rise phase that is synchronized with the transfer symbol 302. This coefficient rise phase 310 is a dynamic control parameter of the branch that repeats synchronously with the transfer symbol 302. In some embodiments, the dynamic control parameter changes between transfer symbols 302.

[0037] It should be noted that not all branches need to be subject to a dynamic control parameter. In various embodiments, one or more branches may have a dynamic control parameter, while the remaining branches are static or constant during a symbol transmission interval. This is illustrated in the following. Fig. 3. For example, the cursor branch value 320 is constant for each transfer symbol. Thus, the FFE cursor branch 320 in the example of Fig. 3 is fixed, while the branch values ​​for the precursor 310, the postcursor 330, the second postcursor 330, and the third postcursor 340 are time-modulated synchronously with the data transmission interval 302. In this way, improved ISI compensation is achieved over a wider time interval. Example circuit diagram

[0038] With the preceding explanation of the theoretical operation and waveforms of equalization systems, it may be helpful to describe an exemplary circuit diagram that could be used to design the equalizer of the Fig. 1. In this regard, this is illustrated. Fig. 4A An exemplary FFE equalizer circuit 400, in which current-mode logic is used, according to an exemplary embodiment. The circuit 400 comprises differential loads 402 and 404, which can be resistors, each having a first node connected to a first reference node, which in this example is VDD. In the example of the Fig. 4 there are two branches: the first represented by the differential transistors 406 and 410, connected to the current source 420, and the second represented by the differential transistors 430 and 432, connected to the synchronous time-dependent branch generator 440.

[0039] In various embodiments, transistors 408, 412, 430, and 436 can be based on complementary metal-oxide-semiconductor (CMOS) technology, such as n-channel field-effect transistors (NFETs) and / or p-channel field-effect transistors (PFETs). In some embodiments, bipolar transistors (e.g., PNP or NPN) can be used instead of MOS transistors. The transistor pair 406 and 410 has a common emitter (or source) connected to a current source 420. The current source is connected to a second reference node, which can be ground 422. For example, the inputs of the first transistor pair 406 and 410 have control inputs 408 and 412, respectively (e.g., gates or base inputs), which are to be operated to receive data signals differentially. For example, input 408 can receive the data signal D1, while input 412 receives the complementary signal (e.g. D1).In one embodiment, non-return-to-zero signaling (NRZ signaling) is used. In the example of... Fig. The first branch in input 4A has a constant current source 420. In other words, the level of the branch weighting does not vary over time during a transmission symbol. Inputs 434 and 436 control the polarity of the applied branch weighting as a function of data history and branch sign.

[0040] The fixed-weight cursor branch is formed by switching a fixed current 420 based on the data symbol sign to the output loads 402 and 404, thereby forming a transfer output signal Vo, which is differentially modified by V OP 482 and V ON484 is represented. In one embodiment, a fixed weighting of the cursor branch with the index “i” is formed by summing a current with a fixed weighting, which is determined by the sign of the data at index “i” (S i ) is switched.

[0041] In contrast, the second branch does not provide a constant branch weight. Instead, it is able to vary the branch weight during each transmission symbol. For this purpose, the synchronous time-dependent branch weight generator 440 in one embodiment can include a current interpolator 442 connected to a plurality of current sources that can be selected at different times during a clock cycle. For example, it can have a first current source (I START ) 444 and a second power source (I STOP ) 446. Accordingly, the sum of the differential outputs V is added. OP482 and V ON 484 A variable-weighted current, which has at least one given branch index “i”, is provided using a synchronous time-dependent branch weight generator. In one embodiment, the synchronous time-dependent branch weight generator 440 is implemented using a current interpolator 442, which is capable of deriving a symbol transfer interval from the current I. START 444 to the river I STOP 446 to interpolate, where values ​​for I START 444 and I STOP 446 may be programmatically preconfigured or automatically set by other systems, such as an adaptive equalization control system, given the new ability to control at least two branch configuration parameters (e.g., Istart and Istop) to limit inter-symbol interference to a minimum over a wider time period.

[0042] Fig. Figure 4B illustrates a hardware implementation of the dynamic branching weight generator, using, by way of example only and without limitation, a CMOS circuit system. In one embodiment, a half-rate or C2 clock drives a clock generator block 460. The clock generator produces two differential output clocks, Ci (or interpolator clock) and Cm (or multiplexer clock). In another embodiment, the synchronous time-dependent branching weight generator 440 responds to configuration parameters that allow both the slope and the offset of the slope to be configured by controlling the values ​​of an initial current and an end current over a symbol transmission interval.

[0043] For example, at unit symbol intervals removed from the cursor branch, the FFE circuit 400A switches an FFE branch current 420 based on the sign of the FFE branch, multiplied by the sign of the data (for the NRZ transmission), to the output signal V OP / V ON (482, 484), forming an equalized output signal. The FFE circuit 400A dynamically varies the current of the second FFE branch using the synchronous dynamic branch weighting generator 440. The synchronous dynamic branch weighting generator 440 responds to an input clock 460, which is related to the symbol transfer rates and the programmatic controls, which configure an initial current I. START 444 and a final current I STOP 446 enable. In one embodiment, the branching weighting stream starts nominally at a value I over each data transmission interval. START444 and rises towards a value I STOP 446 at the end of the symbol transmission interval, thus providing the desired variation of the applied equalization as a function of time. The synchronous dynamic branch weight generator 440 responds to at least one system clock to enable the dynamic branch weight generator 440 to produce a current rise 438 that is synchronized to a data transmission interval. Although Fig. 4A describes the circuit 400 as having a differential architecture, it is understood that the teachings contained herein also support an asymmetric approach.

[0044] The circuit diagram of the Fig. 4A is easier to understand by examining example waveforms. To this end, it shows Fig. Five waveforms of branch values ​​for different branches and symbols. The data symbol, represented by the binary values ​​"0" and "1", is illustrated by waveform 502. Waveform 520 represents the data clock to which data symbol 502 is synchronized. The dynamic branch weighting stream at node 438 of the Fig. 4A varies between I START and I STOP and is synchronous to the data clock 520. In one embodiment, the branch current is a linear increase of I. START 532 to I STOP 534.

[0045] It will now be on Fig. Reference is made to Figure 4B, which illustrates a dynamic branching weight generator circuit 400B according to an exemplary embodiment. For illustrative purposes only, and without limitation, the circuit 400B is illustrated using CMOS technology. The branching weight generator circuit 400B comprises a clock generator circuit 411, which has a first group of differential outputs Cip / Cin connected to a current interpolator circuit 415. The clock generator block 411 has a second group of differential outputs Cmp and Cmn connected to the differential inputs of a 2:1 current multiplexer 417.

[0046] The current interpolator 415 comprises two PFETs Q1 and Q2, which share a common source connected to a first current source (11) that is operated to provide a first current IStart. The current interpolator further comprises two PFETs Q3 and Q4, which share a common source connected to a second current source I2 that is operated to provide a second current IStop. The gates of PFETs Q1 and Q4 are connected to the positive terminal Cip, while the gates of transistors Q2 and Q3 are connected to the negative terminal Cin of the first differential clock output.

[0047] The 2:1 current multiplexer circuit 417 has a similar structure to the current interpolator and is therefore not repeated here for the sake of brevity. A first output of the current interpolator circuit 415 (i.e., at the common drain of PFETs Q1 and Q3) is connected to the common source of PFETs Q5 and Q6 of circuit 417. A second output of the current interpolator circuit 415 (i.e., at the common drain of PFETs Q2 and Q4) is connected to the common source of PFETs Q7 and Q8 of circuit 417. The gates of PFETs Q5 and Q8 are connected to the positive terminal Cmp, while the gates of transistors Q6 and Q7 are connected to the negative terminal Cmn of the second differential clock output. The drains of PFETs Q5 and Q7 are connected to a common level (e.g., ground). The drain of PFETs Q6 and Q8 is connected to a current source, represented by the NFET Q9, whose gate is connected to its gate.There is a driver circuit, which can be a full-rate branching weighting driver 421, which has two NFETs Q11 and Q12, which have a common source connected to a current source, represented by the NFET Q10.

[0048] The operation of the 400B dynamic branching weighting generator circuit is better understood by examining its waveforms. For this purpose, the following is illustrated. Fig. 4C Exemplary waveforms of the branch weighting generator circuit 400B of the Fig. 4B. Accordingly, the operation of the branch weighting generator circuit 400B is described with reference to the waveforms of the Fig. 4C discussed.

[0049] In the embodiment of the Fig. In 4B, the synchronous dynamic branching weight generator 400B is implemented using a current interpolator 415, which is capable of interpolating from the current Istart to the current Istop over a symbol transfer interval, where values ​​for Istart and Istop can be programmatically preconfigured or automatically set, as already discussed. In one embodiment, a half-rate or C2 clock drives a clock generator block 411. The clock generator block 411 generates two differential output clocks, Ci or interpolator clock and Cm or multiplexer clock, illustrated by waveforms 471 and 473, respectively. Fig. 4C. In one embodiment, the interpolator clock Ci 471 is a triangular waveform with the same frequency as the input clock C2 of the Fig. 4B, with a deflection suitable for driving a current interpolator circuit 415, comprising the PMOS units Q1, Q2, Q3 and Q4. In the exemplary waveforms shown in Fig. As shown in 4C, the interpolator triangle waveform 471 varies from 0 V to 0.5 V to control the gates of the PMOS current interpolator units Q1 to Q4. Fig. 4B to control. The PMOS current interpolator 415 provides outputs to a PMOS 2:1 current multiplexer 417, which is formed by the PMOS units Q5, Q6, Q7 and Q8.

[0050] The current interpolator clock Cm, illustrated by waveform 473, drives the current switches in the current multiplexer 417 to feed a 2:1 multiplexed current into the NMOS trap diode Q9, which is configured as an NFET with its gate and drain connected, thereby generating the desired full-rate current-rise waveform for controlling the weighting of a branch. In the example waveforms shown in Fig. As shown in Figure 3C, the interpolator clock Cm 473 varies from 0 V to 0.5 V with a nominal square waveform to quickly switch the state of the current multiplexer 417. The trap diode Q9, in combination with the termination current unit Q10, forms a current mirror to generate a dynamic branch weighting current I(t), which is then switched to the line driver termination outputs 483 and 485 by the NMOS transistors Q11 and Q12 based on the sign of the branch weight Si-n, multiplied by the sign of the data Di-n (for NRZ transmission).

[0051] In the waveforms of Fig. Figure 4C shows two exemplary configurations for the dynamic current generator. In particular, waveform 475 illustrates the generation of a branch weighted current that increases over time over the symbol transmission interval, while waveform 477 illustrates the generation of a branch weighted current that decreases over time over the symbol transmission interval. In one embodiment, the phase of clocks Ci 471 and Cm 473 can be adjusted such that the transient part of the dynamic current (when it switches from Istop to Istart) is centered at a desired position within the symbol transmission interval, for example, near the transition edges of the data waveform. The data waveform itself is in Fig. 4C is not shown, but it is understood that it is nominally synchronous with the clock Cm 473.

[0052] In an example where the main or cursor branch is programmed with a fixed current of 10 mA, the normalized dynamic branch weight nominally varies from 0.1 to 0.3. It is understood that due to bandwidth limitations in circuits, the actual programmed start and end currents may not be exactly 1 mA and 3 mA, respectively, but the slope of the current rise, which corresponds to a variation in the branch weight from 0.1 to 0.3 over a symbol transfer, provides a good representation.

[0053] In some scenarios, a desired slope of the rise over a data transmission interval can cause a change in a branch sign, comprising a branch weighting to a negative current, which is achieved by the described current interpolation circuit. Fig. 4B may not be provided correctly. In one embodiment, to simplify the implementation, if the signs of Istart and Istop are changed by a branch weight variation (i.e., Istart is positive and Istop is negative), Istop is saturated to a low value. Alternatively, if Istop is significantly higher than Istart in absolute terms, the sign of the branch weight Si can be reversed, Istop made positive, and Istart saturated to a low value. In another embodiment, polarity crossing can be achieved by using a second static equalizer branch combined with the dynamic equalizer branch, with the static equalizer branch and the dynamic equalizer branch being applied to opposite polarities of the output.As an example, a static branch value of a normalized weight of 0.2 on one polarity, combined with an increase in the normalized weight on the other polarity, which varies from 0.1 to 0.3, results in a normalized net weight of 0.1 to -0.1 of the combined static and dynamic branch. Exemplary results

[0054] The advantages of the systems and methods described herein can be better illustrated with some practical simulation results. For this purpose, in Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. Ten different equalization branch waveforms and the corresponding "eye diagrams" of the equalized data signal are shown. The "eye diagrams" in the figures can be analyzed using various known statistical techniques to generate measurements for horizontal-eye (HEYE) and vertical-eye (VEYE) operating ranges.

[0055] Fig. Figures 6A to 6D illustrate the branching weights for the precursor (i.e., Fig. 6A), the postcursor (i.e. Fig. 6B), the second postcursor (i.e. Fig. 6C) and the third postcursor (i.e. Fig. Figure 6D) shows an example of a 4-level 100 Gb / s transmission with FFE and 5 branches, exhibiting one channel with a 17 dB loss. Both the optimal value (solid lines, e.g., 642) and the linear approximation (dashed lines, e.g., 644) are illustrated. Thus, they illustrate Fig. 6A to 6D the calculation of the temporal variation of the branch weights with time and a linear approximation to these branch weights. Fig. Figure 7A illustrates the HEYE marking of 29.7% of the prior art (where the branch weights are fixed), while Fig. Figure 7B illustrates the resulting improved HEYE span achieved with the application of the invention. In this example, the HEYE improved from approximately 30% HEYE to 47% HEYE when using 4-level data transmission on a channel with a nominal loss of 17 dB.

[0056] Fig. Figures 8A and 8B show eye diagrams of another exemplary time-variable forward line equalizer with an FFE with 8 branches with 2 precursors, Rx DFE1, 4-level transmission of 100 Gb / s, channel with 25 dB loss, both for the prior art (where the branch weights are fixed) and for an exemplary embodiment. This example is based on a higher-loss channel where both FFE and DFE equalization are applied, and there is also degradation due to clock jitter (i.e., random 200 fs RMS clock jitter) and amplitude noise (i.e., 3 mV RMS amplitude noise). As shown in the comparison eye diagram plots of the Fig. 8A and Fig. As shown in Figure 8B, the HEYE is improved from a 12.5% ​​range to a 39% range (i.e., an improvement of more than three times).

[0057] Fig. 9A and Fig. Figure 9B shows eye diagrams of another exemplary time-varying forward line equalizer with a data rate of 200 Gb / s over a single channel with 15 dB loss using a 200 fs RMS clock RJ and 5 mV RMS amplitude noise under 32QAM modulation, resulting in 6-level transmission. In this example, the BER floor is 3 × 10 -11 in the state of the art in Fig. 9A on 8 × 10 -15 an embodiment of the present disclosure in Fig. 9B improved and a HEYE at a confidence level of 1 × 10 -6 increased from 12.5% ​​to 32.7%.

[0058] Fig. 10A and Fig. Figure 10B shows eye diagrams of yet another exemplary time-variable forward line equalizer with an 8-level signal transmission of 210 Gb / s over one channel with 15 dB loss, 200 fs RMS clock jitter, and 5 mV RMS amplitude noise. In this example, after applying a Reed-Solomon error correction code, the HEYE is 12.4% (i.e., state of the art in Fig. 10A, where the branch weights are fixed) to 28.8% (i.e. Fig. 10B) when using the time-dependent equalizer according to an embodiment of the present disclosure. Exemplary procedure

[0059] Following the preceding overview of an exemplary equalization system 100, exemplary waveforms 302 to 340, and an exemplary circuit implementation 400, it may now be helpful to consider a higher-level discussion of an exemplary method. For this purpose, the following is presented: Fig. Section 11 describes a method 1100 for performing equalization of a data signal according to an illustrative embodiment. Method 1100 is illustrated as a collection of procedures in a logical flowchart, each block representing a sequence of operations that can be implemented in hardware, software, or a combination thereof. In the software context, the procedures represent instructions executable by a computer, which, when executed by one or more processors, cause the operations to be performed. In general, instructions executable by a computer can include routines, programs, objects, components, data structures, and the like, which perform functions or implement abstract data types.The order in which the operations are described should not be interpreted as a restriction, and any number of the described procedures can be combined in any order and / or performed in parallel to implement the procedure. For the purposes of discussion, procedure 110 is referred to in relation to . Fig. 4 described.

[0060] As a purely illustrative example, and without being limiting, consider an FFE system comprising an input node configured to receive a data signal, a data clock input, a first branch, and a second branch. Block 1104 receives a clock signal. In block 1106, a data signal is received at the input node from transmission symbols that change their state synchronously with the received clock signal. In block 1108, at least one of the first or second branch weights is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol. Exemplary computer platform

[0061] As discussed above, functions relating to the equalization of a data signal, as well as other functions discussed herein, can be performed using a controller or a data processing unit. Fig.Figure 12 is a functional block diagram of a computer hardware platform that can exchange data with various networked components, which can be used to implement one or more of the functional blocks discussed herein.

[0062] The computer platform 1200 can include a central processing unit (CPU) 1204, a hard disk drive (HDD) 1206, random access memory (RAM) and / or read-only memory (ROM) 1208, a keyboard 1210, a mouse 1212, a display device 1214 and a data exchange interface 1216, which are connected to a system bus 1202.

[0063] In one embodiment, the HDD 1206 has capabilities that include storage for a program capable of executing various procedures, such as that of the equalization machine 1240, as described herein. The equalization machine 1240 may comprise various modules configured to perform different functions. For example, there may be an interaction module 1242 that is operated to receive data signals from various sources via a network, with the data being equalized by the equalization machine 1240.

[0064] There can be a clock module 1244, which is operated such that it receives a clock signal and / or generates its own clock signal to which the input data is synchronized. There are two or more branches, which are exemplified as a first branch module 1245 and a second branch module 1248. Although two branch modules are illustrated, in various embodiments there is no limit to the number of branches supported by the concepts discussed herein. There can be a control parameter module 1250, which is operated such that it controls a branch weighting of at least one of the first branch 1246 or the second branch 1248. The control parameter module 1250 modulates a branch weighting by providing a dynamic control parameter that repeats synchronously with each transfer symbol of the clock.There can be a summing module 1250, which is to be operated in such a way that it sums the branch weights of the first branch and the second branch.

[0065] In one embodiment, a program such as Apache™ can be stored to run the system as a web server. In another embodiment, the HDD 1206 can store an execution application that includes one or more library software modules, such as those for the Java™ runtime environment program to implement a JVM (Java™ Virtual Machine). conclusion

[0066] The descriptions of the various embodiments are given for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without deviating from the scope of the invention. The terminology used herein has been chosen to best explain the principles of the invention, its practical application, or its technical improvement over commercially available technologies, or to enable other skilled persons to understand the embodiments disclosed herein.

[0067] Although the foregoing describes what is considered the best state and / or other examples, it is understood that various modifications can be made to it, that the subject matter disclosed herein can be realized in various forms and examples, and that the teachings can be applied in numerous examples, of which only some have been described herein. It is intended that the following claims encompass any and all applications, modifications, and variations that fall within the scope of the present teachings.

[0068] The components, steps, features, tasks, uses, and advantages discussed herein are merely examples. None of these, nor the discussions relating thereto, are intended to limit the scope of protection. Although various advantages have been discussed herein, it is understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, assessments, positions, heights, sizes, and other specifications set forth in this description, including the following claims, are approximate, not exact. They are intended to have a reasonable range consistent with the functions to which they relate and that is customary in the relevant field.

[0069] Furthermore, numerous other embodiments are provided. These include embodiments with fewer, additional, and / or different components, steps, features, tasks, benefits, and advantages. They also include embodiments in which the components and / or steps are arranged or ordered differently. For example, any signal discussed herein can be scaled, buffered, scaled and buffered, converted to another state (e.g., voltage, current, charge, time, etc.), or converted to another state (e.g., from HIGH to LOW and from LOW to HIGH) without substantially altering the underlying control procedure.

[0070] Although NFETs and PFETs are illustrated and / or discussed in some of the examples herein, these transistors are presented only as examples and are not limited to them. It is understood from the concepts disclosed herein that other types of insulated-gate field-effect transistors (IGFETs) with complementary logic can likewise be used. For example, any FETs from groups III to V of the periodic table, including carbon nanotube FETs, could be used to realize the structures described herein. In some embodiments, bipolar transistors (e.g., PNP or NPN) and / or BiCMOS transistors can be used instead of MOS transistors.

[0071] Aspects of the invention are described herein with reference to flowcharts and / or block diagrams of processes, devices (systems), and computer program products according to embodiments of the application. It is understood that each block of the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, can be executed by means of computer-readable program instructions.

[0072] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or any other programmable data processing device to create a machine such that the instructions executed by the processor of the computer or other programmable data processing device generate means for carrying out the functions / actions specified in the block or blocks of the flowcharts and / or block diagrams.These computer-readable program instructions may also be stored on a computer-readable storage medium capable of controlling a computer, programmable data processing device and / or other units to function in a particular manner, such that the computer-readable storage medium on which instructions are stored comprises a manufactured product, including instructions that implement aspects of the function / action specified in the block or blocks of the flowchart and / or block diagrams.

[0073] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device or other unit to cause a series of operational steps to be carried out on the computer, other programmable device or other unit in order to produce a procedure executed on a computer, such that the instructions executed on the computer, other programmable device or other unit implement the functions / actions specified in the block or blocks of the flowcharts and / or block diagrams.

[0074] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, processes, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams can represent a module, segment, or part of instructions comprising one or more executable instructions for implementing the specific logical function(s). In some alternative embodiments, the functions specified in the block may occur in a different order than shown in the figures. For example, two blocks shown consecutively may in reality be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order depending on the corresponding functionality.It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special hardware-based systems that perform the specified functions or actions, or execute combinations of special hardware and computer instructions.

[0075] Although the foregoing description was given in conjunction with exemplary embodiments, it is understood that the term "exemplary" is meant merely as an example rather than the best or optimal one. Except as stated immediately above, nothing that has been stated or illustrated is intended to constitute, or be interpreted as constituting, a specific determination of any component, step, feature, function, benefit, advantage, or the like for the public, regardless of whether it is included in the claims or not.

[0076] It is understood that the terms and expressions used herein have the ordinary meanings attributed to them in relation to their respective fields of investigation and study, except where specific meanings have been otherwise given herein. Expressions of a relationship such as first and second and the like may be used solely to distinguish one unit or action from another, without necessarily requiring or implying any actual relationship or sequence between such units or actions.The terms "includes," "having," or variations thereof are intended to cover a non-exclusive scope, such that a process, method, object, or device which includes a list of elements may include not only those elements but also other elements not expressly listed or inherent in such process, method, object, or device. The prefix "a" or "an" to an element does not, without further limitations, preclude the presence of other identical elements in the process, method, object, or device which includes the element.

[0077] The summary of the disclosure is given to enable the reader to quickly grasp the nature of the technical disclosure. It is provided with the understanding that it is not intended to interpret or limit the scope of the claims. Furthermore, it can be seen from the preceding detailed description that various features in different embodiments are grouped together to streamline the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly stated in each claim. Instead, as reflected in the following claims, the inventive step lies in fewer than all the features of any single disclosed embodiment.Therefore, the following claims are hereby included in the Detailed Description, with each claim standing alone as a separately claimed subject matter.

Claims

[1] Data equalization system comprising: a data clock input configured to receive a clock signal; an input node which is to be operated in such a way that it receives a data signal of transmission symbols which change their state synchronously with the clock signal; a first branch which is connected to the input node; and a second branch configured to receive a modification of the data signal, wherein at least one of a weighting of the first branch and a weighting of the second branch is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol. [2] Data equalization system according to claim 1, wherein the modification of the data signal is a time delay of the data signal. [3] Data equalization system according to claim 1, wherein the dynamic control parameter provides a time-dependent functional conversion of an input time sequence of the transmission symbols. [4] Data equalization system according to claim 1, wherein the data equalization system is a forward equalizer (FFE). [5] Data equalization system according to claim 1, wherein the data equalization system is part of a transmitter circuit. [6] Data equalization system according to claim 1, wherein the data equalization system is part of a receiver circuit. [7] Data equalization system according to claim 1, wherein the dynamic control parameter is a linear increase. [8] Data equalization system according to claim 1, wherein the dynamic control parameter is a non-linear function. [9] Data equalization system according to claim 1, wherein: The first and second branches are part of a plurality of branches, and at least one of the multiple branches has a branch weighting that is statically controlled with each transfer symbol. [10] Data equalization system according to claim 1, wherein: the first branch is a precursor branch which has a branch weighting that is constant for each transfer symbol, and The second branch is a first postcursor branch which has a branch weighting that is modulated by the dynamic control parameter. [11] Data equalization system according to claim 1, wherein the dynamic control parameter is differential. [12] Equalization method, wherein the method has: Providing an equalization system that has a first branch and a second branch; Receiving a data clock signal; Receiving a data input of transmission symbols that change their state synchronously with the data clock; Modulating a branch weighting of at least one of the first branch or the second branch with a dynamic control parameter that repeats synchronously with each transmission symbol of the data clock. [13] Method according to claim 12, further comprising summing a weighting of all branches in the equalization system; and providing output data based on the summed weighting of all branches in the system. [14] Method according to claim 12, wherein the second branch receives a time-delayed version of the data input. [15] Method according to claim 12, wherein the dynamic control parameter provides a time-dependent functional conversion of an input time sequence of the transmission symbols. [16] Method according to claim 12, wherein the data equalization system is a forward equalizer (FFE). [17] Method according to claim 12, wherein the dynamic control parameter is a linear increase, or wherein the dynamic control parameter is a non-linear function. [18] Method according to claim 12, wherein: The first and second branches are part of a plurality of branches, and at least one of the multiple branches has a branch weighting that is statically controlled with each transfer symbol. [19] Method according to claim 12, further comprising: Maintaining a constant weighting of the first branch for each transfer symbol; and Modulating the weighting of the second branch using the dynamic control parameter. [20] Method according to claim 12, wherein the weighting of at least one of the first branch or the second branch is differentially controlled by the dynamic control parameter. [21] Data processing unit comprising: a processor; a network interface which is connected to the processor to enable data exchange over a network; an equalization machine which is connected to the processor and configured to perform actions of the method according to any one of claims 12 to 20. [22] Non-volatile computer-readable storage medium which physically embodies a computer-readable program code which includes computer-readable instructions which, when executed, cause a computer unit to perform the method according to any one of claims 12 to 20.

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