Automatic configuration of pipeline modules in electronic equipment systems - Patents.com

Abstract

To provide an automatic optimization method of a pipeline configuration in design of an electronics system and a computing platform.SOLUTION: A method for generating a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration which optimizes an area and timing.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THEINVENTION The present invention relates generally to the design of electronic systems, and more particularly to automated optimization of pipeline configurations. [Background technology]

[0002] background Register Transfer Level (RTL) typically refers to a design abstraction that models digital circuits as the flow of data signals between hardware registers, and the logical operations performed on those signals; that is, it describes how data is manipulated and moved between registers. RTL can be used in the design and verification flows of electronic systems. For example, RTL can be used in the design and verification flows of systems on chips (SoCs).

[0003] Traditional RTL generation of SoCs is extremely time consuming for systems that utilize reconfigurable and parameterizable hardware components. For example, an initial RTL description is generated and sent to an SoC integrator to determine if certain constraints are met. If the constraints are violated, a new RTL description is generated and the verification is repeated. It may take several hours to perform multiple iterations. The challenge or problem is not only the time it takes to generate the RTL, but also the time to generate a final acceptable RTL. Currently, a designer or user manually creates the configuration of the pipeline modules and generates the RTL. Problems in the configuration settings are not found until later in the synthesis flow, when timing and / or area criteria / constraints are not met. This forces the user to go back and change the pipeline configuration again (expensive iterations) and keep trying this process until it works. Thus, there is a need for a system and method for automatically configuring pipeline modules in an electronic system. Summary of the Invention [Means for solving the problem]

[0004] overview Various embodiments and methods are disclosed for automatically configuring pipeline modules in an electronic system. The method implemented by the embodiments of the present invention includes generating a complete register transfer level (RTL) description of an electronic system. The method includes generating an optimized pipeline configuration from inputs including a database of RTL elements and a list of configurable pipeline components, and generating the complete RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for configurations that optimize area and timing. As disclosed herein, various advantages result from the embodiments and methods according to the present invention. Furthermore, the methods disclosed herein are general and are not limited to where the pipelines reside or are located.

[0005] BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, reference is made to the accompanying drawings or figures. The present invention is described according to aspects and embodiments in the following description with reference to the drawings or figures, in which like numbers represent the same or similar elements. With the understanding that these drawings should not be considered as limiting the scope of the present invention, the presently described aspects and the best currently understood aspects of the present invention will be described with further details by using the accompanying drawings. [Brief description of the drawings]

[0006] [Figure 1] 1 illustrates a computer-implemented method for generating an RTL description of an electronic device system according to various aspects and embodiments of the present invention. [Diagram 2] 1 illustrates configurable pipeline components in accordance with various aspects and embodiments of the present invention. [Diagram 3]1 illustrates configurable pipeline components in accordance with various aspects and embodiments of the present invention. [Figure 4A] 1 illustrates a table of configurable pipeline components in accordance with various aspects and embodiments of the present invention. [Figure 4B] 1 illustrates configurable pipeline components in accordance with various aspects and embodiments of the present invention. [Figure 4C] 1 illustrates configurable pipeline components in accordance with various aspects and embodiments of the present invention. [Diagram 5] 1 illustrates a system that utilizes several configurable pipeline components in accordance with various aspects and embodiments of the present invention. [Figure 6] 10 illustrates input and production data for a method of automatic configuration of a pipeline module using the platform of FIG. 9 according to various aspects and embodiments of the present invention. [Figure 7] 10 illustrates the high-level steps involved by a method for automatic generation of pipeline modules using the platform of FIG. 9 in accordance with various aspects and embodiments of the present invention. [Figure 8] 1 illustrates an example of a method for iteratively modifying flow paths to find an optimized pipeline configuration in accordance with various aspects and embodiments of the present invention. [Figure 9] 1 illustrates components of a computing platform in accordance with various aspects and embodiments of the present invention. [Figure 10] 1 illustrates a network-on-chip (NoC) having pipeline components configured in accordance with various aspects and embodiments of the present invention. [Figure 11] 1 illustrates an NoC having pipeline components configured in accordance with various aspects and embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Detailed Description In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and which show by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that mechanical, procedural, and other changes may be made without departing from the spirit and scope of the invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined solely by the appended claims, including the full scope of equivalents to which such claims are entitled.

[0008] Throughout this specification, reference to "one embodiment," "embodiment," "one example," or "example" means that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "example" in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, databases, or characteristics may be combined in any suitable combination and / or subcombination in one or more embodiments or examples. Additionally, it should be understood that the drawings provided herein are for illustrative purposes to persons skilled in the art and that the figures are not necessarily drawn to scale.

[0009] As used herein, "source", "master", and "initiator" refer to similar intellectual property (IP) blocks, modules, or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, "sink", "slave", and "target" refer to similar IP modules or units, and these terms are used interchangeably within the scope and embodiments of the present invention. As used herein, a transaction may be a request transaction or a response transaction. Examples of request transactions include a write request and a read request.

[0010] The flowcharts and block diagrams in the accompanying figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each step of the flowcharts or block diagrams may represent a module, segment, or portion of code that includes one or more executable instructions for performing the specified logical functions. Furthermore, it should be noted that each step of the block diagrams and / or flowchart diagrams, and combinations of steps or blocks of the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or a combination of dedicated hardware and computer instructions. Furthermore, these computer program instructions may be stored in a tangible computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a specific manner, and thus the instructions stored in the computer-readable medium produce an article of manufacture that includes instruction means for performing the functions / operations specified in the steps or blocks of the flowcharts and / or block diagrams.

[0011] Referring to Figure 1, Figure 1 illustrates a computer-implemented method for generating a complete RTL description of an electronics system. The electronics system utilizes reconfigurable and / or parameterizable hardware blocks. In Figure 1, the blocks include reconfigurable pipeline components. Examples of electronics systems include, but are not limited to, artificial intelligence (AI), SoC, and system-in-package (SiP).

[0012] In step 100, an "optimized" pipeline configuration is generated. The optimized configuration is generated from inputs including a database of RTL elements and a list of reconfigurable and / or parameterizable hardware components. The list of configurable pipeline elements identifies different configuration modes for each of the pipeline elements. The list refers to target pipeline instances in the system under design. According to some aspects and embodiments of the invention, the target list may include all possible pipeline instances or may include only a subset of instances present in some particular subsystem. Logical operations and timing path information are known for each configuration mode. The terms "timing path" and "timing arc" are related in that a timing arc is one of the components of a timing path. A timing arc refers to a path between ports of the same library component. A timing path is a path that traverses multiple instances of a library component.

[0013] Generating an optimized configuration includes performing a search for configurations that optimize area and timing. According to some aspects and embodiments of the present invention, the process prioritizes timing over area. In the search, the process reduces the number of registers (thus saving area) as long as the timing constraints are met. When the process hits a configuration of the pipeline on a path that leads to a timing violation, it stops reducing the relaxation on the path and uses the last configuration without a violation. Thus, according to some aspects and embodiments of the present invention, some optimized configurations are not necessarily optimal, nor are they necessarily the only possible configurations. There may be multiple configurations that satisfy both the timing and area constraints. However, the search quickly finds a configuration that strikes a balance between timing and area.

[0014] In step 110, a complete RTL description is generated with the pipeline components configured according to the optimized pipeline configuration. As used herein, a complete RTL description refers to an RTL description that is accurately synthesized from a very large library of primitives. The method of FIG. 1 has several advantages over conventional methods of generating a complete RTL description. The method of FIG. 1 has greater predictability and significantly reduces the generation time of a complete RTL generation that meets timing and area constraints. The method of FIG. 1 is less computationally intensive. A complete RTL description can be generated only once without modification. Instead of taking hours to generate, a complete RTL description can be generated in a short time, such as a few minutes.

[0015] 1 is not limited to any particular intellectual property (IP) block, but is particularly useful for configurable pipeline components. The following paragraphs describe examples of configurable pipeline components, as well as example computing platforms and computer-implemented methods for generating optimized pipeline configurations.

[0016]

[0023] Referring now to Figure 2, Figure 2 illustrates an example of an architecture for a configurable pipeline component 210. The component 210 includes a control section (Ctl) 220 and a data section (dp) 230. Certain signals associated with the pipeline component 210 will now be described in relation to configuration modes.

[0017] With further reference to Figure 3, Figure 3 illustrates examples of different configuration modes of the pipeline component 210. This particular example illustrates four modes: P00, P01, P10, and P11.

[0018] Mode P00 reflects a transparent or "disabled" mode of the pipeline component 210. Timing paths exist between out_ready and in_ready, and between in_valid and out_valid. There are no timing paths that end within the pipeline component or that start within the pipeline component. Mode P00 has no logical cost.

[0019] Mode P01 has a timing path between out_valid and in_valid, but no timing path between in_ready and out_ready. All timing paths entering from in_ready end within a pipeline module. All timing paths originating from out_ready start within a pipeline component.

[0020] Mode P10 does not have a timing path between out_valid and in_valid, but does have a timing path between in_ready and out_ready.

[0021] Mode P11 reflects a full validity mode. Mode P11 has no timing path between out_ready and in_ready, and no timing path between in_valid and out_valid. Mode P11 has the highest logic cost.

[0022] A pipeline component 210 can be characterized for each mode of configuration by a look-up table (LUT). For each mode, the paths between output ports and registers, the paths from input ports to registers, and the paths between inputs and outputs are described. According to various aspects and embodiments of the invention, a configurable pipeline element 210 has the same port interfaces regardless of its mode. According to some aspects and embodiments of the invention, it is important for the relaxation-based algorithm to have the same port interfaces for a pipeline instance to prevent having to resynthesize the design every time a different implementation mode of the pipeline is attempted.

[0023] In the LUT, the modes are preferably sorted in descending order of the number of registers used. Mode P11 is considered first since it is the mode with the most registers enabled. Mode P00 is considered last since it is the mode with the least registers enabled. This order is called the "relaxation order." For example, the modes in Figure 3 are considered in the following order: mode P11 → mode P01 → mode P10 → mode P00. Starting with mode P11 and moving towards mode P00 is called "progressive relaxation."

[0024] Reference is now made to FIG. 4A, which illustrates LUTs 410, 420, and 430 that characterize an example of a pipeline component having three modes, namely, disabled, mode 1, and mode 2, according to various aspects and embodiments of the present invention. Each path in each LUT 410, 420, and 430 is described in terms of registers and combinational logic. The path type represents the type of timing path. According to some aspects and embodiments of the present invention, there are multiple types of paths: 1) Pi2Po is a direct path between an input port and an output port, 2) Pi2Reg is a path between an input port and a register, and 3) Reg2Po is a path from a register to an output port. The information in LUT 420 is present for documentation / reporting purposes. It is not required by the search algorithm.

[0025] Reference is now made to Figures 4B and 4C. Figure 4B illustrates a pipeline component configured in mode 1 according to various aspects and embodiments of the present invention. Three registers (Reg1, Reg2, and Reg3) are utilized. Figure 4C illustrates a pipeline component configured in mode 2 according to various aspects and embodiments of the present invention. Two registers are utilized. Disabled (not shown) utilizes the least number of registers (zero) and Mode 1 utilizes the most registers. Thus, the order of relaxation is Mode 1 → Mode 2 → Disabled.

[0026]

[0023] Referring now to Figure 5, Figure 5 illustrates a system 510 including multiple configurable pipeline components 520, 530, 540, and 550 between block instances B1, B2, B3, and B4. According to some aspects and embodiments of the present invention, B1, B2, B3, and B4 are instances of any general-purpose data processing module. Figure 5 highlights the fact that it may be necessary to configure pipelines between these blocks to help the system operate at the required frequency.

[0027] The pipeline components of Figures 2-4C and system 510 of Figure 5 are provided merely to facilitate understanding of the following platform and method, as pipeline components having different architectures and modes and LUTs may also be utilized.

[0028] 6 and 7, which illustrate an example of a method of using module 610 to generate an optimized pipeline configuration for an electronics system. A finite set of pipeline configuration options is available to the system.

[0029] 6 illustrates input data processed by module 610. The input data includes a complete RTL description 620 of a design according to various aspects and embodiments of the invention. The RTL description at the input (block 620) includes all components in the system being designed before synthesis. The pipeline modules have not yet been configured. Thus, the design description includes all components and has not yet been synthesized or pipeline components have not yet been configured.

[0030] The input data further includes a list 630 of existing configurable pipeline components in the RTL design, including their names and locations in the design, as well as their parameters used to configure them, and the values ​​of the existing parameters for each. According to some aspects and embodiments of the invention, the list of configurable pipeline elements (block 630) refers to pipeline modules and their instantiations in the system being designed. The configurable pipeline components are instantiated as modules in the RTL description.

[0031] The input data further includes logic operation and timing path information 640 for each configuration mode in accordance with various aspects and embodiments of the present invention. This information may be provided by a LUT that sorts the configuration modes by their order of relaxation.

[0032] The input data further includes synthesis primitives 650 and 660 for delay and area. These synthesis primitives include a basic set of logic gates, flip-flops, etc. These primitives are mapped to the RTL description to calculate the area and delay.

[0033] 6 further illustrates output data generated by module 610. The output data includes a report 670 on timing paths based on the combinatorial delay paths extracted between IOs, between IOs and registers, and between registers. According to some aspects and embodiments of the invention, report 670 provides the evaluated timing paths after all pipelines are configured.

[0034] Delays are synthesized for their delays through logic primitives, not for the wires that connect them, according to various aspects and embodiments of the present invention. This greatly simplifies the logic synthesis process, since no physical information is required about how the components are placed on the system. The output data further includes a report 680 of area numbers on a per cell instance basis. According to some aspects and embodiments of the present invention, the cell instance basis refers to the primitive cells, and since final synthesis with optimization has not been performed at this stage, it only reports the area numbers for the primitive instances (primitive cells), including how many instances are present in the design, such as number of gates, number of muxes, number of registers, etc.

[0035] Finally, the output data further includes, most importantly, a report 690 of all configured pipeline components, which includes, for each configurable pipeline component, the values ​​of each of its configuration parameters. The information in this report 690 is used to generate a complete RTL description.

[0036] Further referring to FIG. 7, FIG. 7 illustrates an example of a method for generating an optimized pipeline configuration. In step 710, a user option is provided to select all pipeline components to be considered for configuration. Not all configurable pipeline components are configured. For example, a user may want to preserve user-explicit configuration of pipeline components. This allows the user to implement their own ideas regarding the configuration space, such as reusing blocks from a previous version of the system. As another example, certain pipeline components may be optional, and some of those optional components may not be selected. All selected pipeline components are considered for configuration.

[0037] In step 720, all pipeline components considered for configuration are fully enabled in accordance with various aspects and embodiments of the present invention. A configurable pipeline component is considered fully enabled when it is configured in the mode that has the most registers. A fully enabled pipeline component achieves the best timing but utilizes the most area.

[0038] At block 730, the baseline RTL description with the fully enabled pipeline is synthesized to generate a set of flow paths that achieves the best timing but utilizes the most area. The synthesis process involves mapping the RTL representation to basic primitive cells, including logic gates and registers. It generates a netlist of connected instances of those primitive cells, which is used by the inventors' method for constructing the pipeline and the associated timing and area evaluation. A large library of complete logic primitives can be used and accurate synthesis can be performed. However, it has been found that using small basic logic primitives significantly reduces processing time while still producing accurate results. The technology libraries used by the synthesis tool can contain thousands of cells that vary in type, size for transistors, drive strength, power consumption, etc. Thus, synthesis mapping and optimization can take hours to map the RTL to a proper gate level representation. According to some aspects and embodiments of the present invention, the process uses a very small set of cells, namely inverters, AND gates, OR gates, Muxes, and registers, and no changes are made since no optimization is required. Various aspects of the present invention simply require a quick mapping onto this small set for a quick assessment of the area and timing required for a pipeline configuration.

[0039] In block 740, path and area delays are calculated from the RTL synthesized using primitives 650 and 660. This step gives the best timing baseline, but the worst area and leakage, since the pipeline is configured in the most register mode.

[0040] In block 750, the worst timing impact but best area is determined for the entire design. This can be done by disabling the pipeline components under consideration. If all paths still meet the timing constraints, a pipeline configuration is found and all pipeline components are disabled. According to some aspects and embodiments of the invention, step 750 refers to a baseline where all timing paths meet the required frequency when all pipeline modules are "disabled". This is a corner case that may not occur in practice, but is still worth checking. According to some aspects and embodiments of the invention, the process performs step 760 if 750 is not called at all. According to some aspects and embodiments of the invention, the process performs step 760 if step 750 does not successfully meet the timing requirements after all pipeline modules are disabled.

[0041] According to some aspects and embodiments of the present invention, the process of step 760 is detailed in FIG. 8 and starts by enabling all pipeline modules. In step 760, if the timing constraints are not met, the valid flow paths in the baseline RTL description are iteratively modified until an optimized pipeline configuration is found according to various aspects and embodiments of the present invention. In general, iteratively modifying the valid flow paths involves reducing the total number of registers while still meeting the timing constraints. With each iteration, the number of registers is further reduced and the area is further reduced (but the timing increases). An example of such an iterative modification is shown in FIG. 8. The modification can be performed incrementally according to various aspects and embodiments of the present invention. That is, the modification is performed in the order of relaxation.

[0042] In step 770, the configured pipeline settings are reported. These settings are used to generate a complete RTL description that points to the final RTL description where all pipeline module instances are configured. Area and timing are also reported in accordance with various aspects and embodiments of the invention. This is related to blocks 670 and 680, which report the impact of timing and area after all pipelines are configured. This accompanying result provides a reference point that may be useful for a designer to know.

[0043] 8 illustrates an example of a method for iteratively modifying flow paths to find an optimized pipeline configuration according to various aspects and embodiments of the present invention. After step 740 is completed, the flow paths are sorted in descending order of their timing length (step 810). An analysis of each path is then performed in descending order as follows:

[0044] In steps 820 and 830, a pipeline component instance is selected and a more relaxed configuration mode for that instance is selected. In steps 840 and 850, timing paths traversing the selected instance are recalculated and analyzed against timing constraints.

[0045] If the constraint is violated (step 860), then the previous less relaxed configuration mode for the selected instance is selected (step 870) and the next pipeline instance in descending order of timing length is selected (step 820).

[0046] If the selected configuration mode does not violate the target frequency (step 860), then the next configuration mode is selected for the instance (step 830) if a more relaxed configuration mode exists (step 880).

[0047] If there is no more permissive configuration mode for the selected instance (step 880), but there are more pipeline instances to consider (step 890), then another pipeline instance is selected (step 820).

[0048] If there are no more pipeline instances to consider (block 890), the search chooses the next timing path to work on. When all timing paths have been processed (all pipelines along those paths have been configured), the final pipeline configuration is reported (step 770).

[0049]

[0036] Referring now to Figure 9, Figure 9 illustrates an example of components of a computing platform 910 for performing the methods herein. The computing platform 910 includes a memory 920 and a processing unit 930. The memory 920 stores instructions 940 that, when executed, cause the processing unit 620 to generate an optimized pipeline configuration, and optionally generate a complete RTL description having the optimized pipeline configuration. Examples of computing platforms 910 include, but are not limited to, workstations, laptops (Windows, MacOS), servers, and cloud computing.

[0050] The methods and platforms disclosed herein are not limited to any particular electronic system, examples of possible systems include, but are not limited to, any electronic system made of reconfigurable pipeline components.

[0051] Consider an example of an SoC 1010 including a NoC 1020 as shown in Figure 10 according to various aspects and embodiments of the present invention. The SoC includes multiple initiators and targets such as video, a central processing unit (CPU), a camera, a direct memory access (DMA), a random access memory (RAM), a dynamic random access memory (DRAM), input / output (IO), and a hard disk drive (HDD). The NoC 1020 provides packet-based communication between the initiators and targets.

[0052] The NoC 1020 of FIG. 10 includes a network interface unit (NIU) 1030 that is responsible for translating several supported protocols and data sizes to and from the packet transport architecture. The NoC further includes switches, width adapters, firewalls, clock adapters, and individual pipeline registers. These components allow the creation of various network topologies (mesh, ring, etc.), accommodate data widths and packet styles, and are parameterized to enable / disable certain features based on the user's requirements. Configurable pipeline components are available in many places within the NIU unit as individual blocks. The parameterizable and configurable pipeline components of the NoC 1020 can be configured according to the methods herein.

[0053] 11, which illustrates an example of a layered NIU 1030 having multiple pipeline components in accordance with certain aspects and embodiments of the present invention. Pipeline components are used in the native layer 1110, the common layer 1120, and the packet layer 1130. In accordance with certain aspects and embodiments of the present invention, the common layer 1120 includes a partial address map (PAM) that defines an address space for the NIU initiator in terms of which target NIU to communicate with, and other related routing information. Each of these pipeline components can be configured in accordance with the methods herein.

[0054] Embodiments according to the invention may be embodied as an apparatus, a method, or a computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be referred to broadly herein as a "circuit," "module," or "system." Additionally, embodiments of the present invention may take the form of a computer program product embodied in any tangible medium.

[0055] Any combination of one or more computer usable or computer readable media may be utilized. For example, the computer readable medium may include one or more of a portable computer diskette, a hard disk, a random access memory (RAM) device, a read only memory (ROM) device, an erasable programmable read only memory (EPROM or flash memory) device, a portable compact disk read only memory (CDROM), an optical storage device, and a magnetic storage device. Computer program code for carrying out the operations of the present invention may be written in any combination of one or more programming languages. Such code may be compiled from source code into a computer readable assembly language or machine code suitable for the device or computer that executes the code.

[0056] Embodiments may be implemented in a cloud computing environment. For purposes of this specification and the following claims, "cloud computing" may be defined as a model for enabling ubiquitous and convenient on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned via virtualization, released with minimal management effort or service provider interaction, and then scaled accordingly.

[0057] It should be noted that although specific examples have been described herein, different combinations of different components from different examples may be possible. Although salient features have been presented to better explain the examples, it will be apparent that certain features can be added, modified, and / or omitted without changing the functional aspects of these examples as described.

[0058] Various examples are methods that use any or combination of machine behaviors. Examples of methods are completed wherever in the world most configuration steps are performed. For example, according to various aspects and embodiments of the present invention, an IP element or unit includes a processor (e.g., CPU or GPU), random access memory (e.g., RAM such as off-chip dynamic RAM or DRAM), network interfaces for wired or wireless connections such as Ethernet, WiFi, 3G, 4G Long Term Evolution (LTE), 5G, and other wireless interface standard radios. The IP can include various I / O interface devices for various peripheral devices such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (such as keyboards and mice, among others), as needed. By executing instructions stored in the RAM device, the processor performs the steps of the methods described herein.

[0059] Some examples are one or more non-transitory computer-readable media configured to store such instructions for the methods described herein. Any machine that holds a non-transitory computer-readable medium containing any of the necessary code can perform an example. Some examples may be implemented as a physical device such as a semiconductor chip, a hardware description language representation of the logical or functional behavior of such a device, and one or more non-transitory computer-readable media configured to store such a hardware description language representation. The descriptions herein that recite principles, aspects, and embodiments encompass both their structural and functional equivalents. Elements described herein as "coupled" have an effective relationship that may be realized by a direct connection or indirectly by one or more other intervening elements.

[0060] Those skilled in the art will appreciate that various other modifications may be made to the device without departing from the spirit and scope of the present invention, particularly the various programmable features. All such modifications and variations are intended to be within the scope of the appended claims and to be protected by the claims. Moreover, those skilled in the art will recognize numerous modifications and variations. The modifications and variations include any relevant combination of the disclosed features. The descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that may be achieved by a direct connection or an indirect connection using one or more other intervening elements. An embodiment described herein as "communicating" or "in contact" with another device, module, or element includes any form of communication or link and includes an effective relationship. For example, a communication link may be established using a wired connection, a wireless protocol, a short-range wireless protocol, or radio frequency identification (RFID).

[0061] All illustrations in the drawings are for the purpose of illustrating selected versions of the invention and are not intended to limit the scope of the invention. Thus, the scope of the invention is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the invention is embodied by the claims.

Claims

1. A method for a computer to generate a complete register transfer level (RTL) description of an electronic device system, the method comprising: generating an optimized pipeline configuration from inputs including a database of RTL elements and a list of configurable pipeline components, said generating a configuration including performing a search for configurations that optimize area and timing; generating the complete RTL description with the pipeline components configured according to the optimized pipeline configuration; performing the search generating a baseline RTL description that configures the pipeline as fully enabled to generate a set of flow paths with the best timing; eliminating flowpaths selected from the set of flowpaths that do not satisfy timing constraints of the description; and iteratively modifying valid flow paths of the baseline RTL description until an optimized pipeline configuration is found.

2. 2. The method of claim 1, wherein the list of configurable pipeline elements identifies different configuration modes for each pipeline element, and the input further includes timing path information for each configuration mode.

3. 2. The method of claim 1, wherein the baseline RTL description is generated from a library of base logic primitives, and flow path delays and pipeline areas are synthesized by mapping the baseline RTL description to the logic primitives.

4. The method of claim 3 , wherein the flow path delay takes into account delays through the logic primitives.

5. 4. The method of claim 3, wherein iteratively modifying comprises modifying the effective flow paths by progressive relaxation of the configuration, where all of the pipeline components that are fully enabled are least relaxed and all of the pipeline components that are fully disabled are most relaxed.

6. The method of claim 1 , wherein generating the baseline RTL description comprises retaining user-explicit configurations of pipeline components and configuring remaining pipeline components.

7. The method of claim 1 , wherein iteratively modifying the valid flow paths comprises reducing a total number of registers while still meeting timing constraints.

8. The target parameters include frequency, Modifying the flow path by gradual relaxation sorting the paths in descending order of their timing length; selecting each of said paths for analysis, beginning with said path having the longest timing length, said analysis of each selected path comprising: analyzing the selected path against a target clock frequency, and if the selected path does not violate the target clock frequency, then selecting a pipeline component instance and selecting a more permissive configuration mode for the selected instance; recalculating timing paths that traverse the selected instances; re-instantiating a previous, less lenient configuration mode if the selected path violates a target clock frequency; If the selected configuration mode does not violate the target clock frequency and if a more lenient configuration mode exists, save the selected instance.

8. The method of claim 7, further comprising looping through instances of pipeline components along the selected path by:

9. 2. The method of claim 1 , wherein the electronics system includes a network-on-chip (NoC), at least some of the configurable pipeline components are associated with the NoC, and the complete RTL description includes an NoC pipeline configured according to the optimized configuration.

10. A computer implemented method for generating an optimized pipeline configuration for an electronics system, comprising: accessing a database of register transfer level (RTL) elements, a list of configurable pipeline components for said electronics system, and timing path information and timing constraints for each configuration mode of each configurable pipeline component; generating a baseline RTL description of the system from the RTL elements with all of the configurable pipeline components fully enabled; eliminating flow paths that do not satisfy the timing constraints of said description; and iteratively modifying the configuration of said pipeline components within valid flow paths in a relaxation order until an optimized pipeline configuration is found.

11. The method of claim 10 , wherein timing is optimized for area.

12. 11. The method of claim 10, wherein iteratively modifying comprises modifying the effective flow path by progressive relaxation of the configuration until a target parameter is met, where all of the pipeline components that are fully enabled are least relaxed and all of the pipeline components that are fully enabled are most relaxed.

13. 11. The method of claim 10, wherein the electronics system includes a network-on-chip (NoC), at least some of the configurable pipeline components are associated with the NoC, and the complete RTL description includes an NoC pipeline configured according to the optimized configuration.

14. A processing unit; When executed, the processing unit: accessing a database of register transfer level (RTL) elements, a list of configurable pipeline components for the electronics system, and timing path information and timing constraints for each configuration mode of each configurable pipeline component; generating a baseline RTL description of the electronic device system from the RTL elements with all of the configurable pipeline components fully enabled; eliminating flow paths that do not satisfy the timing constraints of said description; Iteratively modifying the configuration of the pipeline components within a valid flow path in a relaxation order until an optimized pipeline configuration is found. A memory that stores executable instructions; A computing platform comprising:

15. The computing platform of claim 14 , wherein timing is optimized for area.

16. 15. The computing platform of claim 14, wherein iteratively modifying comprises modifying the effective flow paths by progressive relaxation of the configuration until target parameters are met, where all of the pipeline components that are fully enabled are least relaxed and all of the pipeline components that are fully enabled are most relaxed.

17. 15. The computing platform of claim 14, wherein the electronics system includes a network-on-chip (NoC), at least some of the configurable pipeline components are associated with the NoC, and the description includes an NoC pipeline configured according to the optimized configuration.

18. 15. The computing platform of claim 14, wherein the executable instructions further cause the computing platform to generate a complete RTL description of the electronics system with the pipeline components configured according to the optimized pipeline configuration.

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