Method, device, processor, computer device, and computer program for processing multiple input floating-point numbers

Abstract

A method for processing multiple-input floating-point numbers executed by a computer device includes the steps of: acquiring a plurality of floating-point numbers to be processed corresponding to a target task, and extracting an exponent value of an exponent part and a mantissa value of a mantissa part of each floating-point number (S102); sorting the plurality of floating-point numbers according to the magnitude of the exponent value of each floating-point number, acquiring a sorting result, and assigning a shift unit from a plurality of shift units having different predetermined numbers of bits to each floating-point number based on the sorting result (S104); performing a shift process on the mantissa value of the corresponding floating-point number by the shift unit assigned to the floating-point number for each floating-point number, and acquiring a shift result (S106); and determining a floating-point number processing result corresponding to the target task based on each shift result (S108).

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application filed on December 29, 2021, bearing application number 2021116348560 and entitled "Method, apparatus, processor and computer equipment for processing multi-input floating-point numbers," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the technical field of data processing, and more particularly to a method, apparatus, processor, computer device and storage medium for processing multiple-input floating-point numbers. [Background technology]

[0003] With the development of computer technology, AI (Artificial Intelligence) technology is also developing rapidly. In the field of AI technology, AI algorithms are usually realized by AI processors. In AI processors, the matrix calculation unit is the core data processing device, and the performance and computing power of the matrix calculation unit directly determine the superiority or inferiority of the AI ​​processor's performance. Meanwhile, in matrix calculation units, the multi-input floating-point calculation unit is the key to determining the superiority or inferiority of performance.

[0004] In the conventional multi-input floating-point number arithmetic method, in order to achieve the goal of eliminating intermediate precision loss, the bit width of the shifted data is very wide, so multiple high-bit (digit) shifting units are usually required to reduce intermediate precision loss. If the shift range is too large, the hardware overhead becomes large, and the processor needs to occupy more hardware resources. Summary of the Invention

[0005] SUMMARY OF THE PRESENT EMBODIMENTS Embodiments of the present invention provide a method, apparatus, processor, computer device and storage medium for multi-input floating-point number processing.

[0006] In one embodiment of the present invention, a method for processing multiple-input floating-point numbers executed by a computing device is provided, the method including the steps of: acquiring a plurality of floating-point numbers to be processed corresponding to a target task, and extracting an exponent value of an exponent part and a mantissa value of a mantissa part in each floating-point number; sorting the plurality of floating-point numbers according to the magnitude of the exponent value of each floating-point number, acquiring a sorting result, and assigning a shift unit to each floating-point number from a plurality of shift units having different predetermined bit numbers based on the sorting result; for each floating-point number, a shift process is performed on the mantissa value of the corresponding floating-point number by the shift unit assigned to the floating-point number, acquiring a shift result; and determining a floating-point number processing result corresponding to the target task based on each of the shift results.

[0007] In one embodiment of the present invention, a multi-input floating-point processing device is provided, the device including: an acquisition module that acquires a plurality of floating-point numbers to be processed corresponding to a target task, and extracts an exponent value of an exponent part and a mantissa value of a mantissa part of each floating-point number; an allocation module that sorts the plurality of floating-point numbers according to the magnitude of the exponent value of each floating-point number, acquires a sorting result, and assigns a shift unit to each floating-point number from a plurality of shift units having different predetermined bit numbers based on the sorting result; a shift module that, for each floating-point number, performs a shift process on the mantissa value of the corresponding floating-point number using the shift unit assigned to the floating-point number, and acquires a shift result; and a determination module that determines a floating-point number processing result corresponding to the target task based on each of the shift results.

[0008] In one embodiment of the present invention, a processor is provided that includes at least one shift unit having a different predetermined number of bits, each shift unit being assigned to perform a shift operation on a mantissa value of a mantissa part of one of a plurality of floating-point numbers to be processed, and the shift unit assigned corresponding to each floating-point number is determined based on a rearrangement result obtained by rearranging the exponent values ​​of the exponent part of each floating-point number according to their magnitudes, and a logic processing unit that performs logic processing on the multiple shift results obtained by each shift unit performing the shift operation, to obtain a floating-point number processing result.

[0009] In one embodiment of the present invention, there is provided a computing device including a memory having computer readable instructions stored thereon and a processor, the processor implementing the steps of the above method when executing the computer readable instructions.

[0010] In one embodiment of the present invention, a computer readable storage medium having a computer program stored thereon is provided, the computer program implementing the steps of the above method when executed by a processor.

[0011] In one embodiment of the invention there is provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of the above method.

[0012] The details of one or more embodiments of the invention are set forth in the drawings and description which follow. Other features, objects, and advantages of the invention will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic flow diagram illustrating a method for multi-input floating-point number processing in accordance with one or more embodiments. [Diagram 2] FIG. 2 is a schematic diagram of a floating-point number format in accordance with one or more embodiments. [Diagram 3] 1 is a schematic flow diagram illustrating a step of allocating a shift unit according to one or more embodiments; [Figure 4] 1 is a schematic flow diagram illustrating steps of a shifting process in accordance with one or more embodiments. [Diagram 5] 11 is a schematic flow diagram illustrating steps of a shifting process in accordance with one or more alternative embodiments. [Figure 6] 10 is a schematic flow diagram illustrating the steps of determining a floating-point processing result corresponding to a target task based on each shift result according to one or more embodiments. [Figure 7] 1 is a schematic flow diagram illustrating steps of a segment compression process in accordance with one or more embodiments. [Figure 8] FIG. 2 is a schematic diagram illustrating the principle of a segment compression process according to one or more embodiments. [Figure 9] 1 is a schematic flow diagram illustrating the steps of determining a floating-point processing result corresponding to a target task based on a plurality of segment compression results according to one or more embodiments. [Figure 10] 1 is a schematic flow chart illustrating steps of a selection unit outputting a selection result according to one or more embodiments. [Figure 11] 1 is a schematic flow diagram illustrating steps of performing a normalization process on a floating-point processing result in accordance with one or more embodiments. [Figure 12] 1 is a schematic flowchart illustrating conventional addition of multiple floating-point numbers in accordance with one or more embodiments. [Figure 13] FIG. 2 is a schematic diagram illustrating a data bit width configuration according to one or more embodiments. [Figure 14] 1 is a schematic flow chart illustrating the present invention applied to adding multiple floating point numbers in accordance with one or more embodiments. [Figure 15]1 is a block diagram illustrating a configuration of a multi-input floating-point number processing device according to one or more embodiments. [Figure 16] FIG. 1 is a block diagram illustrating a configuration of a processor in accordance with one or more embodiments. [Figure 17] FIG. 2 is a block diagram illustrating a logic processor configuration in accordance with one or more embodiments. [Figure 18] FIG. 1 is a diagram illustrating the internal configuration of a computer device according to one or more embodiments. To better explain the embodiments and / or aspects of the invention disclosed herein, reference may be made to one or more drawings. Additional details or aspects used to explain the drawings should not be considered as limiting the scope of the disclosed invention, either of the currently described embodiments and / or aspects, or the best mode of these inventions as currently understood. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In order to make the object, technical means and advantages of the present invention more clearly understood, the present invention will be described in more detail below with reference to the drawings and examples. Note that the specific examples described in this specification are merely for the purpose of illustrating the present invention and are not intended to limit the present invention.

[0015] The present invention provides a method, apparatus, processor, computer equipment, storage medium, and computer program product for processing multi-input floating-point numbers, which not only enables efficient processing of multiple floating-point number operations by optimizing the floating-point number operation method and corresponding processing logic, but also reduces the area of ​​the shift section, efficiently reduces the area of ​​the AI ​​processor, reduces the critical path in a time series, improves the main frequency of the AI ​​processor, and provides higher computing power for a single chip to which an AI processor is applied.

[0016] In some embodiments, as shown in FIG. 1, a method for processing a multi-input floating-point number is provided. In this embodiment, the method is applied to a computer device as an example. The computer device may be a terminal or a server. Here, the server may be an independent physical server, a server cluster or a distributed system configured by a plurality of physical servers, or a cloud server providing a cloud computing service. The terminal may be one or more of various personal computers, laptop computers, smartphones, tablets, IoT (Internet of Things) devices, portable wearable devices, etc., but is not limited thereto. The IoT device may be one or more of a smart speaker, a smart TV, a smart air conditioner, or a smart in-vehicle device. The portable wearable device may be one or more of a smart watch, a smart wristband, or a headset. For example, the method for processing a multi-input floating-point number according to the embodiment of the present invention may be applied to a data processing device in a computer device, such as a processor or a sensor.

[0017] In this embodiment, the method includes the following steps.

[0018] Step S102: Obtain a plurality of floating-point numbers to be processed corresponding to the target task, and extract an exponent value of the exponent part and a mantissa value of the mantissa part in each floating-point number respectively.

[0019] Here, the target task is a computation task that a computer device executes to achieve a certain goal, and the computation includes, but is not limited to, mathematical operations such as addition, subtraction, multiplication, or division. For example, the target task may be a computation task in the process of training a neural network, including, but not limited to, a convolution addition task or a similarity calculation task. As another example, the target task may be a cloud computing or distributed computing task for calculating multiple data.

[0020] Floating-point numbers are a numeric representation of a certain subset of rational numbers, and are used to approximately represent any real number in a computer. For example, the currently popular floating-point format generally conforms to the IEEE Standard for Binary Floating-Point Arithmetic (ANSI / IEEE Std 754-1985, commonly abbreviated as IEEE 754) established by the Microprocessor Standards Committee (MSC).

[0021] The IEEE 754 standard specifies a specific standard for storing decimal floating-point numbers in binary form in computer memory, and specifies four ways of representing floating-point values: single precision floating-point numbers, double precision floating-point numbers, extended single precision floating-point numbers, and extended double precision floating-point numbers.

[0022] As shown in FIG. 2, IEEE 754 represents a floating-point number as three parts: a sign, an exponent, and a mantissa. Here, the sign S is used to indicate whether the floating-point number is a positive number or a negative number. "0" indicates that the floating-point number is a positive number, and "1" indicates that the floating-point number is a negative number. The exponent value E (usually also called the exponent) in the exponent part is represented by a shift code (also called an addition code or a bias code). Taking a 32-bit single-precision floating-point number as an example, the exponent value E has a range of 8 bits (bits) and represents an exponent value from 0 to 255. The exponent value indicates the position of the decimal point. The mantissa value M of the mantissa part of the floating-point number is represented by a sign magnitude. Similarly, taking a 32-bit single-precision floating-point number as an example, the mantissa value M has a range of 24 bits and determines the precision of the real number that the floating-point number can represent. Note that because the most significant bit of the sign magnitude is always a significant bit (i.e., it must be 1), computer memory typically omits (or hides) the most significant bit of the mantissa to conserve memory. This allows 24-bit information to be represented by the 23-bit mantissa shown in the figure.

[0023] For ease of explanation and ease of understanding, the examples set forth in the following embodiments comply with the IEEE 754 standard, but should not be construed as limiting the scope of the embodiments of the present invention.

[0024] In some embodiments, the floating point numbers to be processed are stored in a memory, which may be an internal memory provided in the computing device or an external memory separate from and in communication with the computing device.

[0025] Specifically, the computer device retrieves two or more floating-point numbers to be processed from a memory, and extracts an exponent value of the exponent part and a mantissa value of the mantissa part of each floating-point number according to the format of the floating-point number, where the exponent value is used to rearrange the subsequent floating-point numbers to determine the size of the shift part assigned to each floating-point number, and the mantissa value is the part specifically used for performing the shift process.

[0026] Still taking a 32-bit single-precision floating-point number as an example, the computer device extracts a value corresponding to the 31st bit (the most significant bit) as the value of the sign bit, extracts values ​​corresponding to the 30th bit to the 23rd bit as the exponent value of the exponent part, and extracts a value corresponding to the 22nd bit to the 0th bit (the least significant bit) as the mantissa value of the mantissa part. As described above, the computer device expresses the mantissa value by hiding the most significant bit 1 of the mantissa part, so the number of bits extracted by the computer device is from the 22nd bit to the 0th bit.

[0027] Step S104: sorting the multiple floating-point numbers according to the magnitude of the exponent value of each floating-point number to obtain sorting results, and assigning a shift unit to each floating-point number from multiple shift units having different predetermined bit numbers based on the sorting result.

[0028] Since the exponent values ​​of the floating-point numbers are different, the dimensions of the floating-point numbers may not match. In order to realize the calculation of floating-point numbers, it is first necessary to unify the different floating-point numbers into the same dimension. Here, a plurality of shift units (shifters) are provided to realize the shift processing for each floating-point number so that each floating-point number has the same dimension. The number of shift units is determined based on the number of floating-point numbers. For example, the number of shift units may be the same as the number of floating-point numbers. As another example, since the floating-point number corresponding to the maximum value of the exponent value does not require the shift processing, the number of shift units may be the number of floating-point numbers minus 1 in order to reduce the overhead of the required hardware resources.

[0029] Each shifting unit is preset with a different number of bits, and the predetermined number of bits of each shifting unit includes the maximum range of the mantissa value and the maximum shiftable range when the shifting unit performs the shifting process. For example, the number of bits of a 50-bit shifting unit is 50 bits, and the mantissa value is a maximum of 24 bits, so that the maximum shiftable range w of the shifting unit is 26 bits, excluding the space occupied by the mantissa value. In the subsequent shifting process, the shifting unit shifts the mantissa value within its maximum shiftable range.

[0030] In order to reduce the hardware overhead as much as possible, in some embodiments, the different predetermined bit numbers of the multiple shifting units are within a first predetermined range, and the predetermined bit numbers of each shifting unit are evenly distributed within the first predetermined range. Specifically, the maximum number of the predetermined bit numbers of the multiple shifting units is set to the first predetermined range, and the shift ranges of the remaining shifting units are all within the first predetermined range. The predetermined bit numbers of each shifting unit may be evenly distributed, may increase or decrease by a certain multiple, or may be distributed in an arithmetic or geometric progression. For example, a number of q (e.g., q=24bit+wbit, w=26)-bit shifting units, b number of 2*w-bit shifting units, c number of 3*w-bit shifting units, ...x number of n*w-bit shifting units are provided in advance, where the value of n is the number of floating-point numbers minus 1.

[0031] For the purpose of distinction, in the embodiment of the present invention, the range in which the predetermined number of bits of the shifting unit is located is referred to as the first predetermined range, and the range in which the value of the compression ratio of the compression unit is located is referred to as the second predetermined range. Note that the above terms "first" and "second" are used in this specification to describe different numerical ranges, but these numerical ranges should not be limited by these terms. These terms are used only to distinguish one numerical range from another numerical range. For example, without departing from the scope of various described embodiments, the first predetermined range may be referred to as the second predetermined range, and similarly, the second predetermined range may be referred to as the first predetermined range, and both mean different ranges unless explicitly indicated by the context. The same applies to the following first area segment, second area segment and third area segment, first code identifier and second code identifier, first shift direction and second shift direction, etc.

[0032] Specifically, after obtaining the exponent value of each floating-point number, the computer device sorts each floating-point number according to the magnitude of the exponent value of each floating-point number to obtain the sorting result. For example, the computer device sorts each floating-point number in ascending order of exponent value to obtain the sorting result. Also, for example, the computer device sorts each floating-point number in descending order of exponent value to obtain the sorting result. Since the floating-point number with the largest exponent value does not require a shift process, the computer device assigns one shift unit to each of the remaining floating-point numbers in sequence based on the sorting result of the floating-point numbers obtained, except for the floating-point number with the largest exponent value.

[0033] In the above embodiment, by assigning different shift units to different floating-point numbers, the hardware overhead is significantly reduced, the timing characteristics are good, and the efficiency is high compared to the prior art in which shift processing is performed using multiple shift units of the same number of bits regardless of the size of each floating-point number.

[0034] In some other embodiments, the different predetermined bit numbers of the multiple shifting units may be distributed unevenly in the first predetermined range. For example, in the first predetermined range, the predetermined bit number of one shifting unit is q bits, and the predetermined bit number of each of the remaining shifting units is n*w bits. As another example, in the first predetermined range, the predetermined bit number of each shifting unit increases or decreases exponentially. Also, for example, in the first predetermined range, the predetermined bit number of each of the x shifting units is the same, and tends to increase or decrease overall.

[0035] Step S106: For each floating-point number, a shift unit assigned to the floating-point number performs a shift process on the mantissa value of the corresponding floating-point number to obtain a shift result.

[0036] Specifically, the computer device obtains a shift result of one floating-point number by performing a shift process on the mantissa value of the floating-point number within a predetermined number of bits of the shift unit using a shift unit assigned to the floating-point number. Since the floating-point number having the largest exponent value does not require a shift process, the computer device performs a shift process using the shift units assigned to each of the remaining floating-point numbers, respectively, to obtain a plurality of shift results.

[0037] Here, the shift process means moving the mantissa value by a certain distance in a certain shift direction. The shift direction includes a left shift or a right shift. The number of bits moved in the shift process is the difference between the floating-point number and the maximum value of the floating-point number. For example, for a floating-point number A, if the difference between its exponent value and the maximum exponent value is b, the computer device shifts the mantissa value of the floating-point number A to the left or right by b bits. Here, the maximum exponent value is the maximum value of the exponent values ​​of the multiple floating-point numbers.

[0038] Step S108: Determine a floating-point processing result corresponding to the target task based on each shift result.

[0039] Specifically, after the shift is completed, the computer device may perform subsequent processing according to a specific target task. Specifically, based on the shift results corresponding to each floating-point number, compression processing may be performed sequentially on each shift result to obtain a compression result. Then, the computer device performs post-processing on the compression result to obtain a floating-point number processing result corresponding to the target task. Here, the post-processing includes normalization processing and rounding processing, etc. For example, in the post-processing, normalization processing is performed on the compression result so that the compression result conforms to a format specified by IEEE 754, and a final floating-point number processing result is obtained by rounding.

[0040] In the above multi-input floating-point processing method, a plurality of shift units having different predetermined bit numbers are designed in advance, and when a plurality of floating-point numbers to be processed are processed, the plurality of floating-point numbers are rearranged according to the magnitude of the exponent value of each floating-point number, and a corresponding shift unit is assigned to each floating-point number from a plurality of shift units having different predetermined bit numbers based on the rearrangement result, and the assigned shift unit is used to perform shift processing on the plurality of floating-point numbers, and a floating-point processing result corresponding to the target task is obtained based on the shift processing result. This introduces the idea of ​​effective shifting, performs effective shifting on the lower mantissa value after rearrangement, ensures that the shift range of the upper mantissa value is small (sometimes there is no need to move), and there is no intermediate precision loss, and greatly reduces the area overhead of the shift unit, saves the hardware overhead of the processor, and when hardware resources are limited, can achieve good compatibility between the processing efficiency and accuracy of floating-point numbers.

[0041] As described above, in some embodiments, the number of the plurality of shifting units is the same as the number of the plurality of floating-point numbers. As shown in Fig. 3, the step of respectively allocating a shifting unit from the plurality of shifting units having different predetermined bit numbers to each floating-point number based on the rearrangement result includes the following steps:

[0042] Step S302: A sorting number for each floating-point number in the sorting result is determined.

[0043] Step S304: Determine a predetermined number of bits corresponding to each permutation number, and assign the multiple shift units to the floating-point numbers designated by the permutation numbers corresponding to the corresponding predetermined number of bits according to the respective predetermined number of bits.

[0044] Specifically, the computer device determines a sorting number to which each floating-point number belongs based on the sorting result of each floating-point number. The sorting number indicates the position of the floating-point number in the sorting result. A corresponding predetermined number of bits is preset for each sorting number, for example, the first sorting number corresponds to an x-bit shift part, and the second sorting number corresponds to a y-bit shift part. For one floating-point number, the computer device determines a shift part having the predetermined number of bits based on the predetermined number of bits corresponding to the sorting number to which the floating-point number belongs. This allows the computer device to determine a correlation between the floating-point number and the shift part, and assign the shift part to process the floating-point number.

[0045] For example, the first floating-point number in the sorting result does not need to be shifted, the second floating-point number is assigned a q-bit shift part, the third floating-point number is assigned a 2q-bit shift part, and so on for the floating-point numbers other than the first floating-point number.

[0046] In this embodiment, by assigning different shifting units to different floating-point numbers, the hardware overhead is significantly reduced, and the timing characteristics are good and the efficiency is high.

[0047] After allocating the shift unit corresponding to each floating-point number, the computer device performs a shift operation on the floating-point number using the shift unit. Here, in the shift operation process, the number of bits by which the shift unit shifts the mantissa value of the floating-point number may be determined based on the difference between the exponent value and the maximum exponent value. To this end, in some embodiments, as shown in FIG. 4, for each floating-point number, the step of performing a shift operation on the mantissa value of the corresponding floating-point number by the shift unit allocated to the floating-point number to obtain a shift result includes the following steps:

[0048] Step S402: Determine a shift bit number corresponding to each mantissa value of each floating-point number based on a respective difference between an exponent value of each floating-point number and a maximum exponent value, respectively, where the maximum exponent value is the maximum value among the exponent values ​​of the multiple floating-point numbers.

[0049] Step S404: For each floating-point number, a shift unit assigned to the floating-point number performs a shift process on the mantissa value of the corresponding floating-point number based on the number of shift bits corresponding to the mantissa value of the corresponding floating-point number, and obtains a shift result.

[0050] Specifically, the computer device determines the number of shift bits corresponding to each mantissa value of each floating-point number based on the difference between the exponent value of the floating-point number and the maximum exponent value, and performs a shift process according to the determined number of shift bits using a shift unit assigned to the floating-point number, where the difference may be the difference between the exponent value and the maximum exponent value, the ratio between the exponent value and the maximum exponent value, or a multiple of the difference between the exponent value and the maximum exponent value.

[0051] For example, the exponent value E1 and the maximum exponent value E of floating-point number A are maxIf the difference between the maximum exponent value E and the maximum exponent value E is x, the computer device determines that the number of shift bits corresponding to the mantissa value M1 of the floating-point number A is x bits. After determining the number of shift bits, the computer device shifts the mantissa value of the floating-point number by x bits using the shift unit assigned to the floating-point number to obtain a shift result of the floating-point number. max (which does not need to be shifted), the shift operation is performed on each remaining floating-point number to obtain multiple shifted results.

[0052] In this embodiment, by allocating different shift units to different floating-point numbers, it is possible to significantly reduce the hardware overhead and save the resources of the shift units required for the shift process.

[0053] In the shifting process, the determined number of shift bits may be greater than the predetermined number of bits of the shifting unit. Here, in some embodiments, as shown in FIG. 5, for each floating-point number, the step of performing a shifting process on the mantissa value of the corresponding floating-point number by the shifting unit assigned to the floating-point number according to the number of shift bits corresponding to the mantissa value of the corresponding floating-point number to obtain a shift result includes the following steps:

[0054] Step S502: For each floating-point number, determine whether a shift bit number corresponding to a mantissa value of the floating-point number is within a shift range, where the shift range corresponds to a predetermined number of bits of a shift part allocated to the floating-point number.

[0055] Step S504: If the number of shift bits is within the shift range, the shift unit assigned to the floating-point number moves each mantissa element constituting the mantissa value of the floating-point number in the corresponding shift range in the same shift direction by the number of shift bits, where the shift direction includes a left shift or a right shift.

[0056] Step S506: If the number of shift bits is outside the shift range, the shift unit assigned to the floating-point number moves each mantissa element constituting the mantissa value of the floating-point number by a predetermined number of bits in the same shift direction.

[0057] Step S508: The mantissa values ​​obtained by performing the shift process on each floating-point number are regarded as the shift results of each floating-point number.

[0058] Specifically, the computer device executes the above step S502 to obtain, for one floating-point number, a shift bit number corresponding to the mantissa value of the floating-point number. At the same time, the computer device determines a shift unit assigned to the floating-point number and obtains a predetermined bit number of the shift unit. The computer device compares the shift bit number with the predetermined bit number to determine whether the shift bit number is within a shift range corresponding to the predetermined bit number. If the shift bit number is within the shift range, the computer device shifts the mantissa value by the shift bit number in the shift direction using the shift unit. If the shift bit number is outside the shift range, the computer device shifts the mantissa value by the predetermined bit number in the shift direction using the shift unit. After performing a shift process on the mantissa value of the floating-point number, the computer device sets the obtained mantissa value as the shift result of the floating-point number. The computer device performs the above shift process on each remaining floating-point number except for the floating-point number corresponding to the maximum exponent value (which does not need to be shifted), to obtain multiple shift results.

[0059] For example, for a floating-point number A, the computer device determines that the number of shift bits corresponding to the mantissa value M1 is 22 bits, and the shift section S assigned to the floating-point number A is 16 bits. A In this case, the computer device determines that the number of shift bits of the floating-point number A is 50 bits, that is, the shift range is 26 bits. A In order to determine that the shift unit S is within the shift range of the Ais used to shift each mantissa element of the mantissa value of floating-point number A by 22 bits in the same shift direction, for example, to the right by 22 bits.

[0060] For example, for the floating-point number B, the computer device determines that the number of shift bits corresponding to the mantissa value M2 is 56 bits, and the shift unit S assigned to the floating-point number B is 16 bits. B The predetermined number of bits of the floating-point number B is 76 bits, that is, the shift range is determined to be 52 bits. In this case, the computer device determines that the number of shift bits of the floating-point number B is the shift range of the shift section S. B In other words, the number of bits to be shifted of the floating-point number B is outside the shift range of the shift part S. B Therefore, the computer device determines that the shift unit S B is used to shift each mantissa element of the mantissa value of the floating-point number B by 52 bits in the same shift direction.

[0061] In this embodiment, by performing shift processing using a shift unit that assigns different predetermined numbers of bits to each floating-point number, there is no need to use a shift unit with a relatively large bit width to ensure no loss of intermediate precision, which saves hardware resources in the shift unit and reduces the area overhead of the shift unit.

[0062] As described above, after determining the shift results of the plurality of floating-point numbers, the computer device performs compression processing on the floating-point numbers. In order to reduce the area of ​​the compression unit used and reduce the timing path, in some embodiments, as shown in Figure 6, the step of determining the floating-point processing result corresponding to the target task according to each shift result includes the following steps:

[0063] Step S602: According to a first predetermined range in which shift parts with different predetermined bit numbers are located, divide the first predetermined range to obtain a plurality of area segments, and determine a plurality of compression parts respectively corresponding to the plurality of area segments, where the different compression parts have different predetermined compression ratios.

[0064] The compression ratio means the ratio between the number of inputs and the number of outputs of a compressor. For example, a compressor with a preset compression ratio of (n:2) has n inputs and 2 outputs. As another example, a compressor with a preset compression ratio of (n:3) has n inputs and 3 outputs.

[0065] In some embodiments, the different predetermined compression ratio values ​​of the multiple compressors are within a second predetermined range, and the predetermined compression ratio values ​​of each compressor are evenly distributed within the second predetermined range. The second predetermined range is obtained based on a number of floating-point numbers. Specifically, the compression ratios of the preset compressors are within a second predetermined range, with (n:2) being determined as the maximum value of the range. The second predetermined range includes, for example, (n-1):2, (n-2):2, etc., where n is a number of floating-point numbers.

[0066] Specifically, the computer device divides a first predetermined range in which each shifting unit having a different predetermined number of bits is located to obtain a plurality of region segments. For example, the computer device determines a range from the most significant bit to the maximum predetermined number of bits according to the maximum predetermined number of bits between each shifting unit, and divides the range equally into a plurality of region segments, where the range of each region segment is equal.

[0067] For example, in a compression process having four floating point numbers, the computer device determines that for the most significant region segment, the compression ratio of the compression section corresponding to the region segment is 4:2, for the next most significant region segment, the computer device determines that the compression ratio of the compression section corresponding to the region segment is 3:2, and for the least significant bit and the next least significant region segment, no compression is required and therefore no compression section needs to be allocated. Since the mantissa values ​​in the least significant bit and the next least significant region segment do not need to be compressed, the number of compression sections is the number of floating point numbers minus 2.

[0068] Step S604: For each region segment, determine a plurality of intra-region shift results in the respective region segment, where a single intra-region shift result is an intra-region portion of the shift result corresponding to a single floating-point number.

[0069] Specifically, for one range segment, the computer device is located in the range segment, and determines the part where the shift results of all floating-point numbers are in the range segment, and this part is called the intra-range part. For example, if the most significant range segment is, for example, the most significant w bits, in the range segment, the computer device obtains the value of the most significant w bits of the shift results of each floating-point number, and the obtained intra-range shift results of all floating-point numbers are the multiple intra-range shift results in the range segment.

[0070] Step S606: Each compression unit performs a segment compression process on the multiple intra-area shift results in the area segment corresponding to the corresponding compression unit, and obtains multiple segment compression results.

[0071] Specifically, the computer device performs segment compression processing on each of a plurality of intra-area shift results in each divided area segment using a compression unit assigned to each area segment, thereby obtaining a plurality of segment compression results.

[0072] For example, in a compression process having n floating point numbers, for the most significant region segment, the computer device performs segment compression processing using a compressor with a compression ratio of (n:2). For the next most significant region segment, the computer device performs segment compression processing using a compressor with a compression ratio of (n-1):2, and so on. However, for the least significant bits and the next least significant region segments, no compression processing is required.

[0073] Step S608: Determine a floating-point processing result corresponding to the target task based on the multiple segment compression results.

[0074] Specifically, the computer device further processes each segment compression result according to the segment compression result corresponding to each region segment to determine a floating-point processing result corresponding to the target task. For example, for a plurality of segment compression results after the segment compression process, the computer device connects each segment compression result in descending order of bit number to form a complete compression result, inputs the compression result to an adder for processing, and finally obtains a floating-point processing result corresponding to the target task.

[0075] In this embodiment, by dividing the region into multiple region segments and performing segment compression, the input to the lower region segment compression section is reduced (in some cases no compression is necessary), the area of ​​the compression section is significantly reduced, and the timing path is made smaller.

[0076] As shown in FIG. 7 , in some embodiments, the step of each compression unit performing a segment compression process on a plurality of intra-area shift results in the area segment corresponding to the corresponding compression unit, respectively, to obtain a plurality of segment compression results includes the following steps:

[0077] Step S702: For each compressor, a plurality of intra-region shift results in each corresponding region segment are taken as inputs of the corresponding compressor.

[0078] Step S704: Each compression unit performs a segment compression process on each input according to a corresponding predetermined compression ratio, and obtains an addition result and a carry result, which constitute a segment compression result corresponding to the corresponding compression unit.

[0079] Specifically, for one compression unit, the computer device takes a plurality of intra-area shift results in an area segment corresponding to the compression unit as input to the compression unit, and then performs a segment compression process on the plurality of intra-area shift results in the area segment according to a preset compression ratio of the compression unit to obtain an addition result and a carry result, where the addition result is a sum value obtained by compressing each intra-area shift result, and the carry result is a carry value of the sum value.

[0080] For example, as shown in FIG. 8, taking the compression process of four floating-point numbers (floating-point number A, floating-point number B, floating-point number C, and floating-point number D) as an example, for the most significant w-bit area segment, the computer device uses a 4:2 compressor to perform segment compression processing on the four intra-area shift results in the area segment to obtain an addition result and a carry result. If there is a carry in the addition result, the corresponding carry result becomes 1, and vice versa becomes 0. For the next most significant w-bit area segment, the computer device uses a 3:2 compressor to perform segment compression processing on the three intra-area shift results in the area segment. On the other hand, there is no need to perform compression processing on the least significant bit and the next least significant area segment.

[0081] In this embodiment, different compression units are set for each area segment, and compression is performed, so that the area of ​​the compression unit can be significantly reduced, and the overhead of hardware resources can be reduced.

[0082] As described above, after obtaining the segment compression result corresponding to each region segment, the computer device further processes each segment compression result to determine the final floating-point processing result. In the prior art, after compressing to obtain the carry (corresponding to the carry result according to the embodiment of the present invention) and sum (corresponding to the addition result according to the embodiment of the present invention), the computer device uses one CPA (Carry Propagate Adder) to perform carry propagation addition on the carry and sum to obtain the floating-point processing result.

[0083] On the other hand, the method adopted in the prior art requires carry propagation addition for two full-bit-width inputs (carry and sum), so at least one 128-bit adder is required, occupying a large amount of hardware resources and resulting in poor timing characteristics. For this reason, the computer device assigns different adders to different area segments to perform addition processing. Since the addition processing is performed for each segment, the carry of each area segment must also be considered. Therefore, in order to reduce the hardware resource occupation, in some embodiments, as shown in FIG. 9, the step of determining a floating-point processing result corresponding to a target task based on a plurality of segment compression results includes the following steps:

[0084] Step S902: For a first region segment among the divided region segments that has not been subjected to compression processing and that corresponds to only a single intra-region shift result, the single intra-region shift result is set as a selection result of the first region segment.

[0085] Step S904: For a second region segment among the divided multiple region segments that has not been subjected to compression processing and corresponds to two or more intra-region shift results, true value results and simulated value results of the second region segment are generated based on the two or more intra-region shift results within the second region segment.

[0086] Step S906: For the third area segments that have been compressed among the multiple divided area segments, true value results and simulation value results of the corresponding third area segments are generated based on the segment compression results corresponding to each third area segment.

[0087] Step S908: According to the ranking of the area segments, sequentially determine the selection result corresponding to each area segment from the lowest area segment to obtain the selection result of the highest area segment, where the selection result of the area segment other than the first area segment among the area segments is one of the true value result and the simulation value result of the corresponding area segment.

[0088] Step S910: Determine a floating-point processing result corresponding to the target task according to the selection result of each region segment.

[0089] For each area segment, the computer device first performs an addition process on the segment compression results within the area segment to obtain a true value result and a simulation value result. Here, the true value result is an actual total result obtained by performing an addition process on the area shift results, and the simulation value result is a simulation total result calculated assuming that a carry occurs when performing an addition process on the area shift results. Then, the computer device inputs the true value result and the simulation value result within each area segment to a selection unit for selection, and the selection unit determines which result to finally output.

[0090] Specifically, the computer equipment does not need to perform compression processing on the lowest area segment (referred to as the first area segment) among the multiple divided area segments, and when there is only one intra-area shift result in the area segment, the intra-area shift result can be directly obtained as the selection result of the first area segment without allocating an addition unit and a selection unit, so the computer equipment does not need to perform addition processing on the area segment and does not need to perform selection.

[0091] In addition, there is no need to perform compression processing on the next lowest region segment (referred to as the second region segment). In the second region segment, there are multiple intra-region shift results, and an addition process is required. The computer device adds up all intra-region shift results in the second region segment to calculate the true value result and the simulated value result of the second region stage.

[0092] Except for the lowest region segment and the next-lowest region segment, the intra-region shift results in each remaining region segment (referred to as third region segment) are compressed, and there are multiple intra-region shift results in the third region segment. Thus, for each third region segment, the computer device adds the segment compression results in the third region segment to generate true value results and simulated value results of the third region segment.

[0093] After determining the true value result and the simulation value result of each area segment other than the first area segment, the computer device inputs the true value result and the simulation value result of each area segment into one selection unit, respectively, and determines whether the output result is a true value result or a simulation value result by the selector. In order to improve efficiency, the computer device sequentially determines the selection result of the lowest area segment, the lowest area segment, the lower area segment, ... the highest area segment according to the rank of the area segment. Here, the selection result corresponding to the lowest area segment is the original intra-area shift result within the area segment. Since the lowest area segment has not been subjected to compression and addition processing, there is no carry, but the selection result of the next lower area segment after the lowest is a true value result. For each third area segment, the selection result of the relatively higher area segment needs to consider whether there is a carry in the relatively lower area segment of the adjacent area segments. If there is a carry in the lower area segment, the selection unit outputs the selection result of the higher area segment as the simulation value result. In the opposite case, the selection unit outputs the selection result of the higher-order area segment as the true value result.

[0094] As an example, as shown in FIG. 10, for the top area segment, the selection unit of the next top area segment outputs a true value or a simulation value result depending on the carry status input via the selection unit of the next top area segment. Similarly, for the next top area segment, the computer device performs similar processing. For the next bottom area segment, since there is no carry in the bottom area segment, the selection unit of the next bottom area segment outputs a true value result. Since there is no need to perform compression or addition processing for the bottom area segment, the original intra-area shift result is obtained as it is.

[0095] In this way, the computer device outputs the selection results corresponding to all the area segments by the selection unit.

[0096] In this embodiment, a means of adding on a segment-by-segment basis is adopted, and different addition units are assigned to different area segments to perform segment addition processing. By using multiple selection units to propagate the carry according to the carry situation of each area segment, the required hardware resources are reduced, the length of the critical path is effectively shortened, and the timing characteristics are good compared to the addition of the prior art that propagates the carry using the full bit width.

[0097] Then, the computer device concatenates the selection results of each area segment to obtain a floating-point processing result in the complete first predetermined range. Therefore, in some embodiments, the step of determining the floating-point processing result corresponding to the target task based on the selection results of each area segment includes the step of sequentially concatenating the selection results of each area segment according to the rank of each area segment to obtain the floating-point processing result corresponding to the target task. Specifically, the computer device obtains the entire floating-point processing result in the first predetermined range by sequentially concatenating the selection results of two adjacent area segments from high to low (low to high) according to the rank of each area segment.

[0098] In this embodiment, the segment compression and segment addition method is adopted, and the results of each area segment obtained can be further concatenated to obtain a complete floating-point processing result. This method does not require the use of a full-bit width compression unit and addition unit, reduces the length of the critical path, and has good timing characteristics.

[0099] Floating-point numbers have a high effective precision and are more suitable for scientific and engineering calculations. In scientific counting, unless the representation of floating-point numbers is explicitly specified, the encoded representation of a floating-point number is not unique in the computer, which is disadvantageous for computer recognition and processing. For example, the decimal number is 1.11 × 10 0 , 0.111×10 1 , 0.0111×10 2 Since normalized floating-point numbers have a unique representation, floating-point numbers must be normalized for operations on them.

[0100] In order to ensure that the obtained floating-point processing result meets the standard of normalized floating-point numbers, in some embodiments, the computer device performs a normalization process on the floating-point processing result, so as to make the floating-point processing result conform to a predetermined floating-point standard. By performing a normalization process on the floating-point processing result, it is ensured that the obtained floating-point processing result meets the standard of normalized floating-point numbers, and there is no need to identify and convert each floating-point processing result during computer processing, which leads to higher processing efficiency and avoids the problem of calculation inaccuracy caused by the encoding representation of floating-point numbers being not unique.

[0101] Here, the normalization process is also called formatted output, and means converting a floating-point number into a specified format. The absolute value of the mantissa M of the floating-point processing result after the normalization process must satisfy 1 / r≦|M|<1, where r is a base number, and r is usually 2, 8, or 16.

[0102] The normalization process is a process of adjusting the magnitude of the mantissa and exponent values ​​of a non-normalized floating-point number to ensure that the most significant digit of the mantissa value of the non-zero floating-point number is a valid value. In some embodiments, as shown in FIG. 11, the step of performing the normalization process on the floating-point processing result includes the following steps:

[0103] Step S1102: Determine a first code identifier and a second code identifier in the floating-point number processing result.

[0104] Step S1104: If the first code identifier and the second code identifier are identical, the mantissa value in the floating-point number processing result is shifted in a first shift direction.

[0105] Step S1106: If the first code identifier and the second code identifier are different, shift the mantissa value in the floating-point number processing result in a second shift direction, where the second shift direction is opposite to the first shift direction.

[0106] There are two methods for normalizing floating-point numbers: left normalization and right normalization. Here, left normalization refers to performing normalization when the result of a floating-point operation is denormalized, by shifting the mantissa value one digit to the left and subtracting 1 from the exponent (when base r=2). Left normalization may be performed multiple times. Right normalization refers to shifting the mantissa value one digit to the right and adding 1 to the exponent when the mantissa value in the result of a floating-point operation overflows (when base r=2). Right normalization is performed only once.

[0107] Specifically, the computer device obtains a first code identifier and a second code identifier in the floating-point processing result. If the first code identifier and the second code identifier are the same (i.e., the first code identifier and the second code identifier are 00 or 11), the computer device shifts a mantissa value in the floating-point processing result in a first shift direction. If the first code identifier and the second code identifier are different (i.e., the first code identifier and the second code identifier are 01 or 10), the computer device shifts a mantissa value in the floating-point processing result in a second shift direction. Here, the second shift direction is opposite to the first shift direction. Taking the floating-point normalization method in the IEEE 754 standard as an example, the first shift direction is a left shift, and the second shift direction is a right shift.

[0108] For example, if a computer determines that the two code identifiers are the same, it indicates that there is no overflow. However, if the most significant bit of the floating-point processing result is unified with the code, a left normalization process must be performed, that is, the mantissa value must be shifted left until the most significant bit is different from the code value. For example, the floating-point processing results for two cases, 111xxx and 000xxx, will be described. The result of shifting 111xxx one digit to the left is 11xxx0, and the result of shifting 000xxx one digit to the left is 00xxx0, and finally the number of shifts is subtracted from the exponent value.

[0109] If the computer device determines that the two code identifiers are different, it indicates that the calculation result has overflowed. In this case, it is necessary to perform right normalization processing and shift the mantissa of the floating-point processing result to the right, and the process stops until the overflow is eliminated. Then, the number of shifts is added to the exponent value. Specifically, the floating-point processing results for two cases, 01xxx and 10xxx, will be explained. The result of shifting 01xxx one digit to the right is 001xxx, and the result of shifting 10xxx one digit to the right is 110xxx, and finally 1 is added to the exponent value.

[0110] In this embodiment, the floating-point processing result is normalized, so that the number of effective bits of the mantissa value can be fully utilized and the accuracy of floating-point calculations can be improved.

[0111] In some embodiments, after the floating-point number is normalized, some values ​​are added to the least significant digits of the mantissa, and the added value is rounded, for example, 1.2349999 is rounded down to 1.23, or 1.2350001 is rounded up to 1.24. The IEEE 754 standard specifies rounding to nearest even, rounding up, rounding down, rounding towards zero, etc. However, the present invention is not limited to these, and different floating-point standards may adopt different rounding methods, and an appropriate rounding method may be selected for rounding as required in practical applications.

[0112] The present invention further provides an application scenario for applying the above multi-input floating-point number processing method. In some embodiments, the multi-input floating-point number processing method is applied to the application scenario, for example, to process a target task, where the target task is a subtask in a neural network processing task, and the neural network processing task includes at least one of a convolution processing task or a similarity processing task. In the application scenario, the above multi-input floating-point number processing method further includes: according to the floating-point number processing result, execute each subsequent subtask in the neural network processing task, and obtain a neural network processing result.

[0113] Specifically, in the process of training and applying a neural network, it is necessary to perform calculation processing on, for example, image data, voice data, text data, etc. Image data, voice data, text data, etc. processed by a neural network are usually represented by floating point numbers in a computer, and for example, each pixel in an image is represented by a 32-bit single precision floating point number of 0 to 255, where 255 represents white and 0 represents black. Also, for example, the read voice data is a floating point number within the sampling range.

[0114] The neural network processing task has a number of subtasks related to the processing of floating-point numbers. For example, the input image data is subjected to a convolution or deconvolution operation. For example, taking the convolution operation as an example, the convolution is multiplying and summing two data within a certain range. In the convolution process, the computer device may use a processor to execute the above multi-input floating-point number processing method, realize summation for a number of floating-point numbers, obtain a floating-point number processing result, and then execute a subsequent convolution operation based on the floating-point number processing result. Thus, in the neural network processing task, the computer device can execute each subsequent subtask in the neural network processing task based on the floating-point number processing result, obtain a neural network processing result, and output, for example, processed image data.

[0115] The above-mentioned multi-input floating-point number processing method may also be applied to a similarity processing task in a neural network processing task. Taking image data as an example, in the similarity processing task, it is necessary to compare the processed image data with preset standard image data and calculate the similarity between the two. In the similarity calculation process, the computer device may use the above-mentioned multi-input floating-point number processing method to perform a calculation to obtain a difference between floating-point numbers corresponding to the image data and obtain a floating-point number processing result. Based on the obtained floating-point number processing result, the computer device may continue to execute each subsequent subtask in the neural network processing task, and, for example, classify the image data based on the difference indicated by the floating-point number processing result, and finally output the neural network processing result (for example, an image classification result).

[0116] However, as will be apparent to those skilled in the art, the target task may be any computational task applicable to multiple floating-point numbers, such as data computation tasks in a cloud computing scenario, or computation tasks in a data processing process performed by a smart sensor (e.g., an edge sensor), without departing from the concepts and ideas of the invention disclosed herein.

[0117] In this embodiment, by applying the above-mentioned multi-input floating-point number processing method to tasks such as neural network processing, high-precision floating-point number processing of the neural network can be realized, and the calculation performance of the neural network can be improved.

[0118] In order to explain the concept of the present invention as clearly as possible, a specific execution of addition of multiple floating-point numbers is taken as an example and the differences and advantages from the conventional method are described in detail.

[0119] In a specific example, the flow of the conventional floating-point processing method is shown in FIG. 12. The computer device first obtains the exponents of n floating-point numbers, and compares them in a comparison unit to obtain the maximum exponent value. At the same time, the computer device obtains the mantissas of n floating-point numbers. Then, for one floating-point number, the computer device inputs the difference between the exponent of the floating-point number and the maximum exponent value, and the mantissa of the floating-point number, into a fixed-size shift unit, and uses the shift unit to perform a shift process on the floating-point number. For other floating-point numbers, the computer device performs a similar process. Since the mantissas of each floating-point number vary in size, in order to avoid loss of intermediate precision, the range of the shift unit used must be a maximum value m*w bits, where m is the number of floating-point numbers minus 1.

[0120] In the shifting process, the bit width of the shifted data is very wide to ensure that there is no loss of intermediate precision. For example, if there are five 32-bit single-precision floating-point numbers, the bit width of the shifted data needs to be 128 bits to ensure that there is no loss of intermediate precision (the specific configuration of 128 bits is as shown in Figure 13, where the mantissa after extension of each floating-point number is 24 bits, and 2 bits are reserved as carry bits). If the shift range is too large, the hardware overhead will be large and the timing characteristics will be poor, making it difficult for the computer processor to achieve a high operating frequency.

[0121] Similarly, after the shift is completed, the computer device inputs the obtained shift result into one n:2 compression unit for compression (where n is the number of inputs of the multi-input floating-point adder) to obtain two outputs, namely, carry and sum. Then, it performs carry-propagate addition on the carry and sum, inputs the final addition result into the normalize unit to perform floating-point standardization operation, performs rounding operation on the standardized data, and finally obtains the floating-point addition result. Here, the compression unit uses n:2 compression for the entire bit width, and when there are five 32-bit single-precision floating-point numbers as an example, the compression unit uses a 128-bit 5:2 compression unit, and the area overhead of the compression unit is large. In the subsequent addition stage, it also performs carry-propagate addition on two full-bit width inputs (carry and sum), and when there are five 32-bit single-precision floating-point numbers as an example, a 128-bit adder is required, resulting in poor timing characteristics.

[0122] Compared with the conventional method, as shown in FIG. 14, the multi-input floating-point processing method according to the embodiment of the present invention has the following process flow. The computer device obtains the exponents of n floating-point numbers, and compares them with a comparator to obtain the maximum exponent value. At the same time, the computer device obtains the mantissas of n floating-point numbers. Before inputting them to the shift unit and performing shift processing, the computer device performs rearrangement processing on each floating-point number according to the magnitude of the exponent value of each floating-point number. That is, there is no need to perform a shift operation on the floating-point number with the maximum exponent. For the second floating-point number, shift by w bits. For the third floating-point number, shift by 2*w bits. ... and the same applies to other cases, and for the floating-point number with the smallest exponent (lowest), the shift range is m*w. As an example, if there are five 32-bit single-precision floating-point numbers, m=4 and w=26. The computer device does not use a fixed-size shifter for each floating-point number, but dynamically allocates the shifter for each floating-point number according to the sorting result. Compared with the prior art, the area overhead of the shifter can be significantly reduced.

[0123] Then, the computer device inputs the mantissa value of each floating-point number to the corresponding shift unit to perform a shift process. The obtained shift results are input to the corresponding compression units. Specifically, the computer device sets a compression unit with a different compression ratio for each area segment. That is, for the most significant w bit, a compression unit with n:2 is used. For the next highest w bit, a compression unit with (n-1):2 is used. The same applies to other cases. For the least significant w bit and the next lowest w bit, there is no need to compress using a compression unit. Therefore, there is no need to allocate a compression unit. Compared to the conventional technology, the area overhead of the compression unit can be significantly reduced.

[0124] Then, for each area segment, the computer device performs addition using one CPA. For the lowest w bit, the shift result of the w bit is directly obtained without performing an addition operation. For the next lowest w bit, since there are two floating-point shift results (corresponding to the intra-area shift result in the above embodiment) in the area segment, the computer device performs addition using one CPA. Since the lower w bit (the lowest) of the w bit (next to the lowest) does not have a carry, the w bit outputs the actual addition result. For other area segments, depending on whether there is a carry in the next area segment (the adjacent lower area segment) of the area segment, a MUX (selection unit) selects whether to output the actual addition result (corresponding to the true value result in the above embodiment) or the addition result including the carry (i.e., the simulation value result in the above embodiment) to obtain multiple selection results.

[0125] Finally, the computer device concatenates each selected result to obtain the final sum result, and then performs post-processing, normalizing the sum result so that the sum result meets the format specified by IEEE 754, and performing rounding operations to obtain the final result.

[0126] Compared with the conventional method, the concept of effective shifting is introduced, and effective shifting is performed on the rearranged mantissa, and the shift range of the upper mantissa is reduced (in some cases, no shifting is required), so that the overhead of the area of ​​the shifting section can be significantly reduced. In addition, based on the concept of efficient shifting introduced, the entire bit width is divided into area segments, and segment compression is performed respectively, so that the input of the compression section of the lower area segment is reduced (in some cases, no compression is required), so that the area of ​​the compression section can be significantly reduced and the timing path can be made smaller. In the final addition stage, the means of segment addition is adopted, and the length of the critical path can be effectively reduced. This makes it possible to realize lossless multi-input floating-point processing with the minimum hardware area, significantly reducing the overall area of ​​the processor, and efficiently improving the core frequency of the processor.

[0127] Taking five 32-bit single-precision floating-point numbers as an example, the Global Foundries (GF) 12 nm process technology is used as the area estimation standard, and the shift unit resources required for the present invention are compared with those of the conventional technology as shown in Table 1 below.

[0128] [Table 1] As can be seen from Table 1, the shift unit resource used in the present invention is only 55.6% of that in the prior art, which can greatly save the area cost of the shift unit.

[0129] In the compression stage, the compressor resources used in the present invention are compared with those used in the prior art as shown in Table 2 below.

[0130] [Table 2] As can be seen from Table 2, the compression section resource used in the present invention is 39% of that in the prior art, which can greatly save the area cost of the compression section.

[0131] Regarding timing, in the prior art, the critical path from the shifting process to the output of the adder is 128-bit shift (shift unit) →>5:2 compressor (compression unit) → 128-bit adder (adder unit), whereas in the present invention, the critical path from the shifting process to the output of the adder is 128-bit shift (shift unit) → 5:2 compressor (compression unit) → 24-bit adder (adder unit), effectively reducing the length of the critical path and enabling a relatively high processor clock frequency to be achieved.

[0132] Although each step in the flowcharts according to the above embodiments is displayed in sequence according to the direction of the arrows, these steps are not necessarily executed in sequence according to the direction of the arrows. Unless otherwise expressly described in this specification, the execution of these steps is not limited to a strict order and may be executed in other orders. Furthermore, at least some of the steps in the flowcharts according to the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same timing, but may be executed at different timings. The execution order of these steps or stages is not necessarily executed sequentially, and they may be executed alternately or alternately with other steps or at least some of the steps or stages in other steps.

[0133] Based on the same inventive idea, the embodiment of the present invention further provides a multi-input floating-point processing device for implementing the above multi-input floating-point processing method. The embodiment for solving the problem provided by the device is the same as the embodiment described in the above method. Therefore, the specific limitations in the embodiments of one or more multi-input floating-point processing devices provided below may refer to the limitations of the multi-input floating-point processing method in the above description.

[0134] In some embodiments, a multi-input floating-point processing device 1500 is provided. As shown in Fig. 15, the device may adopt software modules or hardware modules, or may be part of a computer device by a combination of these. The device specifically includes an acquisition module 1501, an allocation module 1502, a shift module 1503, and a determination module 1504.

[0135] The acquisition module 1501 acquires a number of floating-point numbers to be processed corresponding to a target task, and extracts an exponent value of an exponent part and a mantissa value of a mantissa part in each floating-point number.

[0136] The allocation module 1502 sorts the multiple floating-point numbers according to the magnitude of the exponent value of each floating-point number to obtain a sorting result, and assigns a shift section to each floating-point number from a multiple shift sections having different predetermined bit numbers based on the sorting result.

[0137] The shift module 1503 performs a shift process on the mantissa value of the corresponding floating-point number using a shift unit assigned to the floating-point number, and obtains a shift result.

[0138] The determination module 1504 determines a floating-point processing result corresponding to the target task based on each shift result.

[0139] In some embodiments, the different predetermined numbers of bits of the multiple shifting units are within a first predetermined range, and the predetermined numbers of bits of each shifting unit are evenly distributed within the first predetermined range.

[0140] In some embodiments, the number of the plurality of shifting units is the same as the number of the plurality of floating-point numbers. The allocation module determines a permutation number of each floating-point number in the permutation result, determines a predetermined number of bits corresponding to each permutation number, and allocates the plurality of shifting units to the floating-point numbers designated by the permutation numbers corresponding to the corresponding predetermined number of bits according to the predetermined number of bits each of the shifting units has.

[0141] In some embodiments, the shift module determines a number of shift bits corresponding to a respective mantissa value of each floating-point number based on a respective difference between an exponent value of each floating-point number and a maximum exponent value, the maximum exponent value being the maximum value among the exponent values ​​of the plurality of floating-point numbers; and for each floating-point number, performing a shift operation on the mantissa value of the corresponding floating-point number by a shift unit assigned to the floating-point number based on the number of shift bits corresponding to the mantissa value of the corresponding floating-point number to obtain a shift result.

[0142] In some embodiments, the shift module determines, for each floating-point number, whether a number of shift bits corresponding to the mantissa value of the floating-point number is within a shift range, the shift range being equal to a predetermined number of bits of the shift section assigned to the floating-point number, and if the number of shift bits is within the shift range, the shift section assigned to the floating-point number shifts each mantissa element constituting the mantissa value of the floating-point number by the number of shift bits in the same shift direction within the corresponding shift range, the shift direction including a left shift or a right shift, and if the number of shift bits is outside the shift range, the shift section assigned to the floating-point number shifts each mantissa element constituting the mantissa value of the floating-point number by the predetermined number of bits in the same shift direction, and the mantissa value obtained by performing the shift process on each floating-point number is the shift result of each floating-point number.

[0143] In some embodiments, the determination module further includes a compression unit, which divides the first predetermined range according to a first predetermined range in which shifting parts with different predetermined bit numbers are located to obtain a plurality of region segments, determines a plurality of compression parts corresponding to the plurality of region segments, where the different compression parts have different predetermined compression ratios, respectively determines a plurality of intra-region shifting results in each region segment, where a single intra-region shifting result is an intra-region part in the shifting result corresponding to a single floating-point number, respectively performs a segment compression process on the plurality of intra-region shifting results in the region segment corresponding to the corresponding compression part by each compression part, obtains a plurality of segment compression results, and determines a floating-point number processing result corresponding to the target task according to the plurality of segment compression results.

[0144] In some embodiments, the different predetermined compression ratio values ​​of the multiple compressors are within a second predetermined range, and the predetermined compression ratio values ​​of each compressor are evenly distributed within the second predetermined range.

[0145] In some embodiments, the compression unit, for each compression section, takes multiple intra-area shift results within a corresponding area segment as input to the corresponding compression section, and each compression section performs a segment compression process on each input according to a corresponding predetermined compression ratio, and obtains an addition result and a carry result, and the addition result and the carry result constitute a segment compression result corresponding to the corresponding compression section.

[0146] In some embodiments, the determination module further includes a summing unit. The addition unit takes the single intra-area shift result as a selection result of the first area segment for a first area segment that has not been compressed and corresponds to only a single intra-area shift result, generates a true value result and a simulation value result of the second area segment for a second area segment that has not been compressed and corresponds to two or more intra-area shift results based on two or more intra-area shift results in the second area segment, generates a true value result and a simulation value result of the corresponding third area segment for a third area segment that has been compressed based on a segment compression result corresponding to each third area segment, and sequentially determines the selection results corresponding to each area segment according to the order of the area segments, from the lowest area segment to the highest area segment, and the selection results of other area segments than the first area segment among the area segments are one of the true value result and the simulation value result of the corresponding area segment, and determines a floating-point number processing result corresponding to the target task based on the selection result of each area segment.

[0147] In some embodiments, the determination module further includes a concatenation unit, which sequentially concatenates the selection results of each region segment according to the rank of each region segment to obtain a floating-point processing result corresponding to the target task.

[0148] In some embodiments, the apparatus further includes a post-processing module that performs a normalization process on the floating-point processing result so that the floating-point processing result conforms to a predetermined floating-point standard.

[0149] In some embodiments, the post-processing module determines a first code identifier and a second code identifier in the floating-point processing result, and if the first code identifier and the second code identifier are identical, shifts a mantissa value in the floating-point processing result in a first shift direction, and if the first code identifier and the second code identifier are different, shifts the mantissa value in the floating-point processing result in a second shift direction, the second shift direction being opposite to the first shift direction.

[0150] In some embodiments, the target task is a subtask in a neural network processing task, and the neural network processing task includes at least one of a convolution processing task or a similarity processing task. The apparatus further includes a task module, which executes each subsequent subtask in the neural network processing task according to the floating-point number processing result to obtain a neural network processing result.

[0151] For specific limitations of the multi-input floating-point processing device, reference may be made to the limitations of the multi-input floating-point processing method. All or part of each module in the multi-input floating-point processing device may be realized by software, hardware, or a combination thereof. Each of the modules may be incorporated in a processor in a computer device in the form of hardware, or may be independent, or may be stored in a memory in a computer device in the form of software so that the processor can easily call the operation corresponding to each of the modules.

[0152] Based on the same inventive idea and concept, the embodiments of the present invention further provide a processor for implementing the multi-input floating-point number processing method according to the above embodiments. In some embodiments, as shown in FIG. 16, a processor 1600 includes at least one shift unit 1601 and a logic processor 1602 having different predetermined bit numbers. In different implementation scenarios, the processor can exhibit various package structures according to the needs of application to different computer devices.

[0153] Here, at least one shift unit 1601 having a different predetermined number of bits is assigned to perform a shift process on the mantissa value of the mantissa part of one of the floating-point numbers to be processed. Here, the shift unit assigned to each floating-point number is determined based on the rearrangement result obtained by rearranging the exponent values ​​of the exponent parts of each floating-point number according to their magnitudes.

[0154] The logical processor 1602 performs logical processing on a plurality of shift results obtained by each shift unit performing a shift process, and obtains a floating-point number processing result.

[0155] In some embodiments, the different predetermined numbers of bits of at least one shifting unit are within a first predetermined range, and the predetermined numbers of bits of each shifting unit are evenly distributed within the first predetermined range.

[0156] In some embodiments, as shown in FIG. 17, the logic processor 1602 includes the following components:

[0157] At least one compression unit 16021 has a different predetermined compression ratio and is connected to each of the shift units. Each compression unit is assigned to perform segment compression processing on multiple shift results obtained by the shift processing, and obtain segment compression results.

[0158] At least one adder 16022 is connected to each of the compression units 16021. The adder generates true value results and simulation value results of a plurality of area segments based on the segment compression results.

[0159] At least one selection unit 16023 is respectively connected to the addition unit 16022. The selection unit determines a selection result for each area segment based on the true value results and the simulation value results of the multiple area segments, and the selection results are used to generate a floating-point processing result by concatenation.

[0160] In some embodiments, the different predetermined compression ratio values ​​of the multiple compressors are within a second predetermined range, and the predetermined compression ratio values ​​of each compressor are evenly distributed within the second predetermined range.

[0161] For specific limitations of the processor, reference may be made to the limitations of the above multi-input floating-point processing method. Each element in the above processor may be realized in whole or in part by a combination of other circuit devices such as gate circuits, switch circuits, etc. Each element may be integrated and built into the processor of a computer device, making it convenient for the processor to perform the operations corresponding to each element.

[0162] In some embodiments, a computer device is further provided, and the computer device may be a server or a terminal including the above processor. Here, the server may be an independent physical server, a server cluster or a distributed system consisting of a plurality of physical servers, or a cloud server providing a cloud computing service. The terminal may be a smartphone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, an in-vehicle terminal, a smart TV, etc. The internal configuration of the computer device is shown in FIG. 18. The computer device includes a processor, a memory, and a network interface connected via a system bus. Here, the processor of the computer device is used to provide calculation and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer-readable instructions, and a database. The internal memory provides an environment for the execution of the operating system and the computer-readable instructions in the non-volatile storage medium. The database of the computer device is used to store floating-point numbers. The network interface of the computer device is for communicating with an external terminal via a network connection. The computer readable instructions, when executed by a processor, implement a method for processing multiple-input floating point numbers.

[0163] Those skilled in the art will understand that the configuration shown in FIG. 18 is merely a block diagram of a partial configuration related to the solution of the present invention, and does not constitute a limitation of the computer device to which the solution of the present invention is applied, and that a specific computer device may include more or fewer components than those shown in the figure, may combine some components, or may have a different arrangement of components.

[0164] In some embodiments, there is further provided a computing device including a memory having computer readable instructions stored thereon and a processor, the processor performing the steps of the above method when executing the computer readable instructions.

[0165] In some embodiments, the present invention further provides a computer readable storage medium having a computer program stored thereon, the computer program implementing the steps of the above-described method when executed by a processor.

[0166] In some embodiments, there is further provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of the above-mentioned method.

[0167] Those skilled in the art will understand that implementing all or part of the process of the method of the above embodiment can be achieved by instructing the relevant hardware by a computer program that can be stored in a non-volatile computer readable storage medium that can include the process of the above embodiment of the method when executed. Here, any reference to a memory, database, or other medium used in each embodiment of the present invention can include at least one of a non-volatile memory and a volatile memory. The non-volatile memory can include a Read-Only Memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical memory, a high-density embedded non-volatile memory, a resistive memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, etc. The volatile memory can include a random access memory (RAM) or an external cache memory, etc. By way of example and not limitation, the RAM may be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). A database associated with an embodiment of the present invention may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database. A processor associated with an embodiment of the present invention may be, but is not limited to, a general-purpose processor, a central processor, a graphics processor, a digital signal processor, a programmable logic circuit, a data processing logic circuit based on quantum computing, and the like.

[0168] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, all possible combinations of the technical features in the above embodiments have not been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope described in this specification.

[0169] The above examples only show some examples of the present invention, and the description is more specific and detailed, but therefore should not be construed as limiting the patent scope of the present invention. However, those skilled in the art can make some modifications and improvements within the scope of the present invention without departing from the concept of the present invention. Therefore, the protection scope of the present invention should be subject to the scope of the attached claims.

Claims

1. 1. A method for processing multiple input floating point numbers implemented by a computing device, comprising: Obtaining a plurality of floating-point numbers to be processed corresponding to a target task, and extracting an exponent value of an exponent part and a mantissa value of a mantissa part of each floating-point number; sorting the floating-point numbers according to the magnitude of an exponent value of each floating-point number to obtain a sorting result; and assigning a shift unit to each floating-point number from a plurality of shift units having different predetermined bit numbers based on the sorting result; for each floating-point number, performing a shift operation on a mantissa value of the corresponding floating-point number by a shift unit assigned to the floating-point number to obtain a shift result; determining a floating-point processing result corresponding to the target task based on each of the shift results.

2. 2. The method of claim 1, wherein the different predetermined numbers of bits of the multiple shifting units are within a first predetermined range, and the predetermined numbers of bits of each shifting unit are evenly distributed within the first predetermined range.

3. the number of the plurality of shift units is equal to the number of the plurality of floating-point numbers; The step of allocating a shift unit to each floating-point number from a plurality of shift units having different predetermined bit numbers based on the rearrangement result includes: determining a sorting number for each floating-point number in the sorted result; 2. The method of claim 1, further comprising: determining a predetermined number of bits corresponding to each of the permutation numbers; and allocating a plurality of shift units to the floating-point numbers designated by the permutation numbers corresponding to the corresponding predetermined number of bits according to the predetermined number of bits each of the shift units has.

4. The step of performing a shift process on a mantissa value of a corresponding floating-point number by a shift unit assigned to the floating-point number and obtaining a shift result for each of the floating-point numbers includes: determining a number of shift bits corresponding to each mantissa value of each floating-point number based on a respective difference between an exponent value of each floating-point number and a maximum exponent value, the maximum exponent value being a maximum value among the exponent values ​​of the plurality of floating-point numbers; and for each floating-point number, performing a shift operation on a mantissa value of the corresponding floating-point number by a shift unit assigned to the floating-point number based on a shift bit number corresponding to the mantissa value of the corresponding floating-point number to obtain a shift result.

5. determining a floating-point processing result corresponding to the target task based on each of the shift results, A step of obtaining a plurality of area segments by dividing the first predetermined range based on a first predetermined range in which the shift parts of the different predetermined number of bits are located, and determining a plurality of compression parts respectively corresponding to the plurality of area segments, where the different compression parts have different predetermined compression ratios; determining, for each region segment, a plurality of intra-region shift results within the respective region segment, where a single intra-region shift result is an intra-region portion of the shift result corresponding to a single floating-point number; performing, by each of the compression units, a segment compression process on a plurality of intra-area shift results in the area segment corresponding to the corresponding compression unit, to obtain a plurality of segment compression results; and determining a floating-point processing result corresponding to the target task based on the plurality of segment compression results.

6. 6. The method of claim 5, wherein the different predetermined compression ratio values ​​of the plurality of compressors are within a second predetermined range, and the predetermined compression ratio values ​​of each compressor are evenly distributed within the second predetermined range.

7. The step of performing a segment compression process on a plurality of intra-area shift results in the area segment corresponding to the corresponding compression unit, by each of the compression units, to obtain a plurality of segment compression results, for each compressor, a plurality of intra-region shift results within each corresponding region segment as input to the corresponding compressor; 6. The method of claim 5, further comprising: performing, by each compressor, a segment compression operation on each of its inputs in accordance with a corresponding predetermined compression ratio to obtain an addition result and a carry result, the addition result and the carry result constituting a segment compression result corresponding to a corresponding compressor.

8. determining a floating-point processing result corresponding to the target task based on the plurality of segment compression results, A step of selecting a first region segment that is not compressed and corresponds to only a single intra-region shift result from among the divided region segments, the single intra-region shift result being selected as the first region segment; generating true value results and simulated value results for a second region segment that is not subjected to compression processing and corresponds to two or more intra-region shift results among the divided region segments, based on the two or more intra-region shift results in the second region segment; generating true value results and simulated value results for the third region segments that have been subjected to compression processing, based on the segment compression results corresponding to each of the third region segments; determining a selection result corresponding to each area segment in sequence according to the ranking of the area segments, from the lowest area segment to the highest area segment, wherein the selection result of the area segments other than the first area segment among the area segments is one of a true value result and a simulation value result of the corresponding area segment; and determining a floating-point processing result corresponding to the target task based on the selection of each region segment.

9. determining a floating-point processing result corresponding to the target task based on the selection result of each of the area segments, 9. The method of claim 8, further comprising: sequentially concatenating the selection results of each area segment according to the ranking of each area segment to obtain a floating-point processing result corresponding to the target task.

10. 2. The method of claim 1, further comprising: performing a normalization process on the floating-point processing result so that the floating-point processing result conforms to a predetermined floating-point standard.

11. The step of performing a normalization process on the floating-point number processing result includes: determining a first code identifier and a second code identifier indicative of a presence or absence of an overflow at a left end of the floating-point processing result, the first code identifier and the second code identifier being either 1 or 0; shifting a mantissa value in the floating-point number processing result in a first shift direction when the first code identifier and the second code identifier are identical; 11. The method of claim 10, further comprising: if the first code identifier and the second code identifier are different, shifting a mantissa value in the floating-point processing result in a second shift direction, the second shift direction being opposite to the first shift direction.

12. the target task is a subtask in a neural network processing task; The neural network processing task includes at least one of a convolution processing task or a similarity processing task; The method comprises: The method of claim 1 , further comprising: executing each subsequent subtask in the neural network processing task based on the floating-point number processing result to obtain a neural network processing result.

13. A multi-input floating-point number processing device, comprising: an acquisition module for acquiring a plurality of floating-point numbers to be processed corresponding to a target task, and extracting an exponent value of an exponent part and a mantissa value of a mantissa part of each floating-point number; an allocation module for sorting the floating-point numbers according to the magnitude of an exponent value of each floating-point number to obtain a sorting result, and allocating a shift unit from a plurality of shift units having different predetermined bit numbers to each floating-point number based on the sorting result; a shift module for performing a shift operation on a mantissa value of a corresponding floating-point number by a shift unit assigned to the floating-point number, and obtaining a shift result; a determination module that determines a floating-point processing result corresponding to the target task based on each of the shift results.

14. at least one shift unit having a different predetermined number of bits, each shift unit being assigned to perform a shift process on a mantissa value of a mantissa part of one of the plurality of floating-point numbers to be processed, and the shift unit assigned to each floating-point number is determined based on a rearrangement result obtained by rearranging exponent values ​​of the exponent part of each floating-point number according to their magnitudes; a logic processing unit that performs logic processing on a plurality of shift results obtained by performing the shift processing in each of the shift units, and obtains a floating-point number processing result.

15. 15. The processor of claim 14, wherein the different predetermined number of bits of the at least one shifting unit is within a first predetermined range, and the predetermined number of bits of each shifting unit is evenly distributed within the first predetermined range.

16. The logic processor includes: At least one compression unit having different predetermined compression ratios and connected to the shift unit, each compression unit being assigned to perform a segment compression process on a plurality of sift results obtained by the sift process to obtain a segment compression result; at least one adder unit connected to each of the compression units, the adder unit generating true value results and simulation value results of a plurality of region segments based on the segment compression results; and at least one selection unit connected to each of the addition units, the selection unit determining a selection result for each region segment based on true value results and simulation value results of the multiple region segments, the selection results being used to generate a floating-point processing result by concatenation.

17. A computing device comprising a memory having computer readable instructions stored thereon and a processor, the processor implementing the steps of the method of any of claims 1 to 12 when executing the computer readable instructions.

18. A computer program product which, when executed by a processor, implements the steps of the method according to any of claims 1 to 12.

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