Processor operand management using fused buffers

Abstract

Techniques relating to operand management using a fused buffer are disclosed. A processor includes an operand management circuit, wherein the operand management circuit includes a fusion buffer; and an execution circuit. In one embodiment, operand management circuitry is configured to: detect a first store instruction operation executable to store an operand value usable by one or more consumer instruction operations; and storing the first store instruction operation in the fusion buffer. In response to detecting a drop condition associated with the first store instruction operation, the operand management circuitry is configured to remove the first store instruction operation from the fusion buffer without forwarding the first store instruction operation for execution. The operand management circuitry is configured to forward the first stored instruction operation for execution by the execution circuitry in response to detecting a buffer emptied condition and not detecting a discard condition.

Description

Technical Field

[0001] This disclosure relates generally to a computer processor, and more specifically to dedicated hardware for processing certain instructions. Background Technology

[0002] Modern computer systems typically include a processor integrated onto a chip along with other computer components, such as memory or communication interfaces. During operation, the processor executes instructions to implement various software routines, such as user software applications and operating systems. As part of implementing software routines, the processor typically executes various types of instructions, such as instructions for generating the values ​​required by the software routines. The specific set of instructions executed by a given processor is defined by the processor's instruction set architecture (ISA).

[0003] Some data processing operations, such as vector or matrix operations, involve the use of large operands. For example, the number of operands required can be large compared to the values ​​that the instruction can carry as immediate values ​​or that can be stored in typical registers used by the processor. One type of operation that can use large operands is an interleaving operation. For example, some ISAs include a "zip" instruction that reads elements from two or more vectors stored in corresponding source registers and writes the elements from the source vectors alternately into the destination register (or register set), such that the elements of the input vectors are interleaved in the result. ISAs may also include an "unzip" or deinterleaving instruction to reverse this process.

[0004] An ISA can include instructions suitable for generating large operands for operations that use large operands. For example, a lookup table instruction can use multiple index values ​​from a packed source register, where each index value is mapped to a larger value in a lookup table. Execution of a lookup table instruction causes the larger value corresponding to the index bit to be obtained and written to one or more destination registers. As another example, move instructions can move portions of a memory array, such as rows or columns, to multiple destination registers to form large operands. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example element of a processor configured to use a fusion buffer to manage operands according to some implementation schemes.

[0006] Figure 2 This is a block diagram illustrating example elements of an interleaved execution circuit according to some implementation schemes.

[0007] Figure 3 This is a block diagram illustrating an example element of a processor configured to use a fusion buffer to manage operands according to some implementation schemes.

[0008] Figure 4This is a block diagram illustrating an example element of a coprocessor configured to use multiple fusion buffers to manage operands according to some implementation schemes.

[0009] Figure 5 This is a block diagram illustrating an example element of a processor configured to use a fusion buffer to manage operands according to some implementation schemes.

[0010] Figures 6A to 6B This is a block diagram illustrating how, according to some implementation schemes, storage instruction operations are stored in a fusion buffer.

[0011] Figures 7A to 7C This is a block diagram illustrating a scenario where consumer instruction operations and buffered instruction operations are combined according to some implementation schemes.

[0012] Figure 8 This is a block diagram illustrating the removal of the fusion buffer and forwarding of the execution of stored instruction operations according to some implementation schemes.

[0013] Figure 9 This is a flowchart illustrating example methods related to operand management using a fusion buffer, based on some implementation schemes.

[0014] Figure 10 This is a flowchart illustrating example methods related to operand management using a fusion buffer, based on some implementation schemes.

[0015] Figure 11 This is a flowchart illustrating example methods related to operand management using a fusion buffer, based on some implementation schemes.

[0016] Figure 12A This is a block diagram illustrating an example input vector received by an interleaving execution circuit performing an interleaving operation, according to some implementation schemes.

[0017] Figure 12B This is a block diagram illustrating example content of an array of interleaving execution circuitry configured to store after the first pass of the interleaving process, according to some implementation schemes.

[0018] Figure 12C This is a block diagram illustrating example content of an array of interleaving execution circuitry configured to store data after the second pass of the interleaving process, according to some implementation schemes.

[0019] Figure 12D This is a block diagram illustrating example content of an array of interleaving execution circuitry configured to store data after the third pass of the interleaving process, according to some implementation schemes.

[0020] Figure 12EThis is a block diagram illustrating example content of an array of interleaving execution circuitry configured to be stored after the fourth pass of the interleaving process, according to some implementation schemes.

[0021] Figure 12F This is a block diagram illustrating example row values ​​output by an interleaving execution circuit performing an interleaving operation according to some implementation schemes.

[0022] Figure 13A This is a block diagram illustrating example interleaving values ​​received by an interleaving execution circuit performing a deinterleaving operation according to some implementation schemes.

[0023] Figure 13B This is a block diagram illustrating example content of an array of interleaving execution circuitry configured to store data after the first pass of the deinterleaving process, according to some implementation schemes.

[0024] Figure 13C This is a block diagram illustrating an example of the contents of an array of interleaving execution circuits configured to be stored after the second pass of the deinterleaving process, according to some implementation schemes.

[0025] Figure 13D This is a block diagram illustrating example content of an array of interleaving execution circuitry configured to be stored after the third pass of the deinterleaving process, according to some implementation schemes.

[0026] Figure 13E This is a block diagram illustrating example content of an array of interleaving execution circuitry configured to be stored after the fourth pass of the deinterleaving process, according to some implementation schemes.

[0027] Figure 13F This is a block diagram illustrating example row values ​​output by an interleaving execution circuit performing a deinterleaving operation according to some implementation schemes.

[0028] Figure 14A This is a block diagram illustrating example content of an array using an interleaving execution circuit with two input data ports, configured to store data after the first pass of the interleaving process, according to some implementation schemes.

[0029] Figure 14B This is a block diagram illustrating example content of an array using an interleaving execution circuit with two input data ports, configured to store data after the second pass of the interleaving process, according to some implementation schemes.

[0030] Figure 15 This is a block diagram illustrating example elements of an interleaving execution circuit including a buffer circuit according to some implementation schemes.

[0031] Figure 16 This is a block diagram illustrating example elements of an interleaved execution circuit comprising two array memory circuits according to some implementation schemes.

[0032] Figure 17 This is a flowchart illustrating an example method related to the interleaving process using interleaving execution circuitry, according to some implementation schemes.

[0033] Figure 18 This is a flowchart illustrating an example method related to the deinterleaving process using interleaved execution circuitry, according to some implementation schemes.

[0034] Figure 19 This is a block diagram illustrating example elements of a computing device according to some implementation schemes.

[0035] Figure 20 This is a block diagram illustrating example computing devices that can be used in various types of systems according to some implementation schemes.

[0036] Figure 21 This is a block diagram illustrating a computer-readable storage medium for storing circuit design information of a computing device according to some implementation schemes. Detailed Implementation

[0037] As mentioned above, the instruction set available to a programmer using a given processor is defined by the processor's instruction set architecture (ISA). Multiple instruction set architectures exist (e.g., the x86 architecture originally developed by Intel, ARM from ARM Holdings, Power and PowerPC from IBM / Motorola, etc.). Each instruction is defined within the instruction set architecture, including its memory encoding, its operation, and its effects on registers, memory locations, and / or other processor states. For a given ISA, there are often operations that a programmer wants to implement that do not correspond to a single instruction in the ISA. Therefore, two or more instructions can be used to implement such operations.

[0038] Using a pair (or more) of instructions to implement an operation that can be done with a single instruction can lead to technical problems that degrade processor performance in a variety of ways. As an example, the execution of two instructions can increase the latency or number of clock cycles required to implement the operation. This increase in latency is particularly likely if one or both instructions implement a simple operation that can be completed in a single cycle.

[0039] Besides potentially increasing processor latency, using a pair of instructions instead of a single instruction can degrade performance by increasing throughput in the processor's instruction pipeline, potentially increasing power consumption or congestion in components such as the scheduler and reservation stations. Therefore, "fusion" a pair of instructions into a single decoded instruction (or, as used herein, an "instruction operation") reduces the amount of resources that would otherwise be consumed by processing those instructions individually. For example, storing one decoded instruction instead of two can save entries in the reordering buffer and may eliminate the need to allocate additional physical registers. As another example, instruction fusion can reduce dispatch bandwidth or the number of instruction operations dispatched to the reservation station per cycle. Furthermore, fusion can reduce issue bandwidth or the number of instruction operations scheduled to the execution unit per cycle. Thus, instruction fusion can result in more efficient and / or lower-power operation of the processor at multiple stages.

[0040] In the case of instructions that generate large operands, the ability to avoid writing operands to registers can provide additional benefits beyond those offered by general instruction fusion, especially when the processor has a relatively small number of write ports. This may be the case, for example, in some vector / matrix coprocessors. Depending on the specific instructions involved, there may be more than one consumer instruction that requires operands stored by an operand-store instruction. One way to ensure that these operands are available for appending consumer instructions even after the execution of the fused instruction with the first consumer instruction would be to transfer the store instruction for execution, causing the destination register of the first instruction to be written to the operand. However, since writing can take the time required for multiple registers, this may negate most of the benefits initially gained from instruction fusion for execution.

[0041] This disclosure describes techniques for using fusion buffers to reduce the need for writing to registers during the execution of certain instructions used to generate large operands.

[0042] In one implementation, the fusion buffer is used to store a first store instruction operation (a decoded store instruction) that can be executed to write one or more operand values ​​into one or more destination registers. For example... Figure 1 , Figures 6A to 6B , Figures 7A to 7B and Figures 9 to 11This illustrates such storage of a storage instruction operation. A first stored instruction operation may be held in a fusion buffer until a "buffer vacancy condition" is detected, in which case the first stored instruction operation is removed from the fusion buffer. Examples of buffer vacancy conditions include: the need to place a second stored instruction operation into the fusion buffer, or the need to dispatch the first stored instruction operation for execution to prevent instruction operations or "ops" from going out of order to the execution pipeline (e.g., a hold station or op queue) to which the first stored instruction was assigned. In one embodiment, a "drop condition" associated with the first stored instruction operation is checked. A drop condition is the determination that there is no longer a consumer instruction for the first stored instruction. In one embodiment, detecting a drop condition includes: using register mapping data to determine that there is currently no consumer op in the execution pipeline, and determining that the target register of the first stored instruction is being overwritten such that no future consumer op for the first stored instruction arrives.

[0043] If a "drop condition" is detected when the first store instruction operation is removed from the fusion buffer, the first store instruction operation can be dropped instead of dispatched for execution, so that the destination register of the first store instruction operation is never written to. For example Figure 7C and Figures 10 to 11 This illustrates such discarding of a store instruction operation removed from the fusion buffer. In one implementation, if a discard condition has not been detected when the first store instruction operation is removed from the fusion buffer, the first store instruction operation is dispatched for execution. For example... Figure 8 and Figure 10 The example illustrates such execution of a store instruction operation removed from the fusion buffer. If an eligible consumer instruction operation is detected while the first store instruction operation is in the fusion buffer, the first store instruction operation and the consumer instruction operation can be fused into a fused instruction operation for execution by not writing the operand value to the destination register of the first store instruction. For example... Figure 1 , Figures 7B to 7C and Figure 11 The example illustrates this fusion of store instruction operations and consumer instruction operations.

[0044] The use of a fusion buffer, as disclosed herein, allows store instructions to be potentially discarded without writing the operand value generated by the instruction to the destination register. This can provide significant performance improvements, for example, in write-port-constrained processors handling large operands. A fusion buffer allows store instruction operations to be held for fusion execution when no eligible consumer instruction operation is available in the same decoding group but may arrive in a subsequent decoding group. For consumer instructions that do not overwrite the destination register of the store instruction, the use of a fusion buffer allows the store instruction to be fused with multiple consumer instructions for execution until a free condition removes the store instruction operation from the fusion buffer.

[0045] In various implementations, the execution of fusion instruction operations involves the use of dedicated execution circuitry. An example of such circuitry is an interleaving execution circuit, the implementation of which is described herein. As noted above, interleaving and deinterleaving operations can be specified by some ISA instructions. These operations can be useful in various applications such as image processing applications where pixels are represented by multiple values ​​corresponding to different component colors. Performing interleaving and deinterleaving operations (especially those with a larger number of input values) using typical processor execution circuitry can involve the execution of multiple micro-operations that require significant time and occupy multiple registers.

[0046] This disclosure describes an execution circuit configured to perform interleaving and deinterleaving operations.

[0047] In one embodiment, the execution circuitry includes an array storage circuit and a control circuit. The array storage circuit is configured to store elements of an array having multiple rows and multiple columns. The control circuit is configured to receive multiple input vectors and write the multiple input vectors into the array storage circuit. In one embodiment, the input vectors are written into the array storage circuit such that the elements of a given input vector are split among multiple columns in a given subset of the multiple columns of the array. The input vectors are also written into the array storage circuit such that a given row of multiple rows includes interleaved elements of the multiple input vectors. The control circuit is further configured to output data corresponding to rows of the array to form one or more result values. For example... Figure 2 , Figures 12A to 12F , Figures 14A to 14B and Figure 17 An example of such an implementation is illustrated in the text.

[0048] In another embodiment, the execution includes an array storage circuit as described above and a control circuit, wherein the control circuit is configured to receive a plurality of input interleaved values ​​and write the plurality of input interleaved values ​​into the array storage circuit. The input interleaved values ​​are written such that the elements of a given interleaved input value are split among a plurality of columns in a given subset of a plurality of columns of the array, and a given row in a plurality of rows comprises ordered elements of a vector. The control circuit is further configured to output data corresponding to rows of the array to form one or more vector result values. For example... Figure 2 , Figures 13A to 13F and Figure 18 An example of such an implementation is illustrated in the text.

[0049] In one embodiment, the execution circuitry includes storage circuitry configured to receive writes representing values ​​of columns of the array and to provide reads corresponding to values ​​of rows of the array. In various embodiments of the operation of the execution circuitry, elements of each input vector to be interleaved are split between columns of the array at intervals equal to the number of input vectors. Figures 12A to 12F and Figures 14A to 14B The example illustrates this interval. In a specific implementation with limited write ports, one way to avoid execution latency is to use two array memory circuits within the execution circuitry, such that while the result value from the first interleaving (or deinterleaving) operation is being read from the first array memory circuitry, a new input vector can be written into the second array memory circuitry as part of a second interleaving (or deinterleaving) operation. Figure 16 This configuration is illustrated in the example. Another example configuration includes a single array memory circuit combined with a side buffer, which is configured to accommodate rows in the array memory circuit that cannot be written to the target of the interleaving operation during the first cycle after the array memory circuit is full. In one embodiment, the side buffer is configured to accommodate the number of rows of the array memory circuit equal to the number of missing write ports available for selection during the first cycle after the array memory circuit is full. In such embodiments, all data in the array memory circuit can be read out in one cycle (either via a write port to the intended target or into the side buffer), while new input values ​​are written to the array memory circuit in subsequent cycles, while the side buffer is writing out the remaining resulting values. Figure 15 An example of this configuration is shown in the figure.

[0050] The implementation of the interleaved execution circuit described herein provides improved throughput for interleaving and deinterleaving operations compared to execution via decoding into micro-operations typically used for interleaved reads and writes to registers. The implementation of the interleaved execution circuit can be used to execute single ISA interleaved or deinterleaved instructions, or for the fused execution of, for example, move instructions with interleaved or deinterleaved instructions.

[0051] Figure 1 Examples of certain elements of a processor 100 configured to use a fusion buffer to manage operands are illustrated. As shown, the processor 100 includes operand management circuitry 102 coupled to execution circuitry 106. Execution circuitry 106 is also coupled to data memory 108, which includes register 110. Operand management circuitry 102 includes a fusion buffer 104 configured to store stored instruction operations 112. Figure 6A and Figure 6B The detection and storage of store instruction operations are further illustrated herein. In one embodiment, store instruction operation 112 is a decoded version of a store instruction that can be executed to store one or more first operand values, which can be used by one or more consumer instructions, into one or more destination registers in register 110. Examples of store instructions include lookup table instructions and move instructions, but other instruction types suitable for generating large operands may also be used with the circuitry and methods described herein.

[0052] In various implementations, eligibility criteria can be established for determining whether a stored instruction operation has been removed from the execution pipeline and stored in the fusion buffer 104. In some implementations, for example, only the most recent instruction operation in the execution pipeline is eligible for entry into the fusion buffer. In some implementations, specific instructions (such as specific lookup table or move instructions) can be designated as eligible. Other criteria may also be implemented based on, for example, timing constraints of the processor's execution pipeline.

[0053] In various implementations, operand management circuitry 102 is configured to check for discard conditions associated with store instruction operation 112. Figure 9 This implementation is illustrated below. In response to the detection of a discard condition, the stored instruction operation 112 is discarded from the execution pipeline and is not transmitted to the execution circuit 106. Figure 10 and Figure 11The diagram illustrates an implementation of a method that includes detecting a discard condition. Because store instruction operation 112 is not executed in this scenario, the operand is not written to register 110. In some implementations, detecting a discard condition includes determining that there are no more consumer instruction operations in the processor's instruction pipeline for the operand generated by store instruction operation 112. This determination can be made using a mapper or other register-mapped data structure. Detecting a discard condition may also include determining that no consumer instruction operation for store instruction operation 112 has yet arrived. This determination may, in some cases, stem from the execution of a fused instruction operation 116 that combines the operations of store instruction operation 112 with the incoming consumer instruction operation 114, provided that the execution of fused instruction operation 116 overwrites the destination register specified by store instruction operation 112. As another example, the arrival of an additional store instruction operation specifying the same destination register indicates that the first store instruction operation will not have an additional consumer instruction operation. Figure 7C The example illustrates a scenario where fusion instruction operation 116 is transmitted for execution, while storage instruction operation 112 is discarded.

[0054] In various embodiments, the stored instruction operation 112 may be held in the fusion buffer 104 until either a discard condition or a buffer vacating condition is detected. A buffer vacating condition is a condition requiring the removal of the stored instruction operation from the fusion buffer. As an example, in some embodiments, the arrival of an additional stored instruction operation eligible for storage in the fusion buffer constitutes a buffer vacating condition. Depending on the processor's operation, the arrival of an instruction operation assigned to the same execution pipeline as the buffered instruction operation may also constitute a buffer vacating condition. Other examples of possible buffer vacating conditions include the arrival of certain instructions that set or reset the state in the processor, or the expiration of a time limit established for holding an instruction in the fusion buffer. In one embodiment, if a buffer vacating condition is detected and no discard condition exists, the stored instruction operation 112 is forwarded along the execution pipeline for execution. Figure 8 and Figure 10 This scenario is illustrated below. This execution will cause the operand value to be written to the destination register specified by the store instruction.

[0055] If an incoming consumer instruction operation 114 is detected while the stored instruction operation 112 is in the fusion buffer 104, and any other fusion eligibility requirements are met, then the stored instruction operation 112 and the consumer instruction operation 114 are fused into a fusion instruction operation 116 for execution. Figure 11The text illustrates implementations of methods that include fusing store instruction operations and consumer instruction operations for execution. In various implementations, fusion qualification requirements are implemented to facilitate the proper generation of results specified by the original non-fused instructions through the execution of the fused instruction operations. As an example, for some instruction pairs, the fusion qualification requirement is that the source register specified by the consumer instruction operation matches the destination register specified by the store instruction operation. In some implementations, fusion qualification requirements may also be implemented to reduce timing complexity in the processor's execution pipeline. For example, fusion qualification may be limited to certain specific instructions or instruction types.

[0056] As examples, in embodiments where store instruction operations implement lookup table operations such as those specified by ARM LUTI instructions, qualified consumer instruction operations may, in some embodiments, include consumer instruction operations that implement matrix operations or grid-based operations. In embodiments where store instruction operations implement move instructions from a memory array (such as ARM MOVA instructions), qualified consumer instruction operations may, in some embodiments, include consumer instruction operations that implement shift and saturation operations. In other embodiments where store instruction operations implement move instructions from a memory array, qualified consumer instruction operations may, in some embodiments, implement interleaving or deinterleaving operations. The foregoing is merely illustrative, and other combinations of qualified instructions for fused execution may be implemented using the circuitry and techniques disclosed herein.

[0057] In one implementation, fusion instruction operation 116 is executable to perform the operation specified by consumer instruction operation 114 using operands specified by store instruction operation 112. In another implementation, the execution of fusion instruction operation 116 does not involve writing operands to the destination register specified by store instruction operation 112 and then reading them back, as would occur during the separate execution of instruction operations 112 and 114. For example, if store instruction operation 112 is a lookup table operation, in this implementation, fusion instruction operation 116 is executable to obtain operands from the lookup table and use the obtained operands to perform the operation specified by consumer instruction operation 114. If store instruction operation 112 is a move instruction for moving a specified portion of the stored array to a register, in this implementation, fusion instruction operation 116 is executable to obtain operands from the stored array and perform the operation.

[0058] In some implementations, execution of the fusion instruction operation 116 results in the overwriting of the destination register specified by the store instruction operation 112. This creates a discard condition, allowing the store instruction operation 112 to be removed from the fusion buffer 104 and discarded without further execution. In other implementations, execution of the fusion instruction operation 116 does not overwrite the destination register of the store instruction operation 112. In this implementation, the store instruction operation 112 may remain in the fusion buffer 104 for possible fusion with additional consumer instruction operations that specify operands generated by the store instruction operation 112. Figure 7B This scenario is illustrated in the example. In other implementations, the buffer emptying condition can be set such that only one merge execution is allowed for a given store instruction operation. In this case, store instruction operation 112 will be removed from the buffer and either discarded (if the discarding condition is met) or forwarded for execution.

[0059] Figure 1 The processor 100 can take various forms. For example, the circuits and methods described herein can be made by, for example, Figure 3 and Figure 4 The illustrated coprocessor or is composed of, for example Figure 5 The illustrated core processor implementation. In one embodiment, processor 100 is a non-speculatory processor.

[0060] Figure 2 This is a block diagram illustrating an execution circuit 200 configured to perform interleaving and deinterleaving operations. In various embodiments, the execution circuit 200 includes execution circuitry such as... Figure 1 Circuit 106 or Figure 3 , Figure 4 and Figure 5 The corresponding execution circuits 318, 418, and 540 are used. Execution circuit 200 may also be referred to herein as an "interleaved execution circuit" or an "interleaved / deinterleaved execution circuit." In various embodiments, execution circuit 200 and other interleaved execution circuit embodiments described herein can be used for the execution of interleaved or deinterleaved operations corresponding to a single ISA instruction (such as, for example, ARM ZIP or UZP instructions) or interleaved load and store operations (such as ARM LD4 or ST4 instructions). The interleaved execution circuit as described herein can also be used for the execution of fused instruction operations that combine store instruction operations executable to generate operands, as described herein, with consumer instructions executable to perform interleaved or deinterleaved operations using the generated operands.

[0061] like Figure 2As shown, the execution circuit 200 includes an array storage circuit 202 coupled to the control circuit 204. The array storage circuit 202 includes element storage circuits 206 configured to store elements having rows 212 and columns 214 (examples of which are shown in...). Figure 2 The array 208 (circled in the image) contains elements 210. Although the array storage circuit 202 is shown as having element storage circuitry 206 arranged in a two-dimensional array of the same size as array 208, in various embodiments, the array storage circuitry 202 can be configured differently. For example, in some embodiments, the array storage circuitry 202 may include more element storage circuitry 206 than is required to store the elements of a given array (such as array 208). The array storage circuitry 202 may also include elements arranged in a non-two-dimensional array manner (such as a three-dimensional arrangement or a one-dimensional arrangement along a single line). However, the element storage circuitry 206 may be physically arranged within the array storage circuitry 202, and the circuitry 202 is configured such that elements 210 can be written to or read from with respect to their position in array 208 (such as through rows or columns of array 208). Figure 2 In this text, solid lines are used to depict hardware such as circuits, while dashed lines are used to depict data stored or manipulated by the hardware. As used herein, storing data into an array such as array 208 should be understood as storing the data into the corresponding element storage circuit of the array storage circuit such as circuit 202.

[0062] In one embodiment, control circuitry 204 is configured to receive a plurality of input vectors, such as input vector 216. Each vector 216 includes a plurality of vector elements 218. Receiving input vectors may include reading input vectors from registers or other storage devices. In embodiments where execution circuitry 200 is used to perform fusion instruction operations, the input vectors may be operands obtained from a location specified by a stored instruction fused with interleaving instructions. For example, input vectors may be obtained from a lookup table or a stored array. In some embodiments, control circuitry 204 is further configured to write the plurality of input vectors 216 into array storage circuitry 202 such that the elements of a given input vector are split among a plurality of columns in a given subset of a plurality of columns 214 within array 208. For example Figures 12B to 12E and Figures 14A to 14B An example of this splitting of input vector elements across multiple columns in a subset is shown. In some embodiments, control circuitry 204 is further configured to write multiple input vectors 216 into array storage circuitry 202, such that a given row 212 of multiple rows in array 208 contains interleaved elements of the multiple input vectors. For example Figures 12E to 12F and Figure 14B An example of such a row with interleaved elements having multiple input vectors is shown in the figure.

[0063] The control circuitry is further configured to output data corresponding to row 212 of array 208 from array storage circuitry 202 in the form of row values ​​220. Row value 220 includes result element 222. Result element 222 is element 210 of array 208 and reflects vector elements 218 that have been rearranged (compared to their arrangement in input vector 216) by means of being written into and read from array storage circuitry 202. In various embodiments, row values ​​220 may form individual result values ​​or be concatenated into one or more longer result values. Figure 17 An embodiment of a method for interleaving input vectors using execution circuitry such as circuit 200 is illustrated.

[0064] In another embodiment, the control circuit 204 is configured to receive multiple interleaved input values ​​such as Figure 13A The value is 1302, not the input vector 216. Instead of the element 218 of the given vector, the elements of the interleaved input value 1302 are the interleaved elements of multiple vectors. In some embodiments, the control circuitry 204 is further configured to write multiple interleaved input values ​​into the array storage circuitry 202, such that the elements of the given interleaved value are split among multiple columns of a given subset of multiple columns 214 within the array 208. For example... Figures 13B to 13E An example of this splitting of interleaved input value elements across multiple columns in a subset is shown. In some embodiments, control circuitry 204 is further configured to write multiple interleaved input values ​​into array storage circuitry such that a given row 212 of multiple rows in array 208 has ordered elements of a vector. For example... Figures 13E to 13F An example of such a row with ordered vector elements is illustrated below. The control circuitry is further configured to output data corresponding to row 212 of array 208 from array storage circuitry 202 to form one or more result values. Figure 18 An embodiment of a method for deinterleaving an input vector using an execution circuit such as circuit 200 is illustrated.

[0065] Returning to the operand management circuit discussed above, Figure 3 , Figure 4 and Figure 5 Example elements of a processor configured to use a fusion buffer to manage operands are shown. Figure 3 An example is shown that includes a CPU processor 340, a coprocessor 300, and a secondary (L2) cache 350. The coprocessor 300 is... Figure 1Examples of specific implementations of processor 100. In some implementations, instead of or in addition to L2 cache 350, coprocessor 300 may be coupled to a data cache (DCache, not shown) in CPU processor 340. Coprocessor 300 is configured to receive instructions from CPU processor 340 and provide results to CPU processor 340. In one implementation, coprocessor 300 is a coprocessor for performing vector and matrix operations. Coprocessor 300 includes instruction buffer 310, decoding circuitry 312, map-dispatch-rename (MDR) circuitry 314, op queue 316, data buffer 320, and execution circuitry 318. In various implementations, the circuitry within MDR circuitry 314 implements operand management circuitry, such as... Figure 1 Circuit 102. Execution circuit 318 (in some embodiments, combined with op queue 316) implements the execution circuit, such as... Figure 1 Circuit 106. In various embodiments, data buffer 320 implements a data memory, such as Figure 1 Data storage device 108.

[0066] In various embodiments, coprocessor 300 is configured to perform one or more computational operations and / or one or more coprocessor load / store operations. Coprocessor 300 may employ an instruction set, which in some embodiments may include a subset of the instruction set implemented by CPU processor 340, or may include instructions not implemented by CPU processor. In one embodiment, CPU processor 340 recognizes instructions implemented by coprocessor 300 and transmits those instructions to the coprocessor. Any mechanism for transporting coprocessor instructions from CPU processor 340 to coprocessor 300 may be used. For example, Figure 1 A communication path 335 between CPU processor 340 and coprocessor 300 is illustrated. For example, if coprocessor 300 is physically located near CPU processor 340, this path can be a dedicated communication path. This communication path can also be shared with other communications. For example, a packet-based communication system may be used in some embodiments to send memory requests to system memory and to send instructions to coprocessor 300. In one embodiment, instructions may be bundled and sent to coprocessor 300. In a particular embodiment, coprocessor instructions may be communicated to coprocessor 300 via L2 cache 350. For example, cache operations, cache evictions, etc., may be sent from CPU processor 340 to L2 cache 350, and therefore an interface may exist for sending operation and data cache lines. In one embodiment, the same interface may be used to send instruction bundles to coprocessor 300 via L2 cache 350.

[0067] In one implementation, the coprocessor 300 may support various data types and data sizes (or precisions). For example, floating-point and integer data types may be supported. In various implementations, floating-point data types include 16-bit, 32-bit, and / or 64-bit precision. Integer data types may include 8-bit and 16-bit precision in various implementations and may support both signed and unsigned integers. Other implementations may include subsets of the above precisions, additional precision, or subsets of the above precisions and additional precision (e.g., larger or smaller precision). In one implementation, 8-bit and 16-bit precision may be supported on input operands, and 32-bit accumulation may be supported for the results of operations performed on those operands.

[0068] In various embodiments, coprocessor 300 is configured to receive instructions from CPU processor 340 into instruction buffer 310. Decoding circuitry 312 decodes the received instructions into one or more instruction operations (ops) for execution. In various embodiments, decoding circuitry 312 may implement a decoding stage and a pre-decoding stage at the front end of coprocessor 300. These decoded ops may include, for example, computational ops performed using execution circuitry 318, and memory ops for reading data from memory into data buffer 320 and storing data from data buffer 320 into memory (via L2 cache 350). In one embodiment, computational ops include ops using vector operands stored in data buffer 320. In another embodiment, execution circuitry 318 includes grid execution circuitry having memory distributed among the elements of the grid execution circuitry for storing the results of operations using vector operands. In various embodiments, execution circuitry 318 may also include other types of execution circuitry, such as the interleaved / deinterleaved execution circuitry described herein.

[0069] In one implementation, a coprocessor load operation for coprocessor 300 can load a vector from system memory ( Figure 3(Not shown) The data is transferred to memory within data buffer 320 or execution circuitry 318. In some embodiments, coprocessor memory operations may write vectors from data buffer 320 or from memory within execution circuitry 318 to system memory. System memory may be formed of random access memory (RAM), such as various types of dynamic RAM (DRAM) or static RAM (SRAM). A memory controller may be included to interface with system memory. In one embodiment, coprocessor 300 is a cache consistent with CPU processor 340. In another embodiment, coprocessor 300 may have access to L2 cache 350, and L2 cache 350 ensures cache consistency with the cache of CPU processor 340. In yet another embodiment, coprocessor 300 may have access to the memory system, and a consistency point in the memory system ensures consistent access. As another alternative, coprocessor 300 may have access to the CPU cache. In yet another embodiment, coprocessor 300 may have one or more caches (which may be virtually addressed or physically addressed as needed). If L2 cache 350 is not provided and access to the CPU cache is not provided, the coprocessor cache may be used. Alternatively, the coprocessor 300 may have a cache and access to L2 cache 350 for misses in those caches. In various implementations, any mechanism for accessing memory and ensuring consistency may be used.

[0070] In one implementation, CPU processor 340 may be responsible for fetching instructions to be executed by CPU processor 340 and coprocessor 300. In one implementation, coprocessor instructions may be issued by CPU processor 340 to coprocessor 300 when they are no longer speculative. Generally, an instruction or operation can be non-speculative if it is known that the instruction will complete execution without an exception / interrupt. Therefore, an instruction can be non-speculative once previous instructions (in program order) have been processed to the point that it is known that the previous instructions will not cause an exception / speculative refresh in CPU processor 340 and that the instruction itself will not cause an exception / speculative refresh. Based on the instruction set architecture implemented by CPU processor 340, it may be known that some instructions will not cause an exception and will not cause a speculative refresh. Once it has been determined that other previous instructions are without exception and without refresh, such instructions are also without exception and without refresh.

[0071] Instruction buffer 310 allows coprocessor 300 to queue instructions while other instructions are being executed. In one embodiment, instruction buffer 310 is a first-in, first-out (FIFO) buffer. That is, in this embodiment, instructions are processed in program order. Other embodiments may implement other types of buffers, multiple buffers for different types of instructions (e.g., load / store instructions and compute instructions), and / or may allow instructions to be processed out of order.

[0072] In one embodiment, decoding performed by decoding circuitry 312 includes extracting architecture source register information and destination register information from the received instruction. In another embodiment, mapping-dispatch-rename (MDR) circuitry 314 maps architecture registers to physical registers and passes ops to op queue 316 for execution. In various embodiments, MDR circuitry 314 implements the instruction mapping and dispatch levels of the front end of coprocessor 300. Op queue 316 ensures that the required operands are ready and forwards ops for execution. In one embodiment, op queue 316 is implemented using a reservation station.

[0073] exist Figure 3 In various implementations, the MDR circuit 314 includes register mapping data 322, storage op detection circuitry 324, fusion buffer 326, buffer management circuitry 328, consumer op detection circuitry 330, and fusion circuitry 332. Register mapping data 322 includes one or more data structures for tracking register information, such as architecture register-to-physical register assignments or consumer ops for a given register. In various implementations, register mapping data 322 may include, for example, a register list indicating physical register availability, mapper data indicating which physical registers are mapped to which architecture registers, and / or count data indicating the number of ops consuming data from a given architecture register. In various implementations, register mapping data 322 may be stored in one or more content-addressable memories (CAMs).

[0074] The storage operation detection circuit 324 is configured to identify storage operations eligible for placement in the fusion buffer 326 from among the decoded operations. In one embodiment, certain storage operations executable to write large operands to destination registers are designated as eligible for placement in the fusion buffer. For example, lookup table instruction operations (such as decoded LUTI instructions in an ARM ISA) may be eligible for placement in the fusion buffer 326. In another embodiment, LUTI instruction operations with a larger number of destinations (such as two or four destinations) may be eligible for placement in the fusion buffer. As another example, move instruction operations (such as decoded MOVA instructions in an ARM ISA) may be eligible for placement in the fusion buffer 326.

[0075] In some implementations, more instruction operations are eligible for immediate fusion execution with available consumer instruction operations compared to those eligible for placement in the fusion buffer. For example, in some implementations, a single-target MOVA instruction operation may be eligible for fusion with instruction operations appearing in the same decoding group that perform matrix operations on a target value using the MOVA instruction operation. However, if no consumer instruction is available for fusion when such a single-target MOVA instruction operation appears, it may not be eligible for placement in fusion buffer 326 to await possible subsequent consumer instructions. In some implementations, placement in fusion buffer 326 may be limited to stored instruction operations configured to generate multiple operands or larger operands. In various implementations, the determination of eligibility for placement in fusion buffer 326 may involve other considerations, such as the availability of execution circuitry required for the execution of a particular fusion instruction operation. In one implementation, if multiple eligible instruction operations arrive in the same decoding group, the newer of these eligible instruction operations (the latter in program order) is placed in fusion buffer 326. In some implementations, only certain instructions within the decoding group (such as the latest instruction) are considered for placement in the fusion buffer.

[0076] In one implementation, the fusion buffer 326 is a single-entry buffer configured to store a single store instruction operation. The fusion buffer 326 is configured such that the store instruction operation can be stored in the buffer 326 before reaching the op queue 316. An op placed in the fusion buffer is removed from normal execution for at least the time it remains in the fusion buffer. Placing the op in the buffer provides the possibility that the op is executed only as a fusion op, thus avoiding writes to the destination register of the operands of the operands associated with that op.

[0077] Buffer management circuitry 328 is configured to determine whether an instruction operation should be removed from fusion buffer 326, and whether the removed instruction operation is discarded or forwarded for execution. The condition for removing an instruction operation from fusion buffer 326 is also referred to herein as the "emptying" or "buffer emptying" condition. (As described above...) Figure 1As described, various events can be defined as vacating conditions, including the arrival of another stored instruction operation to be stored in the fusion buffer. In some implementations, vacating conditions arise from events that make maintaining management of a particular instruction operation in the fusion buffer 326 more difficult or otherwise undesirable, such as the arrival of certain system instruction operations or the arrival of instruction operations assigned to the same execution pipeline as the buffered instruction operation. As another example, a vacating condition can be the result of exceeding a time limit. In some implementations, a vacating condition can be defined as removing an instruction operation from the fusion buffer 326 after a single fusion execution with an eligible consumer instruction operation has been performed (in other words, not keeping the instruction operation in the buffer for a desired fusion execution with an additional consumer instruction operation).

[0078] In one embodiment, buffer management circuitry 328 is configured to determine whether an instruction operation can be discarded rather than delivered to its corresponding execution pipeline when a buffer vacancy condition occurs for a given buffered instruction operation. For example, the instruction operation can be discarded if it is determined that there are no current or future consumer instruction operations that would require the result of the buffered instruction operation. In one embodiment, detecting the discard condition includes examining data within register map data 322. For example, checking for a buffer discard condition may include checking a data structure that tracks how many consumer instruction operations are in the processor's execution pipeline for the target register of the buffered instruction operation. In one embodiment, this data structure is a physical register table in the CAM. A count of zero consumer instructions in such a data structure may indicate that there are no existing consumer instruction operations for the buffered instruction operation in the processor's execution pipeline. Checking for a buffer discard condition may also include checking mapper data to see if the target register of the buffered instruction operation is being used by a different instruction. If so, there will be no future consumer instruction operations for the buffered instruction operation. In one embodiment, checking the mapper data includes checking the architecture register table of the target physical register for the buffered instruction operation in the CAM. In various implementations, if no existing or future consumer instruction operation is detected for a buffered (or previously buffered and newly vacated) instruction operation, the instruction operation may be discarded instead of being forwarded for execution when removed from the fusion buffer 326.

[0079] The consumer operation detection circuit 330 is configured to identify consumer instruction operations eligible for fusion execution with stored instruction operations stored in the fusion buffer 326. In various embodiments, the consumer operation detection circuit 330 can implement various fusion eligibility requirements, such as those described above. Figure 1Those discussed. For example, a qualification requirement could be that the source register specified by a consumer instruction operation matches the target register of a buffered store instruction operation. A particular consumer instruction operation can be specified as qualified to be fused with a particular buffered store instruction operation. The fusion circuit 332 is configured to combine qualified consumer instruction operations detected by the consumer op detection circuit 330 with stored instruction operations in the fusion buffer 326 to form fused instruction operations, such as... Figure 1 The fused instruction operation 116 is executable to obtain one or more operands generated by the buffered instruction operation executable, and uses the operands to perform operations to be performed by an eligible consumer instruction operation executable. In one embodiment, execution of the fused instruction operation does not involve writing operands to the destination register of the buffered instruction operation. In some embodiments, execution of the fused instruction operation may involve the use of dedicated execution circuitry within execution circuitry 318. In some embodiments, the buffered instruction operation is retained in fusion buffer 326 for possible fusion with additional eligible consumer instruction operations.

[0080] In some implementations, the detection of eligible consumer instruction operations for fusion implements any relevant criteria used to determine whether fusion should be performed, such as circuit timing considerations or the availability of execution circuitry, such that consumer instruction operations determined to be eligible for fusion are fused with buffered instruction operations. In other implementations, the determination of whether fusion should be performed given eligibility for fusion is determined separately. For example, in some implementations, the consumer op detection circuit may detect eligible consumer instruction operations for fusion with buffered instruction operations, while the fusion circuit 332 determines whether the fusion should be performed. Figure 3 Example elements of coprocessor 300 are illustrated, and it may include a number of other elements not shown. In various embodiments, for example, coprocessor 300 may include detection and fusion circuitry for additional fusion instruction execution (such as fusion execution of suitable unbuffered instruction pairs) that does not involve fusion buffer 326. Such detection and fusion circuitry may be included in… Figure 3 The detection and fusion circuit shown may be included in, or contained in, a separate circuit not shown.

[0081] Figure 4 Example elements of a coprocessor 400 configured to use multiple fusion buffers to manage operands are shown. Coprocessor 400 is similar to... Figure 3The coprocessor 300 includes a first op queue, a second op queue, and a third op queue, as well as a first execution circuit, a second execution circuit, and a third execution circuit. In one embodiment, different execution circuits and op queues are used for different types of instructions. As an example, one combination of execution circuit and op queue can be used for load / store operations, one combination of execution circuit and op queue can be used for grid-based operation execution, and one combination of execution circuit and op queue can be used for operations using other types of execution circuits. The coprocessor 400 also has two fusion buffers within MDR circuitry 414. In one embodiment, operand management circuitry as described herein can use separate fusion buffers for corresponding separate execution pipelines.

[0082] As shown in the figure, the coprocessor 400 includes an instruction buffer 410, a decoding circuit 412, an MDR circuit 414, a data buffer 420, an op queue 416, and an execution circuit 418. The instruction buffer 410, decoding circuit 412, and data buffer 420 are similar to those described above. Figure 3 The instruction buffer 310, decoding circuitry 312, and data buffer 320 are described. The op queue 416 includes a first op queue 434A, a second op queue 434B, and a third op queue 434C, and the execution circuitry 418 includes a first execution circuit 436A, a second execution circuit 436B, and a third execution circuit 436C. In one embodiment, each of the op queues 434A, 434B, and 434C feeds a corresponding set of execution circuits 436A, 436B, and 436C. For example, the first op queue 434A and the first execution circuit 436A may form a first execution pipeline, the second op queue 434B and the second execution circuit 436B may form a second execution pipeline, and the third op queue 434C and the third execution circuit 436C may form a third execution pipeline. In one embodiment, for example, load / store operations may be assigned to the first execution pipeline, grid-based operations may be assigned to the second execution pipeline, and other types of operations may be assigned to the third execution pipeline. In various implementations, the coprocessor 400 is configured such that a given op queue can feed more than one set of execution circuits. For example, in some implementations, it may be possible to use more than one op queue to access dedicated execution units such as mesh execution circuits or interleaving / deinterleaving execution circuits.

[0083] MDR circuit 414 includes register-mapped data 422, storage op detection circuit 424, first fusion buffer 426A, second fusion buffer 426B, buffer management circuit 428, consumer op detection circuit 430, and fusion circuit 432. In one embodiment, the first fusion buffer 426A and the second fusion buffer 426B are used to store different types of storage instruction operations. For example, buffer 426A can be used to store lookup table instruction operations, such as decoded ARM LUTI instructions, while buffer 426B is used to store instruction operations for moving data from the memory array, such as decoded ARM MOVA instructions. In one embodiment, each of fusion buffers 426A and 426B is connected to a set of dispatch channels leading to one of op queues 434A, 434B, or 434C. In another embodiment, each of buffers 426A and 426B is connected to a dispatch channel leading to a different op queue. In some implementations, a fusion instruction operation that combines a stored instruction operation stored in one of the fusion buffers 426A or 426B is assigned to an op queue different from the op queue to which the buffered stored instruction operation would have originally been assigned for execution.

[0084] Register mapping data 422, storage op detection circuit 424, buffer management circuit 428, consumer op detection circuit 430, and fusion circuit 432 are similar to Figure 3 The corresponding circuit within the MDR circuit 314 differs in that each of these elements is configured for use with two fusion buffers instead of one fusion buffer. Although shown as a single circuit for simplicity... Figure 4 The block diagram is provided, but any or all of the circuits 424, 428, 430, or 432 can be implemented as separate circuits corresponding to each of the fusion buffers 426A and 426B. Depending on factors such as the type of instruction used for fusion of buffers 426A or 426B, circuits 424, 428, 430, and 432 can implement different standards for different buffers in terms of storage, fusion, buffer emptying, and / or discarding operations. Figure 4 The example elements of coprocessor 400 are illustrated, and may include several other elements not shown. In various embodiments, for example, different numbers of op queues and / or execution circuitry may be included.

[0085] Figure 5 This is a block diagram illustrating example elements of a core processor or CPU processor configured to use a fusion buffer to manage operands. Figure 5 The processor 500 is Figure 1 Another example of a specific implementation of processor 100. In some implementations, processor 500 is a non-speculatory processor. Figure 5In the implementation scheme, operand management circuitry such as Figure 1 The functional circuitry of circuit 102 is included in the MDR circuitry 520 of processor 500. In an exemplary embodiment, processor 500 includes fetch and decode circuitry 510, MDR circuitry 520, a set of retention stations (RS) 527 and 532, one or more execution circuits 540, register file 545, data cache or “DCache” 517, and load / store unit (LSU) 534. In some embodiments, execution circuitry 540 (in combination with retention stations 527 and 532) implements execution circuitry such as Figure 1 Circuit 106. In various implementations, register file 545 implements data memory, such as Figure 1 The data storage 108. As depicted, the fetch and decode circuitry 510 includes an instruction cache or “ICache” 215 and is coupled to an MDR unit 520, which includes a buffer management circuitry 506, a fusion circuitry 508, a fusion buffer 512, a storage op detection circuitry 524, a register-mapped data 525, and a consumer op detection circuitry 530.

[0086] In various embodiments, the fetch and decode circuit 510 is configured to fetch instructions for execution by processor 500 and decode these instructions into instruction operations (“ops”) for execution. More specifically, the fetch and decode circuit 510 may be configured to cache instructions fetched from memory via an external interface into ICache 515. In embodiments where processor 500 is a speculative processor, the fetch and decode circuit 510 may be configured to fetch speculative paths for instructions for processor 500. As used herein, an “instruction” is an executable entity defined in an ISA implemented by a processor, such as processor 500 or coprocessors 300 and 400. In various embodiments, the fetch and decode circuit 510 may decode an instruction into multiple ops depending on the complexity of the instruction. Particularly complex instructions may be micro-coded. In such embodiments, micro-coded routines for instructions may be decoded in an op. However, in other embodiments, each instruction within the instruction set architecture implemented by processor 500 may be decoded into a single op, and thus the op may be synonymous with its corresponding instruction (although its form may be modified by the decoder). Therefore, the terms “instruction operation” or “op” can be used herein to refer to an operation in which the execution circuitry in the processor is configured to be executed as a single entity.

[0087] In various implementations, ICache 515 and DCache 517 can each be a cache with any desired capacity, cache line size, and configuration. Cache lines can be allocated / deallocated in the cache as units, and thus define the units of allocation / deallocation of the cache. The size of a cache line can vary (e.g., 32 bytes, 64 bytes, or larger or smaller). Different caches can have different cache line sizes. Further additional levels of cache, such as last-level caches, can exist between ICache 515 / DCache 517 and main memory. In various implementations, ICache 515 is used to cache fetched instructions and DCache 517 is used to cache data fetched or generated by processor 500.

[0088] In various implementations, MDR circuit 520 is configured to map the op received from extraction and decoding circuit 510 to a physical register to allow execution. As shown, MDR circuit 520 can dispatch the op to RS 527 or RS 532. Reservation stations 527 and 532 perform actions similar to those described above. Figure 3 The discussion concerns the function of the op queue 316 of the coprocessor 300. Ops can be mapped from architecture registers used in corresponding instructions to physical registers in register file 545. In various embodiments, register file 545 functions similarly to data buffer 320 of coprocessor 300. Register file 545 can implement a set of physical registers larger than the number of architecture registers specified by the instruction set architecture implemented by processor 500. Therefore, MDR circuitry 520 manages the mapping between architecture registers and physical registers. In some embodiments, separate physical registers may exist for different operand types (e.g., integer, floating-point, etc.). However, in some embodiments, physical registers may be shared between different operand types.

[0089] The MDR circuit 520 is further configured to implement operand management circuitry, such as... Figure 1 Circuit 102. Buffer management circuit 506, fusion circuit 508, and fusion buffer 512 are similar to those described above. Figure 3 The described coprocessor 300 includes a buffer management circuit 328, a fusion circuit 332, and a fusion buffer 326. Similarly, the storage op detection circuit 524, the register mapping data 525, and the consumer op detection circuit 530 are similar to those of the coprocessor 300.

[0090] In various implementations, LSU 534 is configured to execute memory operations received from MDR circuitry 520. Typically, a memory operation is an instruction operation that specifies an access to memory, although this memory access may be performed in a cache such as DCache 517. Thus, a load memory operation specifies the transfer of data from a memory location to a register of processor 500, while a store memory operation specifies the transfer of data from a register to a memory location.

[0091] In various implementations, the execution circuit 540 includes any type of execution circuit, and the use of the fusion buffer as described herein is similar to, for example... Figure 1 The execution circuit 106 and Figure 3 The execution circuit 318 functions. The execution circuit 540 may include integer execution circuitry configured to execute integer ops, floating-point execution circuitry configured to execute floating-point ops, or vector execution circuitry configured to execute vector ops, as well as dedicated execution circuitry such as grid execution circuitry and interleaving / deinterleaving circuitry. The execution circuits 540 are typically independent of each other, as each execution unit can be configured to operate on ops posted to that execution unit without relying on other execution circuits 540. In various embodiments (including embodiments with one execution circuit 540 and embodiments with multiple execution circuits 540), any number and type of execution circuits 540 may be included.

[0092] Figures 6A to 8 This document illustrates example buffer management and fusion scenarios using fusion buffers as described in this article. Figure 6A As shown, decoding channels labeled 0, 1, and 2 are configured to carry decoding instructions toward dispatch station 602. Decoding channels 0, 1, and 2 may also be referred to herein as dispatch channels. In various embodiments, dispatch station 602 may be implemented as a reservation station and referred to as an op queue (such as...). Figure 3 op queue 316 and Figure 4 One of the 416 op queues), or what is called a reserve station (such as Figure 5 (Reserved stations 527 or 532). Figures 6A to 8 In one implementation, decoding channels 0, 1, and 2 are connected to dispatch station 602 via multiplexers 604(0), 604(1), and 604(2). Each decoding channel is connected to fusion buffer 606 via multiplexer 608. In one implementation, fusion buffer 606, multiplexer 608, and associated interconnects form operand management circuitry (such as...). Figure 1 Part of the circuit 102. Figure 6AAn example configuration of a decoding / dispatch channel for forwarding instruction operations to the execution circuitry is illustrated; other configurations may be used in other embodiments. For example, different numbers of decoding channels or different multiplexer configurations may be used in other embodiments.

[0093] Figure 6A and Figure 6B This illustrates the sequential time points when the incoming storage instruction operation 112 arrives at a decoding channel within the decoding channel. Figure 6A In the implementation scheme, storage instruction operation 112 arrives at decoding channel 1. Examples of storage instruction operation 112 include those described above. Figure 1 Provided elsewhere in this disclosure. In this example, the storage instruction operation 112 is stored in the fusion buffer 606, as... Figure 6B As illustrated. In various embodiments, the storage instruction operation 112 is selectively placed into the fusion buffer 606 by the operation of a storage operation detection circuit, such as circuits 324, 424, or 524. In one embodiment, the operation of the storage detection circuit includes providing a control signal to the multiplexer 608. Placing the storage instruction operation 112 into the fusion buffer 606 removes the instruction operation 112 from its normal execution flow toward the dispatch station 602.

[0094] Figure 7A An example is illustrated in the scenario where, while store operation 112 is in fusion buffer 606, a consumer instruction operation 114 can be executed to reach a decoding channel using operands generated by the execution of store instruction operation 112. Examples of consumer instruction operation 114 include those described above. Figure 1 Provided elsewhere in this disclosure. In various embodiments, consumer instruction operation 114 arrives at the same decoding group as storage instruction operation 112 or a later decoding group.

[0095] Figure 7B An example of such a scenario is given: Figure 7A Consumer instruction operation 114 has been merged with stored instruction operation 112 to form merged instruction operation 116. In various embodiments, consumer instruction operation 114 is detected by operation of consumer operation detection circuitry such as circuitry 330, 430, or 530, and evaluated by consumer operation circuitry and / or fusion circuitry such as fusion circuitry 332, 432, or 508 to suit fusion execution with stored instruction operation 112. As described above in this disclosure… Figure 1As described, the fusion instruction operation 116 is executable in various embodiments to obtain an operand generated by the execution of the storage instruction operation 112, or at least any portion of that operand required by the consumer instruction operation 114, without writing the operand to the destination register specified by the storage instruction operation 112. Execution of the fusion instruction operation 116 causes the obtained operand to be used to perform the operation specified by the consumer instruction operation 114. In various embodiments, the fusion instruction operation 116 is generated by the operation of a fusion circuit such as circuits 332, 432, or 508. Figure 7B In one embodiment, while stored instruction operation 112 is held in fusion buffer 606, fusion instruction operation 116 is forwarded for execution. In various embodiments, stored instruction operation 112 is held in fusion buffer 606 via the operation of buffer management circuitry such as circuits 328, 428, or 506. In various embodiments, fusion instruction operation 116 may be directed to dispatch station 602 or a different dispatch station (not shown) for forwarding to the appropriate execution circuitry.

[0096] Figure 7C Examples of the same Figure 7B Different scenarios involve Figure 7A The scenario of merging consumer instruction operation 114 and storage instruction operation 112. Figure 7C In one implementation, when the stored instruction operation 112 is discarded from the fusion buffer, the fusion instruction operation 116 is forwarded for execution. In various implementations, the stored instruction operation 112 is discarded from the fusion buffer 606 via the operation of buffer management circuitry such as circuits 328, 428, or 506. In the illustrated implementation, a buffer vacancy condition requiring the removal of instruction operation 112 from the fusion buffer has been detected. Furthermore, a discard condition indicating that separate execution of instruction operation 112 is not required has been detected. Therefore, writing operands generated by the execution of stored instruction operation 112 to registers is avoided.

[0097] Figure 8 This illustrates removing a store instruction operation 112 from the fusion buffer 606 and forwarding the store instruction operation 112 to the execution pipeline for execution. Figure 8 In the illustrated scenario, the buffer management circuit has detected a buffer vacancy condition requiring the removal of instruction operation 112 from the fusion buffer 606, but has not yet detected a discard condition indicating that the execution of instruction operation 112 is unnecessary. Therefore, in this scenario, the operand generated by storing the execution of instruction operation 112 is written to the register.

[0098] Figure 9 This is a flowchart illustrating an example method for operand management using a fused buffer. Method 900 is configured by a processor (such as...) Figure 1Processor 100 Figure 3 coprocessor 300 or Figure 4 coprocessor 400 or Figure 5 One embodiment of the method is executed by processor 500. In one embodiment, method 900 is executed by operand management circuitry within the processor. Other embodiments of the method may include those compared to... Figure 9 More or fewer boxes are shown. Method 900 includes: detecting a first store instruction operation at box 910, the first store instruction operation being executable to store one or more first operand values, which can be used by one or more consumer instruction operations, into one or more destination registers. In one embodiment, the first store instruction operation is detected from instruction operations received from a decoder level of the processor. Figure 1 The store instruction operation 112 is an example of a first store instruction operation. In some embodiments, the first store instruction operation may include lookup table index values ​​and be executable to use those index values ​​to obtain an operand value from the lookup table. In such an embodiment, the ARM LUTI instruction is an example of a store instruction operation. In some embodiments, the first store instruction operation may be executable to move a portion of the memory array to one or more destination registers to form one or more operand values. The ARM MOVA instruction is an example of this type of store instruction operation.

[0099] Method 900 further includes storing the first stored instruction operation into a fusion buffer at block 920, instead of allowing the first stored instruction operation to continue along the execution pipeline of the processor performing method 900. Figure 1 Fusion buffer 104 and Figures 6A to 8 The fusion buffer 606 is an example of a fusion buffer where the first store instruction operation is stored, and Figure 6B An example of placing a store instruction into a fusion buffer is illustrated. At block 930, the method includes removing a first store instruction operation from the fusion buffer in response to detecting a buffer vacancy condition. In one embodiment, detecting a buffer vacancy condition includes detecting a second store instruction operation from instruction operations received by operand management circuitry, the second store instruction operation being executable to store one or more second operand values ​​that can be used by one or more consumer instruction operations. In other embodiments, detecting a buffer vacancy condition may include detecting the satisfaction of one or more other criteria for vacating the buffer. Examples of such other criteria may include: the expiration of a time limit, the arrival of an instruction operation assigned to the same execution pipeline, or the arrival of certain system-level instruction operations. In various embodiments, detecting a buffer vacancy condition may be performed using buffer management circuitry such as circuitry 328, 428, or 506.

[0100] Method 900 further includes checking for a discard condition associated with the first store instruction operation at block 940. In various embodiments, checking for the discard condition may be performed using buffer management circuitry such as circuits 328, 428, or 506. In one embodiment, checking for the discard condition includes determining whether there are any further consumer instruction operations for the first store instruction operation in the processor's execution pipeline, and whether future consumer instruction operations for the first store instruction operation will arrive. The method continues at block 950: based on the result of the check and after the first store instruction operation has been removed from the fusion buffer, the first store instruction operation is processed.

[0101] The processing of the first store instruction operation at block 950 depends on the result of the discard condition check at block 940. For example, in one embodiment, the discard condition check results in a detected discard condition, and processing the first store instruction operation involves discarding the first store instruction operation without forwarding it for execution. In this embodiment, one or more first operand values ​​that the first store instruction operation can execute to store are not written to one or more destination registers. In another embodiment, the discard condition check results in no detected discard condition, and processing the first store instruction operation involves forwarding the first store instruction operation for execution. Figure 8 An example of the latter forwarding scenario is illustrated below. In this implementation, one or more first operand values ​​are written into one or more destination registers as the result of the execution of the first store instruction operation.

[0102] In some embodiments, method 900 may further include: in response to detecting a first consumer instruction operation while the first store instruction operation is in a fusion buffer, fusing the first store instruction operation and the first consumer instruction operation into one or more first fused instruction operations. In this embodiment, the first consumer instruction is eligible to be fused with the first store instruction operation and is executable to perform a first operation using one or more first operand values. The first fused instruction operation is executable to obtain one or more first operand values ​​and perform the first operation without writing one or more first operand values ​​to one or more destination registers. In one embodiment, the first consumer instruction operation is detected from instruction operations received from a decoder level of the processor. Figure 1Consumer instruction operation 114 is an example of a first consumer instruction operation. In one embodiment where the first store instruction operation is executable to move a portion of the memory array to one or more destination registers to form one or more first operands, the first consumer instruction operation is executable to reduce the bit width of one or more first operands. In another embodiment where the first store instruction operation is executable to move a portion of the memory array to one or more destination registers to form one or more first operands, the first consumer instruction operation is executable to interleave or deinterleave elements of one or more first operands.

[0103] In some implementations, method 900 may further include: fusing a second consumer instruction operation with the first store instruction operation after fusing the first consumer instruction operation with the first store instruction operation. In one implementation, fusing the second consumer instruction operation with the first store instruction operation is performed in response to detecting the second consumer instruction operation while the first store instruction operation is in the fusion buffer. This situation may arise from, for example, Figure 7B The scenario shown involves a consumer instruction operation being fused with a store instruction operation for execution while the store instruction operation is held in a fusion buffer. In this implementation, a second consumer instruction operation is eligible to be fused with a first store instruction operation and is executable to perform a second operation using one or more of one or more first operand values.

[0104] Turn now Figure 10 A flowchart of method 1000 is shown. Method 1000 is an implementation of an operand management method using a fused buffer, executed by a processor. In one implementation, method 1000 is executed by operand management circuitry within the processor. Figure 9The description and variations of method 900 also apply to the corresponding elements of method 1000. Method 1000 includes: detecting a first store instruction operation at block 1010, the first store instruction operation being executable to store one or more first operand values, usable by one or more consumer instruction operations, into one or more destination registers. The method further includes: storing the first store instruction operation into a fusion buffer at block 1020, instead of allowing the first store instruction operation to continue along the execution pipeline of the processor performing method 1000. Blocks 1010 and 1020 are similar to blocks 910 and 920 of method 900. If a drop condition is detected (the "yes" branch of decision block 1030), method 1000 includes: removing the first store instruction operation from the fusion buffer at block 1040 without forwarding the execution of the first store instruction operation. This branch of method 1000 will result in the first store instruction operation being executable to store the operand value being written to the destination register. If no discard condition is detected (the "No" branch of decision box 1030), the method includes: at box 1050 and in response to the detection of a buffer emptying condition, removing the first store instruction from the fusion buffer, and forwarding the first store instruction operation for execution. This branch of method 1000 will result in the operand value being written to the destination register.

[0105] In some embodiments, method 1000 may further include: in response to detecting a first consumer instruction operation while the first store instruction operation is in the fusion buffer, fusing the first store instruction operation and the first consumer instruction operation into one or more first fused instruction operations. In this embodiment, the first consumer instruction is eligible to be fused with the first store instruction operation and is executable to perform a first operation using one or more first operand values. The first fused instruction operation is executable to obtain one or more first operand values ​​and perform the first operation without writing one or more first operand values ​​to one or more destination registers. This fusion will be performed before or in conjunction with the removal of the first store instruction operation from the fusion buffer as described at block 1040 or 1050.

[0106] In an additional embodiment, method 1000 may further include: fusing an additional consumer instruction operation with the first storage instruction operation after fusing the first consumer instruction operation with the first storage instruction operation. In one embodiment, fusing the additional consumer instruction operation with the first storage instruction operation is performed in response to detecting the additional consumer instruction operation while the first storage instruction operation is in the fusion buffer. In this embodiment, the additional consumer instruction operation is eligible to be fused with the first storage instruction operation and is executable to perform the additional operation using one or more of one or more first operation values.

[0107] Figure 11 This is a flowchart illustrating an example method 1100 for operand management using a fused buffer, executed by a processor. In one embodiment, method 1100 is executed by operand management circuitry within the processor. Figure 9 Method 900 and Figure 10 The description and variations of method 1000 also apply to the corresponding elements of method 1100. Method 1100 includes: detecting a first store instruction operation at block 1110, the first store instruction operation being executable to store one or more first operand values, usable by one or more consumer instruction operations, into one or more destination registers. The method further includes: storing the first store instruction operation into a fusion buffer at block 1120, instead of allowing the first store instruction operation to continue along the execution pipeline of the processor performing method 1100. Blocks 1110 and 1120 are similar to blocks 910 and 920 of method 900 and blocks 1010 and 1020 of method 1000.

[0108] Method 1100 further includes: at block 1130, in response to detecting a first consumer instruction operation while the first store instruction operation is in the fusion buffer, fusing the first store instruction operation and the first consumer instruction operation into one or more first fused instruction operations. In one embodiment, the first consumer instruction is eligible to be fused with the first store instruction operation and is executable to perform a first operation using one or more first operand values. In various embodiments, the first fused instruction operation is executable to obtain one or more first operand values ​​and perform the first operation without writing one or more first operand values ​​to one or more destination registers. In one embodiment, the first consumer instruction operation is detected from instruction operations received from a decoder level of the processor. Figure 1Consumer instruction operation 114 is an example of a first consumer instruction operation. In one example embodiment where the first store instruction operation is executable to move a portion of the memory array to one or more destination registers to form one or more first operands, the first consumer instruction operation is executable to reduce the bit width of one or more first operands. In another embodiment where the first store instruction operation is executable to move a portion of the memory array to one or more destination registers to form one or more first operands, the first consumer instruction operation is executable to interleave or deinterleave elements of one or more first operands.

[0109] Method 1100 further includes: at block 1140, in response to detecting a discard condition associated with the first store instruction operation, removing the first store instruction operation from the fusion buffer without forwarding its execution. In one embodiment, detecting a discard condition includes determining that there are no more consumer instruction operations for the first store instruction operation in the processor's execution pipeline. Detecting a discard condition may also include determining that no future consumer instruction operations will arrive. For example, in some embodiments, execution of a fusion instruction operation (such as a fusion instruction operation derived from block 1130) may overwrite the destination register associated with the first store instruction operation, such that no additional instruction operations can use the operands generated by the first store instruction operation.

[0110] In some implementations, method 1100 further includes removing a first store instruction operation in response to detecting a buffer vacating condition. In various implementations, this vacating condition can be detected at any time while the first store instruction operation is in the fusion buffer. Therefore, the vacating condition eliminates the option of fusion the first store instruction operation for execution or discarding it without execution. In such implementations, whether the first store instruction operation is discarded or forwarded for execution depends on whether a discard condition is detected when it is removed from the buffer based on the vacating condition.

[0111] Returning to the interleaved execution circuit discussed above, Figures 12A to 12F Examples of using interleaved execution circuits, such as Figure 2 Example input vectors, array contents, and output row values ​​at various stages of the interleaving process of circuit 200. Figure 12A The diagram shows the set of input vectors used for the interleaving execution circuit. Input vectors 1202A, 1202B, 1202C, and 1202D are... Figure 2 An example of an input vector of 216. For illustrative purposes, Figure 12AEach element of the input vector is labeled with a letter and a number, where the letter corresponds to the vector to which the element belongs, and the number corresponds to the element's position within the vector. In some implementations, the number of elements in each input vector 1202 is a multiple of the number of interleaved input vectors. (As used herein, "multiple" means an integer multiple.) Figures 12B to 12E Examples are given for the Figure 12A The contents of array 1204 are stored in array storage circuitry (such as circuit 202) within an array of interleaving / deinterleaving execution circuitry (such as circuit 200) during the interleaving operation of the input vectors. In some embodiments, the number of elements in each input vector 1202 is a multiple of the number of rows in array 1204.

[0112] Figure 12B The diagram illustrates the contents of array 1204 after the first pass of storing the input vector into the array memory circuitry. In one implementation, each pass of the storage operation is completed within a single clock cycle. As illustrated, elements of input vector 1202A are stored into array 1204 during the first pass. A first set of elements, including elements A7, A5, A3, and A1, is stored in the first column of array 1204, where in this case the first column is the leftmost column. The remaining elements of vector 1202A form a second set of elements stored in the second column of array 1204, where in this case the second column is the fifth column from the left. These two columns form a subset of the columns of array 1204. Figure 12B As shown, the two columns within the subset are spaced apart in the array by a number of columns equal to the number of input vectors (IV).

[0113] Figure 12C The diagram illustrates the contents of array 1204 after the second pass of storing the input vector. As illustrated, elements of input vector 1202B are stored in array 1204 during the second pass. The first set of elements from vector 1202B (including elements B7, B5, B3, and B1) is stored in the first column of array 1204, where in this case the first column is the second column from the left. The remaining elements of vector 1202B form the second set of elements stored in the second column of array 1204, where in this case the second column is the sixth column from the left. These two columns form the second subset of the columns of array 1204.

[0114] Figure 12DThe diagram illustrates the contents of array 1204 after the third pass through which the input vector is stored. As illustrated, elements of input vector 1202C are stored into array 1204 during the third pass. The first set of elements from vector 1202C (including elements C7, C5, C3, and C1) is stored in the first column of array 1204, where in this case the first column is the third column from the left. The remaining elements of vector 1202C form the second set of elements stored in the second column of array 1204, where in this case the second column is the seventh column from the left. These two columns form the third subset of the columns of array 1204.

[0115] Figure 12E The diagram illustrates the contents of array 1204 after the fourth pass of storing the input vector. As illustrated, elements of input vector 1202D are stored in array 1204 during the fourth pass. The first set of elements from vector 1202D (including elements D7, D5, D3, and D1) is stored in the first column of array 1204, where in this case the first column is the fourth column from the left. The remaining elements of vector 1202D form the second set of elements stored in the second column of array 1204, where in this case the second column is the rightmost column. These two columns form the fourth subset of the columns of array 1204.

[0116] like Figure 12E As shown, array 1204 is filled with elements when each input vector in the input vector has been written into the array. Furthermore, the elements of the input vectors have been arranged such that each row of the array contains a portion of the interleaved result value, where the elements of the input array alternate in a regular sequence. (As described above...) Figure 2 As described in the discussion, reading the contents of array 1204 row by row will allow the interleaved result values ​​to be stored. Figure 12F The figure shows row values ​​1206(1) to 1206(4) read from array 1204.

[0117] In one implementation, the size of the array (such as array 1204) stored in the array storage circuit of the interleaving / deinterleaving circuit is set such that writing all the input vectors to be interleaved into the array completely fills the array's elements. For example, in various implementations, the number of rows in the array is equal to the number of input vectors to be interleaved, and the number of columns in the array is equal to the number of elements in each input vector. Figures 12A to 12FThe example corresponds to this implementation, where there are four input vectors 1202A to 1202D because there are four rows in array 1204, eight columns in array 1204, and eight elements in each input vector. However, in other implementations, other array sizes may be used. For example, if the number of vectors to be interleaved is even, in some implementations, an array with twice the number of columns and half the number of rows in each input vector may also be suitable.

[0118] In some implementations, writing an input vector into an array includes: selecting elements from a given input vector to form elements for writing a set of elements into a given column of the array such that the elements in the set are spaced within the given input vector at a ratio of the number of elements in the input vector to the number of rows in the array. Figures 12A to 12F The example corresponds to this implementation because the ratio of elements in input vector 1202 to rows in array 1204 is two, and the elements written to a given column are spaced in pairs (such as elements A7, A5, A3, and A1 in the leftmost column). In an implementation where the number of columns in the array equals the number of elements in the input vector, the elements within a set of elements written to a given column of the array can be spaced (within the input vector) in a ratio of the number of columns to the number of rows in the array.

[0119] exist Figures 12A to 12F In the example, the number of elements in each input vector is twice the number of input vectors. In other implementations, different input vector lengths are used. In some implementations, the length of the input vector in terms of elements is much greater than the number of input vectors. The input vector length depends on the specific instruction that triggers the interleaving operation. In some implementations, for example, the input vectors may include 4, 8, 16, 32, or 64 elements. In one implementation, the interleaving execution circuitry, such as... Figure 2 Circuit 200 receives R A set of input vectors to be interleaved, wherein each input vector has Q one element, and Q yes R Multiples of. In another implementation, the data to be stored in the array memory circuitry, such as... Figure 2 The array in circuit 202 includes M Columns and N Each row, among which Q yes N of P times. R A number of input vectors can be written into an array such that the number of columns in a subset of the columns into which a given input vector is written is . P And the elements from the input vector that are written into a given column are spaced apart from each other in the input vector. P1 element. A subset of the column. P The column spacing is R Column. Apply this framework to Figures 12A to 12F Example, R =4, Q =8, M =8, N =4, and P =2. For example... Figures 12B to 12E As can be seen, each subset of columns used to write a given input vector has P There are columns, and the column spacing in the subset is . R Column. The element spacing within a given column is... P Each element. For different examples having four input vectors, each containing 12 elements, and an array with four rows and twelve columns, R =4, Q =12, M =12, N =4, and P =3. In this example, elements can be written into an array such that each subset of columns used to write to a given input vector comprises three columns, and the elements written to a given column are spaced three elements apart in the input vector.

[0120] Figures 12A to 12F The example belongs to the case where the number of elements in each input vector is a multiple of the number of input vectors (i.e., using the above notation, Q yes R (Multiples of the number of elements). However, in some implementations, the number of elements may not be a multiple of the number of input vectors. For example, consider an interleaving process for a set of three input vectors, each with eight elements. Figures 12A to 12F The notation is used, but there are only three input vectors 1202A, 1202B, and 1202C. The first 8-element interleaved row value, starting with element A7, will include elements A7, B7, C7, A6, B6, C6, A5, and B5. The next 8-element interleaved row will include elements C5, A4, B4, C4, A3, B3, C3, and A2, and the last 8-element interleaved row will include elements B2, C2, A1, B1, C1, A0, B0, and C0. Filling an array with 3 rows and 8 elements in this way involves distributing the elements of each input vector across all columns of the array, rather than as... Figures 12A to 12E The four input vectors shown are distributed only in specific pairs of columns, as in the case shown.

[0121] In an alternative implementation of the interleaving process for a set of three 8-element input vectors, the three input vectors can be written column-wise into a 4-row array, similar to... Figures 12B to 12DThe only difference is that only 6 columns of the array will be filled. In one implementation, the resulting array will look like... Figure 12D The array is modified so that the rightmost two columns are empty. Then, four interleaved 6-element rows can be read from the array and written into the appropriate elements of the three interleaved 8-element result values.

[0122] Figures 13A to 13F Examples of using interleaved execution circuits, such as Figure 2 Example interleaving values, array contents, and output row values ​​at various stages of the deinterleaving process of circuit 200. Figures 13A to 13F The illustrated deinterleaving process can be used to achieve practical Figures 12A to 12F The inverse operation of the interlacing process. Instead of, for example... Figures 12A to 12F In this way, it receives the input vector and generates interleaved values. Figures 13A to 13F The process receives interleaved values ​​and produces separate vectors. Figure 13A The diagram shows the set of interleaving values ​​used as input to the deinterleaving process. Interleaving values ​​1302(1), 1302(2), 1302(3), and 1302(4) correspond to... Figure 12F The row values ​​are 1206(1) to 1206(4). Figures 12A to 12F The element marking convention in Figures 13A to 13F The process continues, such that each interleaving value contains elements from each of the four vectors corresponding to the letters A, B, C, and D. In one embodiment, the number of interleaving values ​​1302 is equal to the number of vectors having elements interleaved within values ​​1302. In various embodiments, the number of elements in each value of 1302 is a multiple of the number of interleaved values ​​being uninterleaved. Figures 13B to 13E Examples are given for the Figure 13A The contents of array 1304 are stored in array storage circuitry (such as circuit 202) within the interleaving / deinterleaving execution circuitry (such as circuit 200) during the deinterleaving operation of the interleaved values. In some embodiments, the number of elements in each interleaved value 1302 is a multiple of the number of rows in array 1304.

[0123] Figure 13BThe contents of array 1304 are illustrated after the first pass of storing the interleaved values ​​into the array memory circuitry. In one embodiment, each pass of the storage operation is completed in a single clock cycle. As illustrated, the elements of interleaved value 1302(1) are stored into array 1304 during the first pass. A first set of elements, including elements A7, B7, C7, and D7, is stored in the first column of array 1304, where in this case the first column is the leftmost column. The remaining elements of interleaved value 1302(1) form a second set of elements stored in the second column of array 1304, where in this case the second column is the second column from the left. These two columns form a subset of the columns of array 1304. Figures 12A to 12F Compared to storing input vector elements during the interleaving process, for Figures 13A to 13F The deinterleaving process for storing interleaved value elements involves (at least in this example) storing each group of adjacent elements from interleaved value 1302 into adjacent columns of array 1304. The elements of interleaved value 1302 are stored in array 1304 in such a way that elements from different source vectors are classified into different rows, as shown in the figure.

[0124] Figure 13C The contents of array 1304 are illustrated after the second pass of storing the interleaved values. As illustrated, the elements of interleaved value 1302(2) are stored in array 1304 during the second pass. The first set of elements, including elements A5, B5, C5, and D5, is stored in the first column of array 1304, where in this case the first column is the third column from the left. The remaining elements of interleaved value 1302(2) form the second set of elements stored in the second column of array 1304, where in this case the second column is the fourth column from the left. These two columns form the second subset of the columns of array 1304.

[0125] Figure 13D The contents of array 1304 are illustrated after the third pass of storing the interleaved values. As illustrated, the elements of interleaved value 1302(3) are stored in array 1304 during the third pass. The first set of elements, including elements A3, B3, C3, and D3, is stored in the first column of array 1304, where in this case the first column is the fifth column from the left. The remaining elements of interleaved value 1302(3) form the second set of elements stored in the second column of array 1304, where in this case the second column is the sixth column from the left. These two columns form the third subset of the columns of array 1304.

[0126] Figure 13EThe contents of array 1304 are illustrated after the fourth pass of storing the interleaved values. As illustrated, the elements of interleaved value 1302(4) are stored in array 1304 during the fourth pass. The first set of elements, including elements A1, B1, C1, and D1, is stored in the first column of array 1304, where in this case the first column is the seventh column from the left. The remaining elements of interleaved value 1302(4) form the second set of elements stored in the second column of array 1304, where in this case the second column is the rightmost column. These two columns form the fourth subset of the columns of array 1304.

[0127] like Figure 13E As shown, array 1304 is filled with elements when each interleaved value has been written to the array. Furthermore, the elements of the interleaved values ​​have been arranged such that each row of the array contains one interleaved vector from the interleaved vectors. (As described above...) Figure 2 As described in the discussion, reading the contents of array 1304 row by row will allow the deinterleaved vector values ​​to be stored. Figure 13F The text shows the corresponding... Figure 12A The row values ​​of vectors 1202A to 1202D are 1306(1) to 1306(4).

[0128] In one implementation, the size of the array (such as array 1304) stored in the array storage circuitry of the interleaving / deinterleaving circuit is set such that writing all interleaved values ​​to be deinterleaved into the array completely fills the array's elements. For example, in various implementations, the number of rows in the array is equal to the number of interleaved values ​​to be deinterleaved, and the number of columns in the array is equal to the number of elements in each interleaved value. This implementation can be advantageous because it allows for the efficient use of the same circuitry both for interleaving a set of vectors and for deinterleaving interleaved values ​​to recover individual vectors. However, in other implementations, the deinterleaving process may use a different array size.

[0129] Figure 14A and Figure 14B The array contents at various stages of the interleaving process using an interleaving execution circuit with two input data ports are illustrated. Figures 12B to 12E An example of writing input vector elements to array 1204 is illustrated, wherein elements from one input vector are written to the array during each loop of the operation. In one implementation, each loop is performed during one clock cycle. The writing of a single input vector per loop corresponds to the following implementation: wherein a single write port can be used to... Figure 2 The input vector 216 is written to the array memory circuit 202. In an execution circuit implementation with more available write ports, multiple input vectors can be written to the array memory circuit in a single pass. Figures 14A to 14BThe contents of array 1404 stored in array memory circuitry such as circuit 202 are illustrated. Figure 14A Examples are given in the case of Figure 12A The input vectors are stored in the array storage circuit after a single pass of the array 1404. In one embodiment, array 1404 is stored in the array storage circuit of an interleaving circuit having two write ports available for writing input vectors into its array storage circuit. Therefore, a single pass results in the elements of both input vectors 1202A and 1202B being stored in array 1404. Similarly, a second pass results in vectors 1202C and 1202D being stored in array 1404, as... Figure 14B As shown. The number of passes required for the interleaving or deinterleaving operation depends on the number of write ports the interleaving execution circuit is configured to use.

[0130] The latency limitations described above for the interleaving execution circuitry are related to the number of available write ports for writing data to the array memory circuitry. Reading lines from the array memory circuitry is subject to similar limitations based on the number of available write ports. In one implementation, if a single write port is available to move a line out of the array memory circuitry, only one line can be read per cycle. This can result in delays in processing new interleaving or deinterleaving operations. Figure 15 and Figure 16 The implementation scheme of the interleaved execution circuit includes additional elements to address this delay.

[0131] Figure 15 An embodiment of an interleaving execution circuit 1500 including a side buffer circuit is illustrated, which allows the array memory circuitry to be cleared in a single cycle even when only one write port is available. Combined with Figure 2 The description and variations of the execution circuit 200 also apply to the corresponding elements of circuit 1500. As illustrated, execution circuit 1500 includes an array storage circuit 1502 coupled to control circuit 1504, buffer circuit 1506, and write port 1508. Figure 15 In the implementation scheme, write port 1508 is configured to select one of its four inputs at a time to write to a storage device external to execution circuitry 1500. (In addition to the above...) Figures 12A to 14BIn addition to writing the input value into the array storage circuit 1502, the described process also configures the control circuit 1504 to store three rows of the array stored in the array storage circuit 1502 into the buffer circuit 1506, while the remaining rows are written out of the circuit through the write port 1508. In one embodiment, for an embodiment with one output write port 1508, the side buffer 1506 is configured to store all rows except one row of the array stored by the array storage circuit 1502. In various embodiments, the array storage circuit 1502 can be cleared during one clock cycle, wherein the rows of the array it stores enter the buffer circuit 1506 or are output through the write port 1508. Clearing the array storage circuit 1502 allows data for new interleaving or deinterleaving operations to be written into the array storage circuit 1502 in subsequent cycles, while the rows stored in the buffer 1506 are being written out one by one using the write port 1508.

[0132] Figure 16 An embodiment of an interleaved execution circuit 1600 including two array memory circuits is illustrated. Combined with... Figure 2 The execution circuit 200 and Figure 15 The description and variations of the execution circuit 1500 also apply to the corresponding elements of circuit 1600. As illustrated, execution circuit 1600 includes two array memory circuits 1602A and 1602B coupled to control circuit 1604 and write port 1608. Figure 16 In one implementation, write port 1608 is configured to select one of its eight inputs at a time to write to a storage device external to execution circuit 1600. Control circuit 1604 is configured to alternate between the use of array storage circuits 1602A and 1602B during successive interleaving or deinterleaving operations. For example, in an implementation where execution circuit 1600 uses a single write port (not shown) to write to the array storage circuit, control circuit 1604 can use four cycles to fill array storage circuit 1602A with four input values ​​for interleaving or deinterleaving. Once all elements of the array are stored in array storage circuit 1602A, its four rows can be sequentially read out through write port 1608 during the subsequent four cycles. During the four cycles used to write out rows of array storage circuit 1602A, input values ​​can be stored in array storage circuit 1602B, so that the start of a new interleaving or deinterleaving operation does not need to be delayed until array storage circuit 1602A is emptied.

[0133] Figure 17 An implementation scheme of a method related to an interleaving process using an interleaving execution circuit as described herein is illustrated. Method 1700 is performed by a processor (such as...) Figure 1 Processor 100 Figure 3 coprocessor 300 or Figure 4 400 or Figure 5 This is one embodiment of a method executed by interleaved execution circuitry (such as circuitry 200, 1500, or 1600) of a processor 500. In some embodiments, the processor is a coprocessor configured to perform vector and matrix operations. In one embodiment, method 1700 is executed by control circuitry within the interleaved execution circuitry. Method 1700 includes receiving a plurality of input vectors at block 1710 by execution circuitry of the processor, wherein the execution circuitry includes a first array storage circuitry configured to store elements of a first array having a plurality of rows and a plurality of columns. Input vectors 1202A-1202D are examples of the plurality of received input vectors. Array storage circuitry 202, 1502, 1602A, and 1602B are examples of the first array storage circuitry included in the execution circuitry. Arrays 208, 1204, and 1304 are examples of the first array to be stored by the first array storage circuitry.

[0134] Method 1700 further includes, at block 1720, writing a plurality of input vectors into a first array storage circuit such that elements of a given input vector are split among a plurality of columns, and a given row among a plurality of rows has interleaved elements of the plurality of input vectors. In some embodiments, the plurality of columns are columns in a given subset of the plurality of columns. Figure 12E The example shown is an input vector that is written such that the elements of a given input vector are split across multiple columns in a given subset of multiple columns, and a given row in multiple rows has interleaved elements of multiple input vectors. Figure 12E In the example, the elements of each input vector are split between two columns, thus forming a subset of columns for that input vector. For example, the elements of input vector 1202A are split between columns that include the subset of the first and fifth columns from the left of array 1204, while the elements of input vector 1202C are split between columns that include the subset of the third and seventh columns from the left. Figure 12E Each row of the array contains interleaved elements from all input vectors from input vectors 1202A-1202D.

[0135] In some implementations, the first array has M column sum N Rows, each input vector has Q One element, Q yes N of P The process of writing multiple input vectors into the first array storage circuit includes writing multiple input vectors such that the elements of a given input vector written into a given column are spaced apart within the given input vector. P Each element. (Combined with the above) Figures 12A to 12FTo describe such an implementation. In another implementation, a given subset of multiple columns includes P Columns, and given a subset of P The columns in the first array are spaced apart by a number equal to the number of input vectors in the plurality of input vectors. In some implementations, the number of columns... M Also the number of rows N of P times.

[0136] In some implementations, the multiple columns in block 1720 where the elements of a given input vector are split include all columns of the array. This may be the case, for example, when the number of elements in the input vector is not a multiple of the number of elements in the input vector.

[0137] In some implementations, the first array storage circuitry includes element storage circuitry corresponding to the respective elements of the first array. Figure 2 The element storage circuit 206 is an example of an element storage circuit in a first array storage circuit, and element 210 is an example of a corresponding element of the first array. In another embodiment, writing multiple input vectors into the first array storage circuit includes: for a given input vector, writing a first set of elements of the given input vector into an element storage circuit corresponding to elements in a first column of a corresponding subset of multiple columns, and writing additional elements of the given input vector into an element storage circuit corresponding to elements in an additional column of the corresponding subset. In yet another embodiment, the elements in the first set of elements are spaced apart in the given input vector by a ratio of the number of elements in the input vector to the number of rows in the first array.

[0138] Figure 17 Method 1700 further includes: outputting data corresponding to the rows of the first array at box 1730 to form one or more result values. Figure 12F Row values ​​1206(1)-1206(4) are examples of the resulting values. In some embodiments, the execution circuitry further includes a buffer circuit configured to store data output from the first array memory circuitry. Execution circuitry 1500 with buffer circuitry 1506 is an example of such execution circuitry. In some such embodiments, outputting data corresponding to rows of the first array includes clearing the first array memory circuitry by transferring data corresponding to each of the plurality of rows to an entry of the buffer circuitry or a data port of the execution circuitry. In one embodiment, this clearing is performed during a given single clock cycle of the processor. Figure 15 Write port 1508 is an example of a data port for the execution circuit.

[0139] In some other implementations, the execution circuitry includes a second array storage circuitry configured to store elements of the second array. Figure 16The execution circuit 1600 is an example of such an execution circuit. In some such embodiments, method 1700 further includes: receiving a plurality of additional input values; and writing the plurality of additional input values ​​to a second array storage circuit while outputting data corresponding to rows of the first array from the first array storage circuit. In this embodiment, a single write port can be used to output rows of the first array one by one without slowing down the process of writing new input values ​​as the second array to the second array storage circuit. In some embodiments, such additional or new input values ​​are additional input vectors, and the next operation to be performed by the execution circuit is an additional interleaving operation. In other embodiments, such additional input values ​​are interleaved input values, and the next operation to be performed by the execution circuit is, as in conjunction with the following... Figure 18 The described deinterleaving operation.

[0140] Figure 18 An implementation scheme of a method related to a deinterleaving process using an interleaving execution circuit as described herein is illustrated. Method 1800 is performed by a processor (such as...) Figure 1 Processor 100 Figure 3 coprocessor 300 or Figure 4 400 or Figure 5 This describes one embodiment of a method executed by an interleaving execution circuit (such as circuits 200, 1500, or 1600) of a processor 500. In some embodiments, the processor is a coprocessor configured to perform vector and matrix operations. In one embodiment, method 1800 is executed by control circuitry within the interleaving execution circuitry. In some embodiments, a single interleaving execution circuitry is configured to perform both an interleaving process, such as method 1700, and a deinterleaving process, such as method 1800. In some embodiments, a method includes performing both an interleaving process and a deinterleaving process. The description and variations provided in connection with method 1700 also apply to the corresponding elements of method 1800.

[0141] Method 1800 includes: receiving a plurality of interleaved input values ​​at block 1810 by execution circuitry of a processor, wherein the execution circuitry includes a first array storage circuit configured to store elements of a first array having a plurality of rows and a plurality of columns. Interleaved values ​​1302(1)-1302(4) are examples of the received plurality of interleaved input values. Method 1800 further includes: writing the plurality of interleaved input values ​​to the first array storage circuit at block 1820 such that the elements of a given interleaved input value are split among a plurality of columns in a given subset of a plurality of columns, and a given row in a plurality of rows has ordered elements of a vector. Figure 13E The example shown is an example of interleaved input values ​​that are written such that the elements of a given value are split across multiple columns in a given subset, and a given row has ordered elements of a vector. Figure 13EIn the example, the elements of each interleaved input value are split between two columns, thus forming a subset of columns for the input vector. For example, the elements of input value 1302(2) are split between columns in a subset that includes the third and fourth columns from the left in array 1304, while the elements of input value 1302(4) are split between columns in a subset that includes the two rightmost columns of the array. Figure 13E Each row of the array comprises ordered elements that match one of vectors 1202A-1202D. In some implementations, columns from a given subset of the columns are adjacent to each other in the first array, such as... Figures 13A to 13F As illustrated in the example. In some implementations, the elements written to a given column of the first array for a given interleaving value are adjacent elements within the interleaving value.

[0142] Method 1800 further includes: outputting data corresponding to the rows of the first array at box 1830 to form one or more vector result values. Figure 13F Row values ​​1306(1)-1306(4) are examples of vector result values. In some embodiments, the execution circuitry further includes a buffer circuitry configured to store data output from the first array memory circuitry. In some such embodiments, outputting data corresponding to rows of the first array includes clearing the first array memory circuitry by transferring data corresponding to each of the plurality of rows to an entry of the buffer circuitry or a data port of the execution circuitry. In one embodiment, this clearing is performed during a given single clock cycle of the processor. In some other embodiments, the execution circuitry includes a second array memory circuitry configured to store elements of a second array. In some such embodiments, method 1800 further includes receiving a plurality of additional input values; and writing the plurality of additional input values ​​to the second array memory circuitry when outputting data corresponding to rows of the first array from the first array memory circuitry. In this embodiment, a single write port can be used to output rows of the first array one by one without slowing down the process of writing new input values ​​as the second array to the second array memory circuitry. In some embodiments, such additional input values ​​are additional interleaving input values, and the next operation to be performed by the execution circuitry is an additional deinterleaving operation. In other implementations, such additional input values ​​are input vectors, and the next operation to be performed by the execution circuitry is an interleaving operation.

[0143] Example device Now for reference Figure 19A block diagram illustrating an example embodiment of device 1900 is shown. In some embodiments, elements of device 1900 may be included within a system-on-a-chip. In some embodiments, device 1900 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 1900 may be an important design consideration. In the illustrated embodiment, device 1900 includes a structure 1910, a computing complex 1920, an input / output (I / O) bridge 1950, a cache / memory controller 1945, a graphics unit 1975, a coprocessor 1980, and a display unit 1965. In some embodiments, in addition to or in lieu of the illustrated components, device 1900 may also include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc. As shown, coprocessor 1980 includes components such as those combined with... Figure 1 The described operand management circuit 102 and how it is combined Figure 2 The execution circuitry 200 is described. In other embodiments, one or both of circuitry 102 and circuitry 200 may be absent from coprocessor 1980. In some embodiments, one or both of circuitry 102 and circuitry 200 may be included in different processors such as core 1935 or core 1940.

[0144] Structure 1910 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 1900. In some embodiments, portions of structure 1910 may be configured to implement various different communication protocols. In other embodiments, structure 1910 may implement a single communication protocol, and components coupled to structure 1910 may internally switch from a single communication protocol to other communication protocols.

[0145] In the illustrated implementation, computing complex 1920 includes a bus interface unit (BIU) 1925, a cache 1930, and cores 1935 and 1940. In various implementations, computing complex 1920 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 1920 may include one, two, four, or any other suitable number of processor cores. In one implementation, cache 1930 is a set-associative L2 cache. In some implementations, cores 1935 and 1940 may include internal instruction and data caches. In some implementations, a coherence unit (not shown) in architecture 1910, cache 1930, or elsewhere in device 1900 may be configured to maintain coherence between the various caches of device 1900. BIU 1925 may be configured to manage communication between computing complex 1920 and other elements of device 1900. Processor cores (such as cores 1935 and 1940) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions. These instructions can be stored in computer-readable media, such as memory coupled to the memory controller 1945 discussed below. Figure 5 The processor 500 is an example of processor cores such as cores 1935 and 1940.

[0146] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling may include intermediate elements. For example, in Figure 19 In this context, the graphics unit 1975 can be described as being "coupled" to memory via structure 1910 and cache / memory controller 1945. In contrast, in... Figure 19 In the exemplary implementation, the graphics unit 1975 is "directly coupled" to the structure 1910 because there are no intermediate elements.

[0147] The cache / memory controller 1945 can be configured to manage data transfer between the structure 1910 and one or more caches and memories. For example, the cache / memory controller 1945 can be coupled to an L3 cache, which in turn can be coupled to system memory. In other embodiments, the cache / memory controller 1945 can be directly coupled to memory. In some embodiments, the cache / memory controller 1945 may include one or more internal caches. The memory coupled to the controller 1945 can be any type of volatile memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR4, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices can be coupled onto a circuit board to form a memory module, such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), etc. Alternatively, these devices can be mounted with integrated circuits in a chip-stacked configuration, a package-stacked configuration, or a multi-chip module configuration. The memory coupled to the controller 1945 can be any type of non-volatile memory, such as NAND flash memory, NOR flash memory, nanometer RAM (NRAM), magnetoresistive RAM (MRAM), phase-change RAM (PRAM), raceway memory, memristor memory, etc. As noted above, this memory can store program instructions executable by the computing complex 1920 to cause the computing device to perform the functionality described herein.

[0148] The graphics unit 1975 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 1975 may receive graphics-oriented instructions, such as OpenGL. ® Metal ® Or DIRECT3D ®Instructions. The graphics unit 1975 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 1975 is typically configured to process large blocks of data in parallel and can construct an image in a frame buffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 1975 may include a transformation engine, a lighting engine, a triangle engine, and a rendering engine in one or more graphics processing pipelines. The graphics unit 1975 can output pixel information of the displayed image. In various embodiments, the graphics unit 1975 may include programmable shader circuitry, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or not).

[0149] One or more coprocessors in coprocessor 1980 may be used to implement specific operations. In some embodiments, coprocessor 1980 may implement specific operations more efficiently than a general-purpose processor. In various embodiments, coprocessor 1980 includes optimized and / or dedicated hardware that is not typically implemented by the core processor in computing complex 1920. In one embodiment, coprocessor 1980 implements vector and matrix operations. Coprocessors 300 and 400 described herein are examples of coprocessor 1980.

[0150] Display unit 1965 may be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 1965 may be configured as a display pipeline. Additionally, display unit 1965 may be configured to blend multiple frames to produce an output frame. Furthermore, display unit 1965 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0151] I / O bridge 1950 may include various elements configured to implement, for example, Universal Serial Bus (USB) communication, security, audio, and low-power always-on functionality. I / O bridge 1950 may also include interfaces such as, for example, pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 1900 via I / O bridge 1950.

[0152] In some embodiments, device 1900 includes network interface circuitry (not explicitly shown) that can be connected to structure 1910 or I / O bridge 1950. This network interface circuitry can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via Wi-Fi), or a wireless LAN. ™ The network interface circuitry can communicate via one or more cellular networks using one or more radio access technologies, or wide area networks (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to use device-to-device communication (e.g., Bluetooth). ® or Wi-Fi ™ Communication can be achieved through direct connection, etc. In various implementations, the network interface circuitry can provide device 1900 with connectivity to various types of other devices and networks.

[0153] Example Application Turn now Figure 20 This illustrates various types of systems that may include any of the circuits, devices, or systems discussed above. The system or device 2000, which may utilize one or more of the techniques described herein in combination with or otherwise, can be used in a wide range of fields. For example, the system or device 2000 may be used as part of the hardware of a system such as a desktop computer 2010, a laptop computer 2020, a tablet computer 2030, a cellular or mobile phone 2040, or a television 2050 (or a set-top box coupled to a television).

[0154] Similarly, the disclosed components can be used in wearable devices 2060, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0155] The system or device 2000 can also be used in a variety of other contexts. For example, the system or device 2000 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing a cloud-based service 2070. Furthermore, the system or device 2000 can be implemented in a wide range of dedicated everyday devices, including common household appliances 2080 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). The component can also be implemented in various modes of transportation. For example, the system or device 2000 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 2090.

[0156] Figure 20 The applications illustrated are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0157] Example computer-readable media Various example circuits have been described in detail above in this disclosure. It is intended that this disclosure covers not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. Therefore, this disclosure is intended to support claims that specify storage media for circuits in formats that cover not only means including the disclosed circuits, but also analog models for programming computing systems to generate hardware circuits, computing systems configured to generate hardware (e.g., integrated circuits) including the disclosed circuits. Claims for such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves perform complete operations (such as design simulation, design synthesis, circuit fabrication, etc.).

[0158] Figure 21 This is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, computing system 2140 is configured to process the design information. This may include executing instructions included in the design information, interpreting instructions included in the design information, compiling, transforming, or otherwise updating the design information. Thus, in some embodiments, the design information (e.g., by programming computing system 2140) controls computing system 2140 to perform the various operations discussed below.

[0159] In the illustrated example, computing system 2140 processes the design information to generate both a computer simulation model 2160 of the hardware circuit and lower-level design information 2150. In other embodiments, computing system 2140 may generate only one of these outputs, may generate other outputs based on the design information, or both. Regarding the computational simulation, computing system 2140 may execute instructions in a hardware description language, which includes register transfer level (RTL) code, behavioral code, structural code, or some combination thereof. The simulation model may perform the functionality specified by the design information, facilitate verification of the functional correctness of the hardware design, generate power consumption estimates, generate timing estimates, etc.

[0160] In the illustrated example, computing system 2140 also processes the design information to generate lower-level design information 2150 (e.g., gate-level design information, netlists, etc.). As shown, this may include synthesis operations such as constructing multi-level networks, optimizing the network using technology-independent techniques, technology-dependent techniques, or both, and outputting a gate network (with potential constraints based on a library of available gate pairs, size adjustments, delays, power, etc.). Based on the lower-level design information 2150 (and potentially other inputs), semiconductor manufacturing system 2120 is configured to manufacture integrated circuit 2130 (which may correspond to the functionality of simulation model 2160). Note that computing system 2140 may generate different simulation models based on design information at various descriptive levels (including information 2150, 2115, etc.). Data representing design information 2150 and model 2160 may be stored on medium 2110 or one or more other media.

[0161] In some implementations, lower-level design information 2150 controls (e.g., programs) the semiconductor manufacturing system 2120 to manufacture integrated circuit 2130. Thus, when processed by the manufacturing system, the design information can program the manufacturing system to manufacture circuits including the various circuits disclosed herein.

[0162] The nontransitory computer-readable storage medium 2110 may include any of a variety of suitable types of memory devices or storage devices. The nontransitory computer-readable storage medium 2110 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as a hard disk drive or optical storage device; registers or other similar types of memory elements, etc. The nontransitory computer-readable storage medium 2110 may also include other types of nontransitory memory or combinations thereof. Therefore, the nontransitory computer-readable storage medium 2110 may include two or more memory media; such media may reside in different locations—for example, in different computer systems connected via a network.

[0163] Design information 2115 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The formats of various design information can be recognized by one or more applications executed by computing system 2140, semiconductor manufacturing system 2120, or both. In some embodiments, design information may also include one or more cell libraries specifying the composition, layout, or both of integrated circuit 2130. In some embodiments, design information is specified, wholly or partially, in the form of a netlist specifying cell library elements and their connectivity. Individually, the design information discussed herein may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information may specify circuit elements to be manufactured but not their physical layout. In this case, design information may need to be combined with layout information to actually manufacture the specified circuit.

[0164] In various implementations, integrated circuit 2130 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In this case, design information may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. Mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0165] The semiconductor manufacturing system 2120 may include any of the various suitable elements configured to manufacture integrated circuits. This may include elements for, for example, depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 2120 may also be configured to perform various tests on the manufactured circuits to ensure proper operation.

[0166] In various implementations, integrated circuit 2130 and model 2160 are configured to operate according to a circuit design specified by design information 2115, which may include performing any of the functionalities described herein. For example, integrated circuit 2130 may include Figures 1 to 8 and Figures 15 to 16 Any of the various components shown. Furthermore, integrated circuit 2130 can be configured to perform the various functions described herein in conjunction with other components. Moreover, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0167] As used herein, a phrase in the form of “design information specifying a circuit configured to…” does not imply that the circuit in question must be manufactured to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components. Similarly, stating that “instructions of a hardware description programming language” are “executable” to program a computing system to generate a computer simulation model does not mean that the instructions must be executed to satisfy the element, but rather specifies the characteristics of those instructions. In this context, additional features associated with the model (or the circuit represented by the model) can similarly relate to the characteristics of these instructions. Therefore, an entity selling a computer-readable medium having instructions that satisfy the stated characteristics may provide an infringing product even if another entity actually executes those instructions on the medium.

[0168] It is important to note that a given design, at least within a digital logic context, can be implemented using multiple different gate arrangements, circuit techniques, etc. As an example, different designs may choose or connect gates based on design trade-offs (e.g., focusing on power consumption, performance, circuit area, etc.). Furthermore, different manufacturers may have proprietary libraries, gate designs, physical gate implementations, etc. Different entities may also use different tools to process design information at various layers (e.g., from behavioral specifications to the physical layout of gates).

[0169] However, once a digital logic design is specified, those skilled in the art do not need to perform extensive experiments or studies to determine these implementations. Instead, they understand the process for reliably and predictably producing one or more circuit implementations that provide the functionality described by the design information. Different circuit implementations may affect the performance, area, power consumption, etc., of a given design (potentially trade-offs between different design goals), but the logic function remains unchanged between different circuit implementations of the same circuit design.

[0170] In some implementations, instructions included in design information instructions provide RTL information (or other higher-level design information) and can be executed by a computing system to synthesize a gate-level netlist representing the hardware circuitry based on the RTL information as input. Similarly, these instructions provide behavioral information and can be executed by the computing system to synthesize netlists or other lower-level design information. The lower-level design information can be used to program manufacturing system 2120 to manufacture integrated circuit 2130.

[0171] The following numbered clauses list the various non-restrictive embodiments disclosed herein: Set A A1. A processor, said processor comprising: Operand management circuitry, the operand management circuitry including a fusion buffer, wherein the operand management circuitry is configured to: Receive instruction operation; Detect a first store instruction operation from the received instruction operations, the first store instruction operation being executable to store one or more first operand values ​​that can be used by one or more consumer instruction operations into one or more destination registers; The first stored instruction operation is stored in the fusion buffer instead of being allowed to continue along the processor's execution pipeline; In response to detecting a discard condition associated with the first store instruction operation, the first store instruction operation is removed from the fusion buffer without forwarding its execution, such that the one or more first operand values ​​are not written to the one or more target registers; and In response to the detection of a buffer emptying condition and the absence of the discard condition, the first store instruction operation is removed from the fusion buffer and forwarded for execution; and An execution circuit, coupled to the operand management circuit and configured to execute an instruction operation including the first stored instruction operation.

[0172] A2. A processor according to any of the foregoing clauses within set A, wherein: The operand management circuit is further configured to, in response to detecting a first consumer instruction operation from among the received instruction operations when the first stored instruction operation is in the fusion buffer, fuse the first stored instruction operation and the first consumer instruction operation into one or more first fused instruction operations. The first consumer instruction operation is eligible to be merged with the first store instruction operation and can be executed to perform a first operation using one or more of the one or more first operand values; The first fusion instruction operation is executable to obtain one or more first operands from the one or more first operand values, and executes the first operation without writing one or more first operands from the one or more first operand values ​​to the one or more destination registers; and The execution circuit is further configured to execute instruction operations including the first fusion instruction operation.

[0173] A3. The processor as described in Clause A2, wherein: The operand management circuitry is further configured to, in response to detecting an additional consumer instruction operation while the first stored instruction operation is in the fusion buffer, fuse the first stored instruction operation and the additional consumer instruction operation into one or more additional fused instruction operations; and The additional consumer instruction operation is eligible to be merged with the first storage instruction operation and can be executed to perform the additional operation using one or more of the one or more first operand values.

[0174] A4. A processor according to any of the foregoing provisions in set A, wherein detecting a discard condition associated with the first memory instruction operation includes determining that there is no longer a current or future consumer instruction operation for the first memory instruction operation.

[0175] A5. A processor according to any of the foregoing provisions in set A, wherein detecting a buffer vacancy condition includes detecting a second store instruction operation from among received instruction operations, the second store instruction operation being executable to store one or more second operand values ​​that can be used by one or more consumer instruction operations.

[0176] A6. A processor according to any of the foregoing provisions in set A, wherein the first storage instruction operation includes a lookup table index value and is executable to use the index value to obtain the one or more first operation values ​​from the lookup table.

[0177] A7. The processor according to clause A2 or A3, wherein the first memory instruction operation is executable to move a portion of the memory array to the one or more destination registers to form the one or more first operation values.

[0178] A8. The processor according to clause A7, wherein the first consumer instruction operation is executable to reduce the bit width of one or more of the one or more first operands.

[0179] A9. The processor as described in Clause A7, wherein: The first consumer instruction operation is executable to interleave or deinterleave elements of the one or more first operand values; and The execution circuit includes an interleaved execution circuit.

[0180] A10. A processor according to any of the foregoing clauses in set A, wherein the processor is a coprocessor configured to perform vector and matrix operations.

[0181] A11. A non-transitory computer-readable medium having stored thereon design information, the design information specifying at least a portion of a circuit design for a processor according to any of the foregoing provisions in set A, in a format recognizable by a manufacturing system configured to use the design information.

[0182] Set B B1. A method comprising: The first store instruction operation is detected by the operand management circuit in the processor and in the instruction operation received by the operand management circuit. The first store instruction operation can be executed to store one or more first operand values ​​that can be used by one or more consumer instruction operations into one or more destination registers. The operand management circuit stores the first stored instruction operation into the processor's fusion buffer instead of allowing the first stored instruction operation to continue along the processor's execution pipeline; In response to the detection of a buffer emptying condition, the operand management circuit removes the first stored instruction operation from the fusion buffer; A check is performed on the discard conditions associated with the first storage instruction operation; and Based on the results of the inspection and after the first storage instruction operation is removed from the fusion buffer, the first storage instruction operation is processed.

[0183] B2. The method described in Clause B1, wherein: The result of the inspection includes detecting the discard condition; and The process includes: discarding the first store instruction operation without forwarding the first store instruction operation for execution, so that the one or more first operand values ​​are not written to the one or more target registers.

[0184] B3. The method described in Clause B1, wherein: The results of the inspection do not include the detection of the discard condition; and The process includes forwarding the first storage instruction operation for execution.

[0185] B4. The method described according to any of the foregoing clauses within set B, the method further comprising: In response to detecting a first consumer instruction operation from the instruction operations received by the operand management circuit while the first store instruction operation is in the fusion buffer, the operand management circuit fuses the first store instruction operation and the first consumer instruction operation into one or more first fused instruction operations, wherein... The first consumer instruction operation is eligible to be merged with the first store instruction operation and can be executed to perform a first operation using one or more of the one or more first operand values. The first fusion instruction operation can be executed to obtain one or more first operands from the one or more first operands, and the first operation is performed without writing the one or more first operands from the one or more first operands into the one or more target registers.

[0186] B5. The method described in accordance with Clause B4, the method further comprising: In response to detecting an additional consumer instruction operation from the instruction operation received by the operand management circuit while the first stored instruction operation is in the fusion buffer, the operand management circuit fuses the first stored instruction operation and the additional consumer instruction operation into one or more second fusion instruction operations, wherein the additional consumer instruction operation is eligible to be fused with the first stored instruction operation and is executable to perform an additional operation using one or more of the one or more first operand values.

[0187] B6. The method according to any of the foregoing clauses in set B, wherein checking the discard condition associated with the first storage instruction operation includes determining whether there are any current or future consumer instruction operations for the first storage instruction operation.

[0188] B7. The method according to any of the foregoing clauses in set B, wherein detecting a buffer emptying condition includes detecting a second storage instruction operation from the instruction operation received by the operand management circuitry, the second storage instruction operation being executable to store one or more second operand values ​​that can be used by one or more consumer instruction operations.

[0189] Set C C1. An apparatus comprising: A first array storage circuit, configured to store elements of a first array having multiple rows and multiple columns; and Control circuit, the control circuit being configured to: It can accept multiple input vectors; The plurality of input vectors are written into the first array storage circuit such that: The elements of a given input vector are split across multiple columns; and A given row among the plurality of rows has interleaved elements of the plurality of input vectors; and Output the data corresponding to the rows of the first array to form one or more result values.

[0190] C2. The apparatus according to any of the foregoing clauses in set C, wherein the control circuitry is further configured to: Receive multiple interleaved input values; The plurality of interleaved input values ​​are written into the first array storage circuit, such that: The elements of a given interleaved input value are split among multiple columns in a given subset of the multiple columns; and A given row among the plurality of rows has ordered elements of a vector; and Output the data corresponding to the rows of the first array to form one or more vector result values.

[0191] C3. The apparatus according to clause C2, wherein the plurality of columns in the given subset are adjacent to each other in the first array.

[0192] C4. A device according to any of the foregoing clauses in set C, wherein: The first array has M column sum N OK; Each input vector has Q One element; Q yes N of P times; The elements of the given input vector are in M Split among multiple columns in a given subset of columns; and The control circuit is further configured to write the plurality of input vectors into the first array storage circuit, such that the elements of a given input vector written into a given column are spaced apart within the given input vector. P Each element.

[0193] C5. The apparatus according to clause C4, wherein: The M The given subset of the column includes P Column; and The given subset of P The columns in the first array are spaced apart by a number equal to the number of input vectors in the plurality of input vectors.

[0194] C6. The apparatus according to any one of clauses C1 to C3, wherein: The first array has M column sum N Yes; and M yes N of P times.

[0195] C7. An apparatus according to any of the foregoing provisions in set C, the apparatus further comprising a buffer circuit configured to store data output from the first array memory circuit, wherein the control circuit is further configured to clear the first array memory circuit during a given clock cycle of the apparatus by transmitting data corresponding to each of the multiple rows to an entry of the buffer circuit or a data port of the apparatus.

[0196] C8. The apparatus according to any one of clauses C1 to C6, the apparatus further comprising a second array storage circuit configured to store elements of a second array, wherein the control circuit is further configured to write an additional input vector into the second array storage circuit when outputting data corresponding to a row of the first array from the first array storage circuit.

[0197] C9. A non-transitory computer-readable medium having stored thereon design information, the design information specifying at least a portion of a design of an execution circuit in the form of an apparatus according to any of the foregoing provisions of set C, in a format recognizable by a manufacturing system configured to use the design information to produce a hardware integrated circuit.

[0198] C10. A computer-readable medium as described in Clause C8, wherein the design information further specifies at least a portion of the design of a processor incorporating the execution circuitry.

[0199] C11. A computer-readable medium as described in Clause C9, wherein the processor is a coprocessor configured to perform vector and matrix operations.

[0200] set D D1. A method comprising: The processor's execution circuitry receives multiple input vectors, wherein the execution circuitry includes a first array storage circuitry configured to store elements of a first array having multiple rows and multiple columns; The execution circuit writes the plurality of input vectors into the first array storage circuit, such that: The elements of a given input vector are split across multiple columns; and A given row among the plurality of rows has interleaved elements of the plurality of input vectors; and The execution circuit outputs data corresponding to the rows of the first array to form one or more result values.

[0201] D2. The method described according to any of the foregoing clauses within set D, wherein: The first array storage circuit includes element storage circuits corresponding to the respective elements of the first array; and Writing the plurality of input vectors into the first array storage circuit includes: for a given input vector: Write the first set of elements of the given input vector into the element storage circuit corresponding to the elements in the first column of the corresponding subset of the plurality of columns; and The additional elements of the given input vector are written into the element storage circuit corresponding to the elements of the additional column in the corresponding subset.

[0202] D3. The method according to clause D2, wherein the elements in the first group of elements are spaced in the given input vector at a ratio of the number of elements in the given input vector to the number of rows in the first array.

[0203] D4. The method described according to any of the foregoing clauses within set D, wherein: The elements of the given input vector are split among multiple columns in a given subset of the multiple columns; and The columns in the given subset of the plurality of columns are spaced apart from each other in the first array by a number of columns equal to the number of columns in the input vector.

[0204] D5. The method described according to any of the foregoing clauses within set D, the method further comprising: The execution circuit receives multiple interleaved input values; The execution circuit writes the plurality of interleaved input values ​​into the first array storage circuit, such that: The elements of a given interleaved input value are split among multiple columns in a given subset of the multiple columns; and A given row among the plurality of rows has ordered elements of a vector; and The execution circuit outputs data corresponding to the rows of the first array to form one or more vector result values.

[0205] D6. The method described according to any of the foregoing clauses within set D, wherein: The execution circuit further includes a buffer circuit configured to store data output from the first array storage circuit; and Outputting data corresponding to a row of the first array includes clearing the first array memory circuit during a given single clock cycle of the processor by transmitting data corresponding to each of the plurality of rows to an entry of the buffer circuit or a data port of the execution circuit.

[0206] D7. The method according to any one of clauses D1 to D5, wherein the execution circuitry further comprises a second array storage circuitry configured to store elements of the second array, and the method further comprises: The execution circuit receives multiple additional input vectors; and The execution circuit writes the plurality of additional input vectors into the second array storage circuit when outputting the data corresponding to the row of the first array from the first storage array circuit.

[0207] This disclosure includes references to “implementations”, which are non-limiting specific implementations of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” “some implementations,” “various implementations,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including the specific implementations detailed herein, as well as modifications or alternatives falling within the substance or scope of this disclosure. Not all of these implementations will necessarily exhibit any or all of the potential advantages described herein.

[0208] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0209] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0210] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the filing of this application (or an application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0211] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations may be claimed in this application or in another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0212] In appropriate circumstances, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0213] Since the present disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0214] Unless the context clearly dictates otherwise, a reference to an item in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of the item. A "plurality" of items refers to a collection of two or more of the items.

[0215] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0216] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0217] When the term "or" is used in the present disclosure in reference to a list of options, it is generally understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make clear that "or" is used in an exclusive sense.

[0218] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0219] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0220] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0221] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond only to those factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be executed jointly in response to B and C. This phrase is also intended to cover implementation schemes where A is executed only in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0222] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0223] In some cases, various units / circuits / components may be described herein as a collection of entities that perform tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated otherwise.

[0224] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0225] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that a structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the “component for [performing a function]” structure to state the elements of the claims.

[0226] Different “circuits” may be described in this disclosure. These circuits, or “circuits”, constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0227] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0228] In various implementations, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation.

[0229] Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often leads to scenarios where circuit or logic designers never specify a particular set of structures for the low-level implementations that goes beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0230] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0231] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. A processor, the processor comprising: Operand management circuitry, the operand management circuitry including a fusion buffer, wherein the operand management circuitry is configured to: Receive instruction operation; Detect a first store instruction operation from the received instruction operations, the first store instruction operation being executable to store one or more first operand values ​​that can be used by one or more consumer instruction operations into one or more destination registers; The first stored instruction operation is stored in the fusion buffer instead of being allowed to continue along the processor's execution pipeline; In response to detecting a discard condition associated with the first store instruction operation, the first store instruction operation is removed from the fusion buffer without forwarding the first store instruction operation for execution, such that the one or more first operation values ​​are not written to the one or more target registers; as well as In response to the detection of a buffer emptying condition and the absence of the discard condition, the first storage instruction operation is removed from the fusion buffer and forwarded for execution; and An execution circuit, coupled to the operand management circuit and configured to execute an instruction operation including the first stored instruction operation.

2. The processor according to claim 1, wherein: The operand management circuit is further configured to, in response to detecting a first consumer instruction operation from among the received instruction operations when the first stored instruction operation is in the fusion buffer, fuse the first stored instruction operation and the first consumer instruction operation into one or more first fused instruction operations. The first consumer instruction operation is eligible to be merged with the first store instruction operation and can be executed to perform a first operation using one or more of the one or more first operand values; The first fusion instruction operation can be executed to obtain one or more first operand values ​​from the one or more first operand values, and the first operation is performed without writing the one or more first operand values ​​from the one or more first operand values ​​to the one or more target registers; and The execution circuit is further configured to execute instruction operations including the first fusion instruction operation.

3. The processor according to claim 2, wherein: The operand management circuitry is further configured to merge the first stored instruction operation and the additional consumer instruction operation into one or more additional fused instruction operations in response to detecting an additional consumer instruction operation when the first stored instruction operation is in the fusion buffer. and The additional consumer instruction operation is eligible to be merged with the first storage instruction operation and can be executed to perform the additional operation using one or more of the one or more first operand values.

4. The processor of claim 1, wherein detecting the discard condition associated with the first storage instruction operation includes determining that there is no longer a current or future consumer instruction operation for the first storage instruction operation.

5. The processor of claim 1, wherein detecting a buffer vacancy condition includes detecting a second store instruction operation from among received instruction operations, the second store instruction operation being executable to store one or more second operation values ​​that can be used by one or more consumer instruction operations.

6. The processor of claim 1, wherein the first storage instruction operation includes a lookup table index value and is executable to use the index value to obtain the one or more first operation values ​​from the lookup table.

7. The processor of claim 2, wherein the first memory instruction operation is executable to move a portion of the memory array to the one or more target registers to form the one or more first operand values.

8. The processor of claim 7, wherein the first consumer instruction operation is executable to reduce the bit width of one or more of the one or more first operands.

9. The processor according to claim 7, wherein: The first consumer instruction operation is executable to interleave or deinterleave elements of the one or more first operand values; and The execution circuit includes an interleaved execution circuit.

10. A method, the method comprising: The first store instruction operation is detected by the operand management circuit in the processor and in the instruction operation received by the operand management circuit. The first store instruction operation can be executed to store one or more first operand values ​​that can be used by one or more consumer instruction operations into one or more destination registers. The operand management circuit stores the first stored instruction operation into the processor's fusion buffer instead of allowing the first stored instruction operation to continue along the processor's execution pipeline; In response to the detection of a buffer emptying condition, the operand management circuit removes the first stored instruction operation from the fusion buffer; Check the discard conditions associated with the first storage instruction operation; as well as Based on the results of the inspection and after the first storage instruction operation is removed from the fusion buffer, the first storage instruction operation is processed.

11. The method of claim 10, wherein: The result of the inspection includes detecting the discard condition; and The process includes: discarding the first store instruction operation without forwarding the first store instruction operation for execution, so that the one or more first operand values ​​are not written to the one or more target registers.

12. The method according to claim 10, wherein: The results of the inspection do not include the detection of the discard condition; and The process includes forwarding the first storage instruction operation for execution.

13. The method according to claim 10, further comprising: In response to detecting a first consumer instruction operation from the instruction operations received by the operand management circuit while the first store instruction operation is in the fusion buffer, the operand management circuit fuses the first store instruction operation and the first consumer instruction operation into one or more first fused instruction operations, wherein... The first consumer instruction operation is eligible to be merged with the first store instruction operation and can be executed to perform a first operation using one or more of the one or more first operand values. The first fusion instruction operation can be executed to obtain one or more first operands from the one or more first operands, and the first operation is performed without writing the one or more first operands from the one or more first operands into the one or more target registers.

14. The method according to claim 13, further comprising: In response to detecting an additional consumer instruction operation from the instruction operation received by the operand management circuit while the first stored instruction operation is in the fusion buffer, the operand management circuit fuses the first stored instruction operation and the additional consumer instruction operation into one or more second fusion instruction operations, wherein the additional consumer instruction operation is eligible to be fused with the first stored instruction operation and is executable to perform an additional operation using one or more of the one or more first operand values.

15. The method of claim 10, wherein checking the discard condition associated with the first storage instruction operation includes determining whether there are any current or future consumer instruction operations for the first storage instruction operation.

16. The method of claim 10, wherein detecting a buffer vacancy condition includes detecting a second storage instruction operation from the instruction operation received by the operand management circuit, the second storage instruction operation being executable to store one or more second operand values ​​that can be used by one or more consumer instruction operations.

17. A non-transitory computer-readable medium having design information stored thereon, the design information specifying at least a portion of a circuit design for a processor in a format recognizable by a manufacturing system configured to use the design information, the processor comprising: Operand management circuitry, the operand management circuitry including a fusion buffer, wherein the operand management circuitry is configured to: Receive instruction operation; Detect a first store instruction operation from the received instruction operations, the first store instruction operation being executable to store one or more first operand values ​​that can be used by one or more consumer instruction operations into one or more destination registers; The first stored instruction operation is stored in the fusion buffer instead of being allowed to continue along the processor's execution pipeline; In response to detecting a discard condition associated with the first store instruction operation, the first store instruction operation is removed from the fusion buffer without forwarding the first store instruction operation for execution, such that the one or more first operation values ​​are not written to the one or more target registers; as well as In response to the detection of a buffer emptying condition and the absence of the discard condition, the first storage instruction operation is removed from the fusion buffer and forwarded for execution; and An execution circuit, coupled to the operand management circuit and configured to execute an instruction operation including the first stored instruction operation.

18. The computer-readable medium of claim 17, wherein: The operand management circuit is further configured to, in response to detecting a first consumer instruction operation from among the received instruction operations when the first stored instruction operation is in the fusion buffer, fuse the first stored instruction operation and the first consumer instruction operation into one or more first fused instruction operations. The first consumer instruction operation is eligible to be merged with the first store instruction operation and can be executed to perform a first operation using one or more of the one or more first operand values; The first fusion instruction operation can be executed to obtain one or more first operand values ​​from the one or more first operand values, and the first operation is performed without writing the one or more first operand values ​​from the one or more first operand values ​​to the one or more target registers; and The execution circuit is further configured to execute instruction operations including the first fusion instruction operation.

19. The computer-readable medium of claim 17, wherein the first storage instruction operation includes a lookup table index value and is executable to use the index value to obtain the one or more first operation values ​​from the lookup table.

20. The computer-readable medium of claim 17, wherein the processor is a coprocessor configured to perform vector and matrix operations.

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