Performing asynchronous memory clock changes on a multi-display system

Abstract

A system, apparatus and method for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem that stores a frame buffer used to drive pixels for the multiple displays. For example, if real-time memory bandwidth demand differs from the memory bandwidth available at the existing memory clock frequency, a control unit tracks vertical blanking interval (VBI) timing of a first display. The control unit also causes a second display to enter a panel self-refresh (PSR) mode. When the PSR mode of the second display overlaps with the VBI of the first display, a memory clock frequency change including memory training is initiated. After the memory clock frequency change, the displays are driven by the frame buffer in the memory subsystem at the updated frequency.

Description

[Background technology]

[0001] Description of Related Art Many types of computer systems include display devices for displaying images, video streams, and data. Thus, these systems typically include functionality for generating and / or manipulating image and video information. In digital imaging, the smallest item of information in an image is called a "picture element," or more commonly, a "pixel."

[0002] Some systems include multiple individual displays. In these systems, multi-display technology allows a single graphics processing unit (GPU) (or other device such as an accelerated processing unit (APU) or other type of system on chip (SOC), or any application-specific integrated circuit (ASIC) with a display controller) to simultaneously support multiple independent display outputs. In one example, a computing system can independently connect multiple high-resolution displays to a large integrated display surface to provide an expanded visual workspace. Gaming, entertainment, medical, audio and video editing, business, and other applications can take advantage of the expanded visual workspace and increase the opportunities for multitasking.

[0003] For each supported display, the video subsystem maintains a respective frame buffer that stores data, such as one or more video frames, which may be stored in dynamic random access memory (DRAM). For each supported display, the video controller reads data through a given one of one or more DRAM interfaces to access the respective frame buffer. A memory clock is typically used to control the data rate for accessing the frame buffer in the DRAM. In some cases, the computer is directly connected to the display device through an interface, such as a DisplayPort (DP), embedded DisplayPort (eDP), high-definition multimedia interface (HDMI), or other type of interface, to provide a physical connection for transmitting the pixel bitstream from the frame buffer to the display device. In one embodiment, the limit on the bandwidth of the video stream transmitted from the computer to the display device will be the maximum bitrate of the DisplayPort, eDP, or HDMI cable.

[0004] In scenarios where multiple workloads (e.g., game rendering, video processing) are accessing the memory subsystem, the memory subsystem may be clocked at its maximum possible frequency, ensuring that the memory subsystem can handle a large number of reads and writes. In some cases, if the memory subsystem is not overly loaded, the system may attempt to lower the memory clock frequency to reduce power consumption. Changing the memory clock frequency may require a training session performed on the memory interface, a configuration / mode change, or another action that requires access to be temporarily halted. However, in a multi-display system, each display may have different timing characteristics associated with sending (driving) pixels to the display. This makes it difficult or impossible to find a sufficient duration to halt all memory access without introducing visual artifacts on either display when the memory interface needs to be retrained or other types of mode changes need to be performed. Thus, in some systems, the memory clock may be forced to remain at its maximum frequency or other predetermined frequency. As a result, the power consumption of multiple displays may be significant. As modern integrated circuits (ICs) consume increasing amounts of power, more expensive cooling systems such as larger fans, larger heat sinks, and ambient temperature control systems are used to remove excess heat and prevent IC failure, which can lead to louder acoustics and therefore unpleasant customer experiences.

[0005] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of one embodiment of a computing system. [Diagram 2] FIG. 1 is a block diagram of one embodiment of a multi-display system. [Diagram 3] FIG. 2 is a timing diagram of one embodiment of the timing of memory clock frequency updates in a multi-display system. [Figure 4] FIG. 13 is a timing diagram of memory clock frequency updates in a multi-display system according to one embodiment. [Diagram 5] FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for performing memory clock frequency modification in a multi-display system. [Figure 6] FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for operating a multi-mode timing controller. [Figure 7] FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for performing a memory clock frequency update during partial PSR mode. [Figure 8] FIG. 1 is a generalized flow diagram illustrating one embodiment of a method for determining when to change a memory clock frequency. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In the following description, numerous specific details are described to provide a thorough understanding of the methods and mechanisms presented herein. However, those skilled in the art should recognize that various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions and techniques are not shown in detail to avoid obscuring the approach described herein. It will be understood that for simplicity and clarity of illustration, elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements.

[0008] Systems, apparatus, and methods are disclosed for performing asynchronous memory clock changes on multiple displays. In one embodiment, a multi-display system drives multiple displays from a frame buffer in a memory subsystem. In one embodiment, a control unit determines a memory bandwidth demand for the memory subsystem in real time based on current operating conditions. The control unit then compares the real time or predicted memory bandwidth demand with the bandwidth available at an existing memory clock frequency setting. If the bandwidth available at the existing memory clock frequency setting differs from the real time or predicted demand, the control unit makes a decision to modify the existing memory clock frequency setting to better match the real time demand. In various embodiments, the predicted memory bandwidth demand is generated based on machine learning models, heuristics, or other techniques.

[0009] When the control unit determines that a memory clock frequency change is desired for the memory subsystem, the control unit transitions the first display into panel self-refresh (PSR) mode. The transition into PSR mode may take some time, such as one or more frames. As used herein, "PSR mode" is defined as when a display device (i.e., a panel) uses its own memory to refresh what is seen on the screen, rather than relying on an interface to provide a stream of pixels. Simultaneously with placing the first display into PSR mode, the control unit checks the second display to determine when a vertical blanking interval (VBI) occurs. When the PSR mode of the first display overlaps with the VBI of the second display, a memory clock frequency change is initiated. Also, many memory devices (e.g., graphics double data rate (GDDR6) synchronous dynamic random-access memory (SDRAM) devices) require memory training when the memory clock frequency is changed. For these memory devices, memory training is performed as part of the memory clock frequency change. After the memory clock frequency change, the first display is transitioned out of PSR mode, which may take some time, and the display is driven by a frame buffer in the memory subsystem operating at the updated memory clock frequency.

[0010] 1, a block diagram of one embodiment of a computing system 100 is shown. In one embodiment, computing system 100 includes at least processors 105A-105N, input / output (I / O) interface 120, bus 125, memory controller 130, network interface 135, memory device 140, display controllers 150A-150N, displays 155A-155N, and control unit 160. In other embodiments, computing system 100 includes other components and / or computing system 100 is arranged differently.

[0011] Display controllers 150A-150N represent any number of display controllers included in system 100, the number varying depending on the embodiment. Each display controller 150A-150N drives a corresponding display 155A-155N, which may represent any number of displays. In some embodiments, a single one of display controllers 150A-150N drives multiple displays.

[0012] The display controller 150A includes a buffer 152A for storing frames that are displayed when the display 155A is in a panel self-refresh (PSR) mode. The PSR mode is used when static content is being displayed, allowing the display 155A to be driven from the buffer 152A instead of being driven from the frame buffer 142 in the memory device 140. This helps reduce power consumption when the screen content is not changing. For example, in a desktop computer setting, when a user is looking at a document or other static content, the screen pixels are not changing and frames can be stored in the buffer 152A and sent repeatedly to the display 155A. In another example, in a mobile device setting, when the mobile device is displaying a home screen, the screen content is not changing and the display 155A is driven from the frames stored in the buffer 152A. Other examples of static screen content can be encountered in various other use cases.

[0013] Display controller 150N also includes buffer 152N for the same purpose when display 155N is in PSR mode. However, not all displays 155A-155N need to support PSR mode. Thus, in one embodiment, system 100 includes one or more displays that support PSR mode and one or more displays that do not support PSR mode.

[0014] In one embodiment, control unit 160 determines whether a condition for performing a power state change has been detected. Also in this embodiment, control unit 160 monitors the timing of the vertical blanking intervals of displays 155A-155N. As used herein, the term "vertical blanking interval" is defined as the time that elapses after the last visible line of a first frame is displayed but before the first visible line of a second frame is displayed, where the second frame immediately follows the first frame in a video sequence. Within a frame, there are active lines (i.e., scan lines) and vertical blanking lines. The number of active lines determines the active frame time, and the number of vertical blanking lines determines the duration of the vertical blanking interval. In some cases, a vertical synchronization (or Vsync) pulse is generated at the beginning of the vertical blanking interval. In these cases, the vertical synchronization pulse serves as a marker of the occurrence of the vertical blanking interval.

[0015] When a condition for performing a power state change is detected, the control unit 160 determines when to perform the power state change to coincide with the first display being in PSR mode while the second display is undergoing a vertical blanking period. In one embodiment, the power state change involves adjusting the memory clock frequency of one or more memory devices 140. The control unit 160 may be implemented using any suitable combination of circuits, memory elements, and program instructions. It should be noted that the control unit 160 may be referred to by other names, such as a system management controller, a system management unit, a system controller, a controller, etc. Although a single control unit 160 is shown in FIG. 1, it should be understood that this is merely representative of one embodiment. In other embodiments, the system 100 may include multiple control units 160 located in any suitable location. Also, in another embodiment, the control unit 160 is implemented by any of the processors 105A-105N.

[0016] Processors 105A-105N represent any number of processors included in system 100. In one embodiment, processor 105A is a general-purpose processor such as a central processing unit (CPU). In this embodiment, processor 105A executes drivers 110 (e.g., graphics drivers) for communicating with and / or controlling the operation of one or more of the other processors in system 100. It should be noted that, depending on the embodiment, drivers 110 may be implemented using any suitable combination of hardware, software, and / or firmware.

[0017] In one embodiment, processor 105N is a data parallel processor having a highly parallel architecture. Data parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and the like. In some embodiments, processors 105A-105N include multiple data parallel processors. In one embodiment, processor 105N is a GPU that renders pixel data representing an image into frame buffer 142. This pixel data is then provided to display controllers 150A-150N for transmission to displays 155A-155N, respectively. In other embodiments, the pixel data is rendered into multiple frame buffers, with each frame buffer being used to drive a separate display 155A-155N.

[0018] Memory controller 130 represents any number and type of memory controller accessible by processors 105A-105N. Although memory controller 130 is shown as separate from processors 105A-105N, it should be understood that this represents just one possible embodiment. In other embodiments, memory controller 130 may be embedded within one or more of processors 105A-105N and / or memory controller 130 may be located on the same semiconductor die as one or more of processors 105A-105N. Memory controller 130 is coupled to any number and type of memory devices 140. Memory devices 140 represent any number and type of memory devices. For example, types of memory in memory device 140 may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Graphics Double Data Rate 6 (GDDR6) Synchronous DRAM (SDRAM), NAND flash memory, NOR flash memory, Ferroelectric Random Access Memory (FeRAM), and the like.

[0019] I / O interface 120 represents any number and type of I / O interface (e.g., a peripheral component interconnect (PCI) bus, a PCI-Extended (PCI-X), a PCI Express (PCIE) bus, a gigabit Ethernet (GBE) bus, a universal serial bus (USB)). Various types of peripheral devices (not shown) are coupled to I / O interface 120. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks, other types of game controllers, media recording devices, external storage devices, network interface cards, and the like. Network interface 135 can receive and transmit network messages over a network.

[0020] In various embodiments, computing system 100 is a computer, a laptop, a mobile device, a game console, a server, a streaming device, a wearable device, or any of a variety of other types of computing systems or devices. It should be noted that the number of components of computing system 100 varies from embodiment to embodiment. For example, in other embodiments, there are more or less of each component than shown in FIG. 1. It should also be noted that in other embodiments, computing system 100 includes other components (e.g., phase-locked loops, voltage regulators) that are not shown in FIG. 1 to avoid cluttering the diagram. Additionally, in other embodiments, computing system 100 is constructed in a manner other than that shown in FIG. 1.

[0021] Referring to FIG. 2, a block diagram of one embodiment of a multi-display system 200 is shown. In one embodiment, the system 200 includes a processing element 205, a control unit 210, a fabric 215, a memory subsystem 220, timing controllers 240 and 260, and display devices 250 and 270. Although the timing controllers 240 and 260 are shown as separate components from the display devices 250 and 270, respectively, this does not exclude the timing controllers 240 and 260 from being integrated within the display devices 250 and 270, respectively. In other words, the timing controllers 240 and 260 can be located inside or outside the display devices 250 and 270, respectively, depending on the embodiment. Similarly, although the buffer 245 is shown as being located within the timing controller 240, this does not exclude that in other embodiments the buffer 245 is located outside the timing controller 240. It should be noted that the timing controller may be referred to as "TCON" or "T-CON" for short. Generally speaking, the TCON receives video image and frame data from a variety of sources, processes the data, and then sends the data out in a format compatible with its target display.

[0022] Processing elements 205 represent any number, type, and arrangement of processing resources (e.g., CPUs, GPUs, FPGAs, ASICs). Control unit 210 includes any suitable combination of execution units, circuitry, memory, and program instructions. Although control unit 210 is shown as a separate component from processing elements 205, this represents one particular embodiment. In another embodiment, the functions of control unit 210 are performed, at least in part, by processing elements 205. Fabric 215 represents any number and type of buses, communication devices / interfaces, interconnects, and other interface modules for connecting the various components of system 200 together.

[0023] In one embodiment, processing element 205 generates pixel data for display on display devices 250 and 270. In one embodiment, this pixel data is written by processing element 205 to a frame buffer 230 in memory 220 and then sent from frame buffer 230 to display devices 250 and 270. In one embodiment, the pixel data stored in frame buffer 230 represents frames of a video sequence. In another embodiment, the pixel data stored in frame buffer 230 represents the screen content of a laptop or desktop personal computer (PC). In a further embodiment, the pixel data stored in frame buffer 230 represents the screen content of a mobile device (e.g., smartphone, tablet).

[0024] The memory subsystem 220 includes any number and type of memory controller and memory devices. In one embodiment, the memory subsystem 200 is capable of operating at a variety of different clock frequencies that may be adjusted according to various operating conditions. However, when memory clock frequency changes are implemented, memory training is typically performed to change various parameters, adjust characteristics of signals generated for the transfer of data, etc. For example, the phase, delay, and / or voltage levels of various memory interface signals are tested and adjusted during memory training. To train these memory interface signals, various signal transmissions may be performed between the memory controller and memory. It may be difficult to find the right time to perform this memory training when changing memory clock frequencies.

[0025] In one embodiment, the control unit 210 causes a memory clock frequency update to be performed when the display device 250 is in PSR mode and when the display device 270 has a vertical blanking interval. This allows memory training to be performed without interrupting the transmission of display data to the display devices 250 and 270. During the PSR mode, pixel data is stored in the buffer 245 of the timing controller 240 and sent to the display device 250 without going through the memory subsystem 220. In other words, when operating in the PSR mode, the display device 250 performs a self-refresh using the pixel data stored in the buffer 245. Also, when a vertical blanking interval (VBI) occurs for the display device 270, no data is transferred from the frame buffer 230 to the display device 270. This provides a window of opportunity to initiate a memory clock frequency change to the memory subsystem 220.

[0026] In one embodiment, the control unit 210 includes a memory bandwidth monitor 212, a tracking unit 213, and a frequency adjustment unit 214. The memory bandwidth monitor 212, the tracking unit 213, and the frequency adjustment unit 214 may be implemented using any combination of circuits, execution units, and program instructions. Also, in another embodiment, the memory bandwidth monitor 212, the tracking unit 213, and the frequency adjustment unit 214 are not part of the control unit 210, but are separate units separate from the control unit 210. In other embodiments, the control unit 210 may include other arrangements of components that perform similar functions as the memory bandwidth monitor 212, the tracking unit 213, and the frequency adjustment unit 214.

[0027] In one embodiment, the memory bandwidth monitor 212 compares the real-time memory bandwidth demand of the memory subsystem 220 with the memory bandwidth available at the existing memory clock. If the memory bandwidth available at the existing memory clock differs from the real-time memory bandwidth demand by more than a threshold value, the control unit 210 makes a decision to change the frequency of one or more clocks of the memory subsystem 220. Once the decision is made to change the frequency of one or more clocks of the memory subsystem 220, the tracking unit 213 puts the display device 250 into the PSR mode by sending a corresponding command to the timing controller 240. It may take several frames for the display device 250 to enter the PSR mode. The number of frames it takes for the display device 250 may vary depending on the embodiment. The tracking unit 213 also tracks the timing of the VBI of the display device 270.

[0028] In one embodiment, to facilitate the transition from non-PSR mode to PSR mode, the tracking unit 213 sends a signal to the timing controller 240 via the sideband interface 247 for the timing controller 240 to scan out the previously stored frame. Note that the sideband interface 247 is separate from the primary interface 242 used to pass pixels to the timing controller 240. In one embodiment, the primary interface 242 is an eDP interface. In other embodiments, the primary interface 242 is compatible with any of a variety of other protocols. By sending a signal via the sideband interface 247, the timing and scheduling of the call to scan out the previously stored frame can occur within a relatively short period (i.e., line time) before the VBI period of the display device 270. This method is in contrast to the conventional method of sending a request via the primary interface 242, which may result in a delay of several frames before the timing controller 240 enters PSR mode.

[0029] When the timing controller 240 is in the PSR mode, the frequency adjustment unit 214 generates a command to program the PLL 225 to generate the memory clock at a different frequency if the tracking unit 213 determines that there is a VBI for the display device 270. In other embodiments, the control unit 210 includes other arrangements of logic and / or units to cause adjustments to be made to the memory clock frequency during overlap between the PSR mode and the VBI for the display devices 250 and 270, respectively. For example, in another embodiment, the tracking unit 213 and the frequency adjustment unit 214 are combined together into a single unit. In a further embodiment, the frequency adjustment unit 214 is split into multiple units, with a first unit generating commands to change the frequency generated by the PLL 225 and a second unit sending the commands to the PLL 225. Other arrangements of circuits, processing elements, execution units, interface units, program instructions, and other components for implementing the functions of the control unit 210 are possible and contemplated.

[0030] The functionality of the Timing Controller (or TCON) varies from TCON to TCON. Some TCONs only hold a portion of the current picture. In these TCONs, for the PSR to function, the TCON must enter a mode (i.e., "enable PSR") in which the picture is copied to the TCON's memory every time a picture is scanned in. Then, when the PSR is entered, the last history picture is read from memory. Some TCONs or certain modes of the TCON always have the previous picture available. Entering the PSR mode in this case does not require the enable PSR mode. Thus, entering the PSR mode can involve two steps or one step, depending on the capabilities or functionality of the TCON.

[0031] System 200 can be any of a variety of types of computing systems. For example, in one embodiment, system 200 includes a laptop connected to an external display. In this embodiment, display device 250 is the laptop's internal display and display device 270 is the external display. In another embodiment, system 200 includes a mobile device connected to an external display. In this embodiment, display device 250 is the mobile device's internal display and display device 270 is the external display. Other scenarios employing components of system 200 to implement the techniques described herein are possible and contemplated.

[0032] In some embodiments, the system may have more than two displays. For example, in one embodiment, the system has multiple internal displays that are PSR-enabled. In this embodiment, the second internal display may include logic similar to the first internal display, such that if one display is placed in a PSR, the other will also be placed in a PSR. In another embodiment, the system includes multiple external displays that are PSR-enabled. The system will query the external displays to determine their capabilities and how to trigger a PSR or "self-refresh" mode, if applicable.

[0033] In one embodiment, only a single "non-self-refreshable" display can be supported as long as the other display is "self-refreshable", with the following exception: multiple non-self-refreshable displays can be treated as a single display if their vertical blanking periods can be synchronized to match from time to time. For example, two 60Hz displays can be synchronized to have matching clocks by (slightly) "pulling" the timing of one display until it matches the other display bit by bit. Once synchronized, very small adjustments can be used from time to time to keep them synchronized. This is a standard technique often known as "clock pulling" or "genlocking". In another example, 60Hz and 30Hz displays can have a VBI every other time (with respect to the 30Hz display) in synchronization with a similar technique. The VBI period can differ between displays, so a shorter matching period would be applicable for training / clock changes.

[0034] Referring to FIG. 3, a timing diagram 300 of one embodiment of the timing of memory clock frequency updates for a multi-display system is shown. Waveform 302 illustrates the case where an external display connection is actively established according to some protocol such as HDMI or DP. The external display may already be physically connected shortly before the display connection becomes active. In the prior art, when an external display is connected to a system, the memory clock is typically set to its highest possible frequency. The reason is that future adjustments to the frequency are not feasible while the external display is connected, since it is difficult to find a time when both the internal and external displays can be quiesced. However, using the techniques described in this disclosure, adjustments to the memory clock frequency are possible while the external display is connected and actively displaying frames / images.

[0035] Waveform 304 represents the vertical blanking (or VBLANK) period timing for the external display. Each pulse shown in waveform 304 indicates when a vertical blanking period is occurring. Waveform 306 represents the timing of the vertical blanking period for the internal display. Waveform 308 represents when the internal display enters Panel Self Refresh (PSR) mode. Waveform 310 represents when a power state (or PState) change occurs. Waveform 312 represents when a memory clock change occurs.

[0036] At a time indicated by dashed line 314, a vertical blanking period occurs for the internal display. At a time indicated by dashed line 316, the internal display enters PSR mode. Then, at a time indicated by dashed line 318, an external display is connected to the system. Once the external display is connected to the system, PSR mode is disabled (if already enabled) and the memory clock frequency is changed to its maximum (or predetermined) possible frequency since future memory clock frequency changes would be difficult to implement. In this example, overlapping of the vertical blanking periods of the primary display and the external display occurs infrequently or rarely and therefore cannot be relied upon as a reliable method of changing the memory clock frequency. However, keeping the memory clock at its maximum frequency is not efficient in terms of power consumption. Therefore, an improved method for changing the memory clock frequency is desired.

[0037] 4, a timing diagram 400 of memory clock frequency updates in a multi-display system is shown according to one embodiment. Timing diagram 400 includes the same waveforms as shown in timing diagram 300 (of FIG. 3). For example, waveform 402 represents the connection of an external display to the system, waveform 404 represents the timing of the vertical blanking period for the external display, waveform 406 represents the timing of the vertical blanking period of the internal display, waveform 408 represents when the internal display enters PSR mode (or may already be in PSR mode), waveform 410 represents a change in power state, and waveform 412 represents when the memory clock frequency is adjusted.

[0038] At the time represented by dashed line 414, the internal display vertical blanking period occurs. At the time represented by dashed line 416, the internal display enters PSR mode. At the time represented by dashed line 418, a power state change is made when an external display is connected to the system, bringing the memory clock frequency to its maximum value, similar to what occurred in the approach shown in FIG.

[0039] At some point in the period between the time represented by dashed line 418 and a later time represented by dashed line 420, a decision is made to change the memory clock frequency. Once the decision is made to change the memory clock frequency, a signal is sent to the internal display to transition to PSR mode (if the internal display is not already in PSR mode). In some cases, this transition may take some time to occur, as multiple frames may have passed before the internal display enters PSR mode. Once the internal display enters PSR mode at dashed line 420, this may cause a power state change to occur at a time represented by dashed line 422 that coincides with when the external display has its vertical blanking period. The power state change is performed to reduce the memory clock frequency, resulting in reduced power consumption. The memory clock frequency may be in a low state or somewhere intermediate between the highest and lowest frequencies. After the power state change is performed, the internal display may return to its previous PSR mode, either on or off, depending on the state the internal display was in before the decision was made to change the memory clock frequency.

[0040] This technique of using PSR mode to perform a power state change makes it easier to select the time to perform the power state change compared to the conventional technique of waiting for overlapping vertical blanking periods on both the internal and external displays. The choice to be in PSR mode to save power when the display is not being updated is an independent decision, and when using PSR to facilitate memory / clock / mode changes, it is necessary that the PSR state be restored once this action is completed.

[0041] Referring to FIG. 5, one embodiment of a method 500 for performing memory clock frequency modification in a multi-display system is shown. For purposes of explanation, the steps in this embodiment and in FIGS. 6-8 are shown in sequence. However, it should be noted that in various embodiments of the described method, one or more of the described elements are performed simultaneously, in a different order than shown, or omitted entirely. Other additional elements are also performed as desired. Any of the various systems or devices described herein may be configured to perform the method 500.

[0042] The control unit determines that one or more conditions are met to trigger a change to a memory clock frequency of a memory subsystem driving the multiple displays (block 505). In one embodiment, the change to the memory clock frequency of the memory subsystem is performed as part of a power state change. The one or more conditions that trigger the change to the memory clock frequency may vary from embodiment to embodiment. Method 800 describes one example of a condition for triggering a change to the memory clock frequency. In other embodiments, other conditions may cause the memory clock frequency change. For example, in one embodiment, the memory clock frequency may be changed by connecting or disconnecting alternating current (AC) power or direct current (DC) power. There may be different allowable clock ranges depending on the power source. In another embodiment, a change in the temperature of the host system or device may trigger a desire to change the memory clock frequency. For example, if the temperature of the host system / device exceeds a first threshold, the control unit will attempt to reduce power consumption to reduce the temperature. One way to reduce power consumption is by reducing the memory clock frequency. In a further embodiment, if the temperature is below a second threshold, the control unit may increase the memory clock frequency, but in order not to overheat the system / device in doing so. In yet another embodiment, if increased performance is deemed desirable, the control unit will attempt to increase performance by increasing the memory clock frequency. Other conditions for changing the memory clock frequency are possible and contemplated.

[0043] In some embodiments, the conditions for triggering a change to the memory clock frequency can be event-driven. The memory controller can place an event if the throughput used exceeds / below some threshold, over a window, instantaneously, or is filtered in some way in time. There can also be software, firmware, or hardware-based mechanisms where the mechanism knows or predicts that a workload will need resources when submitted, even before the workload is scheduled or executed. Similarly, when a workload is finished, the mechanism knows which resources are no longer needed. Similar mechanisms can also handle periodic workloads. In another embodiment, a real-time operating system (RTOS) may be aware of the deadline, and the RTOS can choose a more optimal clock depending on the approaching deadline.

[0044] Next, in response to detecting the condition for changing the memory clock frequency, the control unit tracks when the first display device has a vertical blanking period (VBI) (block 510). Also, in response to detecting the condition for causing a change in the memory clock frequency, the control unit causes the second display device to enter PSR mode (block 515). In some cases, entering PSR mode can involve two steps, where the PSR mode is enabled in a first step, and then entering PSR mode in a second step. This may depend on the capabilities of the particular TCON of the second display device, in at least one embodiment. If the second display device is already in PSR mode, block 515 may be skipped. After the second display device enters PSR mode, if the first display device has a vertical blanking period (condition block 520, "yes"), the control unit initiates a memory clock frequency update during the vertical blanking period (block 525). In one embodiment, memory training is performed as part of the memory clock frequency update. After the memory clock frequency update is performed, the control unit causes the second display device to exit PSR mode (block 530). Note that the second display device can remain in PSR mode if other conditions for remaining in PSR mode are detected. After block 530, method 500 ends. If the second display device is not in a vertical blanking interval (condition block 520, "no"), method 500 remains at condition block 520. Note that method 500 can be repeated each time a condition for changing the memory clock frequency is detected.

[0045] In various embodiments, the first and second display devices described in method 500 have different refresh rates. For example, in one embodiment, the first display device has a first refresh rate (e.g., 60 frames per second (fps)) and the second display device has a second refresh rate (e.g., 24 fps). For the purposes of this description, it is assumed that the second refresh rate is different from the first refresh rate. In this embodiment, the VBIs of the display devices occur at different rates, and waiting for the VBIs to match is not a reliable strategy for generating memory clock frequency updates. Therefore, method 500 is a useful technique for still generating memory clock frequency updates even when the display devices have different frame refresh rates.

[0046] 6, one embodiment of a method 600 for operating a multi-mode timing controller is shown. The timing controller operates in a first mode to send pixels to a display (block 605). While operating in the first mode, the timing controller receives pixels to be sent to the display via a first interface (block 610). In one embodiment, the first interface is an eDP interface. In other embodiments, the first interface can be any of a variety of other types of interfaces.

[0047] Then, at a later point in time, the timing controller receives a signal or command from the host (e.g., a processor) to preemptively switch to the second mode (block 615). The signal or command can be communicated over the first interface or using a sideband signal, depending on the embodiment. In one embodiment, the second mode is a pre-PSR mode, which allows for a relatively fast transition to the PSR mode. For example, in this embodiment, it may take 4 or 5 cycles to switch from the first mode to the PSR mode, but it may take only 1 or 2 cycles to switch from the pre-PSR mode to the PSR mode.

[0048] The timing controller then receives a signal or command from the host to switch to the third mode (block 620). In one embodiment, the third mode is a PSR mode. In one scenario, the signal or command specifies the number of frames for which the timing controller operates in the third mode. While operating in the third mode, the timing controller receives pixels to be sent to the display from a second interface coupled to the embedded frame buffer (block 625). In one embodiment, the timing controller sends pixels from the embedded frame buffer to the display for the specified number of frames. In another embodiment, the timing controller sends pixels from the embedded frame buffer to the display until it receives a signal or command from the host to exit the third mode. In either case, the timing controller returns to the second or first mode at a later point in time (block 630). Whether the timing controller returns from the third mode to the second or first mode may depend on a variety of factors, including a specific command from the host, a programmable setting, the state of one or more operating conditions, etc. After block 630, the method 600 ends.

[0049] 7, one embodiment of a method 700 for performing a memory clock frequency update during a partial PSR mode is shown. The system sends pixel data to a first and second display device (block 705). While sending the pixel data to the first and second display devices, the control unit detects one or more conditions for updating a memory clock frequency of a memory subsystem (block 710). The detected conditions may vary from embodiment to embodiment.

[0050] In response to detecting the condition for updating the memory clock frequency of the memory subsystem, the control unit tracks when the first display device has a VBI (block 715). Also, in response to detecting the condition for updating the memory clock frequency of the memory subsystem, the control unit puts the second display device into a partial PSR mode (block 720). Partial PSR mode refers to a mode in which only a portion of the screen is redrawn and the remaining portion is refreshed (i.e., repeated) from the previous frame. For example, if a user moves the mouse to a new portion of the screen but other screen content remains the same, partial PSR mode may be implemented to reuse most of the previous frame while updating only the portion of the frame affected by the mouse movement. Partial PSR mode may also be used in other scenarios where only a portion of the screen is being updated. Note that partial PSR mode is sometimes referred to as "Selective Update PSR."

[0051] The control unit then tracks the timing of the different stages of the partial PSR mode (block 725). The control unit then schedules updates to the memory clock frequency of the memory subsystem to occur when the VBI of the first display device overlaps (i.e., aligns) with the refresh portion of the partial PSR mode of the second display device (block 730). After block 730, method 700 ends.

[0052] Referring to FIG. 8, one embodiment of a method 800 for determining when to change the memory clock frequency is shown. A memory bandwidth monitor (e.g., memory bandwidth monitor 212 of FIG. 2) compares the real-time memory bandwidth demand of the memory subsystem to the available memory bandwidth at the existing frequency of the memory clock (block 805). The comparison can be instantaneous or multiple times over a fixed or adaptable duration. The real-time memory bandwidth demand depends on the control algorithm and can include a current peak, a recent peak, a rolling average, a filtered, or other variation. In one embodiment, the real-time memory bandwidth demand includes a predicted demand when a workload is requested or scheduled to occur but has not yet begun. In another embodiment, the real-time memory bandwidth demand includes a trended demand.

[0053] If the available memory bandwidth (BW) at the existing frequency of the memory clocks differs from the real-time memory bandwidth demand by more than a threshold (condition block 810, “Yes”), the control unit (e.g., control unit 210) makes a decision to change the frequency of one or more memory clocks (block 815). In one embodiment, each memory clock has an individual control parameter (e.g., individual threshold). In various embodiments, the threshold can include components such as time filters, hysteresis, etc. In one embodiment, there can be heuristic or mathematical conditions that can delay the change in frequency if the available memory bandwidth is greater than the demand. If the available memory bandwidth is less than the demand, the control unit may want to increase the frequency as quickly as possible. Thus, the condition in condition block 810 is programmable and can include time, filtering, etc.

[0054] The tracking unit (e.g., tracking unit 213) and the frequency adjustment unit (e.g., frequency adjustment unit 214) then cause a memory clock frequency change if the VBI on the first display device and the PSR mode on the second display device overlap (block 820). After a programmable delay (block 825), the method 800 returns to block 805. The programmable delay in block 825 prevents hysteresis in the memory clock frequency change. Otherwise, if the available memory bandwidth at the existing frequency of the memory clock is within the real-time memory bandwidth demand threshold (condition block 810, "no"), the method 800 returns to block 805.

[0055] In various embodiments, program instructions of a software application are used to implement the methods and / or mechanisms described herein. For example, program instructions executable by a general purpose or special purpose processor are contemplated. In various embodiments, such program instructions are expressed by a high level programming language. In other embodiments, the program instructions are compiled from the high level programming language into a binary, intermediate or other form. Alternatively, program instructions are written that describe the behavior or design of hardware. Such program instructions are expressed by a high level programming language such as C. Alternatively, a hardware design language (HDL) such as Verilog is used. In various embodiments, the program instructions are stored in any of a variety of non-transitory computer readable storage media. The storage media are accessible by the computing system during use to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors configured to execute the program instructions.

[0056] It should be emphasized that the above-described embodiments are merely non-limiting examples of embodiments. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

1. An apparatus comprising: A tracking unit; A frequency adjusting unit, The tracking unit is In response to determining that a condition is met for modifying a memory clock frequency of the memory subsystem, Tracking a vertical blanking interval (VBI) timing of a first display device; transitioning the second display device into a panel self-refresh (PSR) mode; The device is configured to: The frequency adjusting unit includes: configured to cause an adjustment of the memory clock frequency when a VBI of the first display device overlaps with a state in which the second display device is in a PSR mode; Device.

2. the adjusting comprises changing the memory clock frequency from a first frequency to a second frequency different from the first frequency; 2. The apparatus of claim 1.

3. the condition for changing the memory clock frequency includes a memory bandwidth demand that differs from a memory bandwidth available at the memory clock frequency by more than a threshold.

2. The apparatus of claim 1.

4. the tracking unit is configured to cause the second display device to exit a PSR mode after the adjustment is made to the memory clock frequency.

2. The apparatus of claim 1.

5. The apparatus comprises: placing the second display device in a partial PSR mode; scheduling the adjustment of the memory clock frequency to occur when a refresh portion of a partial PSR mode of the second display device overlaps with the VBI of the first display device; 4. The method of claim 3, 2. The apparatus of claim 1.

6. the apparatus is configured to cause memory training to be performed while the second display device is in a PSR mode and simultaneously while the VBI is occurring for the first display device.

2. The apparatus of claim 1.

7. the frequency adjustment unit is configured to send a command to a phase locked loop to cause an adjustment of the memory clock frequency when the PSR mode of the second display overlaps with the VBI of the first display device.

2. The apparatus of claim 1.

8. 1. A method comprising: In response to the control unit determining that a condition is met for modifying a memory clock frequency of the memory subsystem, tracking a vertical blanking interval (VBI) timing of the first display device; transitioning the second display device into a panel self-refresh (PSR) mode; and adjusting the memory clock frequency in response to a VBI of the first display device overlapping a state in which the second display device is in a PSR mode. method.

9. the adjusting comprises changing the memory clock frequency from a first frequency to a second frequency different from the first frequency; 9. The method of claim 8.

10. the condition for changing the memory clock frequency includes a real-time memory bandwidth demand that differs from the memory bandwidth available at the memory clock frequency by more than a threshold value.

9. The method of claim 8.

11. causing the second display device to exit a PSR mode after the adjustment is made to the memory clock frequency.

9. The method of claim 8.

12. placing the second display device in a partial PSR mode; and scheduling the adjustment of the memory clock frequency to occur when a refresh portion of a partial PSR mode of the second display device overlaps with the VBI of the first display device.

9. The method of claim 8.

13. performing memory training while the second display device is in a PSR mode while simultaneously generating the VBI for the first display device.

9. The method of claim 8.

14. sending a command to a phase locked loop to cause an adjustment of the memory clock frequency in response to determining that the PSR mode of the second display device overlaps with the VBI of the first display device.

9. The method of claim 8.

15. 1. A system comprising: a timing controller configured to send pixel data to a first display device; A control unit, the control unit, in response to determining that a condition is met for changing a memory clock frequency of a memory subsystem, transitioning the timing controller to a panel self-refresh (PSR) mode; Tracking a vertical blanking interval (VBI) timing of a second display device; in response to the timing controller determining that the PSR mode overlaps with a VBI of the second display, causing an adjustment of a memory clock frequency; 4. The method of claim 3, system.

16. the adjusting comprises changing the memory clock frequency from a first frequency to a second frequency different from the first frequency; 16. The system of claim 15.

17. the condition for changing the memory clock frequency includes a real-time memory bandwidth demand that differs from the memory bandwidth available at the memory clock frequency by more than a threshold value.

16. The system of claim 15.

18. the control unit is configured to cause the timing controller to exit a PSR mode after the adjustment is made to the memory clock frequency.

16. The system of claim 15.

19. The control unit placing the timing controller in a partial PSR mode; scheduling adjustments to the memory clock frequency to occur when a refresh portion of a partial PSR mode of the timing controller overlaps with the VBI of the second display device; 4. The method of claim 3, 16. The system of claim 15.

20. the control unit is configured to cause memory training to be performed while the timing controller is in a PSR mode and simultaneously the VBI is occurring for the second display device.

16. The system of claim 15.

Images