Systems and methods for configuring display devices and display systems - Patents.com

Abstract

The displays and systems and methods can be used in applications including, but not limited to, projectors, heads-up displays, and Augmented Reality (AR), Mixed Reality (MR), and Virtual Reality (VR) systems and devices, such as headsets and other near-eye devices and systems. The tiled or tileable displays and methods of the present invention provide displays of various sizes. Thus, the tiled or tileable displays are configured to accommodate the display sizes required by various wearable and mobile devices that require or incorporate displays.

Description

[Technical field]

[0001] This application claims the benefit of U.S. Patent Application No. 63 / 229,642, filed August 5, 2021, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to displays, such as light emitting diode (LED) displays (such as LED displays, organic light emitting diode (OLED) displays, and micro-displays or micro-versions thereof (such as micro LED and micro OLED displays). In particular, the present disclosure relates to configurable LED displays. [Background technology]

[0003] Typically, mid-sized displays for portable or wearable or mobile or handheld devices (i.e., devices that are not microdisplays, monitors, televisions, etc.) intended for direct viewing applications are often made with transmissive Liquid Crystal Display (LCD) or OLED technology with a TFT backplane. OLED displays suffer from short lifetimes and limited brightness, while LCD displays require backlighting, which consumes power per pixel regardless of whether the pixel is on or off. TFTs are cheap but have excessive resistance (wasting power) and are too large to create sophisticated circuitry under each pixel. As a result, TFTs are limited to drive schemes that drive each row of the display in sequence with a very short duty cycle for each pixel, which requires high current densities to achieve adequate brightness with TFTs. In contrast, microLED displays have long lifetimes, but bonding microLED arrays to silicon backplanes to form microLED displays often produces displays with random defects.

[0004] When building microLED displays with silicon backplanes for applications with large physical size (i.e., not microdisplays, but for direct-view displays such as VR headsets, wearable devices such as watches, smartphones or monitors / TVs), building a variety of shapes and sizes typically requires the display and manufacturing process to be redesigned for each new application. As display sizes increase, yields continue to decrease, making some applications cost prohibitive or at least uncompetitive. Summary of the Invention [Problem to be solved by the invention]

[0005] The displays of the present disclosure may be used in applications including, but not limited to, projectors, heads-up displays, and Augmented Reality (AR), Mixed Reality (MR), and Virtual Reality (VR) systems and devices, such as headsets and other near-eye devices and systems. The tiled or tileable displays and methods of the present disclosure provide displays of various sizes. Thus, the tiled or tileable displays are configured to accommodate the display sizes required by various wearable and mobile devices that require or incorporate displays. [Brief description of the drawings]

[0006] [Figure 1] 1 illustrates a tile array for a circular watch display in an embodiment of the present disclosure. [Diagram 2] 1 illustrates a tile having a seam in accordance with an embodiment of the present disclosure. [Diagram 3]1 illustrates the conversion to a working die (such as a backplane die) in an embodiment of the present disclosure, where the die is converted to a form that allows for nearly seamless mating. [Figure 4] 1 illustrates a cross-sectional view of a tile on a printed circuit board in an embodiment of the present disclosure. [Diagram 5] 1 shows the back side of a tile in an embodiment of the present disclosure. [Figure 6] 1 illustrates the connection of tiles to form an array in an embodiment of the present disclosure. [Figure 7] 1 illustrates tile backplane circuitry in an embodiment of the present disclosure. [Figure 8] 1 illustrates individual pixel circuit elements in an embodiment of the present disclosure. [Figure 9] 3 illustrates a serial stream format in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Detailed embodiments are disclosed herein as necessary. It should be understood that the disclosed embodiments are merely illustrative of various and alternative forms. As used herein, the term "exemplary" is used broadly to refer to embodiments that serve as illustrations, samples, models, and patterns. The drawings are not necessarily to scale, and some features may be exaggerated or minimized to show details of particular elements. In other cases, well-known elements, systems, materials, and methods known to those skilled in the art have not been described in detail to avoid obscuring the present disclosure. Therefore, the specific configuration and functional details disclosed herein should not be construed as limitations, but merely as a basis for the claims and a representative basis for teaching those skilled in the art.

[0008] The present disclosure uses displays that are composed of "tiles" that are manufactured and tested independently (each tile is smaller and tested during manufacturing, and can be repaired before manufacturing is complete, improving yield and eliminating yield limitations). Additionally, various wearable and mobile device manufacturers differentiate themselves with industrial designs that offer a range of display sizes and shapes. This requires a new design for each customer, but the tiled or tileable display and method of the present disclosure allow new displays to be designed and configured by arranging tiles on a Printed Circuit Board (PCB) (which allows for faster design and manufacturing compared to creating a new silicon die and micro LED array).

[0009] 1 shows a pseudo-circular array of display tiles. In some embodiments of the present disclosure, the tiles or array of display tiles are generally circular and can be used as a display device (such as an LED display device or LED panel) for a circular device. In some embodiments of the present disclosure, any number of tiles can be arranged in any shape. In some embodiments of the present disclosure, a light emitting device (such as a tile) has a light emitting die (such as an LED die) and an operating die (such as a backplane die).

[0010] In some embodiments of the present disclosure, a light emitting die (such as an LED die) has a light emitting element bonded or integrated with a light emitting substrate (such as a GaN substrate). In some embodiments of the present disclosure, a plurality of light emitting elements, for example an array of light emitting elements (such as LEDs of any type or size), are formed on the light emitting substrate. The plurality of light emitting elements (such as LEDs) or a light emitting array (such as an array of light emitting elements) and the light emitting substrate (such as an LED substrate) are integrated and / or bonded together to form the light emitting die (such as an LED die).

[0011] In some embodiments of the present disclosure, a pixel is formed by coupling (e.g., electrically coupling) each light-emitting element of the light-emitting die to circuitry (including at least pixel circuitry) that controls or is used to operate (e.g., including driving each of one or more light-emitting elements). In some embodiments of the present disclosure, the pixel circuitry includes at least drive circuitry. In some embodiments of the present disclosure, the drive circuitry includes at least pixel logic circuitry that determines the on / off state of the pixel as a function of time, and input / output circuitry that provides current to the LEDs. In some embodiments of the present disclosure, there is one set of pixel circuitry for each light-emitting element (e.g., LED).

[0012] In some embodiments of the present disclosure, each light emitting die (such as an LED die) is coupled (such as electrically coupled) to an operational die (such as a backplane die) that includes a backplane substrate and pixel circuitry and / or pixel-related circuitry.

[0013] In some embodiments of the present disclosure, the die is formed from silicon and is referred to as a silicon working die (e.g., a backplane die). In some embodiments of the present disclosure, the working die (e.g., a backplane die) has circuit elements (e.g., pixel circuit elements) disposed on, bonded to, integrated with, formed on, deposited on, or embedded in a backplane substrate.

[0014] In some embodiments of the present disclosure, circuit elements (such as pixel circuit elements) or drive circuit elements are separated into at least pixel logic circuit elements and input / output circuit elements. In some embodiments of the present disclosure, the pixel logic circuit elements operate or are located in one or more areas of the backplane substrate that are distinct from the one or more areas of the backplane substrate in which the input / output circuit elements operate or are located.

[0015] In certain embodiments of the present disclosure, the pixel logic circuit elements operate or are located in one or more strips or strip-like areas of the backplane substrate that are distinct from the one or more strips or strip-like areas of the backplane substrate in which the input / output circuit elements operate or are located.

[0016] In some embodiments of the present disclosure, each light emitting element is associated with a pixel circuit element (i.e., associated with a driver circuit or circuit elements that drive the light emitting element (e.g., determine a gray level output for the light emitting element)). In some embodiments of the present disclosure, each light emitting element is associated with its own pixel circuit element (i.e., associated with a driver circuit or circuit elements that drive the light emitting element (e.g., determine a gray level output for the light emitting element). In some embodiments of the present disclosure, each light emitting element is associated with a pixel logic circuit element or circuit and an input / output circuit element or circuit. In some embodiments of the present disclosure, each light emitting element (e.g., LED) in combination with its circuit elements (e.g., pixel circuit elements) form a pixel of the tile, and the circuit elements of each light emitting element (e.g., LED) include, but are not limited to, driver circuit elements. In some embodiments of the present disclosure, the LEDs and pixel circuit elements are on different wafers before bonding, so that electrical contact elements exist between the LEDs and the pixel circuit elements. In some embodiments of the present disclosure, the electrical contact elements exist on the wafer on which each LED is located, or on the wafer on which the pixel circuit elements are located.

[0017] In one embodiment of the present disclosure, a pixel of a tile is formed by a combination of each light-emitting element (such as an LED) and its circuit elements, for example, a pixel of a tile is formed by a combination of each light-emitting element (such as an LED) and its circuit elements (such as a pixel logic circuit element for that light-emitting element and an input / output circuit element for that light-emitting element).

[0018] In some embodiments of the present disclosure, the light emitting element is a master light emitting element. In some embodiments of the present disclosure, the master light emitting element has two or more light emitting elements (such as LEDs). In some embodiments of the present disclosure, the master light emitting element has at least three light emitting elements, for example, a set of three light emitting elements (such as LEDs).

[0019] In some embodiments of the present disclosure, a pixel is formed by coupling (e.g., electrically coupling) a light emitting element (such as an LED) to a circuit element (such as a pixel circuit element) that drives each of the light emitting elements (such as an LED). In some embodiments of the present disclosure, a master pixel is formed by coupling (e.g., electrically coupling) a master light emitting element (such as a group or set of multiple, e.g., three LEDs) to a circuit element (such as a pixel circuit element) that drives each of the light emitting elements (such as an LED) of the master light emitting element. In some embodiments of the present disclosure, each light emitting element (such as an LED) is a group of three primary colors, and when the LEDs are grouped into a group, they abut perceptually seamlessly, even though there are gaps between them. In some embodiments of the present disclosure, a tile has more than one master pixel, such as an array of multiple master pixels. In some embodiments of the present disclosure, the pixel circuit element has at least a driving circuit element. In some embodiments of the present disclosure, the driving circuit element has at least a pixel logic circuit element and an input / output circuit element.

[0020] In some embodiments of the present disclosure, the tiles may be arranged, for example, in any pattern, on a printed circuit board. In some embodiments of the present disclosure, the tiles may be arranged, for example, in any pattern, on a printed circuit board to form a display. To illustrate the use of tiles in embodiments of the present disclosure, a pseudo-circular array of tiles is shown in FIG. 1. For example, as shown in FIG. 1, a pseudo-circular array of display tiles is arranged on a printed circuit board (PCB) (not shown) for use in a watch face display. In the illustrated example, for example, 88 tiles of 3.6 mm×3.6 mm, including 60×60 pixels per tile, are arranged to form a watch face of 36 mm diameter, according to embodiments of the present disclosure. However, those skilled in the art will appreciate that the number of tiles, the number of pixels or master pixels per tile, or both, the shape of the tile or the shape of the array of tiles, or both may be different. In some embodiments of the present disclosure, the pattern or arrangement of tiles on the printed circuit board may be different.

[0021] In some embodiments of the present disclosure, adjacent tiles are arranged on a printed circuit board with a space, gap, or seam between them, as shown in FIG. 2. In some embodiments of the present disclosure, there is a space, gap, or seam between the sides or edges of two adjacent tiles (each tile has one or more master pixels or one or more groups of three light emitting elements (e.g., LEDs and their associated pixel circuit elements)) as shown in FIG. 2. It will be understood by those skilled in the art that reference to LEDs includes any type of LED (e.g., LED, OLED, micro LED, or micro OLED). In some embodiments of the present disclosure, there is a space, gap, or seam between adjacent tiles as shown in FIG. 2. It will be understood by those skilled in the art that the number and color of LEDs in a master light emitting element or master pixel (e.g., a set of LEDs or a set of circuit elements electrically coupled to each of the LEDs or both) may be different.

[0022] In some embodiments of the present disclosure, the pitch (i.e., the center-to-center distance between each light emitting element, such as a collection of light emitting elements (e.g., LEDs) or each master pixel or each master light emitting element) must be sufficient to allow for spaces, gaps, and seams between light emitting elements, such as a collection of light emitting elements (e.g., LEDs) or each master pixel or each master light emitting element or each pixel, that do not disturb the pixel pitch (i.e., the distance between the center of one light emitting element, such as a master pixel or master light emitting element, and the center of another light emitting element, such as a master pixel or master light emitting element). At the same time, it must be sufficient to allow for spaces, gaps, and seams that keep the pixel pitch the same or substantially / nearly the same for all or at least a portion of adjacent light emitting elements (such as each master light emitting element or each master pixel). In some embodiments of the present disclosure, when the tile is a monochromatic tile, the master pixel and pixel are the same.

[0023] 3 shows the difference between a conventional backplane die and a tiled or tileable working die (such as a backplane die). For example, the working die (such as a backplane die, such as a silicon backplane die) in the embodiments of the present disclosure has a form in which the tiles abut seamlessly because the pitch between each master light emitting element or each master pixel is the same. The conventional die layout has or is provided with 1 / 0 and logic circuitry areas (whereby the input area is provided with 1 / 0 buffers, which are used to convert between logic levels used externally and internal logic levels. The logic area has registers, state machines, and pixel drive circuitry, which are used to receive image data from the outside and distribute it to the pixels in the active area).

[0024] In a conventional die arrangement, the input and logic regions are arranged or positioned around the active area of ​​the display (i.e., the area containing the pixels that generate the image, etc.). In some embodiments of the active die, the active die (e.g., backplane die, such as a tileable backplane or silicon backplane) of the disclosed embodiments has strips of alternating pixel logic circuit elements and 1 / 0 circuit elements. In some embodiments of the disclosed embodiments, the 1 / 0 circuit elements have 1 / 0 buffers that are used to convert between logic levels used externally and internal logic levels. In some embodiments of the disclosed embodiments, the logic region has registers, state machines, and pixel drive circuit elements that are used to receive image data from the outside and distribute it to the pixels of the active area. The wiring is arranged in rows and columns so that the connections to the LED pixels in the array are maintained. In some embodiments of the disclosed embodiments, each light emitting element, e.g., LED, is located on a pixel logic circuit element or strip, on a 1 / 0 circuit element or strip, or on both a pixel logic circuit element or strip and a 1 / 0 circuit element or strip. In some embodiments of the present disclosure, the circuit element strips are embedded within the working die backplane substrate.

[0025] Conventional backplanes typically include peripheral bond pads on the silicon die or bump / pillar connections on the silicon die to connect 1 / 0 buffers to the circuitry substrate or package. According to an embodiment of the present disclosure, the tiled or tileable backplane has through-silicon vias (TSVs), which distinguishes it from conventional backplanes. The through-silicon vias are utilized to connect or electrically couple one side or front side of a working die (e.g., a backplane die such as a silicon backplane die) to a second side or back side of the working die, to circuitry on a printed circuit board, or both. The working die has disposed thereon a light emitting die (including a collection of LEDs, a light emitting element (e.g., LED), or a master light emitting element connected or electrically coupled to pixel circuitry to form a master pixel).

[0026] 4 shows a cross-sectional view of a tile on a printed circuit board. In one embodiment of the present disclosure, the tile comprises an operating die (such as a backplane die or wafer, such as a silicon backplane) bonded (e.g., bonded and / or electrically coupled) to a light emitting die (such as an LED wafer or die) using bonding and connection methods known in the art.

[0027] In some embodiments of the light emitting die, according to embodiments of the present disclosure, each LED is formed, integrated, or fabricated on a substrate, such as a GaN substrate. However, one skilled in the art will appreciate that the substrate material may be different, for example, the substrate may be composed of any semiconductor material capable of forming a light emitting structure. In some embodiments of the present disclosure, metallic contacts are bonded to or integrated with the light emitting die (such as the LED die) for electrically coupling the light emitting die to the operating die (such as a backplane die, such as a silicon die or a silicon operating die).

[0028] According to an embodiment of the present disclosure, the light emitting device (e.g., a tile) has vias (e.g., through-substrate vias or through-silicon vias) that are used to provide a connection, power supply, and interface between a first or back surface and a second or front surface of an operational die (e.g., a silicon die) and to provide power to the tile circuit elements (e.g., 1 / 0 logic circuit elements, 1 / 0 logic strips, pixel circuit element logic circuit elements, pixel circuit element logic strips) and / or conductive circuit element portions (e.g., copper deposits or other conductive elements) that are deposited on, bonded to, or integrated with a printed circuit board. In an embodiment of the present disclosure, the vias (e.g., through-substrate vias or through-silicon vias (TSVs)) are used to receive the data voltage input at the 1 / 0 buffer and to connect power and ground devices or components or sources or combinations thereof to the light emitting die (e.g., LED die) and / or operational die (e.g., backplane die).

[0029] In one embodiment of the present disclosure, the openings of the through-substrate vias, e.g., through-silicon-via (TSV) openings, open to the backside of a working die (e.g., a silicon die) and are coated with solder or other conductive material for solder attachment to an underlying printed circuit board or to circuit elements of an underlying printed circuit board.

[0030] In some embodiments of the present disclosure, the tile circuit elements (such as 1 / 0 logic or 1 / 0 circuit element strips and pixel circuit element logic strips or driver circuit element logic strips) are deposited, formed, embedded, or integrated into the operating die (such as a backplane substrate, a silicon operating die or backplane die, or a silicon die). In some embodiments of the present disclosure, the light emitting die (such as an LED die) is at least one of electrically connected, coupled, or bonded to the operating die, and the silicon die is at least one of connected, coupled, or electrically coupled, connected, or bonded to a PC. In some embodiments of the present disclosure, the connections between tiles or within each tile array are made via a printed circuit board (i.e., a substrate that houses each tile or on which each tile is disposed, coupled, bonded, or positioned).

[0031] In some embodiments of the present disclosure, the circuit element or one or more conductive elements are deposited, fabricated, or integrated into a printed circuit board (e.g., one or more surfaces of a printed circuit board). The circuit element or one or more conductive elements may be, for example, (1) electrically connected to a light emitting die (e.g., an LED die) or an operating die (e.g., a backplane die) or both to a power source or power or data source or a voltage source or a current source or a combination thereof, or (2) used to receive data, voltage, or other input, or both. In some embodiments of the present disclosure, the circuit element or conductive element or deposit on the printed circuit board is made of copper material, also referred to as copper trace or copper wiring. However, it will be understood by those skilled in the art that the conductors may be made of conductive materials other than copper. The printed circuit board also functions as a structure that provides support or rigidity or a rigid surface for the tile array. In some embodiments of the present disclosure, the printed circuit board may include one or more layers of circuit elements (e.g., any tile-related circuit elements).

[0032] FIG. 5 shows the back side of the tile. In some embodiments of the present disclosure, the back or bottom side of the tile has an array of through silicon via openings, as shown in FIG. 5, which may be used to receive, for example, input data or voltage, output data or voltage, or signals. In some embodiments of the present disclosure, the through silicon via openings may be used to electrically connect the light emitting die (such as an LED die) to circuit elements on a printed circuit board, including, for example, (1) circuit elements for electrically connecting the LED die to a power source or a power or data source or a voltage source or a current source or combinations thereof, or (2) circuit elements for receiving data, voltage, or other inputs, or both. In some embodiments of the present disclosure, the through silicon vias may be used to output data from the tile.

[0033] As shown in FIG. 5, for example, vias are present in the working die (e.g., silicon die) and are used to establish a power connection between a printed circuit board (which may be connected to a voltage source or other power source) and a light emitting die (e.g., LED die). FIG. 5 also illustrates an embodiment of the present disclosure, which shows an example of an exemplary I-layer wiring pattern of a printed circuit board, e.g., having traces or conductive elements deposited on or embedded within the printed circuit board. In some embodiments of the present disclosure, the through silicon vias labeled D1 are used to connect serial data input from a controller to the tiles (which controller is shown in FIG. 6 and may also be referred to as a tile array controller, array controller, master controller, etc.). In some embodiments of the present disclosure, the controller shown in FIG. 6 is external to the tiles or tile array or both. In some embodiments of the present disclosure, the controller (e.g., tile array controller or master controller) is disposed or connected to a substrate, such as a printed circuit board, to which the tiles are connected or disposed. In some embodiments of the present disclosure, the controller controls the operation of tiles, which are individual tiles in a tile array, or the operation of the tile array as a unit, or both. In some embodiments of the present disclosure, the controller (such as a tile array controller or a master controller) distributes data to the tiles and controls the tiles when they display new data. In some embodiments of the present disclosure, the arrows between the controllers in FIG. 6 and between the tiles in FIG. 6 represent the serial data and clock tapped transmission lines (i.e., conductive elements (e.g., wire elements such as copper wire elements)) shown in FIG. 5 to a printed circuit board.

[0034] The through-silicon vias labeled CK are used to connect the clock voltage output from the controller to each tile to sample the serial data and to provide a clock to the logic circuit elements of the tile. As will be described with reference to Figure 6, the tiles receive serial data (DI) and a clock output (CK) from the controller.

[0035] In some embodiments of the present disclosure, at least one via is used to connect or provide power to the tile or the light emitting die (e.g., LED die) or both, for example, via a power rail (e.g., a conductive element, a ground element or component, a wire line, or other component, or combination thereof, either coupled to, deposited on, embedded in, integrated with, or combinations of a printed circuit board) that is coupled or electrically connected to the working die (e.g., a backplane die or a silicon working die). As a result, according to embodiments of the present disclosure, power is provided to the light emitting device (e.g., the tile or the light emitting die (e.g., LED die)).

[0036] In some embodiments of the present disclosure, a light emitting die (such as an LED die) is coupled to an operating die (such as a silicon operating die or a backplane die). In some embodiments of the present disclosure, through silicon vias (such as four TSVs) are used to connect the printed circuit board to the power rails (i.e., VDD) of the light emitting die (such as an LED die) or the tile or both, providing sufficient current carrying capacity and low resistance. Those skilled in the art will appreciate that the number of vias used to connect components of the operating die (such as a backplane die) to a power source, or other components of the display system, or the printed circuit board, or other components of the printed circuit board (or components electrically connected to the printed circuit board), or combinations thereof, may vary.

[0037] In some embodiments of the present disclosure, a controller (e.g., a tile array controller, array controller, master controller, master controller chip, etc.) is used to broadcast or send data to all tiles, or to broadcast or send data to all tiles or at least some of each tile. Each tile (or at least some of each tile) knows which portion of data it should hold based on its (i.e., the tile's) address, or based on how the tile's address pins are tied, for example. In some embodiments of the present disclosure, the controller (e.g., an array controller) sends data to the first tile, which is then streamed or sent to the next tile in the tile array. In some embodiments of the present disclosure, as shown in FIG. 6, each tile identifies and extracts data destined for that tile according to information in a header associated with data sent from the controller (e.g., an array controller, master controller, master controller chip, etc.). In some embodiments of the present disclosure, each tile may receive data (e.g., data represented as a voltage waveform or pulses) according to the address of the tile identified in the address bits of the data received in the array from the controller (e.g., an array controller, master controller, master controller chip, etc.). For example, in one embodiment of the present disclosure, each of the through silicon vias labeled A0-A5 identifies a location within an LED array or master pixel array and is electrically connected to a pixel or master pixel or LED within the LED array or master light emitting element array or master pixel array.

[0038] In one embodiment of the present disclosure, each tile is embedded in a tile array and electrically interconnected (e.g., by wire lines) via a serial bus comprised of, for example, data signals and possibly a clock signal, as shown in Figure 6. In one embodiment of the present disclosure, a controller (such as an array controller, a master controller, or a master controller chip) converts input image or video data in one format, for example, a standard format (such as MIPI DSI), into a custom serial format that the tiles can process, as shown in Figure 6.

[0039] The first or left side of Figure 6 shows the tile array, and the second or right side of the tile (the side where the arrow is pointing) shows that the array is made up of a number of tiles that are connected in series and controlled by a controller (such as an array controller, master controller, or master controller chip) that is coupled to at least one of each tile in the series or number of tiles.

[0040] In some embodiments of the present disclosure, the custom format is determined according to an embodiment that allows data to be distributed to all tiles and allows each tile to easily retrieve its own portion of the data. In some embodiments of the present disclosure, as described in FIG. 5, each tile has a location in the array and stores and / or displays data identified for that tile. The tile then knows or knows its address and how the data on the serial data input is arranged as it travels along the bus that is associated with its address or its geographic location in the array or a portion of the array (i.e., the entire array or at least a portion of the array). In some embodiments of the present disclosure, the tile ignores data on the serial bus that is not associated with the address of that tile.

[0041] In one embodiment of the present disclosure, a tapped transmission line having a termination at one end has multiple transmission line segments, and each transmission line segment (i.e., a transmission line segment between two tiles in series) is tuned by adjusting its width according to an embodiment of a transmission line matching method (i.e., a method of providing a transmission path free of reflections and other impediments and matching the impedance between the transmission line and at least one of the tiles to which it is electrically connected and other components (e.g., electrical components), which, when combined with the input capacitance of the data input or data input pin connections of each of the tiles, provides a controlled transmission line impedance).

[0042] In some embodiments of the present disclosure, for example, new data is arriving at the tile from a source of image or video data while the previous image or video frame data is being displayed, and new or next frame data can be sent over the entire duration of the video frame (i.e., the frame being displayed), thereby reducing the required data rate. For example, as shown in Figure 1, an array (e.g., an array of master pixels or master light emitting elements) in one embodiment of the present disclosure provides, for example, 220,000 pixels with 660,000 sub-light emitting elements (e.g., red, green, blue LED, etc. subpixels), each of which requires 8 bits of data to define its brightness. In some embodiments of the present disclosure, the serial data rate required to accommodate the embodiment shown in Figure 1 is 158.4 Mb / s with a refresh rate of 60 Hz.

[0043] FIG. 7 illustrates an embodiment of a backplane circuit element in an embodiment of the present disclosure, showing an active die (e.g., silicon die or tile backplane) circuit element as an example. In an embodiment of the present disclosure, (1) the active die (e.g., backplane or backplane die) circuit element of the tile has or is connected to a receiver, logic circuit element, algorithm or software algorithm, or module for DIN (i.e., data input / signal) and CLK input / signal (e.g., serial data and clock voltage input), to decode the received serial data at the receiving logic circuit or circuit element or block, and (2) the active die (e.g., backplane or backplane die) circuit element of the tile determines when to load such serial data into the array of pixel circuit elements and when to update the pixels that display the loaded data. In an embodiment of the present disclosure, each pixel circuit (as shown in FIG. 7) is included in the active die (e.g., backplane, backplane die or silicon die) circuit element, and each pixel circuit includes both a receiving storage device and an active storage device (e.g., a memory device). It can be understood by one skilled in the art that each pixel circuit can use any modulation method to drive the pixel circuit. The pixel structure in an embodiment of the present disclosure is further illustrated in FIG.

[0044] The tile controller logic element and / or tile controller device extracts data from the serial data stream (e.g., represented as a voltage waveform) sent over the serial bus to the tile, places the data on the DATA bus for the column of the pixel array to which it is to be written, and then loads the data into the master pixel using a ROW-WRITE strobe.

[0045] The tile controller also generates LOAD output control voltages to all master pixels or master light emitting elements in a tile (or at least a subset of the tile) and outputs Time Varying Values ​​(TVVs) to the TVV bus, as described in more detail in Figure 8. The LOAD output control voltages control the transfer of data from the receive memory to the active memory.

[0046] The tile control logic / circuitry / software / device further comprises a time-varying value (TVV) generator that creates the varying digital pattern for use with the pixels. In one embodiment of the present disclosure, the bias control circuitry / software / device includes a brightness control register that provides a digital value to a DAC, and a current DAC that converts the register value to a current. The current is then converted to a voltage suitable for biasing a current source electrically coupled to the individual pixels or pixel circuitry electrically coupled to the pixels.

[0047] In some embodiments of the present disclosure, a configuration (Config) register can be written to or from data extracted from the input serial data received by the deserializer and can be used to control bias currents set by bias control circuitry or devices. In some embodiments of the present disclosure, the Config register may and can store information about the number of X and Y pixels in a tiled display (i.e., the number of pixels in each row and the number of pixels in each column) and the activity state of the tile (e.g., sleep or wake).

[0048] As shown in FIG. 8, in one embodiment of the present disclosure, each subpixel (one subpixel of a master pixel or a set of three subpixels per master light emitting element) includes a light emitting element (e.g., an LED, micro LED, OLED, or micro LED device or component). The light emitting element is electrically connected to a memory element (e.g., two sets of memory elements), a logic function circuit element, a final latch, and a current driver. The logic function circuit element has an output that controls a latch (e.g., a final latch) electrically coupled to it. The current driver provides a modulated current to the LED. Those skilled in the art will appreciate that the number of memory elements, latches, and current drivers may vary.

[0049] In one embodiment of the present disclosure, a receiving storage device (such as a memory device or a receiving pixel memory device) is loaded with image data or video data (such as image or video grayscale data) from a tile controller. The tile controller places or transmits the data to be written to the tile, extracted from the serial data stream by the deserializer and decoder, onto the data bus of the column containing the pixel or master pixel to be written. The tile controller then outputs a ROW-WRITE signal for the row of pixels to be written. It will be appreciated by those skilled in the art that other row-column scanning methods can be used to control the ROW-WRITE operation.

[0050] In some embodiments of the present disclosure, the tile controller then outputs a LOAD output voltage or signal that initiates a data transfer from the receiving storage device (such as a memory device or receiving storage memory device) to the active storage device (such as a memory or active pixel memory device). In some embodiments of the present disclosure, a display cycle then begins. During this cycle, the tile controller provides a changing value or voltage on a time varying value (TVV) bus. This changing value or voltage is combined with a value (if software) or a value represented by a voltage in an active storage device such as a memory by pixel logic hardware or software or a pixel logic hardware device or means or software function, algorithm or module to generate a time varying voltage, such as a single bit voltage, voltage pulse or signal used to modulate a current. In some embodiments of the present disclosure, each time the time varying value bus is changed by the tile controller, a COMPUTE signal or output generated by a counter in the tile controller is asserted or output to a logic function circuit element or latch or both to cause the computation of a single bit output or signal and latch it in a final latch. The output of the final latch directly controls the on / off state of the current source. Modulation by pixel logic hardware or software can result in a variety of digital patterns, e.g., PWM or binary weighted pulse width, that are used to vary the brightness of each pixel according to the data loaded into a storage device (e.g., memory).

[0051] In some embodiments of the present disclosure, the serial data stream from the tile array controller or master controller to the tiles is formatted into frames that correspond in duration and frequency to the refresh rate of the display. In some embodiments of the present disclosure, as shown in FIG. 9, each frame has a start-of-frame (SOF) marker that contains a unique pattern that the tile controller's decoding logic can use to reliably detect the start of a frame (i.e., in the data received by the tile). The start-of-frame marker is followed by header information that describes the content of the video data. The video data content is information about the number of pixels per row in the configured display, such as the number of words expected in the data stream and the number of bits in each word. It also includes information including global (i.e., for the entire pixel array or a given portion of it) register updates, such as brightness control and sleep / wake status.

[0052] In some embodiments of the present disclosure, the serial stream of data sent from the tile controller or display controller to the tiles may be encoded, for example with 8b / 10b or 8b / 9b encoding, to provide unique symbols for robust transmission and reception, error detection, frame start and other control purposes (such as tile power state control), etc. Each tile stores its own individual data by using its address to index the received pixel data and identify the start and end of the data intended for that tile.

[0053] In accordance with some embodiments of the present disclosure, a display device includes a light emitting die and a backplane device coupled to the light emitting die, the light emitting die including at least one light emitting element that is coupled to, formed on, or integrated with a light emitting element substrate, the backplane device including a backplane substrate and pixel circuitry that is embedded in, integrated with, formed on, or coupled with the backplane substrate, the pixel circuitry including a pixel logic circuitry and an input / output logic circuitry.

[0054] According to some embodiments, the pixel circuit element comprises a drive circuit element. According to some embodiments, the at least one light emitting element comprises three light emitting elements. The light emitting elements are LEDs in some embodiments and micro LEDs in other embodiments. According to some embodiments, the pixel circuit element is electrically coupled to the at least one light emitting element, and the pixel circuit element drives the at least one light emitting element. According to some embodiments, the pixel circuit element is electrically coupled to the at least one light emitting element by a conductive element, and the pixel circuit element drives the at least one light emitting element.

[0055] According to some embodiments, the backplane device is fabricated from materials including silicon or other semiconductors in which transistors can be formed. According to some embodiments, the light emitting elements have conductive portions, and the pixel circuit elements include conductive portions for electrically coupling the light emitting elements to their respective pixel circuits. In some embodiments, the backplane device includes through silicon vias (TSVs), and a top side of the backplane device is connected to a back side of the backplane device by conductive materials or devices at the ends of the TSVs. According to some embodiments, the printed circuit board is electrically coupled to the backplane device through conductive elements that couple the printed circuit board (PCB) and the backplane device with the TSVs. According to some embodiments, the at least three light emitting elements form a first master pixel. In some embodiments, the display device further includes a second master pixel, and the second master pixel is electrically coupled to the first master pixel through an electrically conductive component or wire line. According to some embodiments, the first master pixel and the second master pixel form a tile.

[0056] According to some embodiments, a display device includes a plurality of tiles, each tile including a light emitting die. The light emitting die includes at least one light emitting element that is coupled to, formed on, or integrated with a light emitting element substrate. A backplane device is coupled to the light emitting die. The backplane device includes a backplane substrate and pixel circuitry, the pixel circuitry being embedded in, integrated with, formed on, or coupled with the backplane substrate. The pixel circuitry includes pixel logic circuitry, input / output logic circuitry, and a printed circuit board (PCB). The plurality of tiles are electrically coupled via the circuitry embedded in, integrated with, formed on, or coupled with the backplane substrate and via the circuitry embedded in, integrated with, formed on, or coupled with the printed circuit board.

[0057] In some embodiments, the pixel logic circuitry is located, embedded, integrated, formed, or coupled to a first strip region of the backplane substrate, and the input / output logic circuitry is located, embedded, integrated, formed, or coupled to a second strip region of the backplane substrate in some embodiments.

[0058] According to some embodiments, a display system includes a tile controller that controls operation of each tile or a plurality of tiles in an array and is provided on or integrated with an operating die of each of the plurality of tiles, each tile of the plurality of tiles having a tile address, a master controller that is coupled to at least one tile of the plurality of tiles or tile array, the master controller transmits data to the tile to which it is coupled, the tile controller identifies tile data from the data received from the master controller, the tile data being a subset of the data transmitted from the master controller, and the tile controller associated with the tile address stores the tile data in a memory component within the tile or associated with the tile.

[0059] According to some embodiments, data transmitted from the master controller includes the tile address in a header of the data transmitted from the master controller. According to some embodiments, the master controller receives data from the first device in a first format, and the master controller converts the data to a second format, the second format being suitable or readable or processable by the tile or a tile controller associated with the tile.

[0060] According to some embodiments, the first device is a device that generates or outputs image or image data. According to some embodiments, the tiles of the plurality of tiles or tile array are electrically connected in series. According to some embodiments, image or video data is sent to the tiles for display in a next frame while image or video data for a current frame is displayed in the tiles. According to some embodiments, each tile comprises a light emitting element, and each light emitting element is coupled to a first storage device and a second storage device.

[0061] According to some embodiments, the display system may further comprise a logic function circuit element electrically coupled to the logic function circuit element and the latch, the logic function circuit element performing an arithmetic or Boolean logic function, such as an equality function or a comparison function, and generating an output that is received by the latch to which the logic function circuit element is coupled, the latch storing the output of the logic function circuit element; a current drive circuit or component electrically coupled to the light-emitting element, the current drive circuit or component providing a modulated current to the light-emitting element, the current drive circuit or component providing a modulated current to the light-emitting element in accordance with the output generated by the logic function circuit element.

[0062] According to some embodiments, the display system comprises a pixel array of pixel elements, each of the light emitting elements of the pixels of the pixel array or each of the light emitting elements of the master pixel being electrically coupled to a pixel circuit element, the pixel circuit element comprising a first storage or receiving pixel memory device and a second storage or active pixel memory device electrically coupled to the receiving pixel memory device. A logic function circuit element is coupled to the active pixel memory device. A latch is coupled to the logic function circuit element, and a current driver is coupled to the latch, the current driver drives the operation of each of the pixels of the pixel array or each of the master pixels of the pixel array. The tile controller comprises a deserializer that receives input data from the receiving storage device. A decoder is electrically coupled to the deserializer, the deserializer extracts image or video data from a data stream received at the deserializer of the tile controller according to or if there is an address of the tile in the data stream, and the deserializer controls the writing of the extracted data to the first storage or receiving pixel memory device.

[0063] According to some embodiments, the decoder decodes the extracted data after extracting it from the data stream, and the tile controller instructs the control logic block to write the extracted and then decoded data for placement on a data bus that corresponds or is associated with a column that includes or includes the light emitting element, pixel, master pixel, LED, or collection of LEDs that has been identified as a destination for the extracted and then decoded data. According to some embodiments, the tile controller outputs a ROW / WRITE output or signal to a row of the light emitting element, pixel, master pixel, LED, or collection of LEDs that has been identified to receive the extracted and then decoded data.

[0064] According to some embodiments, the display system further comprises a control logic element of a tile controller that outputs a LOAD output voltage or signal that initiates data transfer from the receiving storage device to the second or active storage device. According to some embodiments, the display system further comprises a time-varying value (TVV) generator, where after the data is transferred to the second or active storage device a display cycle begins and during the display cycle the time-varying value generator provides a varying value or voltage to a time-varying value (TVV) bus that is combined with the value or voltage of the second or active storage device by a pixel logic circuit or pixel logic device to generate a time-varying voltage used to modulate a current driver circuit or device electrically coupled to the master pixel or master light emitting element.

[0065] According to some embodiments, a COMPUTE signal or output generated by a counter in the time change value generator of the tile controller is sent to a logic function circuit element or a latch or both in the pixel array each time the time change value bus by the time change value generator changes, and the logic function circuit element calculates or performs a Boolean logic function and generates a single bit output or signal to output to the latch, the output of which directly controls the on / off state of a current source which in turn controls the on / off state of a pixel, master pixel, LED, or collection of LEDs.

[0066] The above embodiments are merely exemplary illustrations of implementations set forth for a clear understanding of the principles. Variations, modifications, and combinations of the above embodiments are possible without departing from the scope of the claims. All such variations, modifications, and combinations are encompassed herein by the scope of the disclosure and the claims.

Claims

1. 1. A display device, comprising: A light emitting die, a light emitting die including at least one light emitting element bonded to, formed with, or integral with a light emitting element substrate; a backplane device coupled to the light emitting die; Equipped with the backplane device includes a backplane substrate and pixel circuitry; the pixel circuitry is at least one of embedded in, integrated with, formed in, or coupled to the backplane substrate; the pixel circuitry comprises a pixel logic circuitry and an input / output logic circuitry; Display device.

2. 2. The display device of claim 1, the pixel circuitry comprises drive circuitry; Display device.

3. 2. The display device of claim 1, The at least one light emitting element comprises three light emitting elements. Display device.

4. 2. The display device of claim 1, The light emitting element is an LED. Display device.

5. 5. A display device according to claim 4, The LED is a micro LED. Display device.

6. 2. The display device of claim 1, the pixel circuit element is electrically coupled to the at least one light emitting element; the pixel circuitry drives the at least one light emitting element; Display device.

7. 2. The display device of claim 1, the pixel circuit element is electrically coupled to the at least one light emitting element by a conductive element; the pixel circuitry drives the at least one light emitting element; Display device.

8. 2. The display device of claim 1, the backplane device is fabricated from a material including silicon or other semiconductors in which transistors can be formed; Display device.

9. 2. The display device of claim 1, The light emitting element has a conductive portion, the pixel circuit elements comprising conductive portions for electrically coupling the light emitting elements to respective pixel circuits; Display device.

10. 2. The display device of claim 1, the backplane device having through silicon vias (TSVs); a top side of the backplane device is connected to a back side of the backplane device by conductive material or devices at the ends of through silicon vias; Display device.

11. 11. A display device according to claim 10, a printed circuit board (PCB) electrically coupled to the backplane device via a conductive element coupling the PCB and the backplane device with the through silicon vias. Display device.

12. 4. A display device according to claim 3, The at least three light emitting elements form a first master pixel. Display device.

13. 13. A display device according to claim 12, A second master pixel is further provided, the second master pixel is electrically coupled to the first master pixel via an electrically conductive component or wire; Display device.

14. 14. A display device according to claim 13, the first master pixel and the second master pixel form a tile; Display device.

15. 1. A display device, comprising: With multiple tiles, One tile is A light emitting die, a light emitting die including at least one light emitting element bonded to, formed with, or integral with a light emitting element substrate; a backplane device coupled to the light emitting die, The backplane device includes a backplane substrate and pixel circuitry; the pixel circuitry is at least one of embedded in, integrated with, formed in, or coupled to the backplane substrate; a backplane device, the pixel circuitry comprising pixel logic circuitry and input / output logic circuitry; 1. A printed circuit board (PCB), comprising: The plurality of tiles include: via circuitry embedded in, integrated with, formed on, or coupled to the backplane substrate; and and a circuit element that is embedded in, integrated with, formed on, or coupled to the printed circuit board; a printed circuit board electrically coupled to the Equipped with Display device.

16. 16. A display device according to claim 15, the pixel logic circuit element is at least one of disposed on, embedded in, integrated with, formed in, or coupled to a first strip region of the backplane substrate; Display device.

17. 16. A display device according to claim 15, an input / output logic circuit element is at least one of disposed on, embedded in, integrated with, formed in, or coupled to a second strip region of the backplane substrate; Display device.

18. 1. A display system comprising:

1. A tile controller, comprising: the tile controller controls operation of each tile or a plurality of tiles in the array and is provided on or integrated with an operating die of each of the plurality of tiles; each tile of the plurality of tiles has a tile address; A tile controller; A master controller, a master controller coupled to at least one tile of the plurality of tiles or tile array; Equipped with The master controller transmits data to the tiles to which it is associated; The tile controller identifies tile data from the data received from the master controller; the tile data being a subset of the data transmitted from the master controller; the tile controller associated with the tile address stores the tile data in a memory component within the tile or associated with the tile; Display system.

19. 20. A display system according to claim 18, comprising: The data transmitted from the master controller includes a tile address in a header of the data transmitted from the master controller. Display system.

20. 20. A display system according to claim 19, comprising: the master controller receiving data from a first device of a first type; The master controller converts the data into a second format; the second format being suitable for or readable or processable by the tile or by the tile controller associated with the tile; Display system.

21. 21. A display system according to claim 20, comprising: the first device is a device that generates or outputs images or image data; Display system.

22. 20. A display system according to claim 18, comprising: the tiles of the plurality of tiles or tile array being electrically connected in series; Display system.

23. 23. A display system as claimed in claim 22, comprising: image or video data is transmitted to a tile for display in a next frame while image or video data for a current frame is displayed in said tile; Display system.

24. 20. A display system according to claim 18, comprising: Each tile includes a light emitting element; Each of the light emitting elements is coupled to a first storage device and a second storage device. Display system.

25. 24. A display system according to claim 23, comprising: a logic function circuit element electrically coupled to the logic function circuit element and to the latch; the logic function circuit element performs an arithmetic or Boolean logic function, such as an equality function or a comparison function, to generate an output that is received by a latch to which the logic function circuit element is coupled; the latch stores the output of the logic function circuit element; The latch is also electrically coupled to a current driver circuit or component; the current driver circuit or component is electrically coupled to the light emitting device; the current driver circuit or component supplies a modulated current to the light emitting element; The current driver circuit or component may provide the light-emitting element with a current modulated according to the output generated by the logic function circuit element. Display system.

26. 1. A display system comprising: a pixel array of pixel elements; Tile Controller Equipped with Each light emitting element of a pixel of the pixel array or each light emitting element of a master pixel is electrically coupled to a pixel circuit element; The pixel circuit element comprises: a first storage device or receiving pixel memory device; a second storage device or active pixel memory device electrically coupled to the receiving pixel memory device; a logic function circuit element coupled to the active pixel memory device; a latch coupled to the logic function circuit element; a current driver coupled to the latch for driving operation of each pixel of the pixel array or each master pixel of the pixel array; It has The tile controller: a deserializer for receiving input data from the receiving storage device; Decoder and It is equipped with a pre-decoder electrically coupled to the deserializer; the deserializer extracts image or video data from the data stream received at the deserializer of the tile controller according to or if there is an address of a tile in the data stream; the deserializer controls the writing of the extracted data to the first storage device or a receiving pixel memory device; Display system.

27. 27. A display system according to claim 26, comprising: the decoder decodes the extracted data after extracting it from the data stream; the tile controller instructs a control logic block to write the extracted and subsequently decoded data for placement on a data bus; the data bus corresponds to or is associated with a column that includes or includes a light emitting element, pixel, master pixel, LED, or a group of LEDs; the light emitting element, the pixel, the master pixel, the LED, or the collection of LEDs identified as a destination for writing the extracted and subsequently decoded data; Display system.

28. 28. A display system as claimed in claim 27, comprising: the tile controller outputs a ROW / WRITE output or signal to the row of the light emitting element, the pixel, the master pixel, the LED, or the collection of LEDs; the light emitting element, the pixel, the master pixel, the LED, or the collection of LEDs that have been identified to receive the extracted and subsequently decoded data; Display system.

29. 29. A display system according to claim 28, comprising: a control logic circuit element of the tile controller; The control logic circuitry of the tile controller outputs a LOAD output voltage or signal that initiates a data transfer from the receiving storage device to the second or active storage device. Display system.

30. 30. A display system as claimed in claim 29, comprising: A time-varying value (TVV) generator is further provided; a display cycle begins after the data is transferred to the second or active storage device; During the display cycle, the time change value generator: providing a changing value or voltage, combined with the value or voltage of said second or active storage device by a pixel logic circuit or pixel logic device, on a time-varying value (TVV) bus; generating a time-varying voltage that is used to modulate a current driver circuit or device electrically coupled to the master pixel or master light emitting element; Display system.

31. 31. A display system according to claim 30, comprising: a COMPUTE signal or output generated by a counter in the time change value generator of the tile controller is sent to logic function circuit elements or latches or both of the pixel array every time the time change value bus is changed by the time change value generator; the logic function circuitry operates or performs a Boolean logic function to generate a single bit output or signal to be output to a latch; the output of the latch directly controls the on / off state of a current source, which in turn controls the on / off state of the pixel, the master pixel, the LED, or the collection of LEDs; Display system.

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