Display device

Abstract

To provide a display device which utilizes lamination of a plurality of light emission parts (or light emission structure) in order to achieve the improved efficiency and life property, and a manufacturing method of the same.SOLUTION: A display device includes: a substrate 110 having a plurality of sub-pixels defined thereon; a bank 116 disposed between the plurality of sub-pixels; at least one trench pattern 114 disposed between the plurality of sub-pixels and from which a thickness of an upper surface of the bank 116 is partially removed; a buffer layer 155 on the bank 116, the buffer layer being deposited to cover an inner surface of the trench pattern 114 by an initiated chemical vapor deposition (iCVD) method; and an encapsulation layer 150 disposed on the buffer layer 115. Therefore, it is possible to improve reliability by preventing film formation defects of the encapsulation layer 150 in the trench, and to improve display quality by preventing display quality defects such as light and dark spots and bright spots. There is also provided a manufacturing method of the display device.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a display device and a manufacturing method thereof, and more particularly to a display device and a manufacturing method thereof that can improve color mixing of light emitted from a plurality of light emitting elements. [Background technology]

[0002] As we enter a full-fledged information age, the field of display devices that visually display electrical information signals is rapidly developing, and research is ongoing to develop various display devices with improved performance, such as thinner, lighter, and less power consumption.

[0003] Among these various display devices, the OLED display is a self-emitting display device that does not require a separate light source unlike the LCD device and can be manufactured in a lightweight and thin form. In addition, the OLED display is advantageous in terms of power consumption due to low voltage operation, and is also excellent in color realization, response speed, viewing angle, and light-dark contrast ratio, and is being applied as a next-generation display. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that employ a multi-stack structure that uses stacking of multiple light emitting parts (or light emitting structures) to realize improved efficiency and life characteristics.

[0005] Another object of the present invention is to provide a display device and a manufacturing method thereof, which can reduce and / or minimize leakage current when a multi-stack structure display device is driven by using a trench structure.

[0006] It is still another object of the present invention to provide a display device and a manufacturing method thereof in which defective formation of a sealing layer in a trench is prevented to improve reliability and display quality.

[0007] The object of the present invention is not limited to the above-mentioned objects, and other objects not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0008] A display device according to an embodiment of the present invention may include a substrate having a plurality of sub-pixels defined thereon, a bank disposed between the plurality of sub-pixels, at least one trench pattern disposed between the plurality of sub-pixels and having a portion of an upper surface thickness of the bank removed, a buffer layer deposited on the bank by an initiated chemical vapor deposition (iCVD) method so as to cover an inner surface of the trench pattern, and a sealing layer disposed on the buffer layer.

[0009] According to another embodiment of the present invention, a display device may include a substrate having a plurality of subpixels defined thereon, a bank disposed between the plurality of subpixels, at least one trench pattern disposed between the plurality of subpixels and having a portion of an upper surface thickness of the bank removed, at least one spacer disposed on the bank between the plurality of subpixels, a buffer layer deposited on an inner surface of the trench pattern and on the bank and the spacer along an internal shape of the trench pattern and a curvature of the spacer by an iCVD method, and a sealing layer disposed on the buffer layer.

[0010] A method for manufacturing a display device according to one embodiment of the present invention may include providing a substrate on which a plurality of sub-pixels are defined; disposing a bank between the plurality of sub-pixels; disposing at least one trench pattern between the plurality of sub-pixels, with a portion of an upper surface thickness of the bank removed; depositing a buffer layer on the bank by an initiated chemical vapor deposition (iCVD) method to cover an inner surface of the trench pattern; and disposing an encapsulation layer on the buffer layer.

[0011] A method for manufacturing a display device according to another embodiment of the present invention includes providing a substrate on which a plurality of sub-pixels are defined; disposing a bank between the plurality of sub-pixels; disposing at least one trench pattern between the plurality of sub-pixels, with a portion of an upper surface thickness of the bank removed; disposing at least one spacer on the bank between the plurality of sub-pixels; depositing a buffer layer on an inner surface of the trench pattern and on the bank and the spacer according to an internal shape of the trench pattern and a curvature of the spacer by an iCVD method; and disposing an encapsulation layer on the buffer layer.

[0012] Further details of the embodiments are included in the detailed description and the drawings.

[0013] The present invention can exhibit high efficiency by applying a light emitting element having a multi-stack structure, and can enable low current driving, thereby improving the life span of the light emitting element.

[0014] The present invention can improve current leakage through a common layer of multiple light emitting devices by applying a trench structure.

[0015] The present invention improves reliability by forming a buffer layer by a vapor deposition method before forming the sealing layer, thereby preventing poor formation of the sealing layer in the trench, and improves display quality by preventing display quality defects such as bright and dark spots and bright spots.

[0016] The present invention can stably ensure a disconnected structure of the organic layer, and can improve yield and processability.

[0017] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief description of the drawings]

[0018] [Figure 1] 1 is a schematic configuration diagram of a display device according to a first embodiment of the present invention. [Diagram 2]2 is a circuit diagram of a sub-pixel of the display device of FIG. 1. [Diagram 3] 2 is a plan view showing one pixel structure of the display device of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Diagram 5] 2 is a cross-sectional view showing an outer casing of the display device of FIG. 1. [Figure 6] 1 is a table showing process conditions for an iCVD buffer layer. [Figure 7a] 1 is a photograph showing the surface characteristics of an iCVD buffer layer. [Figure 7b] 1 is a photograph showing the surface characteristics of an iCVD buffer layer. [Figure 7c] 1 is a photograph showing the surface characteristics of an iCVD buffer layer. [Figure 7d] 1 is a photograph showing the surface characteristics of an iCVD buffer layer. [Figure 8a] 11 is another photograph showing the surface characteristics of the iCVD buffer layer. [Figure 8b] 11 is another photograph showing the surface characteristics of the iCVD buffer layer. [Figure 8c] 11 is another photograph showing the surface characteristics of the iCVD buffer layer. [Figure 8d] 11 is another photograph showing the surface characteristics of the iCVD buffer layer. [Figure 9] 11 is a photograph showing a state in which a sealing layer is deposited on a foreign object. [Figure 10a] 1 is a photograph showing the state of an iCVD buffer layer deposited on top of a foreign object. [Figure 10b] 1 is a photograph showing the state of an iCVD buffer layer deposited on top of a foreign object. [Figure 10c] 1 is a photograph showing the state of an iCVD buffer layer deposited on top of a foreign object. [Figure 10d] 1 is a photograph showing the state of an iCVD buffer layer deposited on top of a foreign object. [Figure 11] FIG. 11 is a cross-sectional view of a portion of a display device according to a second embodiment of the present invention. [Figure 12]12 is a cross-sectional view showing an outer casing of the display device of FIG. 11. [Figure 13] FIG. 11 is a cross-sectional view of a portion of a display device according to a third embodiment of the present invention. [Figure 14] FIG. 11 is a cross-sectional view of a portion of a display device according to a fourth embodiment of the present invention. [Figure 15] FIG. 11 is a cross-sectional view of a portion of a display device according to a fifth embodiment of the present invention. [Figure 16] FIG. 13 is a cross-sectional view of a portion of a display device according to a sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The advantages and features of the present invention, and the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the present invention of the scope of the invention. The present invention is only defined by the scope of the claims.

[0020] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the illustrated matters. The same reference symbols refer to the same components throughout the specification. In addition, when describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in the present invention, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0021] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0022] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0023] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0024] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of the present invention.

[0025] Like reference numbers refer to like elements throughout the specification.

[0026] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0027] The respective features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0028] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] FIG. 1 is a schematic diagram showing the configuration of a display device according to a first embodiment of the present invention.

[0030] Referring to FIG. 1, a display device 100 may include a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0031] The gate driver GD can supply a plurality of scan signals to the plurality of scan lines SL in response to a plurality of gate control signals GCS provided by the timing controller TC. The plurality of scan signals can include a first scan signal SCAN1 and a second scan signal SCAN2.

[0032] The data driver DD can convert the image data RGB input from the timing controller TC into a data signal Vdata using a reference gamma voltage according to a plurality of data control signals DCS provided by the timing controller TC, and can supply the converted data signal Vdata to a plurality of data lines DL.

[0033] The timing controller TC aligns externally input image data RGB and supplies the aligned data to the data driver DD, and generates a gate control signal GCS and a data control signal DCS using an externally input synchronous signal SYNC.

[0034] FIG. 2 is a circuit diagram of a sub-pixel of the display device of FIG.

[0035] Referring to FIG. 2, a pixel circuit of each of the sub-pixels SP may include first to sixth transistors T1, T2, T3, T4, T5, and T6 and a capacitor Cst.

[0036] The first transistor T1 may be connected to a second scan line and may be controlled by a second scan signal SCAN2 provided through the second scan line. The first transistor T1 may be electrically connected between a data line providing a data signal Vdata and a capacitor Cst.

[0037] The second transistor T2 may be electrically connected between a high potential power line to which a high potential power signal EVDD is supplied and the fifth transistor T5, and a gate electrode of the second transistor T2 may be electrically connected to the capacitor Cst.

[0038] In addition, the third transistor T3 can be controlled by a first scan signal SCAN1 supplied through a first scan line, and can compensate for the threshold voltage of the second transistor T2, and the third transistor T3 can be referred to as a compensation transistor.

[0039] The fourth transistor T4 may be electrically connected to the capacitor Cst and an initialization signal line to which an initialization signal Vini is supplied, and may be controlled by a light emitting control signal EM supplied through a light emitting control signal line.

[0040] The fifth transistor T5 is electrically connected between the second transistor T2 and the light emitting element 120 and can be controlled by a light emitting control signal EM provided through a light emitting control signal line.

[0041] The sixth transistor T6 is electrically connected between an initialization signal line to which an initialization signal Vini is supplied and the anode of the light emitting element 120, and can be controlled by a first scan signal SCAN1 supplied through a first scan line.

[0042] In the above, an example has been described in which the pixel circuit of each of the multiple sub-pixels SP includes first to sixth transistors T1, T2, T3, T4, T5, and T6 and a capacitor Cst, but as mentioned above, the present invention is not limited to this.

[0043] The pixel structure of the display device 100 according to the first embodiment of the present invention will be described in more detail below with reference to FIGS.

[0044] FIG. 3 is a plan view showing one pixel structure of the display device of FIG.

[0045] FIG. 4 is a cross-sectional view taken along line AA' in FIG.

[0046] FIG. 5 is a cross-sectional view showing an outer casing of the display device of FIG.

[0047] FIG. 4 shows an example of a cross section of one sub-pixel in the pixel structure of FIG.

[0048] Referring to Figures 3 to 5, the display device 100 of the first embodiment of the present invention may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a planarization layer 115, a bank 116, a high potential power supply wiring, a scan wiring, a data wiring, an initialization signal wiring, a light emission control signal wiring, a fifth transistor T5, a light emitting element 120, a spacer 160, a buffer layer 155 and an encapsulation layer 150.

[0049] 3, for ease of explanation, only the anode 121 and the bank 116 are shown among the components of the light emitting element 120. The bank 116 may be disposed in the remaining region excluding the region exposed by the opening OP and the trench pattern 140. Also, for ease of explanation, in FIG. 4, only the fifth transistor T5 is shown among the plurality of transistors T1, T2, T3, T4, T5, T6 and the capacitor Cst of the pixel circuit of the sub-pixel SP.

[0050] 3, the sub-pixels SP are individual units that emit light, and a light-emitting element 120 may be disposed in each of the sub-pixels SP. The sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light of different hues. For example, the first sub-pixel SP1 may be a blue sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a red sub-pixel. However, the present invention is not limited thereto.

[0051] The first sub-pixels SP1 may be arranged in a plurality of columns. That is, the first sub-pixels SP1 may be arranged in the same column. The second sub-pixels SP2 and the third sub-pixels SP3 may be arranged between the columns in which the first sub-pixels SP1 are arranged. For example, the first sub-pixels SP1 may be arranged in one column, and the second sub-pixels SP2 and the third sub-pixels SP3 may be arranged in an adjacent column. The second sub-pixels SP2 and the third sub-pixels SP3 may be arranged alternately in the same column. However, the present invention is not limited thereto.

[0052] In addition, although the present invention has been described in terms of the plurality of sub-pixels SP including the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the arrangement, number, and color combination of the plurality of sub-pixels SP may be variously changed according to design, and are not limited thereto.

[0053] 2 to 5, high potential power supply wiring PL extending in the column direction may be arranged between the sub-pixels SP. The high potential power supply wiring PL is a wiring that transmits a high potential power supply signal EVDD to each of the sub-pixels SP. Each of the high potential power supply wiring PL may be arranged between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. However, the present invention is not limited to this.

[0054] A plurality of data lines DL may be arranged extending in the same column direction as the plurality of high potential power supply lines PL. The plurality of data lines DL are lines that transmit a data signal Vdata to each of the plurality of sub-pixels SP. For example, each of the plurality of data lines DL may be arranged between the second sub-pixel SP2 and the high potential power supply line PL and between the third sub-pixel SP3 and the high potential power supply line PL. However, the present invention is not limited to this, and the plurality of data lines DL may be arranged between the plurality of high potential power supply lines PL and the first sub-pixel SP1.

[0055] In addition, a plurality of scan lines SL may be arranged extending in the row direction. The plurality of scan lines SL are lines that transmit scan signals SCAN1 and SCAN2 to the plurality of sub-pixels SP, respectively. The plurality of scan lines SL may include a first scan line and a second scan line. The first scan line may be arranged extending in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3, and the second scan line may be arranged extending in the row direction across the third sub-pixel SP3.

[0056] Furthermore, a plurality of initialization signal lines ISL extending in the row direction in the same manner as the plurality of scan lines SL may be arranged between the sub-pixels SP. The plurality of initialization signal lines ISL are lines that transmit an initialization signal Vini to each of the sub-pixels SP. Each of the plurality of initialization signal lines ISL may be arranged between the second sub-pixel SP2 and the third sub-pixel SP3. The plurality of initialization signal lines ISL may be arranged between the first scan line and the second scan line. However, the present invention is not limited to this.

[0057] A plurality of light emission control signal lines ESL may be arranged extending in the row direction in the same manner as the plurality of scan lines SL. The plurality of light emission control signal lines ESL are lines that transmit light emission control signals EM to the plurality of sub-pixels SP, respectively. The plurality of light emission control signal lines ESL may be arranged adjacent to the plurality of second scan lines. Furthermore, the plurality of light emission control signal lines ESL may be arranged extending in the row direction across the third sub-pixels SP3. The second scan lines may be arranged between the plurality of light emission control signal lines ESL and the plurality of initialization signal lines ISL.

[0058] The multiple wirings can also be classified into DC wirings that transmit DC signals and AC wirings that transmit AC signals. Of the multiple wirings, the high-potential power supply wiring PL and the initialization signal wiring ISL that transmit the high-potential power supply signal EVDD or the initialization signal Vini, which are DC signals, can be included in the DC wirings. Also, of the multiple wirings, the scan wiring SL and the data wiring DL that transmit the scan signals SCAN1, SCAN2, the data signal Vdata, etc., which are AC signals, can be included in the AC wirings.

[0059] A plurality of spacers 160 may be disposed between the plurality of sub-pixels SP. When forming the light-emitting element 120 in the plurality of sub-pixels SP, a fine metal mask (FMM) may be used as a deposition mask. At this time, the plurality of spacers 160 may be disposed to prevent damage that may occur due to contact with the deposition mask and to maintain a constant distance between the deposition mask and the substrate 110.

[0060] Also, a plurality of trench patterns 140 may be disposed between the plurality of sub-pixels SP. The plurality of trench patterns 140 may be formed by removing a portion of the upper thickness of the bank 116, but the present invention is not limited thereto, and the plurality of trench patterns 140 may be formed by removing the entire thickness of the bank 116. In FIG. 4, for example, a case where one trench pattern 140 is disposed between the plurality of sub-pixels SP is shown, but the present invention is not limited thereto.

[0061] The organic layer 122 and the cathode 123 between adjacent sub-pixels SP may be partially disconnected by the trench pattern 140. In FIG. 3, for example, the trench pattern 140 is divided into a plurality of parts so as to surround the sub-pixels SP, but the present invention is not limited thereto.

[0062] For example, the trench patterns 140 may include a first portion 141 and a second portion 142. The first portion 141 is a portion extending in the column direction between the sub-pixels SP. The first portion 141 may be a portion extending in the column direction between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. The first portion 141 may be divided into a plurality of portions in the column direction, but is not limited thereto. When the first portion 141 is divided into a plurality of portions, the resistance of the cathode 123 may be reduced, and the luminance deviation caused by the voltage drop phenomenon may be reduced.

[0063] At least a part of the first portion 141 may be disposed between a DC wiring and an AC wiring that extend in the column direction among the wirings. For example, the first portion 141 may extend in the column direction, and at least a part of the first portion 141 may be disposed between the high potential power supply wiring PL and the data wiring DL. However, the present invention is not limited to this, and at least a part of the first portion 141 may be overlapped with the high potential power supply wiring PL or the data wiring DL.

[0064] The second portion 142 is a portion extending in the row direction between the subpixels SP. The second portion 142 may be a portion extending in the row direction between the first subpixels SP1. In this case, the second portion 142 may extend in the row direction from the first portion 141, or may be arranged separately from the first portion 141. At least a part of the second portion 142 may overlap with a DC wiring or an AC wiring that extends in the row direction among the wirings. Meanwhile, the second portion 142 may also be arranged between the second subpixel SP2 and the third subpixel SP3.

[0065] Such a trench pattern 140 can reduce and / or minimize side leakage current occurring in a multi-stack structure, which will be described in more detail with reference to FIGS.

[0066] 3 to 5, a substrate 110 is a support member for supporting other components of the display device, and may be made of an insulating material.

[0067] For example, the substrate 110 may be made of glass, resin, etc. The substrate 110 may also be made of a polymer or plastic such as polyimide (PI), and may also be made of a material having flexibility.

[0068] The substrate 110 can be divided into a display area AA and a non-display area NA.

[0069] The display area AA is the area where the video is displayed.

[0070] In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be arranged. The plurality of sub-pixels SP are the smallest units constituting the display area AA, and a display element may be arranged in each of the plurality of sub-pixels SP, and the plurality of sub-pixels SP may constitute a pixel. For example, a light-emitting element 120 including an anode 121, an organic layer 122, and a cathode 123 may be arranged in each of the sub-pixels SP, but is not limited thereto. In addition, the circuit for driving the plurality of sub-pixels SP may include a driving element, wiring, etc. For example, the circuit may be composed of a thin film transistor T5, a storage capacitor, a gate wiring, a data wiring, etc., but is not limited thereto.

[0071] The non-display area NA is an area where no image is displayed.

[0072] Various wirings and circuits for driving the light emitting elements 120 in the display area AA may be arranged in the non-display area NA. Although not shown, for example, link wirings for transmitting signals to the sub-pixels SP and circuits in the display area AA or driving ICs such as a gate driver IC and a data driver IC may be arranged in the non-display area NA, but is not limited thereto.

[0073] A buffer layer 111 may be disposed on the substrate 110. The buffer layer 111 may reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of substrate 110 and the type of transistor, and is not limited to this.

[0074] A fifth transistor T5 may be disposed on the buffer layer 111.

[0075] The fifth transistor T5 may include an active layer ACT, a gate electrode GE, a source electrode SE and a drain electrode DE.

[0076] The active layer ACT may be made of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, polysilicon, etc. When the active layer ACT is made of an oxide semiconductor, the active layer ACT includes a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0077] A gate insulating layer 112 may be disposed on the active layer ACT.

[0078] The gate insulating layer 112 is an insulating layer for insulating the active layer ACT and the gate electrode GE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0079] A gate electrode GE may be disposed on the gate insulating layer 112 .

[0080] The gate electrode GE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0081] An interlayer insulating layer 113 may be disposed on the gate electrode GE.

[0082] Contact holes for connecting the source electrode SE and the drain electrode DE to the active layer ACT may be formed in the interlayer insulating layer 113. The interlayer insulating layer 113 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0083] A source electrode SE and a drain electrode DE may be disposed on the interlayer insulating layer 113. The source electrode SE and the drain electrode DE, which are disposed apart from each other, may be electrically connected to the active layer ACT. The source electrode SE and the drain electrode DE may be made of a conductive material, for example, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0084] A high-potential power supply line and a data line may be disposed on the interlayer insulating layer 113. The high-potential power supply line and the data line may be disposed in the same layer as the source electrode SE and the drain electrode DE and may be made of the same conductive material, but are not limited thereto. For example, the high-potential power supply line and the data line may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0085] A passivation layer 114 may be disposed on the high potential power wiring, the data wiring, the source electrode SE, and the drain electrode DE. The passivation layer 114 is an insulating layer for protecting the components below the passivation layer 114. For example, the passivation layer 114 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the passivation layer 114 may be omitted depending on the embodiment.

[0086] A planarization layer 115 may be disposed on the passivation layer 114. The planarization layer 115 is an insulating layer that flattens the upper surface of the substrate 110. The planarization layer 115 may be made of an organic material, such as, but not limited to, a single layer or multiple layers of polyimide or photo acrylic.

[0087] A plurality of light emitting elements 120 may be disposed in a plurality of sub-pixels SP on the planarization layer 115. The light emitting element 120 may include an anode 121, an organic layer 122, and a cathode 123. Meanwhile, the organic layer 122 may be composed of an emission layer disposed in the emission region and a common layer disposed on the front surface of the substrate 110 including the emission region, but is not limited thereto.

[0088] An anode 121 may be disposed on the planarization layer 115 .

[0089] The anode 121 is electrically connected to the fifth transistor and can receive a driving current of the pixel circuit. The anode 121 supplies holes to the light emitting layer and can be made of a conductive material with a high work function. The anode 121 can be made of a transparent conductive material such as, but not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0090] Meanwhile, the display device 100 may be implemented as a top emission or bottom emission type. In the case of the top emission type, a reflective layer made of a metal material with excellent reflection efficiency, for example, aluminum (Al) or silver (Ag) may be added to the lower part of the anode 121 so that light emitted from the emission layer is reflected by the anode 121 toward the upper direction, i.e., the cathode 123 side, by being directed toward the anode 121. On the other hand, in the case where the display device 100 is a bottom emission type, the anode 121 may be made of only a transparent conductive material. Hereinafter, it is assumed that the display device 100 according to the first embodiment of the present invention is a top emission type.

[0091] Meanwhile, at least one trench pattern 140 may be disposed between the plurality of sub-pixels SP.

[0092] The trench pattern 140 may be formed in the bank 116. That is, the trench pattern 140 may be formed by removing a portion of an upper thickness of the bank 116. In this case, although not shown, an undercut structure may be formed on at least one side of the inside of the trench pattern 140.

[0093] As discussed above, the light-emitting device 120 of the present invention can include an anode 121 , an organic layer 122 , and a cathode 123 .

[0094] The organic layer 122 can be disposed between the anode 121 and the cathode 123 .

[0095] The organic layer 122 is a region where light is emitted by recombination of electrons and holes supplied from the anode 121 and the cathode 123 .

[0096] The organic layer 122 according to the first embodiment of the present invention may include, but is not limited to, a light emitting layer disposed in each of the sub-pixels SP and a common layer disposed in common to the sub-pixels SP.

[0097] That is, in order to improve the quality and productivity of organic light emitting display devices, various structures have been proposed for improving the efficiency and life span of light emitting devices and reducing power consumption.

[0098] As a result, in addition to light emitting device structures that apply one stack, i.e., one light emitting unit, light emitting devices with tandem structures that utilize multiple stacks, i.e., stacking of multiple light emitting units, have been proposed to realize improved efficiency and life characteristics.

[0099] In such a tandem structure, i.e., a two-stack structure light-emitting device using a stack of a first light-emitting unit and a second light-emitting unit, a light-emitting region in which light emission occurs through recombination of electrons and holes is located in each of the first light-emitting unit and the second light-emitting unit, and the lights emitted from the first light-emitting layer of the first light-emitting unit and the second light-emitting layer of the second light-emitting unit respectively cause constructive interference, thereby providing higher brightness than a light-emitting device with a single stack structure.

[0100] In addition, the distance between the sub-pixels constituting one pixel in the light-emitting element becomes smaller as the resolution of the organic light-emitting display device increases. However, auxiliary organic layers such as a hole injection layer (EIL), a hole transport layer (HTL), a charge generation layer (CGL), an electron injection layer (EIL), an electron transport layer (ETL), etc., except for an emission layer (EML), are deposited to correspond to all of the sub-pixels using a common mask to form a common layer, and the emission layers in the sub-pixels, which each generate light of a different wavelength, can be deposited individually to correspond to each sub-pixel using a fine metal mask.

[0101] In the case of the light emitting device as described above, when a voltage is applied between the anode and the cathode, a lateral leakage current occurs in the horizontal direction of the light emitting device through the common layer formed in the light emitting device as described above, resulting in color mixing defects in which not only the sub-pixel required to emit light but also the adjacent undesired sub-pixels emit light.

[0102] The color mixing defect may be more severe in a light emitting device having a two-stack structure using a stack of a first light emitting unit and a second light emitting unit that utilize constructive interference of light, as compared to a light emitting device having a single stack structure.

[0103] Therefore, in the present invention, as shown in Figures 3 and 4, a plurality of trench patterns 140 are formed between a plurality of sub-pixels SP to partially disconnect the common layer and cathode 123 between adjacent sub-pixels SP, thereby reducing and / or minimizing leakage current when driving a display device with a multi-stack structure.

[0104] 3 to 5, a bank 116 may be disposed on the anode 121 and the planarization layer 115. The bank 116 is an insulating layer disposed between the sub-pixels SP to separate the sub-pixels SP.

[0105] The bank 116 may include an opening OP that exposes a portion of the anode 121. The bank 116 may be an organic insulating material disposed to cover an edge or a marginal portion of the anode 121. The bank 116 may be made of, for example, but is not limited to, polyimide, acrylic, or a benzocyclobutene (BCB)-based resin.

[0106] At least one spacer 160 may be disposed on the bank 116 .

[0107] The spacer 160 may be disposed on the bank 116 to maintain a certain distance from the deposition mask when forming the light emitting element 120. That is, the spacer 160 allows the deposition mask and the bank 116 and anode 121 below the spacer 160 to maintain a certain distance from the deposition mask, thereby preventing damage due to contact. The spacer 160 may be formed in a shape that narrows toward the top, for example, a tapered shape, to reduce and / or minimize the area in contact with the deposition mask.

[0108] An organic layer 122 may be disposed on the anode 121 and the bank 116. In this case, the organic layer 122 may be formed on the bottom of the trench pattern 140 but not on the side surfaces thereof, and the organic layer 122 may be partially disconnected between adjacent subpixels SP by the trench pattern 140.

[0109] The organic layer 122 may include a light emitting layer disposed in each of the sub-pixels SP and a common layer disposed in common to the sub-pixels SP. The light emitting layer is an organic layer for emitting light of a specific color, and different light emitting layers may be disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the present invention is not limited thereto, and all the sub-pixels SP may each be provided with a plurality of light emitting layers to emit white light.

[0110] The common layer is an organic layer disposed to improve the light emitting efficiency of the light emitting layer. The common layer may be formed as one layer across a plurality of sub-pixels SP. That is, the common layers of the plurality of sub-pixels SP may be connected to each other to be integrated. In this case, the common layer may include, but is not limited to, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, a charge generation layer, etc.

[0111] A cathode 123 may be disposed on the organic layer 122 .

[0112] The cathode 123 may be made of a conductive material having a low work function since it supplies electrons to the organic layer 122. The cathode 123 may be formed as one layer across the plurality of sub-pixels SP. That is, the cathodes 123 of the plurality of sub-pixels SP may be connected to each other to be integrated. In this case, the cathode 123 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an ytterbium (Yb) alloy, and may further include a metal doping layer, but is not limited thereto. Meanwhile, although not shown in the drawing, the cathode 123 may be electrically connected to a low potential power line to receive a low potential power signal.

[0113] Meanwhile, as described above, the common layer of the plurality of light emitting elements 120 may be formed as one layer over the entirety of the plurality of subpixels SP. Since the light emitting elements 120 of the plurality of subpixels SP are formed in a structure sharing a common layer, when the light emitting element 120 of a specific subpixel SP is caused to emit light, a phenomenon in which a current flows through the light emitting element 120 of the adjacent subpixel SP, i.e., a current leakage phenomenon may occur. The current leakage phenomenon may cause the light emitting element 120 of another subpixel SP to emit light unintentionally, thereby inducing color mixing between the plurality of subpixels SP and increasing power consumption. In addition, the leakage current may cause color abnormalities and spots to be visually recognized, thereby degrading display quality. For example, when only the first subpixel SP1 of the plurality of subpixels SP emits light, a portion of the current supplied to drive the light emitting element 120 of the first subpixel SP1 may leak to the adjacent second subpixel SP2 and / or third subpixel SP3 through the common layer.

[0114] Therefore, the display device 100 according to the first embodiment of the present invention is characterized in that a trench pattern 140 is disposed between the subpixels SP to reduce and / or minimize leakage current through the common layer of the light emitting element 120. First, a plurality of trench patterns 140 are formed between the subpixels SP, and the common layer and the cathode 123 are deposited along the plurality of trench patterns 140, so that the length of the path through which the leakage current flows can be increased. Since the common layer, which serves as the path through which the leakage current flows, is formed along the plurality of trench patterns 140 and the bank 116, the length of the common layer can be extended from the conventional one, and the length of the path through which the leakage current flows can be increased. Therefore, the length of the path through which the leakage current flows can be increased to increase resistance, and the leakage current can be reduced from flowing to the light emitting element 120 of the adjacent subpixel SP.

[0115] Furthermore, in the display device 100 according to the first embodiment of the present invention, the common layer and the cathode 123 between the adjacent sub-pixels SP may be at least partially disconnected by the trench pattern 140. Therefore, leakage current flowing between the adjacent sub-pixels SP may be reduced and / or minimized.

[0116] Meanwhile, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, and a passivation layer 114 may be formed on the outer periphery of the display device 100, extending to the non-display area NA.

[0117] Moreover, a planarization layer 115 and a bank 116 can be formed thereon up to a part of the non-display area NA. The bank 116 may be formed to cover the planarization layer 115, but is not limited to this.

[0118] Although not shown, a capping layer made of an organic material such as a polymer may be formed on the substrate 110 on which the cathode 123 is formed. However, the present invention is not limited thereto, and the capping layer may not be formed if necessary.

[0119] The capping layer may be made of an organic or inorganic material and may be formed by a thermal deposition method, so that the capping layer is relatively thin and may be at least partially disconnected between adjacent sub-pixels SP by the trench pattern 140. For example, the capping layer may have a thickness of about 0.1 μm.

[0120] The capping layer has a specific refractive index in the case of a top emission type and can function to collect light and improve light emission, and in the case of a bottom emission type, it functions as a buffer for the cathode 123 of the light emitting device 120 .

[0121] The capping layer may also function as an optical adjustment layer. The capping layer may increase the reflectance at the interface between the capping layer and the outside by adjusting the refractive index difference with the outside. Through such an increase in reflectance, the capping layer may realize a microcavity effect at a specific wavelength. In this case, the capping layer may be formed to a different thickness for each of the sub-pixels SP1, SP2, and SP3.

[0122] On the capping layer, a buffer layer 155 according to the present invention may be formed, and on top of that, a multi-layered encapsulation layer 150 may be formed.

[0123] For reference, devices using organic materials, including light emitting devices, are very vulnerable to atmospheric gases, especially moisture and oxygen, and are also poorly resistant to heat, requiring a thorough sealing process.

[0124] If an appropriate encapsulation process is not performed, the device lifespan may be rapidly reduced and dark spots may form in the device, leading to product defects.On the other hand, if an appropriate encapsulation process is applied during device fabrication, device reliability can be ensured and high-quality devices can be produced.

[0125] Generally, such sealing processes are broadly divided into two types.

[0126] One is the lid method, in which a moisture absorbent (getter) is attached inside a glass or metal lid, which is then attached to the element using an adhesive with low water permeability, and the other is the thin film method, in which various types of films are laminated and attached to the light emitting element, or films are deposited directly on the light emitting element.

[0127] Among these, the films used in the thin film method mainly use materials having excellent oxygen barrier and water vapor barrier properties, and methods such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD) can be used for deposition.

[0128] To explain the encapsulation layer 150 in detail, a capping layer is formed on the upper surface of the substrate 110 on which the light emitting device 120 is formed, and a primary protective film 150a, an organic film 150b, and a secondary protective film 150c are sequentially formed thereon to constitute the encapsulation layer 150, which is an encapsulation means. However, the number of inorganic films and organic films constituting the encapsulation layer 150 is not limited thereto.

[0129] The primary protective film 150a is made of an inorganic insulating film and has poor stack coverage due to the step at the bottom, but the organic film 150b plays a role in planarization, so the secondary protective film 150c is not affected by the step at the bottom film. In addition, the organic film 150b made of a polymer is thick enough to repair cracks caused by foreign matter.

[0130] A multi-layered protective film for sealing may be positioned opposite the front surface of the substrate 110 including the secondary protective film 150c, and a transparent adhesive having adhesive properties may be interposed between the sealing layer 150 and the protective film.

[0131] A polarizing plate may be attached onto the protective film to prevent reflection of light incident from the outside.

[0132] Meanwhile, in the first embodiment of the present invention, the organic film 150b may be formed by an inkjet method. Accordingly, a plurality of dams 170a, 170b, and 170c may be provided in the non-display area NA of the outer periphery to control the flow of the organic film 150b made of a polymer. Also, the dams 170a, 170b, and 170c may function to block moisture penetration from the outside.

[0133] Therefore, the primary protective film 150a may be formed extending to one end of the non-display area NA, including the tops of the dams 170a, 170b, and 170c, while the organic film 150b may be formed only up to the front of the dams 170a, 170b, and 170c, and the secondary protective film 150c may cover and protect the organic film 150b.

[0134] Meanwhile, the trench patterns 140 are formed between the sub-pixels SP to prevent leakage current between the sub-pixels SP, but the primary protective film 150a of the encapsulation layer 150 is not completely deposited in the trench pattern 140, resulting in a failure in the reliability evaluation. That is, if the primary protective film 150a made of an inorganic film is deposited directly on the trench pattern 140, a void is generated in the center of the trench pattern 140, resulting in poor step coverage. In this case, the primary protective film 150a is not properly deposited, which induces a reliability failure. This also results in display quality failures such as bright and dark spots and bright spots.

[0135] In particular, the inorganic film of the primary protective film 150a is not deposited to completely cover the foreign matter, which causes film formation defects of the sealing layer 150. That is, the primary protective film 150a cannot completely cover the inverted tapered portion of the foreign matter, and a seam is formed in the inverted tapered portion.

[0136] Therefore, the present invention is characterized in that a buffer layer 155 is deposited in the trench pattern 140 by an initiated chemical vapor deposition (iCVD) method using an initiator before forming the sealing layer 150. The buffer layer 155 in the iCVD method may be deposited to cover the inner surface of the trench pattern 140, and if the thickness of the buffer layer 155 is sufficiently thin, it may be deposited along the inner shape of the trench pattern 140. However, the present invention is not limited thereto, and the buffer layer 155 may be deposited to completely fill the trench pattern 140 depending on the deposition conditions.

[0137] Also, the buffer layer 155 of the present invention may be deposited on the spacer 160 along the bends of the spacer 160 .

[0138] In the first embodiment of the present invention, the buffer layer 155 may have a thickness of 0.3 μm-1.0 μm, and the primary protective film 150a, the organic film 150b, and the secondary protective film 150c may have thicknesses of 0.3 μm-1.0 um, 1.0 μm-11.0 um, and 0.3 μm-1.0 μm, respectively.

[0139] In this case, the buffer layer 155 may have a refractive index of about 1.45-1.60, and the primary protective film 150a and the secondary protective film 150c may have a refractive index of about 1.4-1.9.

[0140] The buffer layer 155 may be formed to extend to the non-display area NA of the outer periphery.

[0141] The buffer layer 155 formed extending to the non-display area NA may be deposited on the plurality of dams 170a, 170b, 170c along the bends of the plurality of dams 170a, 170b, 170c.

[0142] In particular, the buffer layer 155 formed by the iCVD method does not react with the inorganic film of the primary protective film 150a thereon, so that the primary protective film 150a can be deposited smoothly.

[0143] The iCVD method uses a chain polymerization reaction using free radicals, known as a liquid phase process, and is a method of depositing a polymer thin film on the surface of a substrate by vaporizing an initiator and a monomer to cause a polymer reaction in the gas phase. At this time, if the initiator and the monomer are simply mixed, a polymerization reaction does not occur, but if the initiator is decomposed by a high-temperature filament located in a gas phase reactor to generate radicals, the monomer is activated by the radicals and a chain polymerization reaction can occur.

[0144] The iCVD method uses only monomers and radicals to initiate a reaction without the use of organic solvents or other additives, and can therefore produce thin films with higher purity than polymer synthesis methods that use existing liquid-phase processes.In other words, the iCVD method does not use organic solvents, so there are no problems caused by various impurities, and as it is a dry process, it can be deposited on a variety of substrates, and as it proceeds at room temperature, there is no damage to light-emitting devices due to heat.

[0145] In this manner, in the first embodiment of the present invention, the buffer layer 155 is deposited by the iCVD method under the primary protective film 150a to cover the inner surface of the trench pattern 140, thereby preventing film formation defects in the sealing layer 150. As a result, the reliability of the display device 100 is improved, and display quality defects such as bright and dark spots and bright spots are prevented, thereby improving the display quality.

[0146] Also, unlike the organic film 150b formed by the inkjet method, the buffer layer 155 formed by the iCVD method may be conformally or planarly deposited depending on the process conditions, and may be flowably deposited depending on the process conditions.

[0147] FIG. 6 is a table showing process conditions for the iCVD buffer layer.

[0148] 7a to 7d are photographs showing the surface characteristics of the iCVD buffer layer.

[0149] 8a-8d are further photographs showing the surface characteristics of the iCVD buffer layer.

[0150] FIG. 6 is a table showing example process conditions for the iCVD buffer layer, including initiator and monomer types.

[0151] 7a to 7d are scanning electron microscope (SEM) photographs showing, as examples, the surface characteristics of an iCVD buffer layer deposited on a 1 μm deep trench pattern.

[0152] 8a-8d are SEM images showing, as examples, the surface characteristics of an iCVD buffer layer deposited on a 5 μm deep trench pattern.

[0153] 7a to 7d show the case where the aspect ratio of the trench pattern is 1:5, and FIGS. 8a to 8d show the case where the aspect ratio of the trench pattern is 5:5.

[0154] 7a and 8a show the surface characteristics of the buffer layer deposited according to #1 in FIG. 6, while FIG. 7b and 8b show the surface characteristics of the buffer layer deposited according to #2 in FIG. 6, while FIG. 7c and 8c show the surface characteristics of the buffer layer deposited according to #3 in FIG. 6, while FIG. 7d and 8d show the surface characteristics of the buffer layer deposited according to #4 in FIG. 6.

[0155] Referring to FIG. 6, for example, an initiator of tert-butyl peroxide (TBPO) is used for deposition of the iCVD buffer layer, and a monomer 1 of glycidyl methacrylate (GMA) or a monomer 2 of 2-hydroxyethyl acrylate (HEA) is used. However, the present invention is not limited thereto, and ethylene glycol diacrylate (EGDA) may be used as a monomer. The monomers used in the present invention include styrene series or siloxane series in addition to acrylic series. In this case, the iCVD buffer layer may have a refractive index of about 1.50 to 1.51 based on a thickness of 0.5 μm, and it can be seen that there is no significant change even if the thickness is increased. In addition, it can be seen that the iCVD buffer layer has a transmittance of about 100% in the visible light region regardless of the monomer material, which is equivalent to the buffer layer of the inkjet method.

[0156] The flow rate of monomer 1 was changed while keeping the conditions such as the flow rate of initiator and monomer 2, and the temperature and pressure of initiator and monomer 1 and 2 the same, and the surface characteristics of the deposited iCVD buffer layer were observed.

[0157] At this time, the flow rates of the initiator and monomer 2 are 30 sccm and 28 sccm, respectively, the temperatures of the initiator and monomers 1 and 2 are 30°C, 30°C and 45°C, respectively, the temperatures of the filament, stage and chamber are 140°C, 30°C and 70°C, respectively, and the chamber pressure is 200 mTorr.

[0158] In this state, the flow rate of Monomer 1 was changed to 45 sccm, 56 sccm, 84 sccm, and 112 sccm.

[0159] As a result, referring to Figs. 7a to 7d and Figs. 8a to 8d, it can be seen that in the cases of #1 and #2 in Fig. 6, the thin film is deposited flowably, and in the cases of #3 and #4, the thin film is deposited conformally. However, in the case of #1, when the aspect ratio of the trench pattern is 1:5, it can be seen that the thin film is deposited flowably as in Fig. 7a, but when the aspect ratio of the trench pattern is 5:5, it can be seen that the thin film cannot completely cover the trench pattern as in Fig. 8a. Whether the thin film is deposited conformally or flowably can be determined by the monomer fraction. As an example, when the ratio of monomer 1 to monomer 2 is about 1.6:1 to 2:1, the thin film can be deposited flowably, and when the ratio is about 3:1 to 4:1, the thin film can be deposited conformally, but is not limited thereto.

[0160] Here, Monomer 1 may be used as a main monomer and Monomer 2 may be used as a sub-monomer, but is not limited thereto. In the copolymerization of two or more monomers, a thin film may be deposited conformally or flowably depending on the fraction.

[0161] FIG. 9 is a photograph showing the state of the sealing layer deposited on the foreign matter.

[0162] 10a to 10d are photographs showing the state of the iCVD buffer layer deposited on top of the foreign object.

[0163] FIG. 9 shows a case where an inorganic primary protective layer is directly deposited on top of a substrate as in the conventional method, and FIGS. 10a to 10d show a case where an iCVD buffer layer is deposited on top of a substrate and then a primary protective layer is deposited.

[0164] Referring to FIG. 9, it can be seen that the inorganic film of the primary protective film cannot completely cover the inverted tapered portion of the foreign object, and a seam is formed in the inverted tapered portion.

[0165] 10a to 10d, when a primary protective film is deposited after depositing an iCVD buffer layer on the substrate, the iCVD buffer layer and inorganic film are deposited to completely cover the reverse tapered portion of the foreign object, regardless of the shape of the foreign object. As a result, the iCVD buffer layer can be deposited without seams on the foreign object, regardless of the shape of the foreign object. That is, the iCVD buffer layer can be deposited without seams on the reverse tapered portion.

[0166] For reference, foreign matter is likely to form on top of the capping layer. Although the processes from the light emitting element to the capping layer may be carried out in one vacuum chamber, the sealing layer is carried out in a different process chamber, so there is a high possibility that foreign matter will form on top of the capping layer.

[0167] Meanwhile, the organic film of the present invention can also be deposited by the iCVD method, which will be described in detail with reference to the following FIGS.

[0168] FIG. 11 is a cross-sectional view of a part of a display device according to a second embodiment of the present invention.

[0169] FIG. 12 is a cross-sectional view showing an outer casing of the display device of FIG.

[0170] The display device of Figures 11 and 12 is substantially the same as the display device 100 of Figures 4 and 5 except for the configuration of the organic film 250b of the encapsulation layer 250, and therefore will not be described again. The same reference numerals will be used for the same components.

[0171] 11 and 12, the display device according to the second embodiment of the present invention may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a planarization layer 115, a bank 116, a high potential power supply wiring, a scan wiring, a data wiring, an initialization signal wiring, a light emission control signal wiring, a fifth transistor T5, a light emitting element 120, a spacer 160, a buffer layer 255 and an encapsulation layer 250, which are substantially the same as the display device of FIGS. 4 and 5 described above.

[0172] For convenience of explanation, FIG. 11 shows only the fifth transistor T5 among the plurality of transistors and capacitors in the pixel circuit of one sub-pixel.

[0173] The sub-pixels are individual units that emit light, and a light-emitting element 120 may be disposed in each of the sub-pixels.

[0174] A number of spacers 160 may be disposed between the sub-pixels.

[0175] Also, a plurality of trench patterns 140 may be disposed between the plurality of sub-pixels. The plurality of trench patterns 140 may be formed by removing a portion of the upper thickness of the bank 116, but the present invention is not limited thereto, and the plurality of trench patterns 140 may be formed by removing the entire thickness of the bank 116.

[0176] The trench pattern 140 may partially disconnect the organic layer 122 and the cathode 123 between adjacent subpixels.

[0177] Such a trench pattern 140 can reduce and / or minimize side leakage current occurring in a multi-stack structure.

[0178] That is, the organic layer 122 and the cathode 123 may be disposed on the anode 121 and the bank 116. At this time, the organic layer 122 and the cathode 123 may be formed on the bottom of the trench pattern 140 but not on the side surfaces, and the organic layer 122 and the cathode 123 may be at least partially disconnected between adjacent subpixels. Therefore, leakage current flowing between adjacent subpixels may be reduced and / or minimized.

[0179] Meanwhile, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, and a passivation layer 114 may be formed on the outer periphery of the display device, extending to the non-display area NA.

[0180] Moreover, a planarization layer 115 and a bank 116 can be formed thereon up to a part of the non-display area NA.

[0181] Although not shown, a capping layer made of an organic material such as a polymer may be formed on the substrate 110 on which the cathode 123 is formed.

[0182] A buffer layer 255 according to the present invention may be formed on the capping layer, and a multi-layer encapsulation layer 250 may be formed thereon.

[0183] The encapsulation layer 250 according to the present invention may include, but is not limited to, a primary protective layer 250a formed on the buffer layer 255, an organic layer 250b formed on the primary protective layer 250a, and a secondary protective layer 250c formed on the organic layer 250b.

[0184] The primary protective film 250a and the secondary protective film 250c may be made of an inorganic insulating film, and the organic film 250b may be made of an organic insulating film formed by iCVD.

[0185] In this case, unlike the first embodiment of the present invention, there is no need to provide multiple dams in the non-display area NA of the outer periphery, and an effect of reducing the bezel width is provided. That is, a dam is a physical structure that prevents ink from spreading and overflowing when hardened in the inkjet process, which is a liquid phase process, but since the iCVD process is a vapor phase deposition, the problem of ink spreading and overflowing does not occur. Therefore, the dam can be eliminated, and as a result, an effect of reducing the bezel width by W compared to the first embodiment described above is provided.

[0186] Therefore, the primary protective film 250a is formed to extend to one end of the non-display area NA, whereas the organic film 250b and the secondary protective film 250c may be formed to extend to only a portion of the non-display area NA, and the secondary protective film 250c may cover and protect the organic film 250b.

[0187] In addition, the inkjet method, which is a wet process, has difficulty achieving a thickness of less than 1μm even when using a high-resolution head and low-viscosity material, but the iCVD process is a dry process, and the thickness can be adjusted by the deposition time to achieve a thickness of less than 1μm, and can also stably achieve a thickness of around 1μm.

[0188] Therefore, the thickness of the encapsulation layer 250 can be thinned even in the display area AA, which reduces the amount of light totally reflected inside the element, and has the advantage of improving the color viewing angle and preventing color mixing in a high-resolution panel. That is, in a high-resolution panel, the pixel pitch, i.e., the distance between pixels, is reduced, but if an encapsulation layer of the existing thickness is used, the light path may invade adjacent pixels, causing color mixing or reducing the color viewing angle.

[0189] Meanwhile, as described above, the present invention is characterized in that the buffer layer 255 is deposited in the trench pattern 140 by the iCVD method before the formation of the encapsulation layer 250. The buffer layer 255 by the iCVD method may be conformally deposited to cover the inner surface of the trench pattern 140, and may be deposited to completely fill the trench pattern 140 depending on the deposition conditions.

[0190] Also, the buffer layer 255 of the present invention may be deposited on the spacer 160 along the bends of the spacer 160 .

[0191] The buffer layer 255 may be formed to extend to one end of the outer non-display area NA.

[0192] A primary protective film 250a may be deposited on the formed buffer layer 255, extending to the non-display area NA.

[0193] In particular, the buffer layer 255 formed by the iCVD method does not react with the inorganic film of the primary protective film 250a thereon, so that the primary protective film 250a can be deposited smoothly.

[0194] In the second embodiment of the present invention, the buffer layer 255 may have a thickness of 0.3 μm-1.0 μm, and the primary protective layer 250 a, the organic layer 250 b, and the secondary protective layer 250 c may have thicknesses of 0.3 μm-1.0 μm, 0.3 μm-1.5 μm, and 0.3 μm-1.0 μm, respectively. In this case, it can be seen that the total thickness is 1.2 μm-4.5 μm, which is reduced compared to 1.9 μm-14.0 μm in the first embodiment described above.

[0195] In this case, the buffer layer 255 may have a refractive index of about 1.45-1.60, and the primary protective film 250a and the secondary protective film 250c may have a refractive index of about 1.4-1.9.

[0196] In this manner, in the second embodiment of the present invention, the buffer layer 255 is deposited under the primary protective layer 250a by the iCVD method to cover the inner surface of the trench pattern 140, thereby preventing poor deposition of the encapsulation layer 250.

[0197] In addition, the second embodiment of the present invention is characterized in that even if a foreign object is generated during the process, the buffer layer 255 is deposited by the iCVD method to completely cover the inverted tapered portion of the foreign object, so that the buffer layer 255 and the primary protective film 250a can be deposited on the foreign object without any seams.

[0198] On the other hand, the iCVD buffer layer of the present invention can be flowably deposited to completely cover the trench pattern, including inside the trench pattern, which will be described in detail with reference to the following FIG.

[0199] FIG. 13 is a cross-sectional view of a part of a display device according to a third embodiment of the present invention.

[0200] The display device according to the third embodiment of the present invention shown in Fig. 13 is different from the display device shown in Fig. 11 in that the iCVD buffer layer 355 is deposited fluidly, and other configurations are substantially the same, so that a duplicated description will be omitted. The same reference numerals will be used for the same configurations.

[0201] Referring to FIG. 13, the display device according to the third embodiment of the present invention may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a planarization layer 115, a bank 116, a high potential power supply wiring, a scan wiring, a data wiring, an initialization signal wiring, a light emission control signal wiring, a fifth transistor T5, a light emitting element 120, a spacer 160, a buffer layer 355 and an encapsulation layer 250, which are substantially the same as the display device of FIG. 11 described above.

[0202] For convenience of explanation, FIG. 13 shows only the fifth transistor T5 among the plurality of transistors and capacitors in the pixel circuit of one sub-pixel.

[0203] The sub-pixels are individual units that emit light, and a light-emitting element 120 may be disposed in each of the sub-pixels.

[0204] A number of spacers 160 may be disposed between the sub-pixels.

[0205] Also, a plurality of trench patterns 140 may be disposed between the plurality of sub-pixels.

[0206] The trench pattern 140 may partially disconnect the organic layer 122 and the cathode 123 between adjacent subpixels.

[0207] Such a trench pattern 140 can reduce and / or minimize side leakage current occurring in a multi-stack structure.

[0208] Although not shown, a capping layer made of an organic material such as a polymer may be formed on the substrate 110 on which the cathode 123 is formed.

[0209] On the capping layer, a buffer layer 355 according to the present invention may be formed, and on top of that, a multi-layer encapsulation layer 250 may be formed.

[0210] The encapsulation layer 250 according to the present invention may include, but is not limited to, a primary protective layer 250a formed on the buffer layer 355, an organic layer 250b formed on the primary protective layer 250a, and a secondary protective layer 250c formed on the organic layer 250b.

[0211] The primary protective film 250a and the secondary protective film 250c may be made of an inorganic insulating film, and the organic film 250b may be made of an organic insulating film formed by iCVD.

[0212] In this case, unlike the second embodiment of the present invention, it is not necessary to provide a plurality of dams in the non-display area of ​​the outer periphery, and the bezel width can be reduced.

[0213] In the third embodiment of the present invention, the buffer layer 355 may have a thickness of 0.3 μm-5.0 μm, and the primary protective layer 250a, the organic layer 250b, and the secondary protective layer 250c may have thicknesses of 0.3 μm-1.0 μm, 0.3 μm-1.5 μm, and 0.3 μm-1.0 μm, respectively. In this case, the total thickness is 1.2 μm-8.5 μm, which is reduced compared to the 1.9 μm-14.0 μm of the first embodiment. The only difference from the second embodiment is the thickness of the buffer layer 355, and the thickness of the encapsulation layer 250 may be the same.

[0214] In this case, the buffer layer 355 may have a refractive index of about 1.45-1.60, and the primary protective film 250a and the secondary protective film 250c may have a refractive index of about 1.4-1.9.

[0215] Meanwhile, the third embodiment of the present invention is characterized in that, before the formation of the encapsulation layer 250, a buffer layer 355 is fluidly deposited by the iCVD method so as to completely cover the trench pattern 140 including the inside of the trench pattern 140.

[0216] The buffer layer 355 may be formed to extend to one end of the non-display area of ​​the outer shell.

[0217] A primary protective film 250a may be deposited on the formed buffer layer 355, extending to the non-display area.

[0218] In particular, the buffer layer 355 formed by the iCVD method does not react with the inorganic film of the primary protective film 250a thereon, and is deposited fluidly to completely cover the trench pattern 140, thereby allowing the primary protective film 250a to be deposited smoothly. As a result, it is possible to prevent poor deposition of the encapsulation layer 250.

[0219] Even if foreign matter is generated during the process, the buffer layer 355 of the iCVD method is deposited fluidly to completely cover the trench pattern 140 including the foreign matter, so that the buffer layer 355 and the primary protective film 250a can be deposited without any seams. In addition, the buffer layer 355 is deposited fluidly to reduce the step of the device. Therefore, by forming the encapsulation layer 250 on the reduced step of the device, the thickness can be made thinner, which is advantageous in enhancing the pure encapsulation function.

[0220] On the other hand, the present invention is also applicable to the case where the spacer is formed to have an inverse taper, which will be described in detail with reference to the following FIGS.

[0221] FIG. 14 is a cross-sectional view of a part of a display device according to a fourth embodiment of the present invention.

[0222] FIG. 15 is a cross-sectional view of a part of a display device according to a fifth embodiment of the present invention.

[0223] FIG. 16 is a cross-sectional view of a part of a display device according to a sixth embodiment of the present invention.

[0224] 14 to 16 are different from the display devices according to the first, second and third embodiments of the present invention only in that the spacers 460 are formed in an inverted taper, and other configurations are substantially the same, so duplicated descriptions will be omitted. The same reference numerals will be used for the same configurations.

[0225] 14 to 16, the display devices according to the fourth, fifth and sixth embodiments of the present invention may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a planarization layer 115, a bank 116, a high potential power supply wiring, a scan wiring, a data wiring, an initialization signal wiring, a light emission control signal wiring, a fifth transistor T5, a light emitting element 120, a spacer 460, buffer layers 455, 655 and encapsulation layers 150, 550, which are substantially the same as the display devices according to the first, second and third embodiments described above.

[0226] For convenience of explanation, only the fifth transistor T5 of the plurality of transistors and capacitors in the pixel circuit of one sub-pixel is shown in FIGS.

[0227] The sub-pixels are individual units that emit light, and a light-emitting element 120 may be disposed in each of the sub-pixels.

[0228] A plurality of spacers 460 may be disposed between the plurality of sub-pixels. The spacers 460 in the fourth, fifth and sixth embodiments of the present invention are characterized in that they have an inverted tapered shape, that is, the length of the lower side of the spacer 460 is shorter than the length of the upper side.

[0229] Also, a plurality of trench patterns 140 may be disposed between the plurality of sub-pixels.

[0230] The trench pattern 140 may disconnect a portion of the organic layer 122 and the cathode 123 between adjacent subpixels.

[0231] Such a trench pattern 140 can reduce and / or minimize side leakage current occurring in a multi-stack structure.

[0232] Although not shown, a capping layer made of an organic material such as a polymer may be formed on the substrate 110 on which the cathode 123 is formed.

[0233] On the capping layer, a buffer layer 455, 655 according to the present invention may be formed, on which a multi-layered encapsulation layer 150, 550 may be formed.

[0234] The sealing layer 150, 550 according to the present invention may include, but is not limited to, a primary protective film 150a, 550a formed on the buffer layer 455, 655, an organic film 150b, 550b formed on the primary protective film 150a, 550a, and a secondary protective film 150c, 550c formed on the organic film 150b, 550b.

[0235] In this case, the primary protective films 150a, 550a and the secondary protective films 150c, 550c may be made of inorganic insulating films. Also, the organic film 150b of the fourth embodiment may be made of an organic insulating film formed by inkjet printing, and the organic film 550b of the fifth and sixth embodiments may be made of an organic insulating film formed by iCVD.

[0236] When the organic film 550b is made of an iCVD organic insulating film, it is not necessary to provide a plurality of dams in the non-display area of ​​the outer periphery as in the second and third embodiments of the present invention, and an effect of reducing the bezel width is provided. On the other hand, the fourth, fifth and sixth embodiments of the present invention are characterized in that the buffer layers 455, 655 are deposited by the iCVD method before the sealing layers 150, 550 are formed.

[0237] At this time, the buffer layer 455 according to the fourth and fifth embodiments of the present invention may be deposited conformally to cover the inner surface of the trench pattern 140, and if the thickness of the buffer layer 455 is sufficiently thin, it may be deposited along the internal shape of the trench pattern 140. However, in this case, the primary protective film 150a, 550a deposited thereon may not completely cover the reverse tapered portion of the spacer 460, and a seam (indicated by dotted lines in FIGS. 14 and 15) may be formed in the reverse tapered portion. However, even in this case, the buffer layer 455 may be deposited to completely cover the reverse tapered portion of the spacer 460 so that no seam is formed.

[0238] Meanwhile, the buffer layer 655 according to the sixth embodiment may be deposited fluidly to completely cover the trench pattern 140 including the inside of the trench pattern 140. In this case, the buffer layer 655 may be deposited to a sufficient thickness to cover the inverted tapered portion of the spacer 460, so that the primary protective film 550a may be deposited thereon without forming a seam. The buffer layers 455, 655 may be formed to extend to one end of the non-display region of the outer portion.

[0239] A primary protective film 150a, 550a may be deposited on the formed buffer layer 455, 655, extending to the non-display area.

[0240] In particular, the buffer layers 455, 655 formed by the iCVD method do not react with the inorganic film of the primary protective films 150a, 550a thereover, and are deposited to cover the inner surface of the trench pattern 140 or completely cover the trench pattern 140, so that the primary protective films 150a, 550a can be deposited smoothly. As a result, poor deposition of the encapsulation layers 150, 550 can be prevented.

[0241] In addition, even if a foreign object is generated during the process, the buffer layer 455, 655 of the iCVD method is deposited to completely cover the inverted tapered portion of the foreign object, so that the buffer layer 455, 655 and the primary protective film 150a, 550a can be deposited on the foreign object without any seams.

[0242] A display device according to an embodiment of the present invention can be described as follows.

[0243] A display device according to an embodiment of the present invention may include a substrate having a plurality of sub-pixels defined thereon, a bank disposed between the plurality of sub-pixels, at least one trench pattern disposed between the plurality of sub-pixels and having a portion of an upper surface thickness of the bank removed, a buffer layer deposited on the bank by an initiated chemical vapor deposition (iCVD) method so as to cover an inner surface of the trench pattern, and a sealing layer disposed on the buffer layer.

[0244] According to another feature of the present invention, the display device further includes an anode disposed in each of the plurality of sub-pixels, an organic layer disposed on the plurality of anodes, and a cathode disposed on the organic layer, and the organic layer and the cathode can be disconnected from each other between adjacent sub-pixels by the trench pattern.

[0245] According to another aspect of the present invention, the buffer layer may be formed by copolymerization of an initiator and at least two acrylic monomers.

[0246] According to another aspect of the present invention, the initiator includes tert-butyl peroxide (TBPO), and the monomers include monomer 1 of glycidyl methacrylate (GMA) and monomer 2 of 2-hydroxyethyl acrylic acid (HEA), and the trench pattern can be deposited conformally or flowably depending on the ratio of monomer 1 and monomer 2.

[0247] According to another feature of the present invention, the ratio of the monomer 1 to the monomer 2 is set to 1.6:1 to 2:1, and the buffer layer may be conformally deposited to cover the inner surface of the trench pattern along the internal shape of the trench pattern.

[0248] According to another feature of the present invention, the ratio of the monomer 1 to the monomer 2 is set to 3:1 to 4:1, and the buffer layer can be deposited fluidly to cover the top of the trench pattern including the inside of the trench pattern.

[0249] According to another aspect of the present invention, when a foreign object is disposed on the top of the bank, the buffer layer can be deposited to cover the entire inverted tapered portion of the foreign object without any seams.

[0250] According to another feature of the present invention, the encapsulation layer includes a primary protective film disposed on the buffer layer, an organic film disposed on the primary protective film, and a secondary protective film disposed on the organic film, and the buffer layer may be disposed to extend to a non-display area of ​​the substrate.

[0251] According to another aspect of the present invention, the display device may further include a plurality of dams disposed in the non-display area, and the organic film may be disposed to extend in front of the plurality of dams.

[0252] According to yet another feature of the invention, the buffer layer may be deposited on the dams along the bends of the dams.

[0253] According to another aspect of the present invention, the organic layer may be deposited on the primary protective layer by the iCVD method, and the organic layer may extend to a portion of the non-display area.

[0254] According to another aspect of the present invention, a dam may not be present outside the organic film that extends to a portion of the non-display area.

[0255] According to another aspect of the present invention, the display device may further include at least one spacer disposed on the bank between the plurality of sub-pixels.

[0256] According to yet another aspect of the invention, the buffer layer may be deposited on the spacer along a bend in the spacer.

[0257] According to another aspect of the present invention, the spacer may have an inverse tapered shape, and the buffer layer may be deposited to completely cover the inverse tapered portion of the spacer such that no seam is formed.

[0258] According to another aspect of the present invention, the primary protective film deposited on the buffer layer may have a seam at a reverse tapered portion of the spacer.

[0259] According to another aspect of the present invention, when the buffer layer is deposited fluidly, the primary protective film can be deposited on the buffer layer without having a seam in the reverse tapered portion of the spacer.

[0260] According to another embodiment of the present invention, a display device may include a substrate having a plurality of subpixels defined thereon, a bank disposed between the plurality of subpixels, at least one trench pattern disposed between the plurality of subpixels and having a portion of an upper surface thickness of the bank removed, at least one spacer disposed on the bank between the plurality of subpixels, a buffer layer deposited on an inner surface of the trench pattern and on the bank and the spacer along an internal shape of the trench pattern and a curvature of the spacer by an iCVD method, and a sealing layer disposed on the buffer layer.

[0261] According to another feature of the present invention, when a foreign object is disposed on the top of the bank, the buffer layer can be deposited to cover the entire inverted tapered portion of the foreign object without any seams.

[0262] According to another aspect of the present invention, the spacer may have an inverse tapered shape, and the buffer layer may be deposited to completely cover the inverse tapered portion of the spacer such that no seam is formed.

[0263] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in this specification are for illustrative purposes only, and are not intended to limit the technical idea of ​​the present invention. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all respects. The scope of protection of the present invention should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

Claims

1. A substrate having a plurality of subpixels defined thereon; a bank disposed between the plurality of sub-pixels; an anode disposed at each of the plurality of subpixels; an organic layer disposed on the anode; a cathode disposed on the organic layer; at least one trench pattern disposed between the plurality of sub-pixels, the trench pattern having a top surface of the bank partially removed; a buffer layer deposited on the bank by an initiated chemical vapor deposition (iCVD) method to cover the inner surface of the trench pattern; and a sealing layer disposed on the buffer layer; the trench pattern includes at least one first portion extending in a column direction between the plurality of sub-pixels and at least one second portion extending in a row direction between the plurality of sub-pixels; the at least one first portion and the at least one second portion are connected; the encapsulation layer includes a primary protective film disposed on the buffer layer, an organic film disposed on the primary protective film, and a secondary protective film disposed on the organic film, The buffer layer is disposed between the primary protective film and the cathode, extends to a non-display area of ​​the substrate, and is disposed on a plurality of dams in the non-display area.

2. The display device as described in claim 1, wherein the organic layer and the cathode are disconnected from each other between adjacent subpixels by the trench pattern.

3. The display device according to claim 1 , wherein the buffer layer is formed by copolymerization of an initiator and at least two acrylic monomers.

4. The initiator includes tert-butyl peroxide (TBPO), The monomers include monomer 1, glycidyl methacrylate (GMA), and monomer 2, 2-hydroxyethyl acrylate (HEA); The display device of claim 3 , wherein the trench pattern is conformally or flowably deposited by a fraction of the monomer 1 and the monomer 2.

5. The ratio of the monomer 1 to the monomer 2 is set to 1.6:1 to 2:1; The display device according to claim 4 , wherein the buffer layer is deposited conformally so as to cover an inner surface of the trench pattern along an internal shape of the trench pattern.

6. The ratio of the monomer 1 to the monomer 2 is set to 3:1 to 4:1; The display device according to claim 4 , wherein the buffer layer is deposited with a flowability so as to cover an upper portion of the trench pattern including an inside of the trench pattern.

7. 2. The display device according to claim 1, wherein a foreign object is disposed on an upper portion of the bank, and the buffer layer is deposited so as to cover the entire inversely tapered portion of the foreign object without any gap.

8. The display device as described in claim 1, wherein the organic film is arranged to extend in front of the multiple dams.

9. The display device of claim 8 , wherein the buffer layer is deposited on the plurality of dams along bends of the plurality of dams.

10. the organic film is deposited on the primary protective film by the iCVD method; The display device according to claim 1 , wherein the organic film extends to a part of the non-display area.

11. The display device according to claim 10 , wherein no dam is present outside the organic film that extends to a portion of the non-display area.

12. The display device of claim 1 , further comprising at least one spacer disposed on the bank between the plurality of sub-pixels.

13. The display device of claim 12 , wherein the buffer layer is deposited on the spacer along a bend in the spacer.

14. The spacer has an inverse tapered shape such that the length of the lower side is shorter than the length of the upper side, The display device according to claim 12 , wherein the buffer layer is deposited so as to completely cover the inversely tapered portion of the spacer so that no gap is formed.

15. The display device according to claim 14 , wherein the primary protective film deposited on the buffer layer has a gap in a reverse tapered portion of the spacer.

16. The display device according to claim 14 , wherein the buffer layer is deposited with a flowability, and the primary protective film is deposited on the buffer layer so as not to have a gap in the reverse tapered portion of the spacer.

17. The organic layer, disposed within the at least one trench pattern; The display device of claim 1 , wherein the buffer layer is disposed on top of the organic layer.

18. The organic layer is disposed on top of the bank, 2 . The display device of claim 1 , wherein a first portion of the organic layer formed in the at least one trench pattern is disconnected from a second portion of the organic layer formed on an upper surface of the bank.

19. The display device according to claim 1 , wherein at least a part of the second portion overlaps with a DC wiring or an AC wiring that extends in the row direction among the wirings.

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