Information processing device

Abstract

To provide an information processor capable of flexible accommodation by a mounting shape and a shape change.SOLUTION: An information processor includes a plurality of chips. The plurality of chips are accumulated in a horizontal direction. Each of the plurality of chips is formed with a transmission coil and a reception coil as one pair. Each of the plurality of chips executes radio communication between the chips using inductive coupling in the horizontal direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an information processing device. [Background technology]

[0002] A system-on-a-chip (Soc) that combines different blocks on a single chip is known. FIG. 2 of Patent Document 1 discloses a processor Soc. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-191920 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, conventional SoCs have the problem that the mounting shape and changes to the shape are limited.

[0005] The present invention has been made in consideration of the above circumstances, and has an object to provide an information processing device that can flexibly accommodate changes in mounting shape and configuration. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided an information processing device having a plurality of chips, the plurality of chips being integrated horizontally, each of the plurality of chips being formed with a pair of a transmitting coil and a receiving coil, and each of the plurality of chips using horizontal inductive coupling to establish wireless connection between the chips. Effect of the Invention

[0007] Advantageous Effects of Invention According to one aspect of the present invention, it is possible to provide an information processing device that can flexibly accommodate changes in mounting shape and configuration. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram (part 1) showing an example of a horizontal inter-chip wireless bus. [Diagram 2] FIG. 2 is a diagram (part 2) showing an example of a horizontal inter-chip wireless bus. [Diagram 3] FIG. 3 is a diagram (part 3) showing an example of a horizontal inter-chip wireless bus. [Figure 4] FIG. 4 is a diagram showing an example of a combination with a wireless power supply technology. [Diagram 5] FIG. 5 is a diagram (part 1) for explaining horizontal inductive coupling between coils. [Figure 6] FIG. 6 is a diagram (part 2) for explaining horizontal inductive coupling between coils. [Figure 7] FIG. 7 is a diagram illustrating an example of a transmission / reception core circuit. [Figure 8] FIG. 8 is a diagram showing an example of operational waveforms in the transmission / reception core circuit. [Figure 9] FIG. 9 is a diagram illustrating an example of a transmission / reception circuit configured on a chip. [Figure 10] FIG. 10 is a diagram illustrating an example of a transmitting coil and a receiving coil. [Figure 11] FIG. 11 is a diagram illustrating an example of an electromagnetic field simulation environment. [Figure 12] FIG. 12 is a diagram showing an example of mutual inductance of vertically long rectangular coils. [Figure 13] FIG. 13 is a diagram showing an example of mutual inductance of horizontally long rectangular coils. [Figure 14] FIG. 14 is a diagram showing the results of a simulation in which the relative angle between the coils is changed. [Figure 15] FIG. 15 is a diagram for explaining the coil diameter and the communication distance. [Figure 16] FIG. 16 is a diagram showing an example of a simulation waveform of a transmission / reception core circuit. [Figure 17] FIG. 17 is a diagram showing the relationship between the coil diameter and the maximum transfer speed. [Figure 18] FIG. 18 is a diagram showing a performance comparison between conventional wired communication technology and wireless bus technology. [Figure 19] FIG. 19 is a diagram showing the influence of ring wiring. [Figure 20] FIG. 20 is a diagram showing the influence of the power supply ring. [Figure 21] FIG. 21 is a diagram showing the effect of a seal ring. [Figure 22] FIG. 22 is a diagram showing an example of a prototype board. [Figure 23] FIG. 23 is a diagram showing an example of a measured eye pattern and a bathtub curve. [Figure 24] FIG. 24 is a diagram illustrating an example of an electromagnetic field simulation environment. [Diagram 25] FIG. 25 is a diagram showing the relationship between the communication distance and the coupling coefficient. [Figure 26] FIG. 26 is a diagram showing the relationship between the positional deviation of the coil and the coupling coefficient. [Figure 27] FIG. 27 is a diagram showing the coupling coefficient when multiple coils are arranged. [Figure 28] FIG. 28 is a diagram for explaining the communication distance. [Figure 29] FIG. 29 is a diagram showing an example of a simulation waveform of a transmission / reception core circuit. [Diagram 30] FIG. 30 is a diagram showing an example of a measured eye pattern and a bathtub curve. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Various characteristic features shown in the following embodiments can be combined with each other.

[0010] In this specification, the term "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In addition, various information is handled in this embodiment, and this information is represented by high and low signal values ​​as a binary bit collection consisting of 0 or 1, and communication and calculation can be performed on the circuit in the broad sense.

[0011] In addition, a circuit in the broad sense is a circuit realized by at least appropriately combining a circuit (cIRCUIT), circuits (cIRCUITRY), a processor (processor), a memory (memory), etc. In other words, it includes an application specific integrated circuit (asic), a programmable logic device (e.g., a simple programmable logic device (simple programmable logic device:spld), a composite programmable logic device (complex programmable logic device:cpld), and a field programmable gate array (field programmable gate array:fpga)).

[0012] <Embodiment 1> 1. Horizontal chip-to-chip wireless bus FIG. 1 is a diagram (part 1) showing an example of a wireless bus between horizontal chips. FIG. 2 is a diagram (part 2) showing an example of a wireless bus between horizontal chips. The information processing device 100 includes a plurality of chips 110. A ~110 E A plurality of chips 110 A ~110 E The chips 110 are integrated in a horizontal direction. A pair of a transmitting coil and a receiving coil is formed on each of the chips 110. A ~110 E Each of these uses horizontal inductive coupling to provide wireless connections between chips. As shown in Figure 1, an on-chip coil is formed using the internal wiring of the chip. Also, as shown in Figures 1 and 2, wireless connections between chips are made using horizontal inductive coupling. With this configuration, it is not necessary to set up and manufacture a silicon interposer, and the information processing device 100 can be constructed inexpensively by flexibly combining chiplets.

[0013] FIG. 3 is a diagram (part 3) showing an example of a wireless bus between horizontal chips. As shown in FIG. 3, the information processing device 100 can be implemented in a free shape. For example, it is possible to implement a series of elongated chips like fibers, chips at an oblique relative angle to each other, and a system whose shape changes during operation. One of the multiple chips constituting the information processing device 100 is a CPU (Central Processing Unit). Also, one of the multiple chips constituting the information processing device 100 is a memory. The information processing device 100 is not limited to these. The hardware constituting the information processing device 100 may be composed of one or multiple chips. For example, a CPU may be composed of at least two or more chips among the multiple chips constituting the information processing device 100. In other words, the chips constituting the information processing device 100 can be flexibly separated. It should be noted that the information processing device 100 does not necessarily have to include a CPU and a memory.

[0014] FIG. 4 is a diagram showing an example of a combination with a wireless power supply technology. In the information processing device 100, by combining a wireless bus between horizontal chips and wireless power supply technology, chips can be mounted on various substrates 400. In addition, chips can be easily replaced after mounting. As shown in FIG. 4, multiple chips are horizontally integrated on the substrate 400. Here, the substrate 400 is a variable shape member. The variable shape member is a member that can change its shape, such as a flexible substrate, plastic, fiber, etc. The information processing device 100 can be constructed by simply fixing and arranging chips on such a variable shape member with a DAF tape or the like, and in the event of a breakdown or system update, a new information processing device 100 can be realized by simply replacing and re-arranging the chips.

[0015] 2. Horizontal inductive coupling between coils First, we will explain the horizontal inductive coupling between on-chip coils. The degree of coupling between coils is mainly determined by the length and distance of one adjacent side of two coils. Therefore, the larger the coils are and the shorter the distance between the adjacent sides is, the stronger the coupling will be. Through this inductive coupling, a signal can be transmitted from the transmitting coil to the receiving coil. For example, as shown in Figure 5, when the transmission current Itx flows toward the back of the screen, a corresponding reception voltage Vrx is induced on the receiving side. The characteristics of this coil can be expressed by an equivalent circuit as shown in Figure 6. The reception voltage is the first-order differential waveform of the transmission current Itx. It is the product of the second-order low-pass filter characteristics on the transmitting and receiving sides. The amplitude of the receiving voltage Vrx is proportional to the transmitting current and the coupling coefficient. If the threshold for correctly restoring data on the receiving side is constant, then if the coupling coefficient is halved, twice the current must flow, which determines the power consumption of the transmitting circuit.

[0016] 3. Transmitter / receiver core circuit Next, the transmit / receive core circuit will be explained using Fig. 7 and Fig. 8. Fig. 7 and Fig. 8 are diagrams for explaining the transmit / receive core circuit configured on a chip. In this example, the coil is driven by two inverters. A transmit current Itx flows to the coil in a direction according to the input Txdata, and as a result, a pulse voltage according to the data transition is generated on the receiving side as shown in Fig. 8. At this time, the polarity of the pulse differs depending on whether the data transition is from LOW to HIGH or from HIGH to LOW. The hysteresis comparator on the receiving side restores this pulse voltage to the original NRZ data, and the final Rxdata is obtained as shown in Fig. 8.

[0017] 4. Transmitter / receiver circuit FIG. 9 is a diagram showing an example of a transceiver circuit configured on a chip. A method is adopted in which parallel signals sent from a core are serialized and burst-transferred. As shown in FIG. 9, the transceiver circuit is equipped with a SerDes (SERializer / DESerializer) and a CDR circuit for connection with a digital circuit. The transceiver circuit is also equipped with a collision detection circuit. When a collision of transmission data occurs between chips, the collision detection circuit retransmits the data according to a procedure defined by a higher-level protocol. The transmitting coil 801 is a transmitting coil. The receiving coil 802 is a receiving coil. FIG. 10 is a diagram showing an example of a transmitter coil 801 and a receiver coil 802. In this embodiment, a large coil of several mm square is used, so the area of ​​the entire interface becomes extremely large. However, since the magnetic field generated by the on-chip coil has a small effect on the internal circuit, the coil can be formed along the periphery where wiring resources are more abundant than inside the core, as shown in FIG. 10, and the core circuit, network interface, and transmission / reception circuit can be formed inside the coil. Considering the communication characteristics and a design example of a typical square chip, the length of each side of the transmitter coil 801 and the receiver coil 802 is at least about 90% of the length of each side of the chip. The opening area of ​​the transmitter coil and the opening area of ​​the receiver coil should be 80% or more of the area of ​​the chip.

[0018] The transmitting coil 801 and the receiving coil 802 may be formed on different layers of the chip, or may be formed at approximately the same position on each of a plurality of chips.

[0019] 5.Electromagnetic field simulation environment Figure 11 shows an example of an electromagnetic field simulation environment. Simulation models of the coil and board were created based on the parameters of the manufacturing process, and the coupling coefficient between the coils was investigated using EmPro, a 3D electromagnetic field simulator from Keysight. The S-parameters obtained from the electromagnetic field simulation were fitted to an equivalent circuit, and the resulting coupling coefficient and mutual inductance were used as the simulation results.

[0020] 6.Mutual inductance of rectangular coils Figures 12 and 13 are diagrams showing an example of mutual inductance of rectangular coils. Figure 12 shows the change in mutual inductance when the side Dw of the transmitting coil perpendicular to the side closest to the adjacent coil is shortened. As can be seen from the results, even when Dw is halved, the mutual inductance is 85% of that of a square coil, and it is clear that the mutual inductance decreases relatively slowly.

[0021] On the other hand, Fig. 13 shows the change in mutual inductance when the side closest to the adjacent coil is shortened. As the side becomes shorter, the mutual inductance decreases linearly, and when the side is halved, the mutual inductance is 49% of that in the square case.

[0022] The results revealed that even in the case of rectangular coils, the coils are coupled, and that the mutual inductance changes depending on the shape. Because the side closest to the adjacent coil contributes strongly to the coupling, the mutual inductance decreases linearly when this side is shortened. For example, to maintain the mutual inductance at 90% or more, using the square coil as the standard, the side perpendicular to the side closest to the adjacent coil (Dw) needs to be 60% or more long, and the side closest to the adjacent coil (Dh) needs to be 90% or more long.

[0023] 7. Relationship between relative angle and coupling coefficient Fig. 14 shows the simulation results when the relative angle between the coils is changed. As shown in Fig. 14, when the coils are oblique to each other, it was confirmed by the simulation that the coupling coefficient increases monotonically as the relative angle decreases. The results showed that although the diagonal coils do couple with each other, the coupling coefficient changes according to the relative angle. Now, considering the hysteresis comparator in the receiving circuit, the input voltage is required to be in a range that is equal to or greater than the comparator threshold and does not exceed the power supply voltage. For example, if the amplitude at the lowest signal amplitude of a relative angle of 180 degrees is 100mV, the received signal amplitude at a relative angle of 0 degrees will be 760mV. Assuming a process with a core power supply voltage of about 1V, this is a typical design example that ensures sufficient amplitude that does not exceed the power supply voltage even at the maximum voltage amplitude and is not buried in the noise floor at the very least.

[0024] 8. Circuit Simulation We used circuit simulation to investigate the performance of the transmitter / receiver circuit and the effect of the ring-shaped wiring on the communication characteristics. We assumed a 45nm CMOS process for the manufacturing process, and investigated coil diameters ranging from 100μm to 5mm for a square coil. At this time, the communication distance was set to 1 / 10 of the coil diameter. Figure 15 is a diagram for explaining the coil diameter and communication distance. A model of the coil and ring-shaped wiring was created based on the results of an electromagnetic field simulation, and this was then incorporated into the circuit simulation.

[0025] 9. Simulation waveforms of the transmitter / receiver core circuit Fig. 16 shows an example of a simulated waveform of a transceiver core circuit. When a PRBS31 signal transfer was simulated under the condition of a coil diameter of 300 μm, a maximum transfer speed of 14.3 Gb / s and power consumption of 7.91 mW were achieved.

[0026] 10.Relationship between coil diameter and maximum transfer speed FIG. 17 is a diagram showing the relationship between the coil diameter and the maximum transfer speed. As the coil diameter becomes smaller, the parasitic capacitance decreases, and therefore the maximum transfer speed increases. In the process of this embodiment, the communication speed is limited by the transceiver circuit, so the transfer speed does not improve with coils of 300 μm or less, but further performance improvement is expected when using advanced processes. In other words, the performance of wireless bus technology is expected to improve with process miniaturization, finer graining of each chiplet, and advances in packaging technology.

[0027] 11.Performance comparison Figure 18 shows a performance comparison between conventional wired communication technology and wireless bus technology. The three on the left are all high-speed communication technologies that use silicon interposers. It shows that wireless bus technology can achieve results that are comparable to wired communication technology that uses silicon interposers in terms of both data transfer efficiency per interface area and power efficiency.

[0028] 12. Effects of ring wiring Figure 19 is a diagram showing the effect of ring-shaped wiring. As shown in Figure 19, if a chip has ring-shaped wiring of the same size as the coil, eddy currents in the opposite direction flow in these ring-shaped wiring when a transmission current flows, and this may adversely affect communication characteristics. Examples of such ring-shaped wiring include a power ring for power distribution and a seal ring for chip protection.

[0029] 13. Power Ring Effect Figure 20 shows the effect of the power ring. When a power ring is present on a chip, the amplitude of the received signal is reduced due to the effect of eddy currents. This effect can be mitigated to some extent by making the power ring thinner and increasing the distance between the coil and the power ring. For example, if the power ring is 20 μm thick and you want to obtain about 80% of the amplitude when the ring is not present, the distance d from the ring needs to be 150 μm or more when the coil diameter is 1 mm.

[0030] 14.Effect of seal ring FIG. 21 shows the effect of a seal ring. Even when a seal ring is present on a chip, the received signal amplitude is reduced due to the effect of eddy currents. This effect can be mitigated to some extent by making the seal ring thinner. For example, to obtain about 50% of the amplitude when the ring is not present, the seal ring thickness must be 2 μm or less. On the other hand, even if a part of the seal ring is cut off, it functions as a seal ring if the length of the cut part is sufficiently short, and can prevent moisture penetration and crack propagation without any problems. When a simulation was performed using a seal ring with a part cut off, no effect on the received signal amplitude was observed. Therefore, if possible in the process, it is also possible to use a divided seal ring.

[0031] 15. Prototype board Figure 22 shows an example of a prototype board. In order to evaluate the wireless bus technology by actual measurement, a prototype board was designed, fabricated, and measured. A high-speed hysteresis comparator IC is used as the receiving circuit, and the pulse waveform transmitted through the coil is restored to an NRZ waveform.

[0032] 16.Measurement results Figure 23 shows an example of the measured eye pattern and bathtub curve. When a PRBS7 signal was applied, a maximum transfer speed of 2.6 Gbps was achieved under the condition of a BER of 10-12 or less. At that time, the timing margin was 0.71 UI, which was a sufficiently wide result.

[0033] 17. Effects of the First Embodiment According to the first embodiment, it is possible to provide an information processing device that can flexibly accommodate changes in mounting form and shape.

[0034] <Variation 1> 1.Electromagnetic field simulation environment Fig. 24 shows an example of an electromagnetic field simulation environment. Simulation models of the coil and the substrate were created based on the parameters of the manufacturing process, and the coupling coefficient between the coils was investigated using Momentum, a three-dimensional planar electromagnetic field simulator from Keysight Corporation.

[0035] 2. Relationship between communication distance and coupling coefficient Fig. 25 is a diagram showing the relationship between communication distance and coupling coefficient. As shown in Fig. 25, the coupling coefficient k decreases monotonically as the communication distance X increases. In the case of horizontal inductive coupling, when the coil diameter D is three times the communication distance X, the coupling coefficient is 0.023, which is less than 1 / 4. Here, if we consider a case where the coil diameter is 5 mm and the communication distance is 800 μm, the coupling coefficient is 0.042. In other words, a transmission current about 3.6 times higher is required compared to conventional inductive coupling communication.

[0036] 3. Relationship between coil misalignment and coupling coefficient Fig. 26 is a diagram showing the relationship between the positional deviation of the coil and the coupling coefficient. It shows the change in the coupling coefficient k according to the positional deviation dY under the condition that the coil diameter D is 12 times the communication distance X. Even if the position is shifted by about 10% of the coil diameter, the coupling coefficient changes by only 3%. For example, if the coil diameter is 5 mm, the transmission current only needs to be increased by 3% even if the coil position is shifted by 500 μm.

[0037] 4. Coupling coefficient when multiple coils are arranged Fig. 27 is a diagram showing the coupling coefficient when multiple coils are arranged. As shown in Fig. 27, the coupling coefficient between adjacent coils in a diagonal direction is about 20% of the coupling coefficient between adjacent coils in the up / down / left / right directions.

[0038] 5. Circuit Simulation A simulation of the transmission and reception core circuit was created, and power consumption, etc. were investigated. The manufacturing process was assumed to be 45 nm CMOS process, and the coil diameter was 5 mm. The communication distance was set to 0.8 mm. Figure 28 is a diagram for explaining the communication distance.

[0039] 6. Simulation waveforms of the transmitter / receiver core circuit 29 is a diagram showing an example of a simulation waveform of a transmission / reception core circuit. A voltage is generated in the receiving coil in response to the transition of input transmission data, and the original data is restored by the receiving circuit.

[0040] 7. Performance of Transmitter / Receiver Core Circuits Figure 30 shows the eye pattern and bathtub curve when a 1.0 Gb / s PRBS-31 signal is input. The designed transceiver core circuit achieves a BER of 10 -12 The timing margin at the time of the experiment was 0.68UI, and it was confirmed that the device could operate with a sufficient margin. The power consumption of the transmitter and receiver core circuits was 11.1mW when the communication distance was 0.8mm, and 6.41mW when the communication distance was 0.5mm.

[0041] It may be provided in any of the following ways: The information processing device, wherein the plurality of chips are integrated horizontally on a substrate, the substrate being a shape-variable member. The information processing device, wherein the shape-variable member is a flexible substrate. The information processing device, wherein the variable shape member is made of plastic. The information processing device, wherein the shape-variable member is a fiber. The information processing device, wherein the transmitting coil and the receiving coil are formed at approximately the same positions on each of the plurality of chips. The information processing device, wherein the transmitting coil and the receiving coil are formed on different layers of the chip. The information processing device, wherein an aperture area of ​​the transmitting coil and an aperture area of ​​the receiving coil are 80% or more of an area of ​​the chip. The information processing device, wherein a seal ring is formed on each of the plurality of chips, and a portion of the seal ring is separated. The information processing device, wherein the seal ring has a thickness of 2 μm or less. The information processing device, wherein a power ring is formed on each of the multiple chips, and when the coil diameter of the transmitting coil and the receiving coil is approximately 1 mm, the distance between the transmitting coil and the receiving coil and the power ring is 150 μm or more. The information processing device, wherein one of the plurality of chips is a CPU (Central Processing Unit). The information processing device, wherein one of the plurality of chips is a memory. The information processing device, wherein hardware constituting the information processing device is configured with one or more of the plurality of chips. The information processing device, wherein the hardware is a CPU (Central Processing Unit). Of course, this is not the case. Furthermore, the above-described embodiments and modifications may be combined in any desired manner.

[0042] Finally, although various embodiments of the present invention have been described, these are presented as examples and are not intended to limit the scope of the invention. The new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their modifications are within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0043] 100: Information processing device 110A: Chip 110B: Chip 110C: Chip 110D: Chip 110E: Chip 400: Base material 801: Transmitting coil 802: Receiving coil

Claims

1. A chip having a coil formed thereon, At least one of a core circuit, a network interface, and a transceiver circuit is formed; The coil is at least one of a transmitting coil and a receiving coil, A wireless connection is established by utilizing inductive coupling between the coil and a coil formed on another chip arranged in the horizontal direction, A tip, wherein the opening area of ​​the coil is 80% or more of the area of ​​the tip.

2. A chip having a coil formed thereon, At least one of a core circuit, a network interface, and a transceiver circuit is formed; The coil is at least one of a transmitting coil and a receiving coil, A wireless connection is established by utilizing inductive coupling between the coil and a coil formed on another chip arranged in the horizontal direction, A chip, wherein each side of the transmitting coil or the receiving coil has a length of 90% or more of each side of the chip.

3. The chip according to claim 1 or claim 2, The coils are the transmitting coil and the receiving coil.

4. In the chip according to claim 3 A chip, wherein the transmitting coil and the receiving coil are formed on different layers.

5. The chip according to claim 1 or claim 2, A seal ring is formed, A portion of the seal ring is disrupted.

6. An information processing device, A plurality of chips are horizontally integrated, Any one of the plurality of chips is configured by the chip according to claim 1 or 2. Information processing device.

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