Signal Line Driver Circuit

Abstract

[Problem] To suppress variations of a signal line voltage. [Solution] A signal line driving circuit for driving a plurality of signal lines, comprising: a reference voltage generating unit for generating, in a first period before the plurality of signal lines are driven, a reference voltage having a voltage level varying in accordance with time; a current holding unit provided corresponding to the signal lines to hold a current in accordance with a load on the signal lines and a temporal change in the reference voltage; and a current control unit for allowing the current being held by the current holding unit to flow in a corresponding signal line in a second period after the elapse of the first period, to generate a driving voltage for the signal line.

Description

[Technical field]

[0001] An embodiment according to the present disclosure relates to a signal line driver circuit. [Background technology]

[0002] In displays and the like, a signal line driver circuit is used to drive multiple pixel circuits. In the signal line driver circuit, a method of driving signal lines with multiple voltage follower circuits is widely used. However, this method requires a bias current to flow through the voltage follower circuit including an amplifier circuit, which increases power consumption.

[0003] In order to reduce this bias current, a method has been proposed in which a constant current source is used to pass a constant current through a capacitive load for a period corresponding to the display data (signal voltage), thereby driving multiple pixel circuits with a desired signal line voltage (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-004720 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, this method has a problem that the write voltage varies due to current variations caused by the characteristic variations such as the mobility of the transistor that serves as the constant current source.Furthermore, such variations in the write voltage (signal line voltage) can cause a problem of, for example, a deterioration in the display quality of the display.

[0006] Therefore, the present disclosure provides a signal line drive circuit capable of suppressing the variation in the signal line voltage. [Means for solving the problem]

[0007] In order to solve the above problems, according to the present disclosure, A signal line driver circuit for driving a plurality of signal lines, a reference voltage generating unit that generates a reference voltage whose voltage level changes with time during a first period before driving the plurality of signal lines; a current holding section provided corresponding to the signal line, the current holding section holding a current corresponding to a load on the signal line and a time change in the reference voltage; A signal line drive circuit is provided, comprising: a current control unit that generates a drive voltage for the signal line by causing the current held by the current holding unit to flow to the corresponding signal line within a second period after the first period has elapsed.

[0008] The current holding section and the current control section may be provided for each of the plurality of signal lines.

[0009] The current holding section may hold a current according to a value obtained by multiplying the load of the corresponding signal line by a voltage change value per unit time of the reference voltage.

[0010] The reference voltage generating section may generate the reference voltage whose voltage level changes linearly with time during the first period, and generate the reference voltage whose voltage level is constant during the second period.

[0011] the second period has a time length specific to each of the signal lines; The current control unit may generate a drive voltage for the signal line by continuously flowing the current through the signal line during the second period.

[0012] The current control unit may switch whether or not to pass the current held in the current holding unit to the corresponding signal line, depending on a logic of a pulse-width modulated signal having a pulse width according to a length of the second period.

[0013] The pulse width modulated signal may have a pulse width according to a drive voltage of the corresponding signal line.

[0014] the driving voltage of the signal line is a gradation voltage of a pixel driven by the signal line, The pulse width modulation signal may have a pulse width corresponding to the gray scale voltage.

[0015] The current control section may include two transistors connected in parallel and having different conductivity types, which are turned on or off in synchronization with each other.

[0016] One of the two transistors may form a part of a source follower circuit.

[0017] The current holding unit is a first capacitor that accumulates a charge according to the current that flows during the first period; The power supply may further include a first transistor that causes the current to flow continuously through the signal line during the second period based on the charge stored in the first capacitor.

[0018] the current holding unit further includes a switch that diode-connects the first transistor during the first period; The first capacitor may store a charge according to the current flowing through the first transistor which is diode-connected.

[0019] the current holding unit further includes a second transistor cascode-connected to the first transistor, the second transistor is set to an on state from the first period to the second period; The switch may store, in the first capacitor, a charge corresponding to a current flowing through the first transistor and the second transistor that are diode-connected, during the first period.

[0020] The current holding unit is an analog-to-digital converter that converts the current corresponding to the time change of the reference voltage into a digital value; a current memory unit that stores the digital value; a digital-to-analog conversion unit that converts the digital value stored in the current memory unit into a current; The current control unit may generate a drive voltage for the signal line by causing the current converted by the digital-to-analog conversion unit to flow through the corresponding signal line.

[0021] a plurality of the current holding units are provided corresponding to the plurality of signal lines; The plurality of current holding units may hold, in parallel, the current output from the reference voltage generating unit.

[0022] The power supply may further include a voltage follower circuit connected between the reference voltage generation unit and the current holding unit, the voltage follower circuit supplying the reference voltage to the current holding unit within the first period.

[0023] The power supply may further include an initial voltage setting section that sets the signal line to a predetermined reference voltage during a third period from when the first period has elapsed until when the second period begins.

[0024] The load may be the parasitic capacitance of each of the signal lines. [Brief description of the drawings]

[0025] [Figure 1] 1 is a block diagram showing a schematic configuration of a display device according to a first embodiment. [Diagram 2] 2 is a circuit diagram showing an example of an internal configuration of a pixel circuit. FIG. [Diagram 3] 4 is a circuit diagram showing an example of an internal configuration of a signal output unit. FIG. [Figure 4] 10 is a timing chart showing an example of an operation of a signal output unit. [Diagram 5] 1 is a timing chart showing an example of an operation of the display device. [Figure 6] 10 is a circuit diagram showing an example of an internal configuration of a signal output unit and a current holding unit according to a comparative example. FIG. [Figure 7] FIG. 11 is a flowchart showing an example of an operation of a signal output unit according to a modified example. [Figure 8] FIG. 11 is a block diagram showing an example of an internal configuration of a current holding unit according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, an embodiment of a signal line driving circuit will be described with reference to the drawings. The following description will focus on the main components of the signal line driving circuit, but the signal line driving circuit may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0027] In addition, the drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as that of the actual product. In the specification and drawings, the same elements as those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0028] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration of a display device 1 according to a first embodiment. The display device 1 in Fig. 1 is a display device having light-emitting elements such as organic EL (Electroluminescence) elements (hereinafter also referred to as OLEDs: Organic Light Emitting Diodes). However, the display device 1 is not limited to this, and may be other display devices.

[0029] The display device 1 includes a pixel array section 11, signal lines SL, and a signal line drive circuit 12.

[0030] The pixel array section 11 has a plurality of pixel circuits 15 arranged in the horizontal and vertical directions. Each pixel circuit 15 has a light-emitting section such as an organic EL element, a plurality of transistors that control the light-emitting section, and a plurality of capacitors. The internal configuration of the pixel circuit 15 will be described later.

[0031] The signal line driving circuit 12 drives a plurality of signal lines SL. The signal line driving circuit 12 shown in Fig. 1 is provided in a display device 1 and is used to drive the signal lines SL of the pixel circuits 15. However, the present invention is not limited to this, and the signal line driving circuit 12 may be used to drive other signal lines. The signal line driving circuit 12 is preferably used in a device that drives a plurality of signal lines, for example.

[0032] The signal line driving circuit 12 may perform signal processing of a video signal to be displayed on the pixel array section 11. The specific content of the signal processing is not important, but it may be, for example, gamma correction.

[0033] As shown in FIG. 2, which will be described later, the signal line driving circuit 12 includes a write scanning section 16, a drive scanning section 17, and a signal output section .

[0034] When writing a signal voltage to each pixel circuit 15, the write scanning section 16 sequentially supplies a write scanning signal to each scanning line to sequentially drive each scanning line WS1 to WSn.

[0035] The drive scanning section 17 supplies a light emission control signal to each drive line in synchronization with the line sequential scanning by the write scanning section 16, and controls whether the light emitting section emits light or not.

[0036] The signal output unit 18 holds the ramp voltage at a timing according to the gradation of each pixel to generate a signal voltage. The signal output unit 18 selectively selects the signal voltage or the offset voltage Vofs and supplies it to the corresponding signal line SL. The offset voltage Vofs is a reference voltage for the signal voltage (for example, a voltage corresponding to the black level of a video signal) and is used to perform a threshold correction operation described later.

[0037] The signal voltage or offset voltage Vofs alternatively output from the signal output unit 18 is supplied to each pixel circuit 15 via a signal line SL, and is set in each pixel circuit 15 on a row-by-row basis selected by scanning by the write scanning unit 16.

[0038] Fig. 2 is a circuit diagram showing an example of the internal configuration of a pixel circuit 15. The pixel circuit 15 in Fig. 2 has a light-emitting section 41 having an organic EL element, a drive transistor 42, a sampling transistor 43, a light-emitting control transistor 44, a holding capacitance (capacitor) 45, and an auxiliary capacitance (capacitor) 46. The pixel circuit 15 is formed on a semiconductor substrate such as silicon, and the drive transistor 42, the sampling transistor 43, and the light-emitting control transistor 44 are, for example, PMOS (Metal Oxide Semiconductor) transistors. A power supply voltage is applied to the back gate of each transistor.

[0039] The sampling transistor 43 samples the offset voltage Vofs or the signal line voltage Vsig supplied from the signal output unit 18 via the signal line SL, and writes it to the holding capacitor 45. The light-emission control transistor 44 is connected between the power supply node of the power supply voltage Vcc and the source electrode of the drive transistor 42, and controls the light emission / non-emission of the light-emitting unit 41 under the drive of a light-emission control signal DS.

[0040] The storage capacitor 45 is connected between the gate electrode and the source electrode of the drive transistor 42. The storage capacitor 45 stores the signal line voltage Vsig written by sampling by the sampling transistor 43. The drive transistor 42 drives the light-emitting section 41 by passing a drive current corresponding to the voltage stored in the storage capacitor 45 through the light-emitting section 41. The auxiliary capacitor 46 is connected between the source electrode of the drive transistor 42 and a node of a fixed potential, for example, a power supply node of a power supply voltage Vcc. The auxiliary capacitor 46 suppresses fluctuations in the source potential of the drive transistor 42 when the signal line voltage Vsig is written, and also acts to adjust the gate-source voltage Vgs of the drive transistor 42 to the threshold voltage Vth of the drive transistor 42.

[0041] The switching transistor 48 controls the light emission of the light-emitting unit 41. A signal AZ is input to the gate of the switching transistor 48, and the switching transistor 48 turns on or off depending on the logic of the signal AZ. While the switching transistor 48 is on, the light-emitting unit 41 stops emitting light. The switching transistor 48 is on during the period in which the threshold voltage and offset voltage of the drive transistor 42 are corrected, and turns off when the correction of the threshold voltage and offset voltage is completed, causing the light-emitting unit 41 to emit light.

[0042] FIG. 3 is a circuit diagram showing an example of the internal configuration of the signal output unit 18. As shown in FIG.

[0043] The signal output unit 18 includes a ramp wave generating circuit 181 , a voltage follower circuit 182 , a switch A, an xPWM switch D, a current holding unit 184 , a current control unit 185 , a voltage setting unit 186 , and a reset unit 188 .

[0044] The ramp wave generating circuit 181 as a reference voltage generating unit generates a reference voltage whose voltage level changes with time during a first period P1 before driving a plurality of signal lines SL. The first period P1 is a current sampling period shown in FIG. 4. The reference voltage is, for example, a ramp wave voltage whose voltage level changes continuously (see FIG. 4). The reference voltage is not limited to a ramp wave voltage, and may be any voltage that changes with time at a substantially constant slope. Details of the first period P1 will be described later with reference to FIG. 4. In the following, an example will be mainly described in which the ramp wave generating circuit 181 generates a ramp wave voltage whose voltage level changes linearly with time during the first period P1, and generates a voltage whose voltage level is constant during the second period P2.

[0045] The voltage follower circuit 182 is connected between the ramp wave generating circuit 181 and the current holding unit 184, and supplies a reference voltage to the current holding unit 184 during the first period P1. The voltage follower circuit 182 outputs a ramp wave voltage to the ramp wiring 180.

[0046] The signal output unit 18 may further include an offset voltage generating circuit (not shown). In this case, the voltage follower circuit 182 switches between an offset voltage Vofs for performing threshold correction of the driving transistor 42 in the pixel circuit 15 and a ramp voltage whose voltage level changes continuously, and outputs the switched voltage to the ramp wiring 180.

[0047] A plurality of switches A and a plurality of reset units 188 are connected to the lamp wiring 180. The switches A, the xPWM switches D, the current holding unit 184, the current control unit 185, the voltage setting unit 186, and the reset unit 188 are a drive unit U corresponding to one signal line SL. Therefore, a plurality of drive units U corresponding to the plurality of signal lines SL are connected to the lamp wiring 180. That is, a current holding unit 184 and a current control unit 185 are provided for each of the plurality of signal lines SL.

[0048] Switch A is connected between lamp wiring 180 and current control unit 185 .

[0049] The xPWM switch D is connected between the switch A and the current control unit 185 and the ground. For example, a signal having a level opposite to that of a PWM (Pulse Width Modulation) signal input to a transistor M3 (described later) is input to the xPWM switch D.

[0050] The current control unit 185 is connected between the signal line SL and the current holding unit 184. The current control unit 185 includes a transistor M2 and a transistor M3. The transistor M2 is, for example, a p-type MOS transistor. The transistor M2 functions as a source follower. That is, the transistor M2 serves both as a part of the current control unit 185 and as a buffer unit. The details of the transistor M3 will be described later.

[0051] The gate of the transistor M2 is connected to the lamp wiring 180 via the switch A. The gate of the transistor M2 is also connected to ground via the xPWM switch D. The drain of the transistor M2 is connected to the current holding unit 184, and the source of the transistor M2 is connected to the signal line SL.

[0052] A transistor M3 is provided in parallel to the transistor M2. A current control unit 185 consisting of the transistors M2 and M3 switches whether or not the current held in the current holding unit 184 is passed to the corresponding signal line SL according to the logic of a PWM signal having a pulse width according to the duration of the drive period P2. The PWM signal has a pulse width according to the drive voltage of the corresponding signal line. In a more specific example, the drive voltage of the signal line SL is a gradation voltage of a pixel driven by the signal line SL, and the PWM signal has a pulse width according to the gradation voltage. That is, the PWM signal has a pulse width unique to each signal line SL.

[0053] The transistors M2 and M3 constituting the current control section 185 have different conductivity types. For example, the transistor M2 is a p-type MOS transistor, and the transistor M3 is an n-type MOS transistor. The transistors M2 and M3 are turned on or off in synchronization. The transistor M2 also constitutes a part of a source follower circuit.

[0054] The current holding unit 184 is provided corresponding to the signal line SL, and holds a current according to the load of the signal line SL and the time change of the reference voltage. That is, the current holding unit 184 holds a current according to a value obtained by multiplying the load of the corresponding signal line by the voltage change value per unit time of the reference voltage. The current holding unit 184 that holds the current in the first period (current sampling period) P1 functions as a constant current source that flows a substantially constant current in the drive period (second period) shown in FIG. 4. Here, the load of the signal line SL is the parasitic capacitance of the signal line SL, and is a value unique to each signal line SL. That is, the load of the signal line SL is a value that can differ for each signal line SL. When the reference voltage is a ramp voltage whose voltage level changes linearly with time, the voltage change of the reference voltage becomes a constant value. Therefore, the current held by the current holding unit 184 holds a current whose current level differs for each signal line SL due to the difference in the parasitic capacitance of each signal line SL.

[0055] The current holding unit 184 includes a first transistor M1, a second transistor M5, a switch Aa, and a first capacitor C1.

[0056] The first capacitor C1 accumulates a charge according to the current flowing in the first period P1. The first capacitor C1 accumulates a charge according to the current output from the ramp wave generating circuit 181 (voltage follower circuit 182).

[0057] The first capacitor C1 is connected between the gate of the first transistor M1 and the switch Aa and ground.

[0058] The first transistor M1 continues to pass a current through the signal line SL during the second period P2 based on the charge stored in the first capacitor C1. The second period P2 is a period within the driving period shown in Fig. 4. Details of the second period P2 will be described later with reference to Fig. 4. The first transistor M1 is, for example, an n-type MOS transistor.

[0059] The first transistor M1 is connected between the second transistor M5 and ground. The gate of the first transistor M1 is connected to the first capacitor C1, and is also connected to the current control unit 185 and the second transistor M5 via the switch Aa.

[0060] The second transistor M5 is cascode-connected to the first transistor M1. The second transistor M5 is set to an on state from the first period P1 to the second period P2. The second transistor M5 is used to suppress voltage fluctuations. The second transistor M5 is, for example, an n-type MOS transistor.

[0061] The second transistor M5 is connected between the current control unit 185 and the switch Aa, and the first transistor M1. The gate of the second transistor M5 is biased to a voltage that turns on both the first transistor M1 and the second transistor M5, for example. The second transistor M5 may be always on, for example. The bias voltage of the second transistor M5 is the same for the second transistors M5 for the other signal lines SL.

[0062] The switch Aa diode-connects the first transistor M1 during the first period P1.

[0063] The switch Aa is connected between the current control unit 185 and the second transistor M5, and between the first capacitor C1 and the gate of the first transistor M1. When the switch Aa is turned on (closed state), the gate of the first transistor M1 and the drain of the first transistor M1 (the drain of the second transistor M5) are connected, so that the first transistor M1 is diode-connected.

[0064] More specifically, the first capacitor C1 stores a charge corresponding to the current flowing through the diode-connected first transistor M1. More specifically, the switch Aa stores a charge corresponding to the current flowing through the diode-connected first transistor M1 and second transistor M5 in the first capacitor C1 during the first period P1. That is, the first capacitor C1 holds a voltage corresponding to the gate-source voltage of the diode-connected first transistor M1 during the first period P1.

[0065] The current control unit 185, during the second period P2 according to the drive voltage of the signal line SL, causes a current to flow between the signal line SL and the current holding unit 184. As described above, the load is the parasitic capacitance of the signal line SL.

[0066] A PWM signal having a pulse width corresponding to the drive voltage of the signal line is input to the gate of the transistor M3, which is a part of the current control unit 185, and the transistor M3 passes a current corresponding to the current held by the current holding unit 184 between the signal line SL and the current holding unit 184. The transistor M3 is, for example, an n-type MOS transistor.

[0067] The transistor M3 is connected between the current holding unit 184 and the signal line SL. That is, the transistor M3 is connected in parallel with the transistor M2.

[0068] Voltage setting unit 186 sets the voltage between current control unit 185 and current holding unit 184. For example, voltage setting unit 186 sets the voltage between current control unit 185 and current holding unit 184 to a desired initial voltage. This allows current control unit 185 to operate more appropriately by the PWM signal.

[0069] The voltage setting unit 186 includes a transistor M4. The transistor M4 is, for example, a p-type MOS transistor.

[0070] The transistor M4 is connected between a power supply and the current holding unit 184 and current control unit 185. The power supply voltage is, for example, about 3 V to about 5 V. The transistor M4, together with the reset unit 188, constitutes an initial voltage setting unit that sets the signal line SL to a predetermined reference voltage (for example, the power supply voltage) during a third period from when the first period P1 has elapsed until the start of the drive period (second period) P2.

[0071] Here, the current control unit 185 generates a drive voltage for the signal line SL by causing the current held by the current holding unit 184 to flow through the corresponding signal line SL during the second period P2 after the first period P1 has elapsed. As described above, the load of the signal line SL is the parasitic capacitance of the signal line SL, and is a unique value for each signal line SL. The drive voltage is a voltage determined by the pulse width of a PWM signal that differs for each signal line SL, and is a different voltage for each signal line SL.

[0072] The current holding unit 184 holds a current according to the parasitic capacitance of the signal line SL. Therefore, by the current control unit 185 passing the current held in the current holding unit 184 through the signal line SL, it is possible to set a drive voltage for each signal line SL that is not dependent on the parasitic capacitance of the signal line SL.

[0073] The reset unit 188 resets the voltage of the signal line SL. The reset unit 188 has a switch C.

[0074] The switch C is connected between the signal line SL and the lamp wiring 180. When the switch C is turned on, it releases the charge stored in the parasitic capacitance of the signal line SL, thereby resetting the signal line voltage.

[0075] Next, the operation of the signal output unit 18 will be described.

[0076] FIG. 4 is a timing chart showing an example of the operation of the signal output section 18. As shown in FIG.

[0077] The current sampling period (first period P1) is a period during which the current holding unit 184 holds a current via the transistor M2 of the current control unit 185 functioning as a buffer unit. The reset period is a period during which the reset unit 188 resets the voltage of the signal line SL during the current sampling period. The drive period is a period during which the current control unit 185 flows a current to generate a drive voltage for the signal line SL.

[0078] RAMP indicates a voltage output by the ramp wave generating circuit 181. A, Aa, indicate the on or off state of the switches A, Aa. B indicates the gate voltage of the transistor M4 of the voltage setting unit 186. The transistor M4 is in the off state when the voltage B is at the H (High) level, and in the on state when the voltage B is at the L (Low) level. C indicates the on or off state of the switch C. PWM indicates a PWM signal input to the gate of the transistor M3 of the current control unit 185. Pix indicates a voltage (signal line voltage) on the signal line SL. The maximum value of the signal line voltage Pix shown in FIG. 4 is, for example, a voltage slightly smaller than about 3V to about 5V, which is the power supply voltage connected to the voltage setting unit 186. The minimum value of the signal line voltage Pix shown in FIG. 4 is, for example, about 1V.

[0079] The timing chart shown in Fig. 4 is executed simultaneously on multiple signal lines. In addition, the pulse width (second period P2) of the PWM signal is different for each signal line. As a result, each signal line is driven by a unique signal line voltage Pix.

[0080] In the initial state before the current sampling period, the switch C is on. The voltage follower circuit 182 outputs the 0 gradation voltage V0. Therefore, the signal line voltage Pix of the signal line SL is biased to the 0 gradation voltage V0.

[0081] Next, after the switch C is turned off, the voltage follower circuit 182 outputs a ramp wave whose voltage changes over time with a constant slope. Also, the switches A and Aa are turned on. As a result, the transistor M2 performs a source follower operation, and the first transistor M1 and the second transistor M5 are diode-connected.

[0082] Here, when the voltage of the ramp wave changes by dV with respect to time dt, if the load capacitance of the signal line is Cp, the current I flowing through the transistor M2 is expressed by Equation 1. I=Cp×(dV / dt) (Equation 1) The magnitude of the current I is proportional to the slope (dV / dt) of the ramp voltage. This current I flows through the signal line SL and the first transistor M1. The gate voltage Vg at which the drain current becomes the current I is generated at the gate of the first transistor M1. The signal line voltage Pix shown in FIG. 4 changes due to the current flowing through the signal line SL.

[0083] Next, when the switches A and Aa are successively turned off, the gate voltage Vg of the first transistor M1 is held in the first capacitor C1.

[0084] By the above operation, the gate voltage Vg is set in the first capacitor C1 simultaneously for multiple signal lines (channels), regardless of the variations in the threshold voltage Vth and mobility of the transistors of each signal line. This gate voltage Vg can generate a current I that changes each signal line with time at the slope (dV / dt) of the ramp voltage. As shown in Equation 1, the current held by the current holding unit 184 depends on the load capacitance Cp, which is the parasitic capacitance of each signal line.

[0085] Furthermore, the ramp voltage in each signal line may have a delay and a voltage difference depending on the distance from the voltage follower circuit 182 to each signal line due to the wiring resistance and parasitic capacitance of the ramp wiring 180. However, the slope of the ramp voltage itself is approximately constant regardless of the location. Therefore, the current holding unit 184 can suppress the influence of the wiring resistance and parasitic capacitance of the ramp wiring 180 and hold an approximately constant current in each signal line. As a result, there is no need to increase the wiring width to reduce the wiring resistance, and implementation can be achieved in a small area.

[0086] The reset period is a period during which the state in which a ramp wave is written in the signal line voltage Pix during the current sampling period is set to the initial state before the drive period.

[0087] First, voltage B goes to L level and switch C turns on. This sets the voltage of the lamp wiring 180 and the source and drain voltages of transistor M2 to the 0 gradation voltage V0. Note that the timing of switch A turning off and the timing of voltage B going to L level are almost synchronized. However, either timing may be slightly earlier than the other.

[0088] The drive period is an operation for writing a signal voltage (drive voltage) to the signal line SL using a constant current source set in the current sampling period and a PWM signal whose pulse width changes depending on the display data.

[0089] First, switch C turns off, voltage B goes to H level, the PWM level goes to H level, the xPWM level goes to L level, and then after a time T according to the display data has elapsed, the PWM signal goes to L level and xPWM goes to H level. As a result, the signal line voltage Pix of V0-(dV / dt)×T is written to the signal line SL.

[0090] That is, the second period P2 has a time length according to the drive voltage of the signal line SL, and is specified by the pulse width of the PWM signal. Moreover, the current control unit 185 generates the drive voltage of the signal line SL by continuously flowing a current through the signal line SL during the second period P2. The second period P2 corresponds to the time T. Therefore, the shorter the second period P2 is, the higher the signal line voltage Pix is. On the other hand, the longer the second period P2 is, the lower the signal line voltage Pix is.

[0091] During the drive period, a current flows from the current holding unit 184 to the signal line SL via the transistors M2 and M3 of the current control unit 185. Therefore, during the drive period, there is no need for the ramp wave generating circuit 181 and the voltage follower circuit 182 to output a current. The voltage follower circuit 182 is an amplifier circuit that requires a bias current. Therefore, there is no need to flow a bias current of the voltage follower circuit 182 during periods other than the current sampling period, and only the minimum current required to drive the signal line is consumed, thereby reducing power consumption.

[0092] In addition, the voltage written to each signal line is set as a current by the operation of the current sampling period described above. Therefore, it is possible to suppress the influence of the variation in the current source in the current holding unit 184 and the variation in the parasitic capacitance of the lamp wiring 180, and it is possible to generate a signal line voltage with suppressed deviation between the signal lines.

[0093] Next, the operation of the display device 1 shown in FIG. 2 will be described.

[0094] FIG. 5 is a timing chart showing an example of the operation of the display device 1. As shown in FIG.

[0095] The signal line driving circuit 12 generates driving voltages for all signal lines every time the write scanning unit 16 drives one scanning line. A plurality of scanning lines are provided in one frame, and a plurality of pixels connected to one scanning line are called one horizontal line (1H). FIG. 5 shows a timing chart of representative signals in the pixel circuit when all pixels in one frame are driven in sequence, one horizontal line at a time. The signal DS is the gate signal of the light emission control transistor 44. The signal AZ is the gate signal of the switching transistor 48. The signal WS is the gate signal of the sampling transistor 43.

[0096] The operation of the pixel circuit of FIG. 2 will be described below based on the timing chart of FIG. 5. First, at time t1, the signal AZ transitions from high to low, so that the switching transistor 48 turns on and the light emission of the light-emitting section 41 stops. In addition, the sampling transistor 43 turns on and the offset voltage Vofs on the signal line is supplied to one end of the holding capacitance 45. At this time, the light-emission control transistor 44 is on and the power supply voltage Vcc is supplied to the other end of the holding capacitance 45. Therefore, a voltage of (Vcc-Vofs) is applied to both ends of the holding capacitance 45.

[0097] After that, at time t2, the light-emission control transistor 44 is turned off. As a result, a part of the charge stored in the storage capacitor 45 moves to the auxiliary capacitor 46, and the charge is distributed. Specifically, a charge according to the threshold voltage of the drive transistor 42 is stored in the storage capacitor 45.

[0098] Then, at time t3, the sampling transistor 43 turns off. Then, at time t4, the signal line voltage Vsig is supplied onto the signal line. Then, at time t5, the sampling transistor 43 turns on, and the signal line voltage Vsig is supplied to the gate of the drive transistor 42. Since the storage capacitor 45 performs a correction for the threshold voltage of the drive transistor 42, a voltage that has been offset-corrected and threshold-corrected for the signal line voltage Vsig is applied between the gate and source of the drive transistor 42.

[0099] Then, at time t6, the light-emitting control transistor 44 is turned on and the switching transistor 48 is turned off, a voltage corresponding to the signal line voltage Vsig is applied to the anode of the light-emitting section 41, and the light-emitting section 41 emits light with a light emission brightness corresponding to the anode voltage.

[0100] As shown in Fig. 5, it is preferable to execute the operations of the current sampling period, the reset period, and the drive period for each horizontal line (1H) that is the rewrite period. This is because the current value is stored in the first capacitor C1, and a single drive may cause the signal line voltage to shift due to switch noise.

[0101] The ramp wave driving for current sampling may be performed in combination with writing of the offset voltage Vofs.

[0102] As described above, according to the first embodiment, the ramp generating circuit 181 generates a reference voltage (ramp voltage) whose voltage level changes with time. Moreover, the current holding unit 184 provided corresponding to the signal line SL holds a current according to the change in the ramp voltage with time.

[0103] This allows the current to be replicated with higher accuracy for the multiple signal lines. That is, the multiple current holding units 184 each hold approximately the same current value. Therefore, the signal line voltage Pix during the drive period changes with approximately the same slope for each signal line. As a result, the signal line voltage variation for each signal line can be suppressed. Therefore, by setting the PWM pulse width for each pixel circuit 15 according to the gradation, a desired drive voltage can be written to each signal line. As a result, the brightness variation of the display device 1 can be suppressed, and the deterioration of display quality can be suppressed.

[0104] As another method for replicating a current value, for example, a current mirror circuit is known. However, in a current mirror circuit, current variations may occur due to variations in the element characteristics of the transistors. In addition, signal line voltage variations occur between signal lines due to variations in parasitic capacitance of each signal line.

[0105] Fig. 6 is a circuit diagram showing an example of the internal configuration of a signal output unit 18C and a current holding unit 184C according to a comparative example. Fig. 6 is a diagram explaining a current sampling circuit as another method for duplicating a current value. In the comparative example shown in Fig. 6, a reference current source is provided instead of the ramp wave generating circuit 181.

[0106] The current holding unit 184C shown in Fig. 6 may be substantially similar to the current holding unit 184 shown in Fig. 3. In the example shown in Fig. 6, the current holding unit 184C is connected to a reference current source via a switch E on the current input side. The current holding unit 184C is connected to a transistor M3 (not shown) of the current control unit 185 on the current output side.

[0107] The current sampling circuit shown in FIG. 6 can replicate the current of the reference current source with high accuracy. However, it is difficult to replicate the current for multiple signal lines at the same time. Therefore, it is necessary to replicate the current of the reference current source in the current holding unit 184C in each signal line one by one in order, which takes time. In addition, the higher the resolution of the panel, the longer the time required for replicating the current. In addition, as with the current mirror circuit, the variation in the parasitic capacitance of each signal line causes variation in the signal line voltage between the signal lines.

[0108] In the first embodiment, in contrast to the current mirror circuit and the current sampling circuit shown in FIG. 6, a plurality of current holding units 184 hold the currents output from the ramp wave generating circuit 181 in parallel. A plurality of current holding units 184 are provided corresponding to a plurality of signal lines SL. Therefore, the current value of the constant current source can be set by simultaneously driving all signal lines (channels) with a ramp waveform and simultaneously sampling the currents flowing at that time in each signal line. This allows the current to be copied simultaneously for a plurality of signal lines, enabling more accurate and shorter current setting. In addition, only a switch and a capacitor need to be added to each signal line, and the circuit can be implemented in a small area. In addition, the current value of the constant current source is a current value according to the parasitic capacitance value of each signal line. When the current flowing from the constant current source is converted into a drive voltage by the parasitic capacitance, the effect of the parasitic capacitance is canceled. Therefore, the signal voltage variation between the signal lines caused by the parasitic capacitance variation can be suppressed.

[0109] In the example shown in Fig. 4, the ramp voltage is changed to the negative side. However, the present invention is not limited to this, and the ramp voltage may be changed to the positive side. In this case, the transistors M1 to M5 shown in Fig. 3 may be MOS transistors of opposite polarity.

[0110] (Modification) 7 is a flow chart showing an example of the operation of the signal output section 18 according to the modified example. The modified example differs from the first embodiment in that the operation during the current sampling period is not performed for each horizontal line (every H).

[0111] In the example shown in Fig. 7, after the current sampling period (S10), the reset period (S20) and the drive period (S30) are repeated. For example, a common current value obtained by one current sampling period (S10) is used for one frame shown in Fig. 5. Meanwhile, in order to change the signal line voltage Vsig for each horizontal line in one frame, the reset period (S20) and the drive period (S30) are repeatedly executed for each horizontal line, as in the first embodiment.

[0112] In this way, if there is no need to change the set value (the current value of the current holding unit 184) after the current sampling period, the drive period may be executed multiple times after the current setting. Since the operation during the current sampling period consumes a lot of power, the power consumption can be further reduced by reducing the number of current sampling periods.

[0113] Other configurations of the signal line driving circuit 12 according to the modification are similar to the corresponding configurations of the signal line driving circuit 12 according to the first embodiment, and therefore detailed description thereof will be omitted. The signal line driving circuit 12 according to the modification can obtain the same effects as those of the first embodiment.

[0114] Second embodiment FIG. 8 is a block diagram showing an example of the configuration of the current holding unit 184 according to the second embodiment.

[0115] The current holding unit 184 includes an ADC (Analog to Digital Converter) 1841, a memory 1842, and a DAC (Digital to Analog Converter) 1843.

[0116] The ADC 184, which serves as an analog-to-digital converter, converts the current corresponding to the time change of the reference voltage into a digital value.

[0117] The memory 1842 serving as a current storage unit stores digital values. The memory 1842 may be, for example, a volatile memory such as a static random access memory (SRAM) or a latch.

[0118] The DAC 1843, which serves as a digital-to-analog converter, converts the digital value stored in the memory 1842 into a current.

[0119] Moreover, the current control unit 185 generates a drive voltage for the signal line SL by passing the current converted by the DAC 1843 through the corresponding signal line SL. More specifically, the current control unit 185 generates a drive voltage for the signal line SL based on the current converted by the DAC 1843 and the time length of the drive period (second period) P2.

[0120] In the second embodiment, the first capacitor C1 can be omitted, and the fluctuation of the set current due to the leakage of the first capacitor C1 can be suppressed. That is, the influence of the noise caused by one driving operation described in the first embodiment can be suppressed. As a result, as described in the modified example, the operation in the current sampling period does not need to be performed for each horizontal line (every H), and may be performed, for example, on a frame-by-frame basis.

[0121] Other configurations of the signal line driving circuit 12 according to the second embodiment are similar to the corresponding configurations of the signal line driving circuit 12 according to the first embodiment, so detailed description thereof will be omitted. The signal line driving circuit 12 according to the second embodiment can obtain the same effects as the first embodiment. In addition, the signal line driving circuit 12 according to the second embodiment may be combined with modified examples.

[0122] The present technology can be configured as follows. (1) A signal line driver circuit for driving a plurality of signal lines, a reference voltage generating unit that generates a reference voltage whose voltage level changes with time during a first period before driving the plurality of signal lines; a current holding section provided corresponding to the signal line, the current holding section holding a current corresponding to a load on the signal line and a time change in the reference voltage; a current control unit that generates a drive voltage for the signal line by causing the current held by the current holding unit to flow to the corresponding signal line during a second period after the first period has elapsed. (2) The signal line driving circuit according to (1), wherein the current holding section and the current control section are provided for each of the plurality of signal lines. (3) The signal line driving circuit according to (1) or (2), wherein the current holding unit holds a current corresponding to a value obtained by multiplying the load of the corresponding signal line by a voltage change value per unit time of the reference voltage. (4) The signal line driving circuit according to any one of (1) to (3), wherein the reference voltage generating unit generates the reference voltage whose voltage level changes linearly with time during the first period, and generates the reference voltage whose voltage level is constant during the second period. (5) the second period has a time length specific to each of the signal lines; The signal line driving circuit according to any one of (1) to (4), wherein the current control unit generates a driving voltage for the signal line by continuously flowing the current through the signal line during the second period. (6) The signal line driving circuit according to any one of (3) to (5), wherein the current control unit switches whether or not to pass the current held in the current holding unit to the corresponding signal line depending on the logic of a pulse-width modulated signal having a pulse width according to the length of the second period. (7) The signal line drive circuit according to (6), wherein the pulse width modulated signal has a pulse width according to a drive voltage of the corresponding signal line. (8) a driving voltage of the signal line is a gradation voltage of a pixel driven by the signal line; The signal line driving circuit according to (7), wherein the pulse width modulation signal has a pulse width corresponding to the gradation voltage. (9) The signal line driving circuit according to any one of (6) to (8), wherein the current control section includes two transistors of different conductivity types connected in parallel and turned on or off in synchronization with each other. (10) The signal line driver circuit according to (9), wherein one of the two transistors constitutes a part of a source follower circuit. (11) The current holding unit is a first capacitor that accumulates a charge according to the current that flows during the first period; A signal line driving circuit according to any one of (5) to (10), further comprising: a first transistor that continuously passes the current through the signal line during the second period based on the accumulated charge of the first capacitor. (12) The current holding unit further includes a switch that diode-connects the first transistor during the first period, The signal line driving circuit according to (11), wherein the first capacitor accumulates a charge according to the current flowing through the first transistor that is diode-connected. (13) The current holding unit further includes a second transistor cascode-connected to the first transistor, the second transistor is set to an on state from the first period to the second period; The signal line driving circuit according to (12), wherein the switch accumulates, in the first capacitor, a charge according to a current flowing through the first transistor and the second transistor that are diode-connected during the first period. (14) The current holding unit is an analog-to-digital converter that converts the current corresponding to the time change of the reference voltage into a digital value; a current memory unit that stores the digital value; a digital-to-analog conversion unit that converts the digital value stored in the current memory unit into a current; The signal line driving circuit according to any one of (1) to (10), wherein the current control unit generates a driving voltage for the signal line by passing the current converted by the digital-to-analog conversion unit through the corresponding signal line. (15) A plurality of the current holding units are provided corresponding to the plurality of signal lines, The signal line driving circuit according to any one of (1) to (14), wherein the plurality of current holding units hold in parallel the currents output from the reference voltage generating unit. (16) The signal line driving circuit according to any one of (1) to (15), further comprising a voltage follower circuit connected between the reference voltage generating unit and the current holding unit, the voltage follower circuit supplying the reference voltage to the current holding unit within the first period. (17) The signal line driving circuit according to any one of (1) to (16), further comprising an initial voltage setting unit that sets the signal line to a predetermined reference voltage within a third period from when the first period has elapsed to when the second period begins. (18) The signal line driver circuit according to any one of (1) to (17), wherein the load is a parasitic capacitance of each of the signal lines.

[0123] The aspects of the present disclosure are not limited to the above-mentioned individual embodiments, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0124] 1 display device, 12 signal line driving circuit, 15 pixel circuit, 18 signal output section, 181 ramp wave generating circuit, 182 voltage follower circuit, 184 current holding section, 185 current control section, Aa switch, C1 first capacitor, M1 first transistor, M5 second transistor, M3 transistor, Pix signal line voltage, P1 first period, P2 second period, SL signal line, Vsig signal line voltage

Claims

1. A signal line driver circuit for driving a plurality of signal lines, a reference voltage generating unit configured to generate a reference voltage whose voltage level changes with time during a first period before driving the signal lines; a current holding section provided corresponding to the signal line, the current holding section holding a current corresponding to a load on the signal line and a time change in the reference voltage; a current control unit that generates a drive voltage for the signal line by causing the current held by the current holding unit to flow to the corresponding signal line during a second period after the first period has elapsed.

2. 2. The signal line driving circuit according to claim 1, wherein the current holding section and the current control section are provided for each of the plurality of signal lines.

3. 2. The signal line drive circuit according to claim 1, wherein the current holding section holds a current according to a value obtained by multiplying the load of the corresponding signal line by a voltage change value per unit time of the reference voltage.

4. 2. The signal line driving circuit according to claim 1, wherein the reference voltage generating section generates the reference voltage whose voltage level changes linearly with time during the first period, and generates the reference voltage whose voltage level is constant during the second period.

5. the second period has a time length specific to each of the signal lines; 2 . The signal line drive circuit according to claim 1 , wherein the current control section generates a drive voltage for the signal line by continuously causing the current to flow through the signal line during the second period.

6. 4. The signal line drive circuit according to claim 3, wherein the current control unit switches whether or not to flow the current held in the current holding unit to the corresponding signal line in accordance with a logic of a pulse width modulation signal having a pulse width according to a length of the second period.

7. 7. The signal line drive circuit according to claim 6, wherein the pulse width modulated signal has a pulse width according to a drive voltage of the corresponding signal line.

8. the driving voltage of the signal line is a gradation voltage of a pixel driven by the signal line, 8. The signal line driving circuit according to claim 7, wherein the pulse width modulation signal has a pulse width corresponding to the gray scale voltage.

9. 7. The signal line driving circuit according to claim 6, wherein the current control section has two transistors connected in parallel and having different conductivity types, the two transistors being turned on or off in synchronization with each other.

10. 10. The signal line driver circuit according to claim 9, wherein one of the two transistors constitutes a part of a source follower circuit.

11. The current holding unit is a first capacitor that accumulates a charge according to the current that flows during the first period; 6. The signal line driving circuit according to claim 5, further comprising: a first transistor that causes the current to flow continuously through the signal line during the second period based on the charge stored in the first capacitor.

12. the current holding unit further includes a switch that diode-connects the first transistor during the first period; 12. The signal line driving circuit according to claim 11, wherein the first capacitor stores a charge according to the current flowing through the first transistor which is diode-connected.

13. the current holding unit further includes a second transistor cascode-connected to the first transistor, the second transistor is set to an on state from the first period to the second period; 13 . The signal line driving circuit according to claim 12 , wherein the switch accumulates, in the first capacitor, a charge according to a current flowing through the first transistor and the second transistor that are diode-connected, during the first period.

14. The current holding unit is an analog-to-digital converter that converts the current corresponding to the time change of the reference voltage into a digital value; a current memory unit that stores the digital value; a digital-to-analog conversion unit that converts the digital value stored in the current memory unit into a current; 2. The signal line drive circuit according to claim 1, wherein the current control section generates a drive voltage for the signal line by causing the current converted by the digital-to-analog conversion section to flow through the corresponding signal line.

15. a plurality of the current holding units are provided corresponding to the plurality of signal lines; 2. The signal line driving circuit according to claim 1, wherein the plurality of current holding sections hold in parallel the currents output from the reference voltage generating section.

16. 2. The signal line driving circuit according to claim 1, further comprising a voltage follower circuit connected between said reference voltage generating section and said current holding section, said voltage follower circuit supplying said reference voltage to said current holding section within said first period.

17. 2. The signal line driving circuit according to claim 1, further comprising an initial voltage setting section that sets the signal line to a predetermined reference voltage within a third period from when the first period has elapsed until when the second period begins.

18. 2. The signal line driver circuit according to claim 1, wherein the load is a parasitic capacitance of each of the signal lines.

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