Photoelectric conversion device, photoelectric conversion system

Abstract

To provide a photoelectric conversion device having an avalanche diode capable of ensuring reliability.SOLUTION: A first electrode to which a first voltage is supplied from outside of the photoelectric conversion device is provided in a first multilayer wiring layer or a second multilayer wiring layer. The first electrode is not electrically connected to a second semiconductor layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to the structure of a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] There is known a photoelectric conversion device that can detect weak light at the single-photon level by utilizing avalanche (electron avalanche) multiplication. Patent Document 1 discloses a photoelectric conversion device in which both a sensor chip in which a plurality of pixels are arranged and a circuit chip in which a circuit for signal processing is formed are electrically connected in a stacked structure. It is disclosed that an avalanche diode that causes charge avalanche multiplication is used for the pixels in the sensor chip of this photoelectric conversion device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, no consideration has been given to the wiring when supplying a high voltage for driving the avalanche diode in the stacked structure, and the reliability of the photoelectric conversion device has not been sufficiently ensured.

Means for Solving the Problems

[0005] The photoelectric conversion device according to the present invention includes a first chip having a first semiconductor layer provided with an avalanche diode and a first multilayer wiring layer, a second semiconductor layer provided with a signal processing unit for processing a signal from the avalanche diode, and a second chip having a second multilayer wiring layer, the first chip and the second chip are stacked, and a first voltage and a second voltage are supplied to the avalanche diode. The signal processing unit is supplied with a third voltage, and the potential difference between the first voltage and the third voltage is larger than the potential difference between the second voltage and the third voltage. A first electrode to which the first voltage is supplied from outside the photoelectric conversion device is provided in the first multilayer wiring layer or the second multilayer wiring layer, and the first electrode is not electrically connected to the second semiconductor layer.

Advantages of the Invention

[0006] According to the photoelectric conversion device of the present invention, it is possible to provide a photoelectric conversion device having an avalanche diode capable of ensuring reliability.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0008] A photoelectric conversion device according to an embodiment of the present invention will be described. Since the common reference numerals in each embodiment denote the same members or members having the same functions and effects, the description may be omitted. In addition, the configurations described in each embodiment can be mutually replaced with the configurations described in other embodiments.

[0009] [First Embodiment] FIG. 1(A) is a diagram showing the configuration of a stacked photoelectric conversion device according to an embodiment of the present invention. The photoelectric conversion device 1010 is configured by stacking and electrically connecting two chips, a sensor chip 11 and a circuit chip 21.

[0010] A pixel region 12 is arranged in the sensor chip 11, and a circuit region 22 for processing the signal detected in the pixel region 12 is arranged in the circuit chip 21.

[0011] FIG. 1(B) is an arrangement diagram of the sensor chip 11. Pixels 100 having a photoelectric conversion unit 101 for converting light into an electrical signal are two-dimensionally arranged to form a pixel region 12. The pixel 100 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it is not necessarily required to form an image. That is, the pixel 100 may be a pixel for measuring the arrival time and the amount of light of the light.

[0012] FIG. 1(C) is a configuration diagram of the circuit chip 21. It has a signal processing unit 102 for processing the charges photoelectrically converted by the photoelectric conversion unit 101 in FIG. 1(B), a control pulse generation unit 109, a horizontal scanning circuit unit 104, signal lines 107, and a vertical scanning circuit unit 103.

[0013] The photoelectric conversion unit 101 in FIG. 1(B) and the signal processing unit 102 in FIG. 1(C) are electrically connected via connection wirings provided for each pixel.

[0014] The vertical scanning circuit unit 103 receives the control pulses supplied from the control pulse generation unit 109 and supplies control pulses to each pixel. Logic circuits such as a shift register and an address decoder are used for the vertical scanning circuit unit 103.

[0015] The signals output from the photoelectric conversion unit 101 of each pixel are processed by the signal processing unit 102. The signal processing unit 102 is provided with a counter and a memory, and digital signals are held in the memory.

[0016] The horizontal scanning circuit unit 104 inputs control pulses for sequentially selecting each column to the signal processing unit 102 in order to read signals from the memories of the pixels in which digital signals are held.

[0017] Signals are output from the signal processing unit 102 of the pixels selected by the vertical scanning circuit unit 103 to the signal lines 107 and 105 for the selected columns.

[0018] The signals output to the signal line 105 are output to a recording unit or a signal processing unit outside the photoelectric conversion device 1010 via the output circuit 108.

[0019] In FIG. 1(B), the arrangement of the pixels 100 in the pixel region 12 may be arranged in a one-dimensional manner. Also, the vertical scanning circuit unit 103 and the horizontal scanning circuit unit 104 may divide the circuit region 22 into a plurality of regions and arrange them for each region. The functions of the signal processing unit 102 do not necessarily have to be provided one by one for all the pixels 100. For example, one signal processing unit 102 may be shared by a plurality of pixels 100, and signal processing may be performed sequentially.

[0020] FIG. 2 is an example of a block diagram including the equivalent circuits of FIGS. 1(B) and 1(C). In FIG. 2, a photoelectric conversion unit 101 having a photodiode 201 is provided on a sensor chip 11, and the other members are provided on a circuit chip 21.

[0021] The photodiode 201 generates a pair of charges corresponding to incident light by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the photodiode 201. Also, a voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the photodiode 201. Although not shown, the voltage VH (second voltage) is also supplied to a circuit provided on the circuit chip 21. A reverse bias voltage is supplied to the anode and cathode of the photodiode 201 such that the photodiode 201 becomes an avalanche diode. By supplying such a voltage, the charges generated by the incident light cause avalanche multiplication, and an avalanche current is generated. When a reverse bias voltage is supplied, when the potential difference between the anode and cathode is greater than the breakdown voltage, the avalanche diode operates in Geiger mode. For example, the voltage VL (first voltage) is -30 V, and the voltage VH (second voltage) is 1.1 V.

[0022] The quench element 202 is connected to a power supply that supplies the voltage VH and the photodiode 201. The quench element 202 has a function of replacing a change in the avalanche current generated in the photodiode 201 with a voltage signal. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has a function of suppressing the voltage supplied to the photodiode 201 to suppress avalanche multiplication (quench operation). The photodiode 201 provided on the sensor chip 11 and the quench element 202 provided on the circuit chip 21 are electrically connected via connection wirings provided for each pixel.

[0023] The signal processing unit 102 includes a waveform shaping unit 203, a counter circuit 209, and a selection circuit 206. In this specification, the signal processing unit 102 may have any one of the waveform shaping unit 203, the counter circuit 209, and the selection circuit 206. For example, the counter circuit 209 is also the signal processing unit 102.

[0024] The waveform shaping unit 203 shapes the potential change at the cathode of the photodiode 201 obtained during photon detection and outputs a pulse signal. As the waveform shaping unit 203, for example, an inverter circuit is used. In FIG. 2, an example using one inverter is shown as the waveform shaping unit 203, but a circuit in which a plurality of inverters are connected in series may also be used, or other circuits having a waveform shaping effect may be used.

[0025] The counter circuit 209 counts the pulse signal output from the waveform shaping unit 203. When the counter circuit 209 is, for example, an N-bit counter (N: a positive integer), it can count the pulse signals caused by single photons up to approximately 2 to the power of N at most. The counted signal is held as the detected signal. Also, when the control pulse pRES is supplied via the drive line 207, the signal held in the counter circuit 209 is reset.

[0026] The selection circuit 206 is supplied with a control pulse pSEL from the vertical scanning circuit unit 103 in FIG. 1(C) via the drive line 208 in FIG. 2 (not shown in FIG. 1(C)), and switches the electrical connection and disconnection between the counter circuit 209 and the signal line 107. The selection circuit 206 includes, for example, a buffer circuit for outputting a signal.

[0027] A switch such as a transistor may be arranged between the quenching element 202 and the photodiode 201, or between the photoelectric conversion unit 101 and the signal processing unit 102 to switch the electrical connection. Similarly, the supply of the voltage VH or the voltage VL supplied to the photoelectric conversion unit 101 may be electrically switched using a switch such as a transistor.

[0028] In the pixel region 12 where a plurality of pixels are arranged in a matrix, an imaging image may be acquired by a rolling shutter operation in which the count of the counter circuit 209 is sequentially reset for each row and the signals held in the counter circuit 209 are sequentially output for each row. Alternatively, an imaging image may be acquired by a global electronic shutter operation in which the counts of the counter circuits 209 for all pixel rows are reset simultaneously and the signals held in the counter circuits 209 are sequentially output for each row. When performing the global electronic shutter operation, it is preferable to provide means for switching between the case where the counter circuit 209 performs counting and the case where it does not. The switching means is, for example, the switch described above.

[0029] In this embodiment, a configuration using the counter circuit 209 is shown. However, instead of the counter circuit 209, a time-to-digital converter (hereinafter referred to as TDC) and a memory may be used to form a photoelectric conversion device 1010 that acquires pulse detection timing. At this time, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC. A control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 103 in FIG. 1(C) via a driving line for measuring the timing of the pulse signal. The TDC acquires, as a digital signal, a signal when the input timing of the signal output from each pixel via the waveform shaping unit 203 is a relative time with respect to the control pulse pREF.

[0030] (Cross-sectional view of the photoelectric conversion device according to this embodiment: FIG. 3) FIG. 3 is a cross-sectional view of the photoelectric conversion device of this embodiment. This embodiment has a structure in which a first chip 301 and a second chip 401 are stacked and electrically connected.

[0031] (Configuration of the first chip 301) The first chip 301 is provided with a pixel region 521. The second chip 401 is provided with a circuit region 531 that processes the signals detected in the pixel region 521. The first chip 301 and the second chip 401 respectively correspond to the sensor chip 11 and the circuit chip 21 in FIG. 1(A).

[0032] The first chip 301 is composed of a semiconductor layer 311 (first semiconductor layer) and a wiring layer 312 (first wiring layer). With the light incident surface of the first chip 301 being surface 313 (first surface) and the surface opposite to surface 313 being surface 314 (second surface), the following description will be given.

[0033] In the semiconductor layer 311 of the first chip 301, a first semiconductor region 321 of the first conductivity type and a second semiconductor region 322 of the second conductivity type are arranged. The first semiconductor region 321 and the second semiconductor region 322 form a PN junction and become an avalanche diode 324.

[0034] Here, among the charge pairs generated in the photoelectric conversion unit, a semiconductor region in which the charge used as the signal charge has majority carriers is called a semiconductor region of the first conductivity type. Also, a semiconductor region in which the charge not used as the signal charge has majority carriers is called a semiconductor region of the second conductivity type. For example, when electrons are used as the signal charge, the semiconductor region of the first conductivity type is composed of an n-type semiconductor, and the semiconductor region of the second conductivity type is composed of a p-type semiconductor. When holes are used as the signal charge, it is the reverse. In this embodiment, it will be described assuming that electrons are used as the signal charge.

[0035] At both ends of the first semiconductor region 321, a third semiconductor region 323 of the first conductivity type or the second conductivity type for relaxing the electric field concentration is arranged. At this time, the impurity concentration of the third semiconductor region 323 is made lower than the impurity concentration of the first semiconductor region 321. For example, when the impurity concentration of the first semiconductor region 321 is 6.0×10 18 [atms / cm3] or more, the impurity concentration of the third semiconductor region 323 is 1.0×10 16 [atms / cm3] or more and 1.0×10 18 [atms / cm3] or less.

[0036] In a region on the side of surface 313 deeper than the second semiconductor region 322, a fourth semiconductor region 325 of the second conductivity type is disposed. Further, between adjacent pixels, a fifth semiconductor region 326 of the second conductivity type is disposed as an inter-pixel isolation region, and in a region on the side of surface 313 deeper than the fourth semiconductor region 325, a sixth semiconductor region 327 of the second conductivity type is disposed.

[0037] Here, the impurity concentrations of the fifth semiconductor region 326 and the sixth semiconductor region 327 are made higher than the impurity concentration of the fourth semiconductor region 325. Thereby, the charges photoelectrically converted in the fourth semiconductor region 325 can be collected by the avalanche diode 324 without leaking into adjacent pixels and can be avalanche amplified.

[0038] On the interface on the side of surface 313 of the first chip 301, a pinning film 341 for suppressing the dark current generated at the chip interface is disposed.

[0039] In the wiring layer 312 of the first chip 301, a multilayer wiring layer 331 (first multilayer wiring layer) is disposed. This multilayer wiring layer 331 is, for example, a wiring layer for applying an anode potential to the avalanche diode 324 or a wiring layer for applying a cathode potential. The signal detected by the avalanche diode 324 is sent to the second chip 401 via the multilayer wiring layer 331 and the junction 332 (first junction).

[0040] At the bottom of the pad opening 501 (first opening), a pad electrode 511 (first electrode) is provided. The pad opening 501 is an opening for exposing the pad electrode 511 in order to conduct the pad electrode 511 and an external power source. The bottom of the pad opening 501 is provided between the surface 313 (first surface) and the surface 314 (second surface) of the first chip 301. A voltage necessary for causing avalanche multiplication at the junction of the first semiconductor region 321 of the first conductivity type and the second semiconductor region 322 of the second conductivity type is applied to the pad electrode 511 (first electrode) via wire bonding. When the uppermost layer of the multilayer wiring layer 331 is the pad electrode 511, the uppermost layer of the multilayer wiring layer 331 may be formed of aluminum wiring and the other wiring layers may be formed of copper wiring.

[0041] The trench oxide film 541 is disposed on the semiconductor layer 311. A semiconductor chip having various circuits and pixels needs to protect the elements from moisture and ions that enter from the atmosphere around the semiconductor chip. Therefore, in order to protect against moisture and ions that enter from the pad opening 501 and the like, the trench oxide film 541 is disposed on the semiconductor layer 311 around the pad opening 501. Also, the trench oxide film 541 is disposed on the semiconductor layer 311 around the pad openings 502 and 503, which will be described later. In order to enhance the moisture resistance, metal wiring may be disposed instead of or in addition to the trench oxide film. By this metal wiring, the elements can be protected from moisture and ions that enter the wiring layer.

[0042] (Configuration of the second chip 401) The second chip 401 has a semiconductor layer 411 (second semiconductor layer) and a wiring layer 412 (second wiring layer). In the second chip 401, the side facing the first chip 301 is defined as the surface 414 (third surface), and the surface opposite to the surface 414 is defined as the surface 413 (fourth surface), and the following description will be made.

[0043] A circuit for processing the signal sent from the first chip 301 is disposed in the semiconductor layer 411 of the second chip 401. Specifically, a well region 422, a gate electrode 423, and a source / drain region 424 are disposed to form one MOS transistor 425. An example of the MOS transistor 425 disposed in the second chip 401 is a quench element. The quench element corresponds to the element 202 in FIG. 2 and functions as a load circuit when the charge photoelectrically converted is avalanche multiplied. It has the function of suppressing the voltage supplied to the avalanche diode 324 and suppressing the avalanche multiplication as a quenching operation.

[0044] An element isolation region 421 is disposed between adjacent MOS transistors. Examples of the element isolation region 421 include LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), and the like.

[0045] The joint 432 (second joint) arranged in the wiring layer 412 of the second chip 401 contacts the joint 332 (first joint) of the first chip 301 and has the role of sending the output of the avalanche diode 324 of the first chip 301 to the second chip 401. This joint is a metal wiring such as a copper wiring.

[0046] A multilayer wiring layer 431 (second multilayer wiring layer) is arranged in the wiring layer 412 of the second chip 401. This multilayer wiring layer 431 is, for example, a wiring for transmitting a signal sent from the first chip 301 to a processing circuit of the second chip 401, a power supply wiring for driving the signal processing unit 102 mounted on the second chip 401, and a ground wiring.

[0047] A ground region 441 is arranged in the semiconductor layer 411 of the second chip 401. Supply of the voltage of the ground potential (ground voltage; third voltage) to the ground region 441 is performed through a pad electrode 513 (third electrode) arranged at the bottom of a pad opening 503 (third opening). The bottom of the pad opening 503 is provided between the surface 414 (third surface) and the surface 413 (fourth surface) of the second chip 401. The third voltage is, for example, 0V. In FIG. 3, although the voltage applied from the pad electrode 513 (third electrode) is supplied to the ground region 41, it is not always necessary to provide the ground region 411. In this case, the voltage applied from the pad electrode 513 (third electrode) is directly supplied to other circuit elements.

[0048] Also, a predetermined potential is supplied to the drain electrode of the MOS transistor 425 disposed on the second chip 401 through the pad electrode 512 (second electrode) disposed at the bottom of the pad opening 502 (second opening). The bottom of the pad opening 502 is provided between the surface 414 (third surface) and the surface 413 (fourth surface) of the second chip 401. As described above, the MOS transistor 425 is, for example, a quench element that functions as a load circuit during signal multiplication by avalanche multiplication. In this case, the predetermined potential, the voltage VH (second voltage), is, for example, 1.1 V. Since the voltage VL (first voltage) is, for example, -30 V, the potential difference between the voltage VL (first voltage) and the voltage VH (second voltage) is larger than the potential difference between the voltage VH (second voltage) and the voltage of the ground potential (third voltage). Also, the potential difference between the voltage VL (first voltage) and the voltage of the ground potential (third voltage) is larger than the potential difference between the voltage VH (second voltage) and the voltage of the ground potential (third voltage).

[0049] FIG. 4(A) shows a plan view when viewed in a plan view of the broken line AA' in FIG. 3. The plan view is an arrangement when the photoelectric conversion device 1010 is viewed from a direction (the normal direction of the main surface) perpendicular to the main surface of the semiconductor layer 311 or 411. When viewed in a plan view, overlapping members shall be assumed to be visible through.

[0050] In FIG. 4(A), within the pixel region 521, the bonding portions 332 for sending the signals generated in each pixel to the second chip 401 are two-dimensionally arranged. That is, the plurality of bonding portions 332 are arranged over both the first direction 550 (row direction) and the second direction 560 (column direction) orthogonal to the first direction 550. Outside the pixel region 521, a plurality of pad electrodes 511, 512, 513 are arranged.

[0051] In the second direction 560 (column direction), the length of each of the pad electrodes 511, 512, and 513 is greater than the length of the joint portion 332. That is, corresponding to the joint portions 332 provided in a plurality of rows (two rows in FIG. 4(A)), one pad electrode is provided. This is because the potential supplied from each pad electrode can be configured to be commonly supplied to the pixels in a plurality of rows. Also, if one pad electrode is arranged corresponding to one row, it is necessary to arrange the pad electrodes for each pixel pitch, which is not suitable for miniaturization.

[0052] Also, in FIG. 4(A), in the first direction 550 (row direction) as well, the length of each of the pad electrodes 511, 512, and 513 is greater than the length of the joint portion 332. As a result, the area of each of the pad electrodes 511, 512, and 513 is larger than the area of the joint portion 332.

[0053] Furthermore, in FIG. 4(A), instead of arranging one pad electrode for the joint portions 332 of all rows, one pad electrode is arranged for the joint portions 332 of a predetermined plurality of rows less than all rows. In the present embodiment, since the pixel portion includes an avalanche diode, an avalanche current will flow through the pad electrode that applies a potential to the pixel. If one pad electrode is arranged for all rows, there is a possibility of exceeding the limit of the allowable current amount that can flow through one pad electrode. Therefore, one pad electrode is provided for the joint portions of a predetermined number of rows that is not all rows.

[0054] Note that in FIG. 4(A), an example is shown in which the length of the pad electrode is made greater than the length of the joint portion in both the first direction 550 and the second direction 560. However, the pitch may be increased by making the length greater in either one of the directions.

[0055] Also, in FIG. 4(A), one pad electrode is arranged for a plurality of rows, but it may be configured to arrange one pad electrode for a plurality of columns.

[0056] Furthermore, in FIG. 4(A), the pad electrodes 511 are aggregated on the right side of the pixel region, and the pad electrodes 512 and 513 are aggregated and arranged on the left side of the pixel region. On the other hand, as shown in FIG. 4(B), units composed of the pad electrodes 511, 512, and 513 may be arranged on each of the right and left sides of the pixel region. The avalanche-multiplied charges (electrons and holes) of each pixel are, for example, collected by the pad electrode 512 for electrons and the pad electrode 511 for holes. For example, in FIG. 4(A), assuming that electrons and holes are generated from the upper left pixel in the pixel region, the electrons are immediately collected by the pad electrode 512 arranged on the left side, while the holes are collected by the pad electrode 511 arranged on the right side after a predetermined time has elapsed. In this case, especially for holes, until they are collected by the pad electrode 511 arranged on the right side, the avalanche charges are integrated for each pixel, which causes a voltage drop. On the other hand, in FIG. 4(B), since the pad electrodes 511 and 512 are arranged on both the right and left sides, both the avalanche-multiplied electrons and holes are collected in a short time, and the voltage drop as described above is less likely to occur. According to the arrangement shown in FIG. 4(B), there is an advantage that the occurrence of shading can be suppressed.

[0057] A voltage VH (second voltage) is supplied from the pad electrode 512 to the first semiconductor region 321 of the first conductivity type of the avalanche diode 324 disposed on the first chip 301. For this voltage supply, the MOS transistor 425, the multilayer wiring layer 431 of the second chip, the joint portion 432 of the second chip, the joint portion 332 of the first chip, and the multilayer wiring layer 331 of the first chip are interposed. Further, a voltage VL (first voltage) is supplied to the second semiconductor region 322 of the second conductivity type via the pad electrode 511 disposed on the first chip, the multilayer wiring layer 331, the fifth semiconductor region 326 of the second conductivity type, and the fourth semiconductor region 325 of the second conductivity type. It is assumed that the voltage difference between the voltage VL (first voltage) and the voltage VH (second voltage) applies a sufficient electric field to cause avalanche multiplication at the junction between the first semiconductor region 321 of the first conductivity type and the second semiconductor region 322 of the second conductivity type. The required voltage difference is, for example, 6V or more, and in the above, an example of 31.1V has been described.

[0058] Incidentally, in order to increase the integration degree of the processing circuit, it is necessary to arrange fine transistors with a low drive voltage in the circuit region 531 of the second chip. On the other hand, the voltage VL (first voltage) applied to the pad electrode 511 is a voltage required only for the first chip 301 provided with the avalanche photodiode, and there is no need to supply it to the circuit region 531 of the second chip. Therefore, in the present embodiment, the pad electrode 511 is configured not to be electrically connected to the semiconductor layer 411 of the second chip 401. Specifically, the wiring electrically connected to the pad electrode 511 is configured not to cross the boundary of the bonding surface between the first chip 301 and the second chip 401. Thereby, a decrease in the reliability of the circuit region 531 of the second chip can be suppressed.

[0059] Also, the potential applied to the pad electrode 512 is supplied not only to the MOS transistor 425 but also to various processing circuits arranged in the second chip 401. When the functions required for the processing circuit increase and the number of elements mounted on the second chip 401 increases, high speed may become an issue. In this case, as shown in FIG. 3, it is preferable to arrange the pad electrode 512 in the second chip 401 and supply the potential rather than arranging the pad electrode 512 in the first chip 301 and supplying the potential through the joint. With this configuration, the propagation delay due to the wiring can be reduced, so that various processing circuits arranged in the second chip 401 can operate at a higher speed.

[0060] Also, the pad electrode 511 arranged in the first chip 301 is arranged in a wiring layer having the same height as the uppermost layer wiring of the multilayer wiring layer 331 of the first chip 301. The pad electrodes 512 and 513 arranged in the second chip 401 are arranged in a wiring layer having the same height as the uppermost layer wiring of the multilayer wiring layer 431 of the second chip. In this specification, the multilayer wiring layers 331 and 431 do not include the joints 332 and 432. Thereby, the step difference of the pad electrodes arranged in the first chip 301 and the second chip 401 is reduced, and the etching process at the time of pad opening can be facilitated. Further, according to this configuration, the formation of wire bonding at the pad opening can be facilitated.

[0061] [Second Embodiment] FIG. 5 is a cross-sectional view of a photoelectric conversion device according to the second embodiment. The difference from the first embodiment is that the pad electrodes 512 and 513 are arranged on the first chip 301, and a potential is supplied to the second chip through the bonding portions 333 and 433. The description of the same members as those in the first embodiment will be omitted.

[0062] As shown in FIG. 3, in the first embodiment, since the depths of the pad opening 501 and the pad openings 502 and 503 are different, it is necessary to apply etching conditions and wire bonding conditions optimal for each pad opening depth. On the other hand, in the second embodiment shown in FIG. 5, the pad electrodes 511, 512, and 513 are formed on the first chip 301. That is, the bottoms of the pad openings 501, 502, and 503 are provided between the surface 313 (first surface) and the surface 314 (second surface) of the first chip 301. According to this configuration, the depths of the pad openings 501, 502, and 503 can be made uniform as compared with the first embodiment. Therefore, it is not necessary to optimize the etching conditions and wire bonding conditions at the time of forming the pad openings for each pad.

[0063] The pad electrodes 511, 512, and 513 are preferably provided in the same wiring layer among the multilayer wiring layers 331 of the first chip 301. Specifically, in FIG. 5, the pad electrodes 511, 512, and 513 are provided in the uppermost layer of the multilayer wiring layer 331. Thereby, since the depths of the respective pad openings are the same, the etching conditions when forming the pad openings and the conditions when forming wire bonding can be made the same, and these can be formed in the same process.

[0064] In FIG. 5, the pad electrodes 512 and 513 and the bonding portion 333 are connected by a plurality of via plugs. That is, one pad electrode and one bonding portion are connected by a plurality of via plugs. Similarly, the wiring provided in the uppermost layer of the multilayer wiring layer 431 provided on the second chip 401 and the bonding portion 433 are connected by a plurality of via plugs. Thereby, the electrical resistance can be reduced, and the signal propagation delay can be suppressed.

[0065] Incidentally, as described in the first embodiment, among the voltages for avalanche multiplying the avalanche diode 324, a voltage VL (first voltage) is applied to the pad electrode 511 of the first chip. Since this voltage is routed through the multilayer wiring layer 331 provided in the first chip 301, it is not supplied to the circuit region 531 of the second chip 401. That is, it is possible to suppress a decrease in the reliability of the circuit region 531 disposed in the second chip 401.

[0066] Note that since the plan view including the broken line AA' in FIG. 5 is equivalent to FIG. 3, a detailed description thereof will be omitted.

[0067] As described above, in the second embodiment, it is possible to suppress a decrease in the reliability of the circuit region 531 of the second chip 401. In addition, it is possible to achieve facilitation of the formation processes of the pad opening and wire bonding.

[0068] [Third Embodiment] FIG. 6 is a cross-sectional view of a photoelectric conversion device according to the third embodiment. The difference from the first embodiment is that the pad electrodes 511 are disposed on the second chip 401, and a potential is supplied to the first chip 301 via the bonding portions 434 and 334. Description of the same members as in the first embodiment will be omitted.

[0069] In the first embodiment, since the depths of the pad opening 501 and the pad openings 502 and 503 are different, it is necessary to apply etching conditions and wire bonding conditions optimal for each pad opening depth. On the other hand, in the third embodiment shown in FIG. 6, the pad electrodes 511, 512, and 513 are formed on the second chip 401. That is, the bottoms of the pad openings 501, 502, and 503 are provided between the surface 414 (third surface) and the surface 413 (fourth surface) of the second chip 401. According to this configuration, it is possible to make the depths of the pad openings 501, 502, and 503 uniform as compared with the first embodiment. Therefore, it is not necessary to optimize the etching conditions and wire bonding conditions at the time of forming the pad openings for each pad.

[0070] As described in the first embodiment, the pad electrode 512 is arranged on the second chip 401, and its potential is supplied not only to the MOS transistor 425 but also to various processing circuits mounted on the second chip 401. Further, when the functions required for the processing circuits increase and the number of elements mounted on the second chip 401 increases, high speed becomes an issue. In this case, as shown in FIG. 6, it is preferable to arrange the pad electrode 512 on the second chip 401 and supply the potential rather than arranging the pad electrode 512 on the first chip 301 and supplying the potential through the bonding portion. With this configuration, the propagation delay due to wiring can be reduced, so that the various processing circuits arranged on the second chip 401 can operate at a higher speed.

[0071] Also, in the third embodiment, the pad electrode 511 is configured not to be electrically connected to the semiconductor layer 411 of the second chip 401. Thereby, deterioration of the reliability of the circuit region 531 of the second chip can be avoided.

[0072] FIG. 7 is a plan view when viewed in a plan view of the broken line AA' in FIG. 6. In the pixel region 521, bonding portions 332 for sending signals generated in each pixel to the second chip 401 are arranged two-dimensionally. Outside the pixel region 521, pad electrodes 511, 512, and 513 arranged on the second chip are arranged. A bonding portion 334 for supplying the voltage applied to the pad electrode 511 arranged on the second chip 401 to the pixel region 521 of the first chip 301 is arranged. In both the first direction 550 and the second direction 560, the length of the bonding portion 334 is larger than the length of the bonding portion 332. Therefore, the area of the bonding portion 334 is larger than the area of the bonding portion 332. The description regarding FIGS. 4(A) and (B) is also applicable to FIG. 7.

[0073] As described above, in the third embodiment, it is possible to increase the speed of various processing circuits mounted on the second chip 401 while suppressing a decrease in the reliability of the circuit region 531 of the second chip. Further, it is possible to achieve facilitation of the formation process of the pad opening and wire bonding.

[0074] [Fourth Embodiment] FIG. 8 is a cross-sectional view of a photoelectric conversion device according to a fourth embodiment. The difference from the first embodiment is that a through-silicon via (TSV) is used instead of wire bonding. Hereinafter, the description of the same members as those in the first embodiment will be omitted.

[0075] Specifically, the wire bonding wiring provided at the bottom of the pad opening 501 in the first embodiment corresponds to the through electrode 504 in the fourth embodiment. Similarly, the wire bonding wiring at the bottom of the pad opening 502 corresponds to the through electrode 505, and the wire bonding wiring at the bottom of the pad opening 503 corresponds to the through electrode 506.

[0076] The pad electrode 511 (first electrode) in the first embodiment corresponds to the electrode 514 (first electrode) in the fourth embodiment. Similarly, the pad electrode 513 (second electrode) corresponds to the electrode 516 (second electrode), and the pad electrode 512 (third electrode) corresponds to the electrode 515. That is, these electrodes are common in that they are electrodes provided in the multilayer wiring layer 431 (second multilayer wiring layer) and are electrodes to which a voltage is supplied from the outside of the photoelectric conversion device.

[0077] In the fourth embodiment, in order to conduct the electrode 514 and an external power supply, the bottom of the opening (first opening) formed to expose the electrode 514 is provided between the surface 313 (first surface) and the surface 314 (second surface) of the first chip 301. This point is also common to the first embodiment. Similarly, the bottoms of the openings (second opening and third opening) formed to expose the electrodes 516 and 515 are provided between the surface 414 (third surface) and the surface 413 (fourth surface) of the second chip 401. This point is also common to the first embodiment. In the present specification, even when an electrode is filled after forming an opening (trench), the location where the opening was formed may be referred to as an "opening".

[0078] When the electrode structure is used as wire bonding wiring as in the first to third embodiments, an extra space for mounting wires is required with respect to the chip size, making it difficult to miniaturize the package size. On the other hand, in the case of through electrodes, since the through electrodes and the package substrate are connected via bumps or the like, it is possible to make the chip size and the package size substantially the same size. Therefore, compared with wire bonding wiring, miniaturization of the package size is advantageous. Similar to the first embodiment, the potential applied to the through electrode 504 is supplied to the pixel region 521 of the first chip 301 via the electrode 514. Also, the potentials applied to the through electrodes 505 and 506 are supplied to the semiconductor layer 411 corresponding to the circuit region 531 of the second chip 401 via the electrodes 515 and 516, respectively. On the other hand, the potential applied to the through electrode 504 is not supplied to the circuit region 531 of the second chip 401. Therefore, similar to the first embodiment, it is possible to suppress a decrease in the reliability of the circuit region 531 arranged in the second chip 401. Also, since the through electrode 505 is arranged in the second chip 401, it is possible to operate various processing circuits arranged in the second chip 401 at a higher speed.

[0079] Also, the electrode 514 arranged in the first chip 301 is arranged in a wiring layer having the same height as the uppermost layer wiring of the multilayer wiring layer 331 of the first chip 301, and the electrodes 515 and 516 arranged in the second chip 401 are arranged in a wiring layer having the same height as the uppermost layer wiring of the multilayer wiring layer 431 of the second chip 401.

[0080] The through electrode is formed by forming an opening (trench) that penetrates the semiconductor layer 411 by etching and then filling the trench with a metal that becomes the electrode material. When forming trenches corresponding to a plurality of through electrodes by etching, it is simpler in terms of the process if the step difference in trench depth is small. Therefore, as described above, by arranging the electrodes in contact with the through electrodes in a wiring layer having the same height as the uppermost layer wiring of each chip, the formation process of the through electrodes can be facilitated.

[0081] FIG. 9 is a plan view when viewed in a plan view of the broken line AA' in FIG. 8. In the pixel region 521, the joints 332 for sending the signals generated by each pixel to the second chip 401 are arranged two-dimensionally. Outside the pixel region 521, the electrodes 514 in the first chip 301 and the electrodes 515 and 516 in the second chip 401 are arranged respectively. The description regarding FIGS. 4(A) and (B) is also applicable to FIG. 9.

[0082] As described above, in the fourth embodiment, it is possible to achieve miniaturization of the package size, suppression of a decrease in reliability with respect to the circuit region 531 of the second chip 401, and speeding up of various processing circuits mounted on the second chip 401.

[0083] [Fifth Embodiment] FIG. 10 is a cross-sectional view of the fifth embodiment. The difference from the fourth embodiment is that the electrodes 515 and 516 are arranged on the first chip 301. The description of the same members as in the first embodiment is omitted.

[0084] In the fourth embodiment, since the locations where the electrode 514 of the first chip and the electrodes 515 and 516 of the second chip are arranged are different, it is necessary to optimize the etching conditions during trench formation and the film formation conditions when embedding metal in the trench according to the locations of the respective electrodes. On the other hand, in the fifth embodiment, by arranging all the through electrodes 514, 515, and 516 on the first chip, it is not necessary to optimize the process conditions according to the locations where the respective electrodes are provided, and the process can be facilitated.

[0085] Also, the electrodes 514, 515, and 516 are preferably provided in the same wiring layer among the multilayer wiring layers 331 of the first chip 301. Specifically, in FIG. 10, the electrodes 514, 515, and 516 are provided in the uppermost layer of the multilayer wiring layer 331. As a result, the trench depths of the respective through electrodes are the same, so that the etching conditions when forming the trenches and the film formation conditions when embedding the metal serving as the electrode material in the trenches can be made the same, and these can be formed in the same process.

[0086] In FIG. 10, the electrodes 515 and 516 and the joint portion 335 are connected by a plurality of via plugs. That is, one electrode provided in the multilayer wiring layer and one joint portion are connected by a plurality of via plugs. Similarly, the wiring provided on the uppermost layer of the multilayer wiring layer 431 provided in the second chip 401 and the joint portion 433 are connected by a plurality of via plugs. As a result, the electrical resistance can be reduced, and the propagation delay of the signal can be suppressed.

[0087] Incidentally, as described in the first embodiment, among the voltages for avalanche multiplication of the avalanche diode 324, a voltage VL (first voltage) is applied to the electrode 514 of the first chip. Since this voltage is routed through the multilayer wiring layer 331 provided in the first chip 301, it is not supplied to the circuit region 531 of the second chip 401. That is, it is possible to suppress a decrease in the reliability of the circuit region 531 arranged in the second chip 401.

[0088] FIG. 11 is a plan view including the broken line AA' in FIG. 10. In the pixel region 521, joint portions 332 for sending signals generated in each pixel to the second chip 401 are two-dimensionally arranged. Outside the pixel region 521, the electrode 514 in the first chip 301, the electrodes 515 and 516 in the first chip 301, and the joint portion 335 for transmitting the applied potential of the electrode to the second chip are arranged. The description regarding FIGS. 4(A) and (B) is also applicable to FIG. 11.

[0089] As described above, in the fifth embodiment, it is possible to suppress a decrease in the reliability with respect to the circuit region 531 of the second chip 401. In addition, it is possible to achieve facilitation of the through electrode formation process.

[0090] [Sixth Embodiment] FIG. 12 is a cross-sectional view of a photoelectric conversion device according to the sixth embodiment. The difference from the fourth embodiment is that the through electrode 514 is arranged in the second chip 401. The description of the same members as in the fourth embodiment is omitted.

[0091] In the sixth embodiment, compared with the fourth embodiment, since the electrodes 514, 515, and 516 are arranged on the second chip, it is not necessary to optimize the etching conditions during trench formation and the film formation conditions during metal filling into the trenches according to the depth of each electrode, and the process can be simplified.

[0092] The depth at which the electrodes 514, 515, and 516 are arranged is desirably the same depth within the second chip 401. As a result, since the trench depths of the respective through electrodes are the same, the etching conditions during trench formation and the film formation conditions when embedding the metal serving as the electrode material into the trenches can be made the same.

[0093] Also, in the sixth embodiment, since the potential applied to the through electrode 504 is supplied to the first chip 301 via the joint portions 436 and 336, it is not supplied to the circuit region 531 of the second chip 401. Therefore, a decrease in the reliability of the circuit region 531 of the second chip can be suppressed.

[0094] The through electrode 515 is arranged on the second chip 401, and its potential is supplied not only to the MOS transistor 425 but also to various processing circuits mounted on the second chip 401. When the functions required for the processing circuits increase and the number of elements mounted on the second chip 401 increases, high speed becomes an issue. In that case, arranging the through electrode 515 on the second chip 401 and supplying the potential enables the various processing circuits arranged on the second chip to operate at a higher speed than arranging the through electrode 515 on the first chip 301 and supplying the potential via the joint portion. Note that since the plan view including the dashed line AA' in FIG. 12 is equivalent to FIG. 9, a detailed description thereof is omitted.

[0095] As described above, in the sixth embodiment, it is possible to achieve suppression of a decrease in reliability with respect to the circuit region 531 of the second chip 401, speeding up of various processing circuits mounted on the second chip 401, and simplification of the through electrode formation process.

[0096] [Seventh Embodiment] FIG. 13 is a regional view showing the configuration of the photoelectric conversion system 1200 according to the present embodiment. The photoelectric conversion system 1200 of the present embodiment includes a photoelectric conversion device 1204. The photoelectric conversion device 1204 can apply any of the photoelectric conversion devices described in the above embodiments. The photoelectric conversion system 1200 can be used, for example, as an imaging system. Specific examples of the imaging system include a digital still camera, a digital camcorder, a surveillance camera, and the like. In FIG. 13, an example of a digital still camera is shown as the photoelectric conversion system 1200.

[0097] The photoelectric conversion system 1200 shown in FIG. 13 includes a photoelectric conversion device 1204, a lens 1202 that forms an optical image of a subject on the photoelectric conversion device 1204, a diaphragm 1203 that variably controls the amount of light passing through the lens 1202, and a barrier 1201 that protects the lens 1202. The lens 1202 and the diaphragm 1203 are an optical system that condenses light on the photoelectric conversion device 1204.

[0098] The photoelectric conversion system 1200 includes a signal processing unit 1205 that processes an output signal output from the photoelectric conversion device 1204. The signal processing unit 1205 performs signal processing operations of performing various corrections and compressions on the input signal and outputting the result as necessary. The photoelectric conversion system 1200 further includes a buffer memory unit 1206 for temporarily storing image data, and an external interface unit (external I / F unit) 1209 for communicating with an external computer or the like. Further, the photoelectric conversion system 1200 includes a recording medium 1211 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1210 for recording or reading from the recording medium 1211. The recording medium 1211 may be built into the photoelectric conversion system 1200 or may be detachable. Also, the communication between the recording medium control I / F unit 1210 and the recording medium 1211 and the communication from the external I / F unit 1209 may be performed wirelessly.

[0099] Furthermore, the photoelectric conversion system 1200 includes an overall control and arithmetic unit 1208 that performs various operations and controls the entire digital still camera, and a timing generation unit 1207 that outputs various timing signals to the photoelectric conversion device 1204 and the signal processing unit 1205. Here, the timing signals and the like may be input from the outside, and the photoelectric conversion system 1200 may have at least the photoelectric conversion device 1204 and a signal processing unit 1205 that processes the output signal output from the photoelectric conversion device 1204.

[0100] The overall control and arithmetic unit 1208 and the timing generation unit 1207 may be configured to implement part or all of the control functions of the photoelectric conversion device 1204.

[0101] The photoelectric conversion device 1204 outputs an image signal to the signal processing unit 1205. The signal processing unit 1205 performs predetermined signal processing on the image signal output from the photoelectric conversion device 1204 and outputs image data. Also, the signal processing unit 1205 generates an image using the image signal. Further, the signal processing unit 1205 may perform a distance measurement operation on the signal output from the photoelectric conversion device 1204. The signal processing unit 1205 and the timing generation unit 1207 may be mounted on the photoelectric conversion device. That is, the signal processing unit 1205 and the timing generation unit 1207 may be provided on the chip on which the pixels are arranged. By configuring an imaging system using the photoelectric conversion device of each of the above-described embodiments, an imaging system capable of acquiring higher-quality images can be realized.

[0102] [Eighth Embodiment] The photoelectric conversion system and the moving body of this embodiment will be described with reference to FIGS. 14 and 15. FIG. 14 is a schematic diagram showing a configuration example of the photoelectric conversion system and the moving body according to this embodiment. FIG. 15 is a flowchart showing the operation of the photoelectric conversion system according to this embodiment. In this embodiment, an in-vehicle camera is shown as an example of the photoelectric conversion system.

[0103] FIG. 14 shows an example of a vehicle system and a photoelectric conversion system that performs imaging mounted thereon. The photoelectric conversion system 1301 includes a photoelectric conversion device 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of a subject on the photoelectric conversion device 1302. The photoelectric conversion device 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric conversion device 1302 is any one of the photoelectric conversion devices of the above-described embodiments. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric conversion device 1302. The function of the image preprocessing unit 1315 may be incorporated in the photoelectric conversion device 1302. At least two sets of the optical system 1314, the photoelectric conversion device 1302, and the image preprocessing unit 1315 are provided in the photoelectric conversion system 1301, and the output from each set of the image preprocessing unit 1315 is input to the integrated circuit 1303.

[0104] The integrated circuit 1303 is an integrated circuit for an imaging system application and includes an image processing unit 1304 including a memory 1305, an optical distance measurement unit 1306, a distance measurement calculation unit 1307, an object recognition unit 1308, and an abnormality detection unit 1309. The image processing unit 1304 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 1315. The memory 1305 stores the primary storage of the captured image and the defect positions of the captured pixels. The optical distance measurement unit 1306 performs focusing and distance measurement of the subject. The distance measurement calculation unit 1307 calculates distance measurement information from a plurality of image data acquired by the plurality of photoelectric conversion devices 1302. The object recognition unit 1308 recognizes subjects such as vehicles, roads, signs, and people. When the abnormality detection unit 1309 detects an abnormality in the photoelectric conversion device 1302, it reports the abnormality to the main control unit 1313.

[0105] Integrated circuit 1303 may be implemented by dedicatedly designed hardware, may be implemented by software modules, or may be implemented by a combination thereof. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc., or may be implemented by a combination thereof.

[0106] The main control unit 1313 comprehensively controls the operations of the photoelectric conversion system 1301, the vehicle sensor 1310, the control unit 1320, etc. It is also possible to adopt a method in which the photoelectric conversion system 1301, the vehicle sensor 1310, and the control unit 1320 do not have the main control unit 1313 and each has a communication interface, and each performs the transmission and reception of control signals via a communication network (for example, the CAN standard).

[0107] Integrated circuit 1303 has a function of receiving a control signal from the main control unit 1313 or transmitting a control signal and a set value to the photoelectric conversion device 1302 by its own control unit.

[0108] The photoelectric conversion system 1301 is connected to the vehicle sensor 1310 and can detect the running state of the host vehicle such as vehicle speed, yaw rate, and steering angle, as well as the state of the external environment of the host vehicle and other vehicles / obstacles. The vehicle sensor 1310 is also a distance information acquisition means for acquiring distance information to an object. In addition, the photoelectric conversion system 1301 is connected to a driving support control unit 1311 that performs various driving supports such as automatic steering, automatic cruise, and collision prevention functions. In particular, regarding the collision determination function, based on the detection results of the photoelectric conversion system 1301 and the vehicle sensor 1310, the collision estimation and the presence or absence of a collision with other vehicles / obstacles are determined. Thereby, avoidance control when a collision is estimated and activation of a safety device at the time of a collision are performed.

[0109] In addition, the photoelectric conversion system 1301 is also connected to an alarm device 1312 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, when the collision determination unit determines that there is a high possibility of a collision, the main control unit 1313 performs vehicle control such as applying brakes, returning the accelerator, suppressing engine output, etc., to avoid collisions and reduce damage. The alarm device 1312 warns the user by sounding an alarm such as a sound, displaying alarm information on a display screen of a display unit such as a car navigation system or a meter panel, or applying vibration to the seat belt or the steering wheel.

[0110] In this embodiment, the photoelectric conversion system 1301 captures images of the surroundings of the vehicle, for example, the front or the rear. FIG. 14(b) shows an example of the arrangement of the photoelectric conversion system 1301 when imaging the front of the vehicle with the photoelectric conversion system 1301.

[0111] The two photoelectric conversion devices 1302 are arranged in front of the vehicle 1300. Specifically, regarding the center line with respect to the advancing / retreating direction or the outer shape (for example, vehicle width) of the vehicle 1300 as the axis of symmetry, it is preferable for obtaining distance information between the vehicle 1300 and the subject and for determining the possibility of a collision that the two photoelectric conversion devices 1302 are arranged symmetrically with respect to the axis of symmetry. In addition, it is preferable that the photoelectric conversion device 1302 is arranged so as not to obstruct the driver's view when the driver visually recognizes the situation outside the vehicle 1300 from the driver's seat. The alarm device 1312 is preferably arranged so as to easily enter the driver's field of view.

[0112] Next, the fault detection operation of the photoelectric conversion device 1302 in the photoelectric conversion system 1301 will be described with reference to FIG. 15. The fault detection operation of the photoelectric conversion device 1302 is performed according to steps S1410 to S1480 shown in FIG. 15.

[0113] Step S1410 is a step of setting at the startup of the photoelectric conversion device 1302. That is, settings for the operation of the photoelectric conversion device 1302 are transmitted from the outside of the photoelectric conversion system 1301 (for example, the main control unit 1313) or from inside the photoelectric conversion system 1301, and the imaging operation and the fault detection operation of the photoelectric conversion device 1302 are started.

[0114] Next, in step S1420, a pixel signal is acquired from the effective pixels. Also, in step S1430, an output value from the failure detection pixels provided for failure detection is acquired. These failure detection pixels include a photoelectric conversion section, just like the effective pixels. A predetermined voltage is written to this photoelectric conversion section. The failure detection pixels output a signal corresponding to the voltage written to this photoelectric conversion section. Note that steps S1420 and S1430 may be reversed.

[0115] Next, in step S1440, a comparison is made between the output expected value of the failure detection pixels and the actual output value from the failure detection pixels. As a result of the comparison in step S1440, if the output expected value and the actual output value match, the process proceeds to step S1450, where it is determined that the imaging operation is being performed normally, and the processing steps proceed to step S1460. In step S1460, the pixel signals of the scanning line are transmitted to the memory 1305 for primary storage. Thereafter, the process returns to step S1420 to continue the failure detection operation. On the other hand, as a result of the comparison in step S1440, if the output expected value and the actual output value do not match, the processing steps proceed to step S1470. In step S1470, it is determined that there is an abnormality in the imaging operation, and an alarm is reported to the main control unit 1313 or the alarm device 1312. The alarm device 1312 causes the display unit to display that an abnormality has been detected. Thereafter, in step S1480, the photoelectric conversion device 1302 is stopped, and the operation of the photoelectric conversion system 1301 is terminated.

[0116] Note that in this embodiment, an example in which the flowchart is looped for each row has been illustrated, but the flowchart may be looped for every plurality of rows, or the failure detection operation may be performed for each frame. The alarm reporting in step S1470 may be notified outside the vehicle via a wireless network.

[0117] In addition, in this embodiment, control for not colliding with other vehicles has been described, but it is also applicable to control for automatically driving while following other vehicles, control for automatically driving so as not to deviate from the lane, and the like. Furthermore, the photoelectric conversion system 1301 can be applied not only to vehicles such as the host vehicle, but also to moving bodies (moving devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving bodies, but also to devices that widely utilize object recognition, such as advanced road traffic systems (ITS).

[0118] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which a part of the configuration of any one of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0119] Note that the above-described embodiments are merely specific examples for implementing the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features.

Explanation of Reference Numerals

[0120] 301 First chip 401 Second chip 324 Avalanche diode 521 Pixel region 531 Circuit region 501, 502, 503 Pad openings 511, 512, 513 Pad electrodes

Claims

1. A photoelectric conversion device, a first chip having a first semiconductor layer including an avalanche diode and a first multi-layer wiring layer; a second chip having a second semiconductor layer including a signal processing unit that processes a signal based on an output from the avalanche diode, and a second multilayer wiring layer; the first chip and the second chip are stacked and bonded together, the first chip has a first bonding portion; the second chip has a second joint portion in contact with the first joint portion; a first voltage and a second voltage are supplied to the avalanche diode; a third voltage is supplied to the signal processing unit; a potential difference between the first voltage and the third voltage is greater than a potential difference between the second voltage and the third voltage; a first electrode to which the first voltage is supplied from an outside of the first chip and the second chip is provided in the first multilayer wiring layer; a second electrode to which the second voltage is supplied from outside the first chip and the second chip is provided in the same wiring layer as the wiring layer in which the first electrode is provided, of the first multilayer wiring layer; the first voltage is not applied to a joint surface between the first chip and the second chip; The photoelectric conversion device, wherein the first electrode is not electrically connected to the second semiconductor layer.

2. 2. The photoelectric conversion device according to claim 1, wherein the first voltage is a negative voltage.

3. 3. The photoelectric conversion device according to claim 1, wherein a potential difference between the first voltage and the second voltage is greater than a breakdown voltage of the avalanche diode.

4. A photoelectric conversion device, a first chip having a first semiconductor layer with an avalanche diode; a second chip having a second semiconductor layer including a signal processing unit that processes a signal based on an output from the avalanche diode; the first chip and the second chip are stacked and bonded together, the first chip has a first bonding portion; the second chip has a second joint portion in contact with the first joint portion; The avalanche diode is supplied with a first voltage, which is a negative voltage, and a second voltage, which is a positive voltage; a first electrode to which the first voltage is supplied from an outside of the first chip and the second chip is provided between a surface of the first semiconductor layer and a bonding surface between the first chip and the second chip; a second electrode to which the second voltage is supplied from outside the first chip and the second chip is provided at the same height as the first electrode between a surface of the first semiconductor layer and the junction surface; the first voltage is not applied to the joining surface; The photoelectric conversion device, wherein the first electrode is not electrically connected to the second semiconductor layer.

5. the first chip has a first multi-layer wiring layer; 5. The photoelectric conversion device according to claim 4, wherein the second chip has a second multi-layer wiring layer.

6. a third voltage is supplied from outside the first chip and the second chip; 6. The photoelectric conversion device according to claim 5, wherein a potential difference between the first voltage and the third voltage is greater than a potential difference between the second voltage and the third voltage.

7. 7. The photoelectric conversion device according to claim 6, wherein a potential difference between the first voltage and the second voltage is greater than a breakdown voltage of the avalanche diode.

8. 8. The photoelectric conversion device according to claim 1, wherein a quench element for suppressing avalanche multiplication of the avalanche diode is disposed on the second chip.

9. The photoelectric conversion device according to any one of claims 1 to 3, 6 and 7, characterized in that a third electrode to which the third voltage is supplied from outside the first chip and the second chip is provided in the first multilayer wiring layer.

10. 10. The photoelectric conversion device according to claim 1, wherein the third voltage is a ground voltage.

11. a bottom of a first opening exposing the first electrode is provided between a first surface of the first chip and a second surface of the first chip opposite to the first surface; 11. The photoelectric conversion device according to claim 1, wherein a bottom of the second opening exposing the second electrode is provided between the first surface and the second surface.

12. the first opening and the second opening are formed through the second semiconductor layer, The photoelectric conversion device according to claim 11 , wherein the first opening and the second opening are filled with an electrode.

13. The photoelectric conversion device according to claim 12 , wherein the electrode is in contact with the first electrode at a bottom of the first opening, and is in contact with the second electrode at a bottom of the second opening.

14. the first chip has a first bonding portion; the second chip has a second joint portion in contact with the first joint portion; the avalanche diode is electrically connected to the quench element via the first junction and the second junction; The photoelectric conversion device according to claim 8 , wherein, in a plan view, a length of the first electrode in a predetermined direction is greater than a length of the first junction.

15. The photoelectric conversion device according to any one of claims 1 to 14, and a signal processing device that processes a signal output from the photoelectric conversion device.

16. 16. The photoelectric conversion system according to claim 15, wherein the signal processing device performs distance measurement and imaging based on the signal from the photoelectric conversion device.

17. The photoelectric conversion device according to any one of claims 1 to 14, a distance information acquisition means for acquiring distance information to an object from distance measurement information based on a signal from the photoelectric conversion device, A moving body further comprising a control means for controlling the moving body based on the distance information.

Images