Error correction method, error correction circuit, and communication system

Abstract

To provide an error correction method capable of suppressing an increase in processing delay and power consumption while maintaining correction capability.SOLUTION: An error correction method of the present invention extracts a predetermined number of correction candidate bits to be subject to error correction decoding based on likelihood information generated for each bit of encoded data before error correction, and performs error correction decoding processing on the extracted correction candidate bits. When the correction candidate bits are extracted, a plurality of low likelihood value data groups having different likelihood values that are equal to or less than a predetermined threshold are searched for, and the predetermined number of correction candidate bits are extracted.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to an error correction method, an error correction circuit, and a communication system for performing error correction using likelihood information. [Background technology]

[0002] In coherent optical communications, in order to improve transmission characteristics, distortion and frequency / phase fluctuations that occur during transmission are compensated for by digital signal processing, and to further improve transmission characteristics, an error correction function is provided between the transmitter and receiver in addition to the compensation function described above to reduce data errors in the transmission characteristics. With the error correction function, the transmitter applies error correction coding to the data, and the receiver applies error correction according to that coding, thereby improving transmission characteristics.

[0003] Well-known error correction codes include, for example, Hamming codes, BCH codes, Reed-Solomon codes, convolutional codes / Viterbi decoding, etc. In recent years, communication devices have become capable of complex and large-volume processing due to the development of CPU computing power, and therefore use high-performance error correction methods such as LDPC (low-density parity-check code).

[0004] In error correction processing using LDPC codes, etc., the correction capability can be improved by increasing the amount of calculation during decoding, but there is a problem that the processing delay and power consumption increase as the amount of calculation during decoding. Therefore, methods have been proposed for improving the correction capability while suppressing the increase in processing delay and power consumption (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 4766013 Summary of the Invention [Problem to be solved by the invention]

[0006] In a decoding method such as that in Patent Document 1, in which the encoded data is rearranged and decoded using likelihood information of the encoded data before decoding, it is possible to improve correction capability while suppressing increases in processing delay and power consumption. However, the amount of calculations increases when rearranging the encoded data using the likelihood information of the encoded data before decoding, which may result in a corresponding increase in processing delay and power consumption.

[0007] The present invention has been made to solve the above-mentioned problems, and aims to provide an error correction method, an error correction circuit, and a communication system that can suppress increases in processing delays and power consumption while maintaining correction capability. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, the error correction method of the present invention is an error correction method executed in an error correction circuit that performs error correction using likelihood information, and includes a correction candidate extraction step of extracting a predetermined number of correction candidate bits for error correction decoding based on likelihood information generated for each bit of encoded data before error correction, and an error correction decoding step of performing error correction decoding on the correction candidate bits extracted in the correction candidate extraction step, wherein the correction candidate extraction step includes a step of searching for a plurality of low likelihood value data groups having a likelihood value below a predetermined threshold and different likelihood values, and the search order in the encoded data when searching for each of the plurality of low likelihood value data groups is different.

[0009] In order to solve the above-mentioned problems, the error correction circuit of the present invention is an error correction circuit that performs error correction using likelihood information, and includes a correction candidate extraction circuit that extracts a predetermined number of correction candidate bits for error correction decoding based on likelihood information generated for each bit of encoded data before error correction, and an error correction decoding circuit that performs error correction decoding on the correction candidate bits extracted by the correction candidate extraction circuit, wherein the correction candidate extraction circuit searches for a plurality of low likelihood value data groups having a likelihood value below a predetermined threshold and having different likelihood values, and the search order in the encoded data when searching each of the plurality of low likelihood value data groups is different.

[0010] In order to solve the above-mentioned problems, the communication system of the present invention is a communication system comprising: a transmitting side device having an error correction encoding circuit that encodes transmission data and a transmitting module that transmits an optical signal modulated using the encoded data output from the error correction encoding circuit; and a receiving side device having a receiving module configured to demodulate the encoded data from the optical signal received from the transmitting side device and an error correction circuit configured to perform error correction on the demodulated encoded data, wherein the error correction circuit comprises a correction candidate extraction circuit that extracts a predetermined number of correction candidate bits to perform error correction decoding based on likelihood information generated for each bit of the encoded data before error correction, and an error correction decoding circuit that performs error correction decoding on the correction candidate bits extracted by the correction candidate extraction circuit, and the correction candidate extraction circuit has a likelihood value below a predetermined threshold and searches for a plurality of low likelihood value data groups having different likelihood values, and the search order in the encoded data when searching each of the plurality of low likelihood value data groups is different. Effect of the Invention

[0011] According to the present invention, it is possible to provide an error correction circuit that can suppress an increase in processing delay and power consumption while maintaining correction capability. [Brief description of the drawings]

[0012] [Figure 1]FIG. 1 is a diagram showing an example of the configuration of a communication system including an error correction circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of an error correction circuit according to an embodiment of the present invention. [Diagram 3] FIG. 3 is a diagram for explaining likelihood information according to an embodiment of the present invention. [Figure 4] FIG. 4 is an example of a table for determining a log-likelihood ratio according to the embodiment of the present invention. [Diagram 5] FIG. 5 is a flow diagram for explaining the operation of the error correction method according to the embodiment of the present invention. [Figure 6] FIG. 6 is a diagram for explaining the operation of the correction candidate extracting method according to the embodiment of the present invention. [Figure 7] FIG. 7 is a diagram for explaining the operation of the correction candidate extracting method according to the embodiment of the present invention. [Figure 8] FIG. 8 shows an example of the configuration of a conventional error correction circuit. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of an input signal to a correction candidate extraction circuit of an error correction circuit. [Figure 10] FIG. 10 is a diagram for explaining a correction candidate extraction method in a conventional correction candidate extraction circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described below.

[0014] <Summary of the Invention> An example of the configuration of an error correction circuit using likelihood information is shown in Fig. 8. The error correction circuit 100 is composed of a likelihood information generation circuit 40 that generates likelihood information for each bit of a main signal, which is encoded data before error correction, a correction candidate extraction circuit 50 that extracts a predetermined number of correction candidate bits for error correction decoding based on the likelihood information generated for each bit of the encoded data before error correction, and an error correction decoding circuit 60 that performs error correction decoding on the correction candidate bits extracted by the correction candidate extraction circuit 50.

[0015] <Likelihood information generation circuit> The likelihood information generating circuit 40 generates a likelihood value for each bit (or symbol) of the main signal, which is the input encoded data, and adds it to the main signal together with address position information indicating the address position of the main signal.

[0016] The correction candidate extraction circuit 50 extracts a predetermined number of correction candidate bits with low likelihood values ​​for performing error correction decoding, based on likelihood information generated for each bit of encoded data before error correction.

[0017] The error correction decoding circuit 60 performs error correction decoding on a predetermined number of correction candidate bits extracted by the correction candidate extraction circuit 50.

[0018] FIG. 9 is a diagram showing an example of the configuration of an input signal to the error correction candidate extraction circuit 50. in Each of the input signals is in It consists of a main signal of 128 bits and likelihood information. The likelihood information is the likelihood value of the main signal and the likelihood of each signal being N in 9, the likelihood value is a log likelihood ratio (LLR: Log Likelihood Ratio).

[0019] In the configuration example of Figure 9, N in Each of the input signals is a 1-bit main signal, N LLR Bit log-likelihood ratio (LLR), N ad Bit (N ad =log 2 N in) address location information. The size of the LLR is N LLR It is expressed in stages of powers. For example, N LLR When the number of bits is 3, the magnitude of the LLR is expressed in eight stages from 0 to 7.

[0020] The correction candidate extraction circuit 50 in For each likelihood information, select n pieces of LLR in ascending order (n is an integer greater than 1, n <N in ) and outputs it as a correction candidate to the error correction decoding circuit 60. For example, in error correction of 256-bit code data, 8-bit likelihood information is output as a correction candidate in ascending order of LLR.

[0021] Fig. 10 is a diagram for explaining a correction candidate extraction method in a conventional correction candidate extraction circuit. In the example of Fig. 10, a search is performed for LLR values ​​(0 to 7) from the likelihood information of 256-bit code data, and 8 pieces of likelihood information are extracted. In this case, a search is performed for the number of loops of 256 x 8 = 2048.

[0022] In the example of Figure 10, for 256-bit code data, a search is performed for 256 x 8 = 2048 loops. This means that the amount of calculation required to extract likelihood information that serves as a correction candidate cannot be reduced, resulting in a problem that the increase in processing load when extracting correction candidates cannot be suppressed.

[0023] In order to solve the above problem, the present invention is configured in an error correction circuit that performs error correction using likelihood information, to reduce the amount of calculations required when searching for likelihood information by reducing the number of search loops when extracting correction candidates while maintaining the number of likelihood information extracted as correction candidates.

[0024] Specifically, in the search for likelihood values ​​when extracting correction candidates, a plurality of low likelihood value data groups having different likelihood values ​​that are equal to or less than a predetermined threshold are searched for. For example, a first low likelihood value data group having a likelihood value that is equal to or less than a predetermined threshold and a second low likelihood value data group having a likelihood value that is equal to or less than a predetermined threshold and that is greater than the first low likelihood value data group are searched for and extracted as a predetermined number of correction candidate bits.

[0025] According to the present invention, the number of likelihood values ​​extracted as correction candidates is maintained, so that the correction capability can be maintained as in the past. On the other hand, by limiting the likelihood value when searching for likelihood information to a likelihood value equal to or less than a predetermined threshold, the number of search loops when extracting correction candidates is reduced compared to the past, and the amount of calculation when searching for likelihood information is reduced, so that the processing load when extracting correction candidates is reduced.

[0026] <Communication system including error correction device> Fig. 1 is a diagram showing a configuration example of a communication system including an error correction circuit according to an embodiment of the present invention. The configuration example of Fig. 1 is a configuration example in which an error correction circuit 100 according to the embodiment of the present invention is applied to a communication system of a coherent optical communication method.

[0027] 1, the transmitting side device includes a transmission signal processing device 300 and an optical transmitting module 400, and the receiving side device includes an optical receiving module 500 and a reception signal processing device 600. The transmitting side device and the receiving side device are connected via an optical fiber transmission line 1000. The transmitting signal processing device 300 includes an error correction coding circuit 200, and the reception signal processing device 600 includes an error correction circuit 100.

[0028] The error correction coding circuit 200 in the transmission signal processing device 300 performs error correction coding on the transmission data. The optical transmission module 400 generates an optical signal by modulating the transmission data that has been subjected to error correction coding, and transmits the optical signal to the optical fiber transmission line 1000.

[0029] In general coherent optical communications, a signal obtained by combining a horizontally polarized optical signal X and a vertically polarized optical signal is transmitted from an optical transmission module 400 to an optical fiber transmission line 1000. For example, when QPSK is used as the modulation method, the transmission data is divided into data for horizontally polarized optical signals (XI, XQ) and data for vertically polarized optical signals (YI, YQ).

[0030] XI and XQ respectively indicate the coordinates on the horizontal axis and orthogonal axis on the complex plane of the data for the horizontally polarized optical signal, i.e., the horizontal component and orthogonal component. Also, YI and YQ respectively indicate the coordinates on the horizontal axis and orthogonal axis on the complex plane of the data for the vertically polarized optical signal, i.e., the horizontal component and orthogonal component. The data for the horizontally polarized optical signal (XI, XQ) and the data for the vertically polarized optical signal (YI, YQ) are mapped to the coordinates on the complex plane of the carrier wave, and are transmitted from the optical transmitting module 400 to the optical fiber transmission line 1000.

[0031] The optical receiver module 500 demodulates an optical signal received via the optical fiber transmission line 1000 to generate received data, and when QPSK is used as the modulation method, the generated data for horizontally polarized optical signals (XI, XQ) and data for vertically polarized optical signals (YI, YQ) are output. The output data (XI, XQ, YI, YQ) are converted into digital signals in the received signal processing device 600, and error correction processing is performed in the error correction circuit 100.

[0032] In a coherent optical communication system, data is transmitted using horizontally polarized optical signals and vertically polarized optical signals, but it is also possible to transmit data using only one of the horizontally polarized and vertically polarized signals. Even in this case, the error correction circuit 100 according to the embodiment of the present invention can be used.

[0033] Furthermore, the communication system in which the error correction circuit 100 according to the embodiment of the present invention can be used is not limited to the above-mentioned coherent optical communication system. The error correction circuit 100 according to the embodiment of the present invention can also be used in other communication systems including wireless communication systems. It goes without saying that such communication systems are also within the scope of the present invention.

[0034] <Error correction circuit configuration> The receiving signal processing device 600 is supplied with data for horizontally polarized optical signals (XI, XQ) and data for vertically polarized optical signals (YI, YQ) from the optical receiving module 500, and the signals converted into digital signals in the receiving signal processing device 600 are subjected to error correction decoding processing in the error correction circuit 100.

[0035] As the error correction algorithm in the error correction circuit 100, various decoding algorithms such as decoding using LDPC codes, convolutional codes / Viterbi decoding, and Chase decoding can generally be applied.

[0036] 2 is a diagram showing an example of the configuration of an error correction circuit according to an embodiment of the present invention. In this embodiment, the error correction circuit 100 is composed of a likelihood information generation circuit 10 that generates likelihood information for each bit of a main signal, which is encoded data before error correction, a correction candidate extraction circuit 20 that extracts a predetermined number of correction candidate bits for performing error correction decoding based on the likelihood information generated for each bit of the encoded data before error correction, and an error correction decoding circuit 30 that performs error correction decoding on the correction candidate bits extracted by the correction candidate extraction circuit 20.

[0037] The likelihood information generation circuit 10, the correction candidate extraction circuit 20, and the error correction decoding circuit 30 that constitute the error correction circuit 100 according to this embodiment have the same configuration as those in FIG. 8. However, the method of extracting correction candidates in the correction candidate extraction circuit 20 is different from that of the conventional correction candidate extraction circuit 50.

[0038] <Likelihood information generation circuit> In the likelihood information generation circuit 10 of the error correction circuit 100, a likelihood value is generated for each bit (or symbol) of the main signal, which is the input encoded data, and is added to the main signal together with address position information indicating the address position of the main signal (likelihood information generation step).

[0039] The configuration of the input signal input to the correction candidate extraction circuit 20 is the same as the configuration of the conventional input signal described in Fig. 9. In this embodiment, as in Fig. 9, a log-likelihood ratio (LLR) is used as the likelihood value of the likelihood information.

[0040] <Correction candidate extraction circuit> The correction candidate extraction circuit 20 of the error correction circuit 100 extracts a predetermined number of correction candidate bits with low likelihood values ​​for performing error correction decoding based on likelihood information generated for each bit of the encoded data before error correction (correction candidate extraction step).

[0041] The correction candidate extraction circuit 20 is an error correction circuit that performs error correction using likelihood information, and is configured to reduce the amount of calculations required to search for likelihood information by reducing the number of search loops when extracting correction candidates while maintaining the number of likelihood information to be extracted as correction candidates.

[0042] Specifically, in a search for likelihood values ​​when extracting correction candidates, a first low likelihood value data having a likelihood value below a predetermined threshold and a second low likelihood value data having a likelihood value below a predetermined threshold and a likelihood value greater than the first low likelihood value data are extracted as a predetermined number of correction candidate bits.

[0043] <Error correction decoding circuit> In the error correction decoding circuit 30 of the error correction circuit 100, an error correction decoding process is performed on the correction candidate bits extracted by the correction candidate extraction circuit 20, and a corrected signal is output (error correction decoding step).

[0044] <About likelihood information> The likelihood information used in the error correction circuit of this embodiment will be described below. The likelihood information represents the likelihood (reliability) of each bit (or symbol). The log likelihood value of the likelihood information of the likelihood information generation circuit 10 in Fig. 2 represents the likelihood of each bit (or symbol) of the input signal before error correction. The larger the log likelihood value, the higher the likelihood and the fewer the errors.

[0045] When calculating likelihood information based on coordinate information, the coordinate information is for each symbol (symbol: a block of data sent in one modulation in communication), so when multiple bits make up one symbol, it is possible to calculate likelihood information for each bit, or it is possible to calculate likelihood for each symbol and use each bit within the symbol as common likelihood information.

[0046] Examples of modulation methods in which multiple bits become one symbol are QPSK, which carries two bits of information per symbol, and 16QAM, which carries four bits of information per symbol. Furthermore, orthogonal polarization multiplexing makes it possible to transmit twice the number of bits of information per symbol time (4 bits for QPSK and 8 bits for 16QAM).

[0047] The likelihood value can be measured by the amount of deviation of the received coordinate value from an ideal coordinate point due to noise, etc. on the complex plane, and can be calculated based on the distance (amount of deviation) between the coordinate value of the ideal point to be transmitted and the received coordinate value. It is estimated that the smaller the amount of deviation, the larger the likelihood value indicating the reliability of the data. In other words, the likelihood value and the amount of deviation on the coordinates have an inverse increase / decrease relationship. The likelihood value of the likelihood information indicating the reliability of the input signal is an analog value, so the number of bits to express it can be set appropriately.

[0048] Therefore, the smaller the likelihood value of the target bit (or symbol), the greater the shift on the coordinates, so the reliability (probability) of that bit (or symbol) can be determined to be low and it can be made a correction candidate for error correction processing based on the likelihood value.

[0049] One possible method for calculating the distance between coordinates on a complex plane is to use the sum of the absolute values ​​of the differences in coordinate values ​​on each axis. The maximum likelihood value occurs when the received coordinates overlap with the ideal coordinate point, and the likelihood value decreases as the difference from the ideal coordinate point increases. When there are multiple ideal coordinate points, the intermediate coordinate between the ideal coordinate points has the smallest likelihood value.

[0050] In the above description, the difference (shift amount) in the coordinates is used as an index of likelihood, but the calculation of likelihood is not limited to using the difference in the coordinates described above. For example, it is also possible to obtain likelihood using only the signal strength or only the phase difference. The likelihood, which is an index indicating likelihood, can generally be calculated by various methods, and in the present invention, other indexes can be used as long as they are indexes indicating likelihood. In the present invention, it is also possible to use indexes other than the coordinate difference as likelihood, and it goes without saying that such cases are also within the scope of the present invention.

[0051] <Examples of likelihood information> In this embodiment, a log likelihood ratio (LLR) is used as the likelihood value of the likelihood information. The likelihood value is not limited to the log likelihood ratio, and other likelihood values ​​may be used. In the following, a specific example of the log likelihood ratio when the log likelihood ratio is used as the likelihood value will be described in the case where QPSK is used as the modulation method.

[0052] The likelihood value can be calculated based on the coordinates of the received signal and the coordinates of the transmitted signal, as described above, and on the positional relationship (distance information) between them, and this value can represent the likelihood of the coordinates of the received signal.

[0053] 3 is a diagram for explaining likelihood information according to an embodiment of the present invention. The ideal coordinate point set on the transmitting side is Xt1 (XIt1, XQt1), the coordinate point of an adjacent signal point different from the coordinate point Xt1 is Xt2 (XIt2, XQt2), and the coordinate point on the receiving side is Xr (XIr, XQr).

[0054] Ar is the amplitude before error correction on the receiving side, At1 is the ideal amplitude of ideal coordinate point Xt1, At2 is the amplitude of adjacent coordinate point Xt2 different from coordinate point Xt1, and φ1 and φ2 are the phase differences between coordinate point Xr on the receiving side and Xt1 and Xt2, respectively.

[0055] When expressed on a complex plane, the following relationship holds between the coordinate points and the amplitude and phase: (XIr-XIt1)+j(XQr-XQt1)=(Ar / At1)exp(jφ1) (XIr-XIt2)+j(XQr-XQt2)=(Ar / At2)exp(jφ2)

[0056] The likelihood value can be calculated, for example, as follows using the absolute value of the difference between the coordinate values ​​on the transmitting side and the coordinate values ​​on the receiving side. L1 = |XIr-XIt1| + |XQr-XQt1| L2 = |XIr-XIt2| + |XQr-XQt2|

[0057] The likelihood value is the ratio of L1 to L2 above, and the log likelihood ratio (LLR) can be calculated by logarithmic transformation of the likelihood ratio as follows: LLR = ln(L1 / L2)

[0058] The likelihood value may be L1 / L2 instead of logarithmically converting the likelihood ratio. In this case, the amount of calculation required for logarithmic calculation can be reduced, and the circuit scale required for the logarithmic calculation can be reduced. Furthermore, the likelihood information is not limited to information based on the difference between coordinate values, and other information may be used as long as it is an index showing the likelihood.

[0059] Although an example of calculating the log-likelihood ratio for one polarized signal (horizontally polarized optical signal X) has been described above, the log-likelihood ratio can be calculated in a similar manner for the other polarized signal (vertically polarized optical signal Y) in the case of orthogonal polarization multiplexing transmission.

[0060] As a method for calculating the log-likelihood ratio from coordinate values, there is a method of using a calculator to calculate the distance or logarithmic value, but other methods are possible, such as having a logarithmic conversion table as a look-up table, or storing a table of coordinate values ​​and likelihood information of the received signal in memory in advance as shown in Figure 4, and referencing this table to establish correspondence, thereby making it possible to calculate logarithmic values ​​or likelihood information. By preparing and using a conversion table such as a logarithmic conversion table or a coordinate-likelihood information conversion table in advance, calculators for logarithmic conversion, likelihood information conversion, etc. are not required, which results in faster processing and reduced circuit size.

[0061] The conversion table may have many patterns, or a partial correspondence table may be stored, and the logarithmic value may be calculated by combining any constant multiplication or any constant addition by utilizing the symmetry or similarity of the logarithmic function, etc. By using such a simplified method for hardware, it is possible to reduce the processing time, circuit size, and power consumption.

[0062] Although the calculation method of the likelihood information when QPSK is used as the modulation method has been described in Fig. 3, the likelihood information can be obtained in a similar manner even when other modulation methods are used as the modulation method. Since the error correction in this embodiment does not depend on the modulation method, the same error correction method can be applied even when BPSK, 8QAM, 16QAM, 64QAM, or other modulation methods are used.

[0063] For example, when BPSK is used, the ideal coordinate points on the transmitting side are Xt1 (XIt1, 0), Xt2 (XIt2, 0), and the coordinate before error correction on the receiving side is Xr (XIr, 0), and the likelihood information can be calculated using the sum of the absolute values ​​of the differences between Xr and the ideal coordinate point (Xt1, XIt2) on the transmitting side. The likelihood information can be calculated in a similar manner for the other polarized signal (vertically polarized optical signal Y) in the case of orthogonal polarization multiplexing transmission.

[0064] <Operation of the correction candidate extraction circuit> 5 is a flow diagram for explaining the operation of the error correction method according to the embodiment of the present invention. The error correction operation of the embodiment is performed in an error correction circuit 100 including a likelihood information generation circuit 10, a correction candidate extraction circuit 20, and an error correction decoding circuit 30.

[0065] The likelihood information generation circuit 10 receives a main signal, which is encoded data before error correction (S1-1), generates likelihood information for each bit of the encoded data before error correction, and adds the likelihood information to the encoded data, which is the main signal (S1-2).

[0066] The correction candidate extraction circuit 20 extracts a predetermined number of correction candidate bits with low likelihood values ​​for error correction decoding based on the likelihood values ​​of the likelihood information generated for each bit of the encoded data before error correction, and supplies them to the error correction decoding circuit 30 (S1-3).

[0067] The error correction decoding circuit 30 performs an error correction decoding process on the correction candidate bits extracted by the correction candidate extraction circuit 20 (S1-4), and outputs the error-corrected signal (S1-5).

[0068] In the correction candidate extraction method in the correction candidate extraction circuit 20 according to an embodiment of the present invention, when the correction candidate extraction circuit 20 extracts correction candidates for performing error correction using likelihood information, the correction candidate extraction circuit 20 is configured to reduce the amount of calculations required for searching for likelihood information by reducing the number of search loops when extracting likelihood information while maintaining the number of likelihood information to be extracted as correction candidates.

[0069] Specifically, while maintaining the number of predetermined correction candidate bits extracted in the correction candidate extraction circuit 20 at the same number as in the conventional method, the likelihood values ​​to be searched for when extracting correction candidates are reduced to first low likelihood value data having a likelihood value below a predetermined threshold and second low likelihood value data having a likelihood value below a predetermined threshold and a likelihood value greater than the first low likelihood value data, thereby reducing the number of search loops when extracting correction candidate bits.

[0070] <Specific examples of how to extract correction candidates> A specific example of the operation of the correction candidate extraction method according to the embodiment of the present invention will be described with reference to Fig. 6 and Fig. 7. In the example of Fig. 6 and Fig. 7, a case where a first group of LLRs (LLR=0 or 1) and a second group of LLRs (LLR=2 or 3) are searched will be described, but the number of groups to search for LLRs and the number of LLRs to search in each group are not limited thereto. As long as the effect of reducing the number of search loops when searching for LLRs can be obtained, all of them are within the scope of the present invention.

[0071] In the examples of Fig. 6 and Fig. 7, the value of LLR is expressed by 3 bits, LLR: 0 to 7, and the number of groups of LLR to be searched is the first group of LLR (LLR = 0 or 1) and the second group of LLR (LLR = 2 or 3), but the value of LLR may be expressed by 4 bits, LLR: 0 to 15, and the number of groups of LLR to be searched is the first group of LLR (LLR = 0 or 1), the second group of LLR (LLR = 2 or 3), the third group of LLR (LLR = 4 or 5), and the fourth group of LLR (LLR = 6 or 7). The number of groups to search for LLR and the number of LLRs to search in each group can be appropriately determined in consideration of the error occurrence situation, correction capability, and the amount of calculation when searching for likelihood information.

[0072] In the examples of Figs. 6 and 7, the LLR to be searched is reduced from LLR: 0 to 7 to LLR: 0 to 3 which is equal to or less than a predetermined threshold (LLR = 4). In Fig. 6, a first group of LLRs (LLR = 0 or 1) is searched from the upper address side of the address position of the coded data, and in Fig. 7, a second group of LLRs (LLR = 2 or 3) having a higher LLR value than the first group of LLRs (LLR = 0 or 1) is searched from the lower address side of the coded data with a likelihood value of LLR = 4 or less. Comparing the first half of the code (lower address side) with the second half of the code (higher address side), there are more errors in the second half of the code (higher address side), so the error correction capability can be improved by searching for the first group of LLRs (LLR = 0 or 1) having a lower LLR from the upper address side of the address position of the coded data.

[0073] Furthermore, when the LLR value is expressed by 4 bits, LLR: 0 to 15, and the number of groups of LLRs to be searched is set to the first to fourth groups of LLRs, the error correction capability can be improved by making the search order in the address of the coded data when searching each of the first to fourth groups of LLRs different. For example, the search for the first and second groups of LLRs may be performed from the upper address side of the address position of the coded data, and the search for the third and fourth groups of LLRs may be performed from the lower address side of the address position of the coded data.

[0074] <Search for the first group (LLR=0 or 1)> In FIG. 6, num indicates the number of likelihood information to be extracted, j is the address position of the 256-bit code data, LLR[j] is the LLR value at address position [j], and Sort[num] is the extraction result of the address position where LLR=0 or 1.

[0075] In searching the first group of LLRs (LLR=0 or 1), the initial value of num is set to [0], and 8 correction candidates are searched for up to num=7 (S2-1). The initial value of j is set to [0], and the likelihood value search is performed from the upper address side of the encoded data (S2-2).

[0076] If the value of j is smaller than 256, it is determined whether num<8 and LLR[j]=0 or 1 are satisfied (S2-3, S2-4). The determination of whether num<8 and LLR[j]=0 or 1 are satisfied (S2-4) is repeated until j<256 is no longer satisfied (S1-3: NO).

[0077] If num<8 and LLR[j]=0 or 1 are satisfied (S1-4: YES), a correction candidate bit with an LLR value of 0 or 1 is detected, so address [j] corresponding to LLR[j]=0 or 1 is stored in Sort[num] (S2-5).

[0078] If num<8 and LLR[j]=0 or 1 are not satisfied (S1-4: NO), then an address with an LLR value of 0 or 1 was not detected, so it is determined whether the LLR value of the next address [j+1] satisfies LLR[j+1]=0 or 1 (S2-6).

[0079] The determination of whether LLR[j]=0 or 1 is satisfied (S1-4) is repeated until num<8 is no longer satisfied. Through the above process, addresses[j] for which LLR[j]=0 or 1 is satisfied can be extracted as correction candidate bits, which are num=8. The number of search loops when searching for the first group of LLRs in FIG. 5 is 256.

[0080] In Fig. 6, the search is continued until j<256 is no longer satisfied (S2-3: NO), but the search process may be terminated when num<8 is no longer satisfied (S2-4). This can further reduce the number of searches.

[0081] <Search for the second group (LLR=2 or 3)> 7, num indicates the number of likelihood information to be extracted, j indicates the address position of 256-bit code data, LLR[j] indicates the LLR value at address position [j], and Sort[num] indicates the extraction result of the LLR. Sort[num] indicates the extraction result of the address position of LLR=2 or 3.

[0082] In Fig. 7, a search is performed for a second group of LLRs (LLR = 2 or 3) having a larger LLR value than the first group of LLRs (LLR = 0 or 1). In the search for the second group of LLRs (LLR = 2 or 3), the initial value of num is set to [7], and 8 correction candidate bits are searched for until num = 0 is satisfied (S3-1). In Fig. 7, the initial value of j is set to

[0255] , and a search for a likelihood value is performed from the lower address side of the encoded data (S3-2).

[0083] The search method for the second group of LLRs (LLR=2 or 3) in Fig. 7 differs from the search for the first group of LLRs in Fig. 6 in that it is determined whether or not LLR[j]=2 or 3 is satisfied, and the search for whether or not LLR[j]=2 or 3 is satisfied is performed from the lower address side of the encoded data. The number of search loops when searching for the second group of LLRs in Fig. 7 is 256, similar to the first group in Fig. 6.

[0084] In FIG. 7, the search is continued until j≧0 is no longer satisfied (S3-3: NO), but 0 If the condition is no longer satisfied (S3-4), the search process may be terminated, which can further reduce the number of searches.

[0085] Eight bits are selected from the correction candidate bits extracted by the search of the first group of LLRs in Fig. 6 and the search of the second group of LLRs in Fig. 7, and error correction decoding processing is performed. If a total of eight or more correction candidate bits are extracted as a result of the search of the first group of LLRs in Fig. 6 and the search of the second group of LLRs in Fig. 7, the correction candidate bits detected by the search of the first group of LLRs with lower LLRs are preferentially selected and error correction is performed. By prioritizing the search of the first group of LLRs with lower LLRs, it is possible to improve error correction capability.

[0086] In addition, the correction candidate bits in each of the first and second groups are selected according to the order in which they are searched: in the first group, correction candidate bits are preferentially selected in ascending order of address position j, and in the second group, correction candidate bits are preferentially selected in descending order of address position j.

[0087] In this embodiment, in searching for likelihood values ​​when extracting correction candidates, the likelihood values ​​to be searched are reduced to first low likelihood value data having a likelihood value below a predetermined threshold and second low likelihood value data having a likelihood value below a predetermined threshold and a likelihood value greater than the first low likelihood value data, thereby reducing the number of search loops when extracting correction candidate bits.

[0088] In this embodiment, the same number of correction candidate bits as in the conventional method are extracted, so that the correction capability is maintained as compared with the conventional method. Meanwhile, the number of search loops when searching likelihood information of correction candidates is 256×2=512, including the first group in FIG. 6 and the second group in FIG. 7. The number of loops when searching likelihood information can be reduced compared to the number of loops (256×8=2048) in the conventional search flow described in FIG. 10.

[0089] In this embodiment, an error correction circuit that performs error correction using likelihood information is configured to reduce the amount of calculation required to search for likelihood information by reducing the number of search loops required to extract likelihood information while maintaining the number of likelihood information extracted as correction candidates. This makes it possible to provide an error correction method, an error correction circuit, and a communication system that can suppress increases in processing delay and power consumption while maintaining correction capability. [Industrial Applicability]

[0090] The present invention can be used as an error correction device and a communication system in optical communications and the like. [Explanation of symbols]

[0091] 10, 40... Likelihood information generation circuit, 20, 50... Correction candidate extraction circuit, 30, 60... Error correction decoding circuit, 100... Error correction circuit, 200... Error correction encoding circuit, 300... Transmission signal processing device, 400... Optical transmitting module, 500... Optical receiving module, 600... Reception signal processing device.

Claims

1. An error correction method executed in an error correction circuit that performs error correction using likelihood information, comprising: a correction candidate extraction step of extracting a predetermined number of correction candidate bits for performing error correction decoding based on likelihood information generated for each bit of the encoded data before error correction; an error correction decoding step of performing error correction decoding on the correction candidate bits extracted in the correction candidate extraction step; Equipped with The correction candidate extraction step includes: a step of limiting the likelihood value when searching for the likelihood information to a likelihood value equal to or less than a predetermined threshold, and searching for a plurality of low likelihood value data groups each having a likelihood value equal to or less than the predetermined threshold and each having different likelihood values; searching for a first low likelihood value data group having a likelihood value equal to or less than a predetermined threshold and a second low likelihood value data group having a likelihood value equal to or less than the predetermined threshold and a likelihood value greater than that of the first low likelihood value data group; searching the first low-likelihood value data group from a higher address side of an address location of the encoded data, and searching the second low-likelihood value data group from a lower address side of an address location of the encoded data to extract the predetermined number of the correction candidate bits; The error correction decoding step includes: The correction candidate bit detected by searching the first low-likelihood value data group is selected with priority over the correction candidate bit detected by searching the second low-likelihood value data group, and error correction decoding is performed. Error correction methods.

2. The correction candidate extraction step includes: when the predetermined number of the correction candidate bits are extracted by searching the first low likelihood value data group, the search of the first low likelihood value data group is terminated; When the predetermined number of the correction candidate bits are extracted by searching the second low-likelihood value data group, the search of the second low-likelihood value data group is terminated. The error correction method according to claim 1 .

3. An error correction circuit that performs error correction using likelihood information, a correction candidate extraction circuit that extracts a predetermined number of correction candidate bits for performing error correction decoding based on likelihood information generated for each bit of encoded data before error correction; an error correction decoding circuit that performs error correction decoding on the correction candidate bits extracted by the correction candidate extraction circuit; Equipped with The correction candidate extraction circuit includes: limiting the likelihood value when searching for the likelihood information to a likelihood value equal to or less than a predetermined threshold, and searching for a plurality of low likelihood value data groups having a likelihood value equal to or less than the predetermined threshold and different from each other in the likelihood value; searching for a first low likelihood value data group having a likelihood value equal to or less than a predetermined threshold and a second low likelihood value data group having a likelihood value equal to or less than the predetermined threshold and a likelihood value greater than that of the first low likelihood value data group; searching the first low-likelihood value data group from a higher address side of an address location of the encoded data, and searching the second low-likelihood value data group from a lower address side of an address location of the encoded data to extract the predetermined number of the correction candidate bits; The error correction decoding circuit includes: The correction candidate bit detected by searching the first low-likelihood value data group is selected with priority over the correction candidate bit detected by searching the second low-likelihood value data group, and error correction decoding is performed. Error correction circuitry.

4. The correction candidate extraction circuit includes: when the predetermined number of the correction candidate bits are extracted by searching the first low likelihood value data group, the search of the first low likelihood value data group is terminated; When the predetermined number of the correction candidate bits are extracted by searching the second low-likelihood value data group, the search of the second low-likelihood value data group is terminated.

4. The error correction circuit according to claim 3.

5. A transmitting device including an error correction coding circuit that codes transmission data and a transmitting module that transmits an optical signal modulated using the coded data output from the error correction coding circuit; a receiving device including a receiving module configured to demodulate the coded data from the optical signal received from the transmitting device, and an error correction circuit configured to correct errors in the demodulated coded data; A communication system comprising: The error correction circuit includes: a correction candidate extraction circuit that extracts a predetermined number of correction candidate bits for performing error correction decoding based on likelihood information generated for each bit of encoded data before error correction; an error correction decoding circuit that performs error correction decoding on the correction candidate bits extracted by the correction candidate extraction circuit; Equipped with The correction candidate extraction circuit includes: limiting the likelihood value when searching for the likelihood information to a likelihood value equal to or less than a predetermined threshold, and searching for a plurality of low likelihood value data groups having a likelihood value equal to or less than the predetermined threshold and different from each other in the likelihood value; searching for a first low likelihood value data group having a likelihood value equal to or less than a predetermined threshold and a second low likelihood value data group having a likelihood value equal to or less than the predetermined threshold and a likelihood value greater than that of the first low likelihood value data group; searching the first low-likelihood value data group from a higher address side of an address location of the encoded data, and searching the second low-likelihood value data group from a lower address side of an address location of the encoded data to extract the predetermined number of the correction candidate bits; The error correction decoding circuit includes: The correction candidate bit detected by searching the first low-likelihood value data group is selected with priority over the correction candidate bit detected by searching the second low-likelihood value data group, and error correction decoding is performed. Communication systems.

6. The correction candidate extraction circuit, when the predetermined number of the correction candidate bits are extracted by searching the first low likelihood value data group, the search of the first low likelihood value data group is terminated; When the predetermined number of the correction candidate bits are extracted by searching the second low-likelihood value data group, the search of the second low-likelihood value data group is terminated.

6. The communication system according to claim 5.

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