Liquid crystal display device

Abstract

To provide a display device capable of improving the image quality.SOLUTION: A pixel includes a plurality of capacitive elements, a plurality of transistors, and a display element. The plurality of capacitive elements is connected in series through wiring, and one of the plurality of transistors is electrically connected to one end and the other end of the plurality of capacitive elements connected in series, and to the wiring, respectively. The display element can be operated in accordance with the sum of the plurality of input data, and the image correction such as up-conversion of an image, HDR display, or improvement in luminance can be performed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of one aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are examples of semiconductor devices. Furthermore, memory devices, display devices, imaging devices, and electronic devices may contain semiconductor devices. [Background technology]

[0004] While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials. Oxide semiconductors include not only oxides of monocrystalline metals such as indium oxide and zinc oxide, but also oxides of multicrystalline metals. Among the oxides of multicrystalline metals, research on In-Ga-Zn oxide (hereinafter also called IGZO) is particularly active.

[0005] Research on IGZO has led to the discovery of CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures in oxide semiconductors, which are neither single-crystal nor amorphous (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 also disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure. Furthermore, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC and nc structures can contain minute crystals.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-currents (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic have been reported (see Non-Patent Documents 7 and 8).

[0007] Furthermore, Patent Document 1 discloses a memory device that uses transistors with extremely low off-currents as memory cells. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2011-119674 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 [Overview of the project] [Problems that the invention aims to solve]

[0010] Display devices are becoming increasingly high-resolution, with hardware being developed that can display at 8K / 4K (7680 x 4320 pixels) or higher resolutions. Furthermore, the introduction of HDR (High Dynamic Range) display technology, which enhances image quality through brightness adjustment, is also progressing.

[0011] To display images correctly on a display device, the image data must be matched to the display device's resolution. For example, if the display device has an 8K4K resolution and the image data is for 4K2K (pixel count: 3840 x 2160), the data size must be quadrupled to achieve full-screen display. Conversely, if the display device has a 4K2K resolution and the image data is for 8K4K, the data size must be reduced to one-quarter of its original size.

[0012] Furthermore, HDR processing requires dedicated circuits for generating image data and converting the number of data points, which also increases power consumption. Ideally, the original image data should be input to the pixels of the display device without conversion.

[0013] Therefore, one aspect of the present invention aims to provide a display device that can improve image quality. Alternatively, it aims to provide a display device that can display images appropriately without converting them. Alternatively, it aims to provide a display device that can perform HDR display. Alternatively, it aims to provide a display device that can perform upconversion. Alternatively, it aims to provide a display device that can increase the brightness of the displayed image. Alternatively, it aims to provide a display device that can display two or more images superimposed on each other. Alternatively, it aims to provide a display device that can apply a voltage to the pixel circuit that is greater than or equal to the output voltage of the drive circuit.

[0014] Alternatively, one of the objectives is to provide a low-power display device. Alternatively, one of the objectives is to provide a highly reliable display device. Alternatively, one of the objectives is to provide a novel display device, etc. Alternatively, one of the objectives is to provide a driving method for the above-mentioned display device. Alternatively, one of the objectives is to provide a novel semiconductor device, etc.

[0015] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0016] One aspect of the present invention relates to a display device capable of improving image quality, or to a display device capable of performing image processing.

[0017] One aspect of the present invention is a display device having a plurality of capacitive elements, a plurality of transistors, and a display element, wherein the plurality of capacitive elements are connected in series via wiring, one of the transistors is electrically connected to the electrode at one end of the plurality of series-connected capacitive elements, one of the transistors is electrically connected to the electrode at the other end of the plurality of series-connected capacitive elements, a display element is electrically connected to the electrode at the other end of the plurality of series-connected capacitive elements, and one of the transistors is electrically connected to the wiring.

[0018] Another aspect of the present invention is a display device having a first transistor, a second transistor, a third transistor, a first capacitive element, a second capacitive element, and a circuit block, wherein one of the sources or drains of the first transistor is electrically connected to one electrode of the first capacitive element, one electrode of the first capacitive element is electrically connected to the circuit block, the other electrode of the first capacitive element is electrically connected to one of the sources or drains of the second transistor, one of the sources or drains of the second transistor is electrically connected to one electrode of the second capacitive element, the other electrode of the second capacitive element is electrically connected to one of the sources or drains of the third transistor, and the circuit block is a display device having a display element.

[0019] Furthermore, the transistor may have a first wiring, where the source or drain of the first transistor is electrically connected to the first wiring, and the source or drain of the third transistor is electrically connected to the first wiring.

[0020] The device may further include a fourth transistor, a fifth transistor, a second wiring, and a third wiring, wherein one source or drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, one source or drain of the fifth transistor is electrically connected to the other electrode of the second capacitive element, the other source or drain of the second transistor is electrically connected to the first wiring, the gate of the first transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the second wiring, the gate of the second transistor is electrically connected to the third wiring, and the gate of the fifth transistor is electrically connected to the third wiring.

[0021] Another aspect of the present invention is a display device having a first circuit, a second circuit, a second transistor, a third transistor, and a second capacitive element, wherein each of the first and second circuits has a first transistor, a first capacitive element, and a circuit block, the source or drain of the first transistor is electrically connected to one electrode of the first capacitive element, one electrode of the first capacitive element is electrically connected to the circuit block, the other electrode of the first capacitive element is electrically connected to one source or drain of the second transistor, the source or drain of the second transistor is electrically connected to one electrode of the second capacitive element, the other electrode of the second capacitive element is electrically connected to one source or drain of the third transistor, and the circuit block has a display element.

[0022] Furthermore, the circuit may have a first wiring, and the source or drain of the first transistor in the first circuit may be electrically connected to the first wiring, and the source or drain of the third transistor may be electrically connected to the first wiring.

[0023] The circuit may further include a fourth transistor, a fifth transistor, a second wiring, and a third wiring, wherein one source or drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, one source or drain of the fifth transistor is electrically connected to the other electrode of the second capacitive element, the other source or drain of the second transistor is electrically connected to the first wiring, the gate of the first transistor in the first circuit is electrically connected to the second wiring, the gate of the first transistor in the second circuit is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the second wiring, the gate of the second transistor is electrically connected to the third wiring, and the gate of the fifth transistor is electrically connected to the third wiring.

[0024] The circuit block may have a sixth transistor, a seventh transistor, a third capacitive element, and an EL element as a display element, wherein one electrode of the EL element is electrically connected to one of the source or drain of the seventh transistor, the other of the source or drain of the seventh transistor is electrically connected to one electrode of the third capacitive element, one electrode of the third capacitive element is electrically connected to one of the source or drain of the sixth transistor, the gate of the sixth transistor is electrically connected to the other electrode of the third capacitive element, and the other electrode of the third capacitive element is electrically connected to one electrode of the first capacitive element.

[0025] Furthermore, the circuit block may have a fourth capacitive element and a liquid crystal element as a display element, wherein one electrode of the liquid crystal element is electrically connected to one electrode of the fourth capacitive element, and one electrode of the fourth capacitive element is electrically connected to one electrode of the first capacitive element.

[0026] The system may further have an eighth transistor, wherein one electrode of the fourth capacitive element is electrically connected to either the source or the drain of the eighth transistor, and the other electrode of the source or drain of the eighth transistor is electrically connected to either the source or the drain of the first capacitive element.

[0027] The first transistor has a metal oxide in the channel formation region, and the metal oxide preferably contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). [Effects of the Invention]

[0028] By using one aspect of the present invention, a display device capable of improving image quality can be provided. Alternatively, a display device capable of appropriate display without converting image data can be provided. Alternatively, a display device capable of HDR display can be provided. Alternatively, a display device capable of upconversion can be provided. Alternatively, a display device capable of increasing the brightness of the displayed image can be provided. Alternatively, a display device capable of displaying two or more images superimposed can be provided. Alternatively, a display device capable of applying a voltage to the pixel circuit that is greater than or equal to the output voltage of the drive circuit can be provided.

[0029] Alternatively, a low-power display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided. Alternatively, a driving method for the above-mentioned display device can be provided. Alternatively, a novel semiconductor device can be provided. [Brief explanation of the drawing]

[0030] [Figure 1] A diagram illustrating the pixel circuit. [Figure 2] A timing chart illustrating the operation of the pixel circuit. [Figure 3] A timing chart illustrating the operation of the pixel circuit. [Figure 4]A diagram illustrating the pixel circuit and a timing chart explaining the operation of the pixel circuit. [Figure 5] A diagram illustrating the pixel circuit and a timing chart explaining the operation of the pixel circuit. [Figure 6] A diagram illustrating the pixel circuit. [Figure 7] A diagram illustrating a circuit block. [Figure 8] A diagram illustrating a circuit block. [Figure 9] A diagram illustrating the pixel circuit. [Figure 10] A diagram illustrating image data correction and image synthesis. [Figure 11] A diagram illustrating a pixel array. [Figure 12] A diagram illustrating a pixel array. [Figure 13] A diagram illustrating a pixel array. [Figure 14] A block diagram illustrating the display device. [Figure 15] A diagram illustrating an example of a neural network configuration. [Figure 16] A diagram illustrating the pixel circuit used in the simulation. [Figure 17] A diagram illustrating the results of the simulation. [Figure 18] A diagram illustrating a display device. [Figure 19] A diagram illustrating a touch panel. [Figure 20] A diagram illustrating a display device. [Figure 21] A diagram illustrating a display device. [Figure 22] A diagram illustrating a transistor. [Figure 23] A diagram illustrating a transistor. [Figure 24] A diagram explaining transistors. [Figure 25] A diagram explaining transistors. [Figure 26] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0031] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0032] (Embodiment 1) In this embodiment, a display device that is one aspect of the present invention will be described with reference to the drawings.

[0033] One aspect of the present invention is a display device having a function for correcting image data within a pixel. Multiple memory nodes are provided in series in each pixel, and the display element can be operated according to the sum of multiple input data.

[0034] Therefore, the display device can perform image correction, such as upconversion of images, HDR display which corrects part or all of the image in the display area, or improvement of the brightness of the displayed image. It can also perform superimposed display of multiple images and supply a voltage to the pixel circuit that is higher than the output voltage of the drive circuit.

[0035] Furthermore, by using one aspect of the present invention, image data of different resolutions can be displayed appropriately without upconverting or downconverting. For example, when the pixel configuration targets three resolution levels: high, medium, and low, when displaying at high resolution, individual data is supplied to each pixel via a first transistor in each pixel. When displaying at medium resolution, the same data is supplied to multiple pixels in a first group via a second transistor that is electrically connected to multiple pixels in that group. When displaying at low resolution, the same data is supplied to multiple pixels in a second group via a third transistor that is electrically connected to multiple pixels in that group.

[0036] Here, high-resolution image data corresponds to data with an information volume equivalent to, for example, 8K4K (pixel count: 7680 x 4320). Medium-resolution image data corresponds to data with an information volume equivalent to, for example, 4K2K (pixel count: 3840 x 2160). Low-resolution image data corresponds to data with an information volume equivalent to, for example, FullHD (pixel count: 1920 x 1080).

[0037] In other words, it is assumed that the ratio of effective data volume (corresponding to the effective number of pixels) between high-resolution image data and medium-resolution image data, and the ratio of effective data volume between medium-resolution image data and low-resolution image data, is 4:1. Furthermore, the ratio of effective data volume between high-resolution image data and low-resolution image data is 16:1. Note that as long as the data volume is in the above ratio, the number of pixels is not limited to the example above and may conform to other standards.

[0038] Figure 1 illustrates a pixel 10 that can be used in a display device according to one embodiment of the present invention. The pixel 10 has two capacitive elements and can display data according to the sum of up to three data points through capacitive coupling.

[0039] Pixel 10 includes transistors 101, 102, and 103, capacitive elements 104 and 105, and a circuit block 110. The circuit block 110 may include transistors, capacitive elements, and display elements, and further details will be described later.

[0040] One of the sources or drains of transistor 101 is electrically connected to one electrode of capacitive element 104. One electrode of capacitive element 104 is electrically connected to circuit block 110. The other electrode of capacitive element 104 is electrically connected to one of the sources or drains of transistor 102. One of the sources or drains of transistor 102 is electrically connected to one electrode of capacitive element 105. The other electrode of capacitive element 105 is electrically connected to one of the sources or drains of transistor 103.

[0041] Here, node NM is defined as the wiring to which one of the source or drain of transistor 101, one electrode of capacitive element 104, and circuit block 110 are connected. Note that the elements of circuit block 110 connected to node NM can make node NM floating. Furthermore, node NB is defined as the wiring to which the other electrode of capacitive element 104, one of the source or drain of transistor 102, and one electrode of capacitive element 105 are connected. Furthermore, node NA is defined as the wiring to which one of the source or drain of transistor 103 and the other electrode of capacitive element 105 are connected.

[0042] The gate of transistor 101 is electrically connected to wiring 121. The gate of transistor 102 is electrically connected to wiring 122. The gate of transistor 103 is electrically connected to wiring 123. The other end of the source or drain of transistor 101 is electrically connected to wiring 124. The other end of the source or drain of transistor 102 is electrically connected to wiring 125. The other end of the source or drain of transistor 103 is electrically connected to wiring 126.

[0043] Wires 121, 122, and 123 can function as signal lines for controlling the operation of the transistor. Wire 124 can function as a signal line for supplying first data. Wire 125 can function as a signal line for supplying second data. Wire 126 can function as a signal line for supplying third data.

[0044] Nodes NM, NB, and NA can function as memory nodes. By making transistor 101 conductive, the first data supplied to wiring 124 can be written to node NM. By making transistor 101 non-conductive, the data can be retained in node NM. Furthermore, by making transistor 102 conductive, the second data supplied to wiring 125 can be written to node NB. By making transistor 102 non-conductive, the data can be retained in node NB. Furthermore, by making transistor 103 conductive, the third data supplied to wiring 126 can be written to node NA. By making transistor 103 non-conductive, the data can be retained in node NA.

[0045] By using transistors 101, 102, and 103 with extremely low off-currents, it becomes possible to maintain the potentials of nodes NM and NB for a long period of time. For example, transistors using metal oxide in the channel formation region (hereinafter referred to as OS transistors) can be used for these transistors.

[0046] Furthermore, OS transistors may be applied to other transistors in the pixels. Alternatively, transistors with Si in the channel formation region (hereinafter referred to as Si transistors) may be applied to the transistors in the pixels. Or, both OS transistors and Si transistors may be used. Examples of the above Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (typically low-temperature polysilicon and single-crystal silicon).

[0047] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors that require high-speed operation.

[0048] OS transistors exhibit extremely low off-current characteristics due to their large energy gap. Furthermore, OS transistors have characteristics that differ from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short-channel effects, enabling the formation of highly reliable circuits.

[0049] The semiconductor layer of an OS transistor can be a film represented as an In-M-Zn oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0050] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to deposit the In-M-Zn oxide satisfy In≧M≧M and Zn≧M. Preferred atomic ratios of the metal elements in such a sputtering target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, and In:M:Zn=5:1:8. The atomic ratio of the deposited semiconductor layer includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target.

[0051] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the carrier density of the semiconductor layer is 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, still more preferably 1×10 10 / cm 3 or less, and an oxide semiconductor of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0052] Note that it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Also, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0053] In the oxide semiconductor constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and it becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0054] Furthermore, alkali metals and alkaline earth metals can generate carriers when bonded with oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0055] Furthermore, if nitrogen is present in the oxide semiconductor constituting the semiconductor layer, electrons, which act as carriers, are generated, increasing the carrier density and making it easier to achieve n-type characteristics. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferable:

[0056] Furthermore, the semiconductor layer may have a non-single-crystal structure, for example. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest defect level density, while CAAC-OS has the lowest defect level density.

[0057] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0058] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0059] The following describes the configuration of CAC (Cloud-Aligned Composite)-OS, which is one form of a non-single-crystal semiconductor layer.

[0060] CAC-OS is a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0061] Furthermore, the oxide semiconductor preferably contains at least indium. It is particularly preferable that it contains indium and zinc. In addition, it may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0062] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide within CAC-OS may be specifically called CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0.) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) The material separates into mosaic-like structures, and the mosaic-like InO X1, or In X2 Zn Y2 O Z2 However, it is a uniformly distributed structure within the membrane (hereinafter also referred to as a cloud-like structure).

[0063] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 This is a composite oxide semiconductor having a structure in which a region in which is the main component is mixed with another region. In this specification, for example, if the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, then the first region is considered to have a higher concentration of In compared to the second region.

[0064] Note that IGZO is a common name and can refer to a single compound composed of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples include crystalline compounds represented by (-1 ≤ x0 ≤ 1, where m0 is any number).

[0065] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is a crystalline structure in which multiple IGZO nanocrystals are c-axis oriented and linked together without orientation in the ab-plane.

[0066] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. CAC-OS is a material composition containing In, Ga, Zn, and O, in which regions observed as nanoparticles mainly composed of Ga and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0067] Furthermore, CAC-OS does not include layered structures of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is not included.

[0068] Note that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary may not be observable in a region where [this component] is the main component.

[0069] Furthermore, if gallium is replaced with one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, CAC-OS refers to a configuration in which regions observed as nanoparticles mainly composed of the said metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0070] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of oxygen gas flow rate to the total deposition gas flow rate during film formation is preferable; for example, an oxygen gas flow rate ratio of 0% or more and less than 30%, preferably 0% or more and 10% or less, is preferable.

[0071] CAC-OS is characterized by the absence of a clear peak when measured using the θ / 2θ scan method, an out-of-plane X-ray diffraction (XRD) measurement technique. In other words, X-ray diffraction measurements indicate that no orientation in the ab-plane direction or the c-axis direction of the measurement region is observed.

[0072] Furthermore, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam), a ring-shaped region of high brightness and multiple bright spots within this ring region are observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0073] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 It can be confirmed that the structure has regions in which the main component is unevenly distributed and mixed.

[0074] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and therefore has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Regions where such are the main components, and In X2 Zn Y2 O Z2 , or InO X1 It has a mosaic-like structure consisting of regions where one element is the main component and regions where each element is the main component, with each region being in a separate phase from the others.

[0075] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y2 O Z2 , or InO X1In the region where this is the main component, the flow of carriers causes conductivity as an oxide semiconductor to emerge. Therefore, In X2 Zn Y2 O Z2 , or InO X1 A high field-effect mobility (μ) can be achieved when regions with this as the main component are distributed in a cloud-like manner within the oxide semiconductor.

[0076] On the other hand, GaO X3 Regions in which these are the main components are, X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties compared to the region where GaO is the main component. X3 Regions with these as the main components are distributed within the oxide semiconductor, which suppresses leakage current and enables good switching operation.

[0077] Therefore, when CAC-OS is used in semiconductor devices, GaO X3 Insulation caused by factors such as, X2 Zn Y2 O Z2 , or InO X1 The conductivity resulting from this works in a complementary manner, resulting in a high on-current (I on ), and high field-effect mobility (μ) can be achieved.

[0078] Furthermore, semiconductor devices using CAC-OS offer high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0079] An example of the operation of pixel 10, which adds the second and third data to the first data, will be explained using the timing charts shown in Figures 2(A), (B), and (C). In the following explanation, high potential will be represented by "H" and low potential by "L". Also, the first data will be represented by "V data1 ", the second data "V data2 ", the third data "V data3 Let's set it as "V". Also, one of the reference potentials (for example, 0V, GND potential, or a specific potential) is set as "Vref Let it be so. Note that the first to third data may be negative values and also support data subtraction.

[0080] First, the operation of writing the first data "V data1 " to the node NM will be described using FIG. 2(A). Here, an ideal operation is described, and detailed changes in potential due to circuit configuration, operation timing, etc. in potential distribution, coupling, or loss are not considered. Also, although the change in potential due to capacitive coupling depends on the capacitance ratio between the supply side and the supplied side, for clarity of explanation, the capacitance values of nodes NB and NM are assumed to be sufficiently small values.

[0081] At time T1, when the potential of wiring 121 is "H", the potential of wiring 122 is "H", the potential of wiring 124 is "V data1 ", and the potential of wiring 125 is "V ref ", transistor 102 conducts, and the potential of node NB becomes "V ref ". This operation is a reset operation for performing a subsequent capacitive coupling operation.

[0082] Also, transistor 101 conducts, and the potential of wiring 124 (the first data "V data1 ") is written to node NM.

[0083] At time T2, when the potential of wiring 121 is "L" and the potential of wiring 122 is "L", transistors 101 and 102 become non-conductive, and the first data "V data1 " is held at node NM. Also, in capacitive element 104, "V data1 - V ref " is held.

[0084] Up to here is the writing operation of the first data "V data1 ". Note that when the first data is not reflected in the display, the same potential as "V data1 " may be supplied as the first data "V ref ".

[0085] Next, using Figure 2(B), we will examine the second data "V data2 This explains the process of writing "" to node NB.

[0086] At time T11, the potential of wire 122 is set to "H", the potential of wire 123 is set to "H", and the potential of wire 125 is set to "V". data2 ", set the potential of wiring 126 to "V ref "Then transistor 103 conducts, and the potential of node NA is "V ref This operation is a reset operation in order to perform the subsequent capacitive coupling operation.

[0087] Also, transistor 102 conducts, and the potential of wiring 125 to node NB (second data "V") data2 The following is written:

[0088] At this time, the potential of node NB is added to the potential of node NM by the capacitive coupling of the capacitive element 104. Therefore, the potential of node NM is "V data1 -V ref +V data2 " and "V ref If "=0", then the potential at node NM is "V data1 +V data2 "That's how it will be.

[0089] If the potential of wiring 122 is "L" and the potential of wiring 123 is "L" at time T12, then transistor 102 becomes non-conductive, and the second data "V" is generated at node NB. data2 The value " is retained. Also, node NM contains "V", which is the sum of the first data and the second data. data1 +V data2 “ is maintained. Also, the capacitive element 105 has “V data2 -V ref " is retained.

[0090] This concludes the second data set, “V”. data2 This is a writing operation for ". Note that if you do not want the second data to be reflected in the display, the second data "V data2 “V ref "Just supply the same potential."

[0091] Next, using Figure 2(C), the third data "V data3 This explains the process of writing "".

[0092] At time T21, the potential of wiring 123 is set to "H" and the potential of wiring 126 is set to "V" data3 "Then transistor 103 conducts, and the potential of node NA is "V data3 "That's how it will be.

[0093] At this time, the potential of node NA is added to the potential of node NB by the capacitive coupling of the capacitive element 105. Therefore, the potential of node NB is "V data2 -V ref +V data3 " and "V ref If "=0", then the potential of node NB is "V data2 +V data3 "That's how it will be.

[0094] Furthermore, the capacitive coupling of the capacitive element 104 adds the potential of node NB to the potential of node NM. Therefore, the potential of node NM is "V data1 +V data2 +V data3 "That's how it will be.

[0095] If the potential of wiring 123 is "L" at time T22, then transistor 103 becomes non-conductive, and the potential of node NM is "V". data1 +V data2 +V data3 It is held in ".

[0096] Based on the above, the first data "V data1 "or the third data" V data3 The writing operation for “V” is completed. Note that if you do not want the third data to be reflected in the display, the third data “V” data3 “V ref You can simply supply the same potential as the previous one. Alternatively, you can omit the third data writing operation.

[0097] Subsequently, the display element of the circuit block 110 performs a display operation corresponding to the potential of node NM. Depending on the configuration of the circuit block, the display operation may also be performed from time T1 or time T11.

[0098] Furthermore, as shown in Figures 3(A), (B), and (C), the order of the operations shown in Figure 2(A) and Figure 2(B) may be reversed.

[0099] Using Figure 3(A), the first data "V data2 This explains the process of writing "" to node NB.

[0100] At time T1, the potential of wire 122 is set to "H", the potential of wire 123 is set to "H", and the potential of wire 125 is set to "V data2 ", set the potential of wiring 126 to "V ref "Then transistor 103 conducts, and the potential of node NA is "V ref This results in ". Also, transistor 102 conducts, and the potential of the wiring 125 at node NB (second data "V" data2 The following is written:

[0101] If the potential of wiring 122 and wiring 123 are set to "L" at time T2, transistors 102 and 103 become non-conductive, and the second data "V" is set at node NB. data2 “ is maintained. Also, the capacitive element 105 has “V data2 -V ref " is retained.

[0102] Next, using Figure 3(B), the first data "V data1 This explains the process of writing "" to node NM.

[0103] At time T11, the potential of wire 121 is set to "H", the potential of wire 122 is set to "H", and the potential of wire 124 is set to "V data1 ", the potential of wiring 125 is "V ref "Then transistor 102 conducts, and the potential of node NB is "V refThis results in ". Also, transistor 101 conducts, and the potential of wiring 124 at node MN (first data "V" data1 The following is written:

[0104] If the potential of wiring 121 is "L" and the potential of wiring 122 is "L" at time T12, then transistor 102 becomes non-conductive, and node NB has a "V" ref The first data "V" is retained. Also, node NM has the first data "V data1 “ is maintained. Also, the capacitive element 105 has “V data2 -V ref Because "V" is retained, ref If "=0", then the potential at node NA is "-V data1 "That's how it will be.

[0105] Next, using Figure 3(C), the third data "V data3 This explains the process of writing "".

[0106] At time T21, the potential of wiring 123 is set to "H" and the potential of wiring 126 is set to "V" data3 "Then transistor 103 conducts, and the potential of node NA is "V data3 "That's how it will be.

[0107] At this time, the potential of node NA is added to the potential of node NB by the capacitive coupling of the capacitive element 105. Therefore, the potential of node NB is "V data3 -(-V data2 )+V ref " and "V ref If "=0", then the potential of node NB is "V data2 +V data3 "That's how it will be.

[0108] Furthermore, the capacitive coupling of the capacitive element 104 adds the potential of node NB to the potential of node NM. Therefore, the potential of node NM is "V data1 +V data2 +V data3 "That's how it will be.

[0109] If the potential of wiring 123 is "L" at time T22, then transistor 103 becomes non-conductive, and the potential of node NM is "V". data1 +V data2 +V data3 It is held in ".

[0110] Based on the above, the first data "V data1 "or the third data" V data3 The write operation is completed.

[0111] The operations in Figures 2(A), (B), and (C) can be performed consecutively within one horizontal period. Alternatively, the operation in Figure 2(A) may be performed in the kth frame (where k is a natural number), and the operations in Figures 2(B) and (C) may be performed in the k+1th frame. Alternatively, the operations in Figures 2(A) and (B) may be performed in the kth frame, and the operation in Figure 2(C) may be performed in the k+1th frame. Alternatively, the operations in Figures 2(A), (B), and (C) may be performed in consecutive but different frames. Alternatively, the operation in Figure 2(A) may be performed in the kth frame, and the operations in Figures 2(B) and (C) may be repeated from the k+1th frame onward. Alternatively, the operations in Figures 2(A) and (B) may be performed in the kth frame, and the operation in Figure 2(C) may be repeated from the k+1th frame onward. The operations in Figures 3(A), (B), and (C) can be performed similarly. Furthermore, the above operation can also be applied to pixels with other configurations in this embodiment.

[0112] A pixel that can be used in a display device according to one aspect of the present invention may have the configuration of pixel 11 shown in Figure 4(A). In pixel 11, the source or drain of transistor 103 is electrically connected to wiring 124. Therefore, wiring 126 can be omitted. The other configurations are the same as those of pixel 10.

[0113] An example of the operation of pixel 11, which adds the second and third data to the first data, will be explained using the timing charts shown in Figures 4(B), (C), and (D). The procedure for writing the first data shown in Figure 4(B) is essentially the same as that for pixel 10, so the explanation will be omitted.

[0114] Using Figure 4(C), the second data "V data2 This explains the process of writing "" to node NB.

[0115] At time T11, the potential of wire 122 is set to "H", the potential of wire 123 is set to "H", and the potential of wire 124 is set to "V ref ", the potential of wiring 125 is "V data2 "Then transistor 103 conducts, and the potential of node NA is "V ref This operation is a reset operation in order to perform the subsequent capacitive coupling operation.

[0116] Also, transistor 102 conducts, and the potential of wiring 125 to node NB (second data "V") data2 The following is written:

[0117] At this time, the potential of node NB is added to the potential of node NM by the capacitive coupling of the capacitive element 104. Therefore, the potential of node NM is "V data1 -V ref +V data2 " and "V ref If "=0", then the potential at node NM is "V data1 +V data2 "That's how it will be.

[0118] If the potential of wiring 122 is "L" and the potential of wiring 123 is "L" at time T12, then transistor 102 becomes non-conductive, and the second data "V" is generated at node NB. data2 The value " is retained. Also, node NM contains "V", which is the sum of the first data and the second data. data1 +V data2 “ is maintained. Also, the capacitive element 105 has “V data2 -V ref " is retained.

[0119] This concludes the second data set, “V”. data2 This is a writing operation for ". Note that if you do not want the second data to be reflected in the display, the second data "V data2 “V ref "Just supply the same potential."

[0120] Next, using Figure 4(D), the third data "V data3 This explains the process of writing "".

[0121] At time T21, the potential of wiring 123 is set to "H" and the potential of wiring 124 is set to "V" data3 "If so, transistor 103 conducts, and the potential of node NA is "V data3 "That's how it will be.

[0122] At this time, the potential of the other electrode of the capacitive element 105 is added to the potential of node NB by capacitive coupling of the capacitive element 105. Therefore, the potential of node NB is "V data2 -V ref +V data3 " and "V ref If "=0", then the potential of node NB is "V data2 +V data3 "That's how it will be.

[0123] Furthermore, the capacitive coupling of the capacitive element 104 adds the potential of node NB to the potential of node NM. Therefore, the potential of node NM is "V data1 +V data2 +V data3 "That's how it will be.

[0124] If the potential of wiring 123 is "L" at time T22, then transistor 103 becomes non-conductive, and the potential of node NM is "V". data1 +V data2 +V data3 It is held in ".

[0125] Based on the above, the first data "V data1 "or the third data" V data3 The writing operation for “V” is completed. Note that if you do not want the third data to be reflected in the display, the third data “V” data3 “V ref You can simply supply the same potential as the previous one. Alternatively, you can omit the third data writing operation.

[0126] Subsequently, the display element of the circuit block 110 performs a display operation corresponding to the potential of node NM. Depending on the configuration of the circuit block, the display operation may also be performed from time T1 or time T11.

[0127] As explained above, since the first and third data can be supplied from wiring 124, the number of wires can be reduced. Although not explained here, pixel 11 can also perform operations equivalent to those shown in Figures 3(A) to (C).

[0128] Furthermore, a pixel that can be used in a display device according to one embodiment of the present invention may have the configuration of pixel 12 shown in Figure 5(A). Pixel 12 has a configuration in which transistors 106 and 107 are added to the configuration of pixel 10. Also, the wiring 125 and 126 required for pixel 10 can be omitted. The other configurations are the same as those of pixel 10.

[0129] In pixel 12, the other end of either the source or drain of transistor 102 is electrically connected to wiring 124. Also, the other end of either the source or drain of transistor 103 is electrically connected to wiring 124.

[0130] Furthermore, one of the sources or drains of transistor 106 is electrically connected to the other electrode of capacitive element 104. One of the sources or drains of transistor 107 is electrically connected to the other electrode of capacitive element 105. The gate of transistor 106 is electrically connected to wiring 121. The gate of transistor 107 is electrically connected to wiring 122.

[0131] The source or drain of transistor 106 is connected to a reference potential "V" ref The source or drain of transistor 107 is electrically connected to wiring capable of supplying the reference potential "V". ref It is electrically connected to wiring that can supply "V". refAs wiring that can supply "", for example, power lines that are electrically connected to the elements of the circuit block 110 can be used.

[0132] Furthermore, to efficiently perform capacitive coupling, the potential of the electrode opposite to the electrode on which the data of the capacitive element is written should be set to "V ref It is preferable to make it sufficiently smaller than the data in question, such as by setting it to "...

[0133] In pixel 10, data supply and “V ref The configuration is such that the power is supplied from the same wiring, but in pixel 12, the power line etc. is supplied from "V ref To supply the first to third data, the first to third data can be supplied from a single wire (wire 124). Therefore, the number of wires can be reduced, and wires 125 and 126 can be omitted.

[0134] An example of the operation of pixel 12, which adds the second and third data to the first data, will be explained using the timing charts shown in Figures 5(B), (C), and (D).

[0135] First, using Figure 5(B), we have the first data "V data1 This explains the process of writing "" to node NM.

[0136] At time T1, the potential of wiring 121 is set to "H" and the potential of wiring 124 is set to "V" data1 In this case, transistor 106 conducts, and the potential of node NB is "V ref This operation is a reset operation in order to perform the subsequent capacitive coupling operation.

[0137] Also, transistor 101 conducts, and the potential of wiring 124 at node NM (first data "V") data1 The following is written:

[0138] When the potential of wiring 121 is set to "L" at time T2, transistors 101 and 106 become non-conductive, and the first data "V" is generated at node NM. data1“ is maintained. Also, the capacitive element 104 has “V data1 -V ref " is retained.

[0139] This concludes the first data set "V". data1 This is a writing operation for "V". Note that if you do not want the first data to be reflected in the display, the first data "V data1 “V ref "Just supply the same potential."

[0140] Next, using Figure 5(C), we will examine the second data "V data2 This explains the process of writing "" to node NB.

[0141] At time T11, the potential of wire 122 is set to "H", the potential of wire 123 is set to "H", and the potential of wire 125 is set to "V". data2 ", set the potential of wiring 126 to "V ref "Then transistor 103 conducts, and the potential of node NA is "V ref This operation is a reset operation in order to perform the subsequent capacitive coupling operation.

[0142] Also, transistor 102 conducts, and the potential of wiring 125 to node NB (second data "V") data2 The following is written:

[0143] At this time, the potential of node NB is added to the potential of node NM by the capacitive coupling of the capacitive element 104. Therefore, the potential of node NM is "V data1 -V ref +V data2 " and "V ref If "=0", then the potential at node NM is "V data1 +V data2 "That's how it will be.

[0144] If the potential of wiring 122 is "L" and the potential of wiring 123 is "L" at time T12, then transistor 102 becomes non-conductive, and the second data "V" is generated at node NB. data2 The value " is retained. Also, node NM contains "V", which is the sum of the first data and the second data. data1 +Vdata2 “ is maintained. Also, the capacitive element 105 has “V data2 -V ref " is retained.

[0145] This concludes the second data set, “V”. data2 This is a writing operation for ". Note that if you do not want the second data to be reflected in the display, the second data "V data2 “V ref "Just supply the same potential."

[0146] Next, using Figure 5(D), the third data "V data3 This explains the process of writing "".

[0147] At time T21, the potential of wiring 123 is set to "H" and the potential of wiring 126 is set to "V" data3 "Then transistor 103 conducts, and the potential of node NA is "V data3 "That's how it will be.

[0148] At this time, the potential of the other electrode of the capacitive element 105 is added to the potential of node NB by capacitive coupling of the capacitive element 105. Therefore, the potential of node NB is "V data2 -V ref +V data3 " and "V ref If "=0", then the potential of node NB is "V data2 +V data3 "That's how it will be.

[0149] Furthermore, the capacitive coupling of the capacitive element 104 adds the potential of node NB to the potential of node NM. Therefore, the potential of node NM is "V data1 +V data2 +V data3 "That's how it will be.

[0150] If the potential of wiring 123 is "L" at time T22, then transistor 103 becomes non-conductive, and the potential of node NM is "V". data1 +V data2 +V data3 It is held in ".

[0151] Based on the above, the first data "V data1 "or the third data" V data3 The writing operation for “V” is completed. Note that if you do not want the third data to be reflected in the display, the third data “V” data3 “V ref You can simply supply the same potential as the previous one. Alternatively, you can omit the third data writing operation.

[0152] Subsequently, the display element of the circuit block 110 performs a display operation corresponding to the potential of node NM. Depending on the configuration of the circuit block, the display operation may also be performed from time T1 or time T11. Although not explained here, pixel 13 can also perform an operation equivalent to that shown in Figures 3(A) to (C).

[0153] Pixels 10, 11, and 12 show an example configuration in which two capacitive elements are connected in series, but as shown in Figure 6, even more capacitive elements C1 to C n The components may be connected in series. In this case, one transistor is added for each additional capacitive element. One of the sources or drains of the transistor is electrically connected to the wiring that connects one capacitive element to the other. That is, the number of nodes, such as node NB, increases.

[0154] The number of capacitive elements connected in series, n, is preferably 2 to 8, more preferably 2 to 6, and even more preferably 2 to 4. The more capacitive elements there are, the more the effects of one embodiment of the present invention can be enhanced. However, increasing the number of capacitive elements necessitates increasing the number of transistors and signal lines, which can lead to drawbacks such as a decrease in the pixel aperture ratio, a decrease in resolution, and insufficient signal input time. Therefore, the number of capacitive elements connected in series, n, is preferably within the above range depending on the application.

[0155] Figures 7(A) to (C) show examples of configurations that can be applied to circuit block 110 and include an EL element as a display element.

[0156] The configuration shown in Figure 7(A) includes a transistor 111, a capacitive element 113, and an EL element 114. One of the sources or drains of the transistor 111 is electrically connected to one electrode of the EL element 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitive element 113. The other electrode of the capacitive element 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to node NM.

[0157] The source or drain of transistor 111 is electrically connected to wiring 128. The other electrode of EL element 114 is electrically connected to wiring 129. Wires 128 and 129 have the function of supplying power. For example, wiring 128 can supply a high-potential power supply, and wiring 129 can supply a low-potential power supply.

[0158] In the configuration shown in Figure 7(A), current flows through the EL element 114 when the potential of node NM exceeds the threshold voltage of transistor 111. Therefore, the EL element 114 may begin to emit light at time T1 in the timing charts shown in Figures 2(A), 3(A), 4(B), or 5(B), which may limit its applications.

[0159] Figure 7(B) shows the configuration of Figure 4(A) with the addition of transistor 112. One source or drain of transistor 112 is electrically connected to one source or drain of transistor 111. The other source or drain of transistor 112 is electrically connected to EL element 114. The gate of transistor 112 is electrically connected to wiring 127. Wiring 127 can function as a signal line to control the conduction of transistor 112.

[0160] In this configuration, current flows through the EL element 114 when the potential of node NM is greater than or equal to the threshold voltage of transistor 111 and transistor 112 conducts. Therefore, the EL element 114 can start emitting light after time T22 in the timing chart shown in Figure 2(C), Figure 3(C), Figure 4(D), or Figure 5(D), making it suitable for operation with correction.

[0161] Figure 7(C) shows the configuration of Figure 6(B) with the addition of transistor 115. One of the sources or drains of transistor 115 is electrically connected to one of the sources or drains of transistor 111. The other of the sources or drains of transistor 115 is electrically connected to wiring 130. The gate of transistor 115 is electrically connected to wiring 131. Wiring 131 can function as a signal line to control the conduction of transistor 115. The gate of transistor 115 may also be electrically connected to wiring 123.

[0162] Wiring 130 can be electrically connected to a source of a specific potential, such as a reference potential. By supplying a specific potential from wiring 130 to either the source or drain of transistor 111, the writing of image data can also be stabilized.

[0163] Furthermore, the wiring 130 can be connected to the circuit 120 and can also function as a monitoring line. The circuit 120 may have one or more functions, such as supplying the specific potential, acquiring the electrical characteristics of the transistor 111, and generating correction data.

[0164] If wiring 130 is used as a monitor line, for example, circuit 120 can generate a potential that corrects the threshold voltage of transistor 111 as the first data to be written to node NM.

[0165] Here, as shown in Figure 5(A) “V refTransistors 106 and 107, which supply "V", can be electrically connected to wiring 128 as shown in Figure 7(D). ref Since " is preferably 0V, GND, or a low potential, wiring 128 also has the function of supplying at least one of those potentials. Wiring 128 has "V" at the timing when writing data to node NM or node NB. ref The system should supply a voltage, and a high-potential power supply should be provided at the timing when the EL element 114 is to emit light.

[0166] Figures 8(A) to 8(C) show examples of configurations that can be applied to circuit block 110 and include liquid crystal elements as display elements.

[0167] The configuration shown in Figure 8(A) includes a capacitive element 116 and a liquid crystal element 117. One electrode of the liquid crystal element 117 is electrically connected to one electrode of the capacitive element 116. One electrode of the capacitive element 116 is electrically connected to node NM.

[0168] The other electrode of the capacitive element 116 is electrically connected to the wiring 132. The other electrode of the liquid crystal element 117 is electrically connected to the wiring 133. Wires 132 and 133 have the function of supplying power. For example, wires 132 and 133 can supply a reference potential such as GND or 0V, or any arbitrary potential.

[0169] In this configuration, the liquid crystal element 117 starts operating when the potential of node NM exceeds the operating threshold of the liquid crystal element 117. Therefore, the display operation may start at time T1 in the timing chart shown in Figure 2(A), Figure 3(A), Figure 4(B), or Figure 5(B), which may limit its applications. However, in the case of a transmissive liquid crystal display device, visibility can be suppressed even if unnecessary display operations occur by using operations such as turning off the backlight until time T22 as shown in Figure 2(C), Figure 3(C), Figure 4(D), or Figure 5(D).

[0170] Figure 8(B) shows the configuration of Figure 8(A) with the addition of transistor 118. One of the sources or drains of transistor 118 is electrically connected to one electrode of the capacitive element 116. The other of the sources or drains of transistor 118 is electrically connected to node NM. The gate of transistor 118 is electrically connected to wiring 127. Wiring 127 can function as a signal line to control the conduction of transistor 118.

[0171] In this configuration, the potential at node NM is applied to the liquid crystal element 117 when the transistor 118 conducts. Therefore, the liquid crystal element can start operating after time T22 in the timing chart shown in Figure 2(C), Figure 3(C), Figure 4(D), or Figure 5(D), making it suitable for operation involving correction.

[0172] Furthermore, since the potential supplied to the capacitive element 116 and the liquid crystal element 117 is maintained while transistor 118 is non-conductive, it is preferable to reset the potential supplied to the capacitive element 116 and the liquid crystal element 117 before rewriting the image data. This reset can be performed, for example, by supplying a reset potential to the wiring 123 and simultaneously making transistors 103 and 118 conductive.

[0173] Figure 8(C) shows the configuration of Figure 8(B) with the addition of transistor 119. One of the sources or drains of transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the sources or drains of transistor 119 is electrically connected to wiring 130. The gate of transistor 119 is electrically connected to wiring 131. Wiring 131 can function as a signal line to control the conduction of transistor 119. The gate of transistor 119 may also be electrically connected to wiring 123.

[0174] The circuit 120 electrically connected to the wiring 130 is the same as described in Figure 7(C) above, and may also have a function to reset the potential supplied to the capacitive element 116 and the liquid crystal element 117.

[0175] Also, transistors 106 and 107 for supplying “V ref ” shown in FIG. 5(A) can be electrically connected to wiring 132 as shown in FIG. 8(D).

[0176] Also, in FIGS. 7(D) and 8(D), an example of supplying “V ref ” from a power supply line is shown, but it can also be supplied from a scanning line. For example, as shown in FIG. 9(A), “V ref ” may be supplied from wiring 121 and wiring 123, etc. For example, as shown in FIG. 2(A), when writing data to node NM (when transistor 101 is conductive), since wiring 123 is supplied with a potential corresponding to “L”, this potential can be used as “V ref ”. Also, as shown in FIG. 2(B), when writing data to node NB (when transistor 102 is conductive), since wiring 121 is supplied with a potential corresponding to “L”, this potential can be used as “V ref ”.

[0177] Also, as shown in FIGS. 9(B) and (C), transistors 101, 102, and 103 may have a configuration with a back gate. FIG. 9(B) shows a configuration in which the back gate is electrically connected to the front gate and has the effect of increasing the on-current. FIG. 9(C) shows a configuration in which the back gate is electrically connected to wiring 134 that can supply a fixed potential and can control the threshold voltage of the transistor. Note that the configuration shown in FIG. 9(B) and the configuration shown in FIG. 9(C) may be appropriately combined. Also, a back gate may be provided for the transistors included in circuit block 110 shown in FIGS. 7(A) to (C) and FIGS. 8(A) to (C).

[0178] Next, the correction operation of the image data will be described using FIG. 10(A).

[0179] The figure shown in Fig. 10(A) shows an example of data potentials input to four pixels (P1 to P4) in the horizontal and vertical directions, including the first data (+A1, +A2, -A1, A0), the second data (+B1, B0, B0, -B1), the third data (+C3, C2, C2, +C1), and the generated image data. In the display element, display can be performed according to the sum of the first to third data, and correction of the original image can be performed.

[0180] For example, the first data and the second data can be used as correction data. Also, the third data can be used as the original image data.

[0181] In such a combination of correction data and image data, any one of up-conversion, HDR display, correction of display unevenness specific to the display device, correction of the threshold voltage of the transistor possessed by the pixel, etc. can be performed. Or, these can be combined and performed.

[0182] In the up-conversion operation, for example, the same image data is supplied to all four pixels. Different images can be displayed at each pixel by correction. For example, image data applied to a specific one pixel of a display device having a pixel count of 4K×2K is input to specific four pixels of a display device having a pixel count of 8K×4K, and display with improved resolution can be performed.

[0183] Also, by using the same image data as the first to third data, the luminance of the displayed image can be significantly improved. In this operation, since a voltage equal to or higher than the maximum output value of the column driver can be supplied to the pixel circuit, not only the image quality can be improved, but also the product cost can be reduced, such as reducing power consumption and using an inexpensive driver IC chip.

[0184] Furthermore, although it is broadly considered image data correction, it is possible to overlay and display different images. Figure 10(B) shows an image of the entire display unit, and shows a composite image of the first image composed of the first data, the second image composed of the second data, the third image composed of the third data, the first image, the second image, and the third image.

[0185] Such combinations of different image data can be applied to, for example, text insertion or augmented reality (AR) display.

[0186] In the pixels 10, 11, and 12 described above, the respective configurations can be arranged in a matrix as elements of a single pixel to form a pixel array. Alternatively, some transistors can be shared among the pixels to provide additional functionality. Sharing transistors reduces the number of wires, improving the pixel aperture ratio, resolution, and reducing power consumption through more efficient signal line charging and discharging and improved driver operation.

[0187] Figure 11 shows a portion (16 pixels) of a pixel array having pixels 13 to which the basic configuration of pixel 10 is applied. Pixel 13 is provided with a transistor 101, a capacitive element 104, and a circuit block 110. Note that n and m in parentheses attached to the symbols represent a specific row, and i, j, and k represent a specific column (n, m, i, j, and k are natural numbers).

[0188] The pixel array is provided with a transistor 102 connected to four pixels 13. It is also provided with a capacitive element 105 connected to four pixels 13. Furthermore, it is provided with a transistor 103 connected to four capacitive elements 105.

[0189] Furthermore, assuming the basic configuration of pixel 10, it can be said that transistor 102 and capacitive element 105 are elements of each pixel 13 and are shared by four pixels. Also, it can be said that transistor 103 is an element of each pixel 13 and is shared by 16 pixels.

[0190] In this pixel array, several of the same operations can be performed with a configuration that uses fewer wires and transistors than a configuration in which the pixels 10 are simply arranged in a matrix.

[0191] Furthermore, even if the resolution of the display device and the image data differ, appropriate display can be achieved without upconversion or downconversion by switching the input paths for the image data and correction data. Basically, the system can be operated according to the timing charts shown in Figures 2(A) to (C) or Figures 3(A) to (C).

[0192] The following describes an example of displaying image data of different resolutions when the pixel array supports 8K and 4K resolutions. Note that other pixel arrays, as described later, can perform similar display operations.

[0193] First, let's explain the case where 8K4K resolution image data is used for display. When displaying 8K4K resolution image data, the image data should be written as first data to each pixel node NM via transistor 101. At this time, if second data is supplied via transistor 102, the second data can be added to the four pixel nodes NM that share transistor 102. Furthermore, if third data is supplied via transistor 103, the third data can be added to the sixteen pixel nodes NM that share transistor 103. In other words, image correction and overlay can be performed using the second and third data.

[0194] Next, we will explain the case of displaying using 4K2K resolution image data. When displaying with 4K2K image data, the image data should be written as second data to the node NB of each pixel. Since the second data is supplied to 4 pixels, even with an 8K4K resolution pixel array, display can be performed without generating new image data.

[0195] At this time, if the first data is supplied to each pixel node NM via transistor 101, different displays can be made at each pixel. This operation makes it possible, for example, to upconvert from 4K2K resolution to 8K4K resolution. Furthermore, if the third data is supplied via transistor 103, the third data can be added to the 16 pixel nodes NM that share transistor 103. In other words, image correction and overlay can be performed using the first data and the third data.

[0196] Next, we will explain the case where image data with FullHD resolution is used for display. When displaying with FullHD image data, the image data is written to each pixel as third data via transistor 103. Since the third data is supplied to 16 pixels, even with an 8K4K resolution pixel array, display can be performed without generating new image data.

[0197] At this time, if the first data is supplied to each pixel node NM via transistor 101, different displays can be performed at each pixel. This operation enables upconversion from FullHD resolution to 8K / 4K resolution, for example. Furthermore, if the second data is supplied via transistor 102, a third data can be added to the four pixel nodes NM that share transistor 102. In other words, image correction and overlay can be performed using the first and second data.

[0198] Figure 12 shows a portion (16 pixels) of a pixel array having pixels 14 to which the basic configuration of pixel 11 is applied. The components are the same as the pixel array shown in Figure 10, except that wiring 126 is omitted and the other side of the source or drain of transistor 103 is connected to wiring 124. Note that although the other side of the source or drain of transistor 103 is shown connected to wiring 124[i], it may also be connected to wiring 124[i+1]. The pixel array shown in Figure 12 can be operated according to the timing charts shown in Figures 4(B) to (D).

[0199] FIG. 13 is a diagram showing a part (for 16 pixels) of a pixel array having a pixel 15 to which the basic configuration of pixel 12 is applied. In pixel 15, a transistor 101, a capacitor element 104, and a circuit block 110 are provided, similar to pixel 13 and pixel 14. Although an example where the other of the source or drain of transistor 103 is connected to wiring 124[i] is shown, it may be connected to wiring 124[i+1]. The pixel array shown in FIG. 13 can be operated according to the timing charts shown in FIGS. 5(B) to (D).

[0200] The pixel array is provided with a transistor 102 connected to four pixels 15. Also, a transistor 106 connected to four pixels 15 is provided. Also, a capacitor element 105 connected to four pixels 15 is provided. Also, a transistor 107 connected to four capacitor elements 105 is provided. Also, a transistor 103 connected to four capacitor elements 105 is provided. Although the electrical connection state is as described above, the operation of transistor 106 follows the operation of two pixels 15 sharing a gate line.

[0201] Assuming the basic configuration of pixel 12, transistor 102 and capacitor element 105 can be said to be elements of each pixel 15 and are shared by four pixels. Also, transistor 106 can be said to be an element of each pixel 15 and is shared by two pixels. Also, transistor 107 can be said to be an element of each pixel 15 and is shared by eight pixels. Also, transistor 103 can be said to be an element of each pixel 15 and is shared by 16 pixels.

[0202] Figure 14(A) is an example of a block diagram of a display device to which the pixel array shown in Figure 11 is applied. This display device has a pixel array 19 in which pixels 13 are arranged in a matrix, a low driver 31, a column driver 32, a circuit 33, and a selection circuit 34. In Figure 14(A), elements to which data can be individually input via transistor 101 are represented as pixels 13, a group of four pixels to which the same data can be input via transistor 102 is represented as a pixel block 17, and a group of sixteen pixels to which the same data can be input via transistor 103 is represented as a pixel block 18.

[0203] Although the number of wires connecting each driver to the pixels differs from the above, the pixel array shown in Figure 12 or Figure 13 can also be applied to the display device.

[0204] The low driver 31 can be configured, for example, by combining a shift register 20 and a buffer circuit 21. By controlling the conduction of the buffer circuit 21, data can be output to wiring 121 or wiring 122.

[0205] The column driver 32 can be configured, for example, by combining a shift register 22 and a buffer circuit 23. By controlling the conduction of the buffer circuit 23, data can be output to the wiring 123. Furthermore, it may also be configured by combining it with a selection circuit.

[0206] Circuit 33 has the function of generating correction data. Circuit 33 can also be considered an external device for generating correction data. Here, correction data is data generated based on the main image data and corresponds to one of the first to third types of data described above.

[0207] The low driver 31 can control the conduction of transistors 101 and 102, 103. The column driver 32 can supply first to third data to wirings 124, 125, 126.

[0208] The first to third data can be input to circuit 33. Circuit 33 generates correction data for upconversion and brightness correction according to the main image data and outputs it as one of the first to third data.

[0209] The selection circuit 34 can receive correction data generated by circuit 33 as well as first, second, and third data, and can output any of them to the column driver 32.

[0210] Note that the generation of correction data can be performed not only by circuit 33 but also by the aforementioned circuit 120 (see Figure 14(B)). Alternatively, the display unit may display a grayscale image, and the correction data may be generated based on data read from a luminance meter or data read from a photograph of the display. Furthermore, a sensor 24 capable of detecting the brightness of the display may be provided, and a circuit 25 capable of detecting the deterioration of the display element and generating correction data may be provided (see Figure 14(C)).

[0211] Circuits 33 and 25 may have neural networks. For example, by using a deep neural network trained on a vast amount of images as training data, it is possible to generate highly accurate correction data.

[0212] As shown in Figure 15(A), a neural network (NN) can be composed of an input layer (IL), an output layer (OL), and a hidden layer (HL). Each of the input layer (IL), output layer (OL), and hidden layer (HL) has one or more neurons (units). The hidden layer (HL) may be one layer or two or more layers. A neural network with two or more hidden layers (HL) can be called a DNN (Deep Neural Network), and learning using a deep neural network can be called deep learning.

[0213] Each neuron in the input layer (IL) receives input data, each neuron in the hidden layer (HL) receives the output signal of a neuron in the preceding or succeeding layer, and each neuron in the output layer (OL) receives the output signal of a neuron in the preceding layer. Each neuron may be connected to all neurons in the preceding and succeeding layers (fully connected), or to some of the neurons.

[0214] Figure 15(B) shows an example of computation by neurons. Here, we show neuron N and two neurons in the pre-layer that output signals to neuron N. Neuron N receives the outputs x1 and x2 of the pre-layer neurons as inputs. Then, in neuron N, the sum x1w1 + x2w2 is calculated by multiplying the output x1 by the weight w1 (x1w1) and the output x2 by the weight w2 (x2w2). After that, a bias b is added as needed to obtain the value a = x1w1 + x2w2 + b. The value a is then transformed by the activation function h, and the output signal y = h(a) is output from neuron N.

[0215] Thus, the calculations performed by neurons include operations that add up the products of the outputs of neurons in the previous layer and their weights, i.e., sum-of-products operations (x1w1 + x2w2 above). These sum-of-products operations may be performed in software using a program, or they may be performed in hardware. When performing sum-of-products operations in hardware, a sum-of-products circuit can be used. This sum-of-products circuit may be a digital circuit or an analog circuit.

[0216] The multiply-accumulate circuit may be constructed using either Si transistors or OS transistors. OS transistors are particularly suitable as the transistors that constitute the analog memory of the multiply-accumulate circuit because they have extremely low off-currents. Alternatively, the multiply-accumulate circuit may be constructed using both Si transistors and OS transistors.

[0217] Next, we will explain the simulation results for a configuration in which the circuit block shown in Figure 8(A) is applied to the pixel 10 shown in Figure 1 (see Figure 16). The parameters were as follows: all transistor sizes were L / W = 4μm / 4μm, the capacitance value of capacitive element 104 was 500fF, the capacitance value of capacitive element 105 was 500fF, the capacitance value of capacitive element 116 was 100fF, and the capacitance value of liquid crystal element 117 was 50fF. The potential of wiring 132 and wiring 133 was set to 0V, and it was assumed that the source driver IC could output linearly from -5V to +5V. The potential of node NM was estimated when the same voltage was written for the first data (D1) to the third data (D3). SPICE was used as the circuit simulation software.

[0218] Figure 17(A) is the timing chart used in the simulation, and it follows the operation described in Figures 3(A) to (C). The data was written in the order of the second data (D2), the first data (D1), and the third data (D3), with the same value written to each data.

[0219] Figure 17(B) shows the simulation results. It compares a configuration in which transistors 102, 103 and capacitive elements 104, 105 are omitted and only the first data (D1) can be input (Conventional), a configuration in which transistor 103 and capacitive element 105 are omitted and both the first data (D1) and the second data (D2) can be input (MEM_×1), and the configuration of the present invention (MEM_×2).

[0220] Simulation results confirmed that, in the present invention's configuration (MEM_×2), the potential applied to the pixel electrodes can be made sufficiently larger than the output of the driver IC. Furthermore, it was confirmed that even negative values ​​can be made large in absolute value. These features are useful for inverting drive and driving liquid crystal elements that require high voltage. Similarly, it becomes possible to apply a high potential to the gate of the drive transistor for EL elements.

[0221] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0222] (Embodiment 2) This embodiment describes examples of display device configurations using liquid crystal elements and EL elements. Note that in this embodiment, the descriptions of the elements, operation, and functions of the display device described in Embodiment 1 are omitted.

[0223] Figures 18(A) to (C) show the configuration of a display device that can be used in one aspect of the present invention.

[0224] In Figure 18(A), a sealing material 4005 is provided so as to surround the display unit 215 which is provided on the first substrate 4001, and the display unit 215 is sealed by the sealing material 4005 and the second substrate 4006.

[0225] The display unit 215 can be provided with a pixel array having any of the pixels 10 to 15 shown in Embodiment 1. The scan line driving circuit described below corresponds to a low driver, and the signal line driving circuit corresponds to a column driver.

[0226] In Figure 18(A), the scan line drive circuit 221a, signal line drive circuit 231a, signal line drive circuit 232a, and common line drive circuit 241a each have multiple integrated circuits 4042 provided on the printed circuit board 4041. The integrated circuits 4042 are formed from single-crystal or polycrystalline semiconductors. The signal line drive circuit 231a and signal line drive circuit 232a have the function of a column driver as shown in Embodiment 1. The scan line drive circuit 221a has the function of a low driver as shown in Embodiment 1. The common line drive circuit 241a has the function of supplying a specified potential to wiring 128, 129, 132, 133, etc., as shown in Embodiment 1.

[0227] The various signals and potentials supplied to the scan line drive circuit 221a, the common line drive circuit 241a, the signal line drive circuit 231a, and the signal line drive circuit 232a are supplied via the FPC (Flexible printed circuit) 4018.

[0228] The integrated circuit 4042 in the scan line drive circuit 221a and the common line drive circuit 241a has the function of supplying selection signals to the display unit 215. The integrated circuit 4042 in the signal line drive circuit 231a and the signal line drive circuit 232a has the function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in an area different from the area surrounded by the sealing material 4005 on the first substrate 4001.

[0229] The connection method for the integrated circuit 4042 is not particularly limited, and methods such as wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), and COF (Chip On Film) can be used.

[0230] Figure 18(B) shows an example of mounting the integrated circuit 4042 included in the signal line drive circuits 231a and 232a using the COG method. Furthermore, a part or all of the drive circuit can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel.

[0231] Figure 18(B) shows an example in which the scan line drive circuit 221a and the common line drive circuit 241a are formed on the same substrate as the display unit 215. By forming the drive circuits simultaneously with the pixel circuits in the display unit 215, the number of components can be reduced. Therefore, productivity can be increased.

[0232] Furthermore, in Figure 18(B), a sealing material 4005 is provided so as to surround the display unit 215, the scan line drive circuit 221a, and the common line drive circuit 241a, which are provided on the first substrate 4001. A second substrate 4006 is also provided on top of the display unit 215, the scan line drive circuit 221a, and the common line drive circuit 241a. Thus, the display unit 215, the scan line drive circuit 221a, and the common line drive circuit 241a are sealed together with the display elements by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0233] Furthermore, Figure 18(B) shows an example in which the signal line drive circuits 231a and 232a are formed separately and mounted on the first substrate 4001, but the configuration is not limited to this. The scan line drive circuit may be formed separately and mounted, or a part of the signal line drive circuit or a part of the scan line drive circuit may be formed separately and mounted. Also, as shown in Figure 18(C), the signal line drive circuits 231a and 232a may be formed on the same substrate as the display unit 215.

[0234] Furthermore, the display device may include a panel in which the display elements are sealed, and a module on which an IC including a controller is mounted.

[0235] Furthermore, the display unit and scan line driving circuit provided on the first substrate have multiple transistors. The transistors shown in the above embodiment can be used as such.

[0236] The transistors in the peripheral drive circuit and the transistors in the pixel circuit of the display unit may have the same structure or be different. The transistors in the peripheral drive circuit may all have the same structure or may have two or more different structures. Similarly, the transistors in the pixel circuit may all have the same structure or may have two or more different structures.

[0237] Furthermore, an input device 4200 can be provided on the second substrate 4006. The display device shown in Figures 18(A) to (C) with the input device 4200 can function as a touch panel.

[0238] The detection element (also called a sensor element) of a touch panel according to one aspect of the present invention is not limited. Various sensors capable of detecting the proximity or contact of an object to be detected, such as a finger or stylus, can be applied as the detection element.

[0239] Various sensor types can be used, such as capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0240] In this embodiment, a touch panel having a capacitive sensing element will be used as an example for explanation.

[0241] Capacitive capacitance methods include surface capacitance and projected capacitance. Projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0242] A touch panel according to one aspect of the present invention can be configured in various ways, such as a configuration in which a separately manufactured display device and a detection element are bonded together, or a configuration in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0243] Figures 19(A) and (B) show examples of touch panels. Figure 19(A) is a perspective view of the touch panel 4210. Figure 19(B) is a schematic perspective view of the input device 4200. For clarity, only representative components are shown.

[0244] The touch panel 4210 has a configuration in which a display device and a sensing element, which were manufactured separately, are bonded together.

[0245] The touch panel 4210 has an input device 4200 and a display device, which are mounted on top of each other.

[0246] The input device 4200 includes a substrate 4263, electrodes 4227 and 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, electrode 4227 can be electrically connected to wiring 4237 or wiring 4239. Also, electrode 4228 can be electrically connected to wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and the plurality of wirings 4238. IC 4273b can be provided on the FPC 4272b.

[0247] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. If a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to a capacitive touch sensor, an optical touch sensor using a photoelectric conversion element may be applied.

[0248] Figures 20(A) and (B) are cross-sectional views of the area indicated by the dashed line N1-N2 in Figure 18(B). The display device shown in Figures 20(A) and (B) has an electrode 4015, which is electrically connected to the terminals of the FPC 4018 via an anisotropic conductive layer 4019. In addition, in Figures 20(A) and (B), the electrode 4015 is electrically connected to the wiring 4014 at openings formed in the insulating layer 4112, insulating layer 4111, and insulating layer 4110.

[0249] Electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and wiring 4014 is formed from the same conductive layer as the source and drain electrodes of transistors 4010 and 4011.

[0250] Furthermore, the display unit 215 and the scan line driving circuit 221a, which are provided on the first substrate 4001, have multiple transistors. Figures 20(A) and (B) illustrate transistor 4010 included in the display unit 215 and transistor 4011 included in the scan line driving circuit 221a. In Figures 20(A) and (B), bottom-gate type transistors are illustrated as transistors 4010 and 4011, but top-gate type transistors may also be used.

[0251] In Figures 20(A) and (B), an insulating layer 4112 is provided on transistors 4010 and 4011. Also, in Figure 20(B), a partition wall 4510 is formed on the insulating layer 4112.

[0252] Furthermore, transistors 4010 and 4011 are provided on an insulating layer 4102. Transistors 4010 and 4011 also have electrodes 4017 formed on an insulating layer 4111. Electrodes 4017 can function as back gate electrodes.

[0253] Furthermore, the display device shown in Figures 20(A) and (B) has a capacitive element 4020. The capacitive element 4020 has an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and electrodes formed in the same process as the source electrode and drain electrode. The respective electrodes overlap via an insulating layer 4103.

[0254] Generally, the capacitance of a capacitive element provided in the pixel portion of a display device is set to hold a charge for a predetermined period of time, taking into account the leakage current of the transistors arranged in the pixel portion. The capacitance of the capacitive element should be set considering the off-current of the transistors, etc.

[0255] A transistor 4010 provided in the display unit 215 is electrically connected to the display element. Figure 20(A) shows an example of a liquid crystal display device using a liquid crystal element as the display element. In Figure 20(A), the liquid crystal element 4013, which is the display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. In addition, insulating layers 4032 and 4033, which function as alignment films, are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are superimposed via the liquid crystal layer 4008.

[0256] Furthermore, the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. A spherical spacer may also be used.

[0257] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a phase difference member, and an anti-reflective member may be provided as needed. For example, circular polarization using a polarizing substrate and a phase difference substrate may be used. Also, a backlight, a sidelight, etc. may be used as the light source. Micro LEDs, etc., may be used as the backlight and sidelight.

[0258] In the display device shown in Figure 20(A), a light-shielding layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.

[0259] Materials that can be used as a light-shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. In addition, a laminated film containing the material for the colored layer can be used as the light-shielding layer. For example, a laminated structure can be used in which a film containing the material for a colored layer that transmits light of one color and a film containing the material for a colored layer that transmits light of another color are used. It is preferable to use the same materials for the colored layer and the light-shielding layer because it is possible to use the same equipment and simplify the process.

[0260] Materials that can be used for the colored layer include metal materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and the colored layer can be formed, for example, using an inkjet method.

[0261] Furthermore, the display device shown in Figures 20(A) and (B) has an insulating layer 4111 and an insulating layer 4104. Insulating layers 4111 and 4104 are used, which are less permeable to impurity elements. By sandwiching the semiconductor layer of the transistor between insulating layers 4111 and 4104, the intrusion of impurities from the outside can be prevented.

[0262] Furthermore, an electroluminescent light-emitting element (EL element) can be used as a display element included in the display device. An EL element has a layer containing a light-emitting compound (also called the "EL layer") between a pair of electrodes. When a potential difference greater than the threshold voltage of the EL element is created between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting compound contained in the EL layer emits light.

[0263] Furthermore, EL elements are distinguished by whether the light-emitting material is an organic compound or an inorganic compound; generally, the former are called organic EL elements, and the latter are called inorganic EL elements.

[0264] In organic light-emitting diodes (ELs), applying a voltage injects electrons into the EL layer from one electrode and holes from the other. These carriers (electrons and holes) then recombine, causing the luminescent organic compound to form an excited state. When this excited state returns to the ground state, it emits light. Because of this mechanism, such light-emitting devices are called current-excited light-emitting devices.

[0265] In addition to luminescent compounds, the EL layer may also contain materials with high hole injection properties, materials with high hole transport properties, hole blocking materials, materials with high electron transport properties, materials with high electron injection properties, or bipolar materials (materials with high electron transport and hole transport properties).

[0266] The EL layer can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0267] Inorganic electroluminescent (EL) devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices based on their device configuration. Dispersed inorganic EL devices have an emissive layer in which particles of emissive material are dispersed in a binder, and their emissive mechanism is donor-acceptor recombination type emissive emission, which utilizes donor and acceptor levels. Thin-film inorganic EL devices have a structure in which the emissive layer is sandwiched between dielectric layers, and then sandwiched between electrodes, and their emissive mechanism is localized type emissive emission, which utilizes inner-shell electron transitions of metal ions. For the purposes of this explanation, organic EL devices will be used as the light-emitting element.

[0268] A light-emitting element only needs to have at least one of its pair of electrodes transparent in order to extract light. A transistor and light-emitting element are formed on a substrate, and there are light-emitting elements with various emission structures, including a top emission structure where light is extracted from the side opposite the substrate, a bottom emission structure where light is extracted from the side facing the substrate, and a dual emission structure where light is extracted from both sides. Any of these emission structures can be applied to the light-emitting element.

[0269] Figure 20(B) shows an example of a light-emitting display device (also called an "EL display device") that uses a light-emitting element as a display element. The light-emitting element 4513, which is the display element, is electrically connected to a transistor 4010 provided in the display unit 215. The configuration of the light-emitting element 4513 is a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, but is not limited to this configuration. The configuration of the light-emitting element 4513 can be appropriately changed according to the direction of the light emitted from the light-emitting element 4513.

[0270] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material and form an opening on the first electrode layer 4030 so that the side surface of the opening is an inclined surface with a continuous curvature.

[0271] The light-emitting layer 4511 may consist of a single layer or multiple layers stacked on top of each other.

[0272] The light-emitting color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, or yellow, depending on the material that makes up the light-emitting layer 4511.

[0273] There are two methods for achieving color display: one involves combining a white-emitting light-emitting element 4513 with a colored layer, and the other involves providing a different-colored light-emitting element 4513 for each pixel. The former method is more productive than the latter. On the other hand, the latter method requires creating a different light-emitting layer 4511 for each pixel, making it less productive than the former method. However, the latter method can produce a more color-pure emitted color than the former method. In addition to the latter method, the color purity can be further improved by adding a microcavity structure to the light-emitting element 4513.

[0274] The light-emitting layer 4511 may also contain inorganic compounds such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

[0275] A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513. The protective layer can be made of silicon nitride, silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, DLC (Diamond-Like Carbon), etc. Furthermore, a filler material 4514 is provided to seal the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this manner, it is preferable to package (encapsulate) the device with a protective film (laminated film, UV-curing resin film, etc.) or cover material that is highly airtight and minimizes degassing, so as not to expose it to the outside air.

[0276] As the filler 4514, in addition to inert gases such as nitrogen and argon, ultraviolet-curing resins or thermosetting resins can be used, and PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. Furthermore, the filler 4514 may contain a desiccant.

[0277] The sealing material 4005 can be made of glass materials such as glass frit, resin materials such as two-component resins that harden at room temperature, photocurable resins, or thermosetting resins. The sealing material 4005 may also contain a desiccant.

[0278] Furthermore, if necessary, optical films such as polarizers, circular polarizers (including elliptical polarizers), phase difference plates (λ / 4 plates, λ / 2 plates), and color filters may be appropriately provided on the emission surface of the light-emitting element. An anti-reflective coating may also be provided on the polarizer or circular polarizer. For example, an anti-glare treatment can be applied that diffuses reflected light due to surface irregularities, thereby reducing reflections.

[0279] Furthermore, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. In addition, by combining the microcavity structure with a color filter, reflections can be reduced, improving the visibility of the displayed image.

[0280] In the first and second electrode layers (also called pixel electrode layers, common electrode layers, or counter electrode layers) that apply voltage to the display element, the light transmittance and reflectivity can be selected based on the direction of the extracted light, the location where the electrode layers are provided, and the pattern structure of the electrode layers.

[0281] The first electrode layer 4030 and the second electrode layer 4031 can be made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added.

[0282] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of the following metals, alloys thereof, or metal nitrides, such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag).

[0283] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof consisting of two or more of aniline, pyrrole, and thiophene.

[0284] Furthermore, since transistors are susceptible to damage from static electricity and other factors, it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using nonlinear elements.

[0285] Furthermore, as shown in Figure 21, a stack structure may be used in which transistors and capacitive elements have overlapping regions in the height direction. For example, by stacking transistors 4011 and 4022 that constitute the drive circuit, a narrow-bezel display device can be created. Also, by arranging transistors 4010, 4023, and capacitive elements 4020 that constitute the pixel circuit so that they overlap in some areas, the aperture ratio and resolution can be improved. Note that Figure 21 shows an example of applying a stack structure to the liquid crystal display device shown in Figure 20(A), but it may also be applied to the EL display device shown in Figure 20(B).

[0286] Furthermore, in pixel circuits, using a highly transparent conductive film with high light transmission to visible light for electrodes and wiring can increase the light transmittance within the pixel, effectively improving the aperture ratio. When using OS transistors, the semiconductor layer is also transparent, allowing for an even greater improvement in the aperture ratio. These methods are also effective when transistors are not arranged in a stacked structure.

[0287] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0288] (Embodiment 3) In this embodiment, an example of a transistor that can be used as a replacement for each of the transistors shown in the above embodiment will be described with reference to the drawings.

[0289] A display device according to one aspect of the present invention can be manufactured using various types of transistors, such as bottom-gate transistors and top-gate transistors. Therefore, the semiconductor layer material and transistor structure used can be easily replaced to match existing manufacturing lines.

[0290] [Bottom-gate transistor] Figure 22(A1) is a cross-sectional view in the channel length direction of a channel-protected transistor 810, which is a type of bottom-gate transistor. In Figure 22(A1), the transistor 810 is formed on a substrate 771. The transistor 810 also has an electrode 746 on the substrate 771 via an insulating layer 772. Furthermore, the electrode 746 has a semiconductor layer 742 via an insulating layer 726. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0291] Furthermore, an insulating layer 741 is provided on the channel-forming region of the semiconductor layer 742. Also, electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the semiconductor layer 742. Electrode 744a can function as either a source electrode or a drain electrode. Electrode 744b can function as either a source electrode or a drain electrode. A portion of electrode 744a and a portion of electrode 744b are formed on the insulating layer 741.

[0292] The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 741 on the channel formation region, exposure of the semiconductor layer 742 that occurs during the formation of electrodes 744a and 744b can be prevented. Therefore, etching of the channel formation region of the semiconductor layer 742 during the formation of electrodes 744a and 744b can be prevented. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0293] Furthermore, the transistor 810 has an insulating layer 728 on electrodes 744a and 744b and insulating layer 741, and an insulating layer 729 on insulating layer 728.

[0294] When an oxide semiconductor is used for the semiconductor layer 742, it is preferable to use a material capable of removing oxygen from a part of the semiconductor layer 742 and creating an oxygen vacancy in at least the portion of electrodes 744a and 744b that is in contact with the semiconductor layer 742. The oxygen vacancy in the semiconductor layer 742 increases in carrier concentration, and the region becomes n-type, and the n-type region (n +This becomes a layer. Therefore, this region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, examples of materials that can remove oxygen from the semiconductor layer 742 and create an oxygen vacancy include tungsten and titanium.

[0295] By forming source and drain regions in the semiconductor layer 742, the contact resistance between electrodes 744a and 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as field-effect mobility and threshold voltage, can be improved.

[0296] When a semiconductor such as silicon is used for the semiconductor layer 742, it is preferable to provide layers that function as n-type or p-type semiconductors between the semiconductor layer 742 and electrode 744a, and between the semiconductor layer 742 and electrode 744b. The layers that function as n-type or p-type semiconductors can function as the source region or drain region of the transistor.

[0297] The insulating layer 729 is preferably formed using a material that has the function of preventing or reducing the diffusion of impurities from the outside to the transistor. The insulating layer 729 may be omitted if necessary.

[0298] The transistor 811 shown in Figure 22(A2) differs from transistor 810 in that it has an electrode 723 on the insulating layer 729 that can function as a back gate electrode. The electrode 723 can be formed using the same material and method as electrode 746.

[0299] Generally, the back gate electrode is formed from a conductive layer and is positioned so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same way as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or it may be the ground potential (GND potential) or any other potential. Furthermore, by changing the potential of the back gate electrode independently of the gate electrode, the threshold voltage of the transistor can be changed.

[0300] Both electrodes 746 and 723 can function as gate electrodes. Therefore, insulating layers 726, 728, and 729 can each function as gate insulating layers. Electrode 723 may be placed between insulating layer 728 and insulating layer 729.

[0301] Furthermore, when one of the electrodes, 746 or 723, is referred to as the "gate electrode," the other is referred to as the "back gate electrode." For example, in transistor 811, when electrode 723 is referred to as the "gate electrode," electrode 746 is referred to as the "back gate electrode." Also, when electrode 723 is used as the "gate electrode," transistor 811 can be considered a type of top-gate transistor. In addition, one of the electrodes, 746 or 723, may be referred to as the "first gate electrode," and the other as the "second gate electrode."

[0302] By providing electrodes 746 and 723 on either side of the semiconductor layer 742, and further by setting electrodes 746 and 723 to the same potential, the region in the semiconductor layer 742 where carriers flow becomes larger in the film thickness direction, thus increasing the amount of carrier movement. As a result, the on-current of transistor 811 increases, and the field-effect mobility also increases.

[0303] Therefore, transistor 811 is a transistor that has a large on-current relative to its occupied area. In other words, the occupied area of ​​transistor 811 can be reduced relative to the required on-current. According to one aspect of the present invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one aspect of the present invention, a semiconductor device with a high degree of integration can be realized.

[0304] Furthermore, since the gate electrode and back gate electrode are formed from conductive layers, they have the function of preventing electric fields generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly an electric field shielding function against static electricity). The electric field shielding function can be enhanced by making the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

[0305] Furthermore, by forming the back gate electrode with a light-shielding conductive film, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, photodegradation of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as a shift in the transistor's threshold voltage can be prevented.

[0306] According to one aspect of the present invention, a highly reliable transistor can be realized. Furthermore, a highly reliable semiconductor device can be realized.

[0307] Figure 22(B1) is a cross-sectional view in the channel length direction of a channel-protected transistor 820 with a different configuration from Figure 22(A1). Transistor 820 has a structure almost identical to transistor 810, except that the insulating layer 741 covers the edge of the semiconductor layer 742. In addition, the semiconductor layer 742 and electrode 744a are electrically connected at an opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. Furthermore, the semiconductor layer 742 and electrode 744b are electrically connected at another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. The region of the insulating layer 741 that overlaps with the channel formation region can function as a channel protection layer.

[0308] The transistor 821 shown in Figure 22(B2) differs from the transistor 820 in that it has an electrode 723 on the insulating layer 729 that can function as a back gate electrode.

[0309] By providing the insulating layer 741, exposure of the semiconductor layer 742 that occurs during the formation of electrodes 744a and 744b can be prevented. Therefore, thinning of the semiconductor layer 742 during the formation of electrodes 744a and 744b can be prevented.

[0310] Furthermore, in transistors 820 and 821, the distance between electrode 744a and electrode 746, and the distance between electrode 744b and electrode 746 are longer than in transistors 810 and 811. Therefore, the parasitic capacitance between electrode 744a and electrode 746 can be reduced. Also, the parasitic capacitance between electrode 744b and electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0311] Figure 22(C1) is a cross-sectional view in the channel length direction of a channel-etched transistor 825, which is a type of bottom-gate transistor. Transistor 825 forms electrodes 744a and 744b without using an insulating layer 741. Therefore, a portion of the semiconductor layer 742 that is exposed during the formation of electrodes 744a and 744b may be etched. On the other hand, because an insulating layer 741 is not provided, the productivity of the transistor can be increased.

[0312] The transistor 826 shown in Figure 22(C2) differs from transistor 825 in that it has an electrode 723 on the insulating layer 729 that can function as a back gate electrode.

[0313] Figures 23(A1) through (C2) show cross-sectional views of transistors 810, 811, 820, 821, 825, and 826 in the channel width direction, respectively.

[0314] In the structures shown in Figures 23(B2) and (C2), the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode are the same. Furthermore, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0315] The length of the gate electrode and back gate electrode in the channel width direction is longer than the length of the semiconductor layer 742 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is covered by the gate electrode or back gate electrode with insulating layers 726, 741, 728, and 729 in between.

[0316] This configuration allows the semiconductor layer 742 included in the transistor to be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0317] A transistor device structure in which the semiconductor layer 742, in which the channel-forming region is formed, is electrically surrounded by the electric fields of the gate electrode and back gate electrode, such as in transistor 821 or transistor 826, can be called a Surrounded Channel (S-channel) structure.

[0318] By adopting an S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 742 by one or both of the gate electrode and / or back gate electrode, thereby improving the transistor's current-driving capability and enabling high on-current characteristics. Furthermore, the ability to increase the on-current allows for miniaturization of the transistor. Additionally, the S-channel structure can increase the mechanical strength of the transistor.

[0319] [Top-gate transistor] The transistor 842 illustrated in Figure 24(A1) is a top-gate type transistor. Electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at openings formed in the insulating layers 728 and 729.

[0320] Furthermore, by removing a portion of the insulating layer 726 that does not overlap with the electrode 746, and using the electrode 746 and the remaining insulating layer 726 as a mask to introduce the impurity 755 into the semiconductor layer 742, an impurity region can be formed in the semiconductor layer 742 in a self-aligned manner. The transistor 842 has a region where the insulating layer 726 extends beyond the edge of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 where the impurity 755 is introduced via the insulating layer 726 is smaller than that in the region where the impurity 755 is introduced without going through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the semiconductor layer 742 in the region that does not overlap with the electrode 746.

[0321] The transistor 843 shown in Figure 24(A2) differs from the transistor 842 in that it has an electrode 723. The transistor 843 has an electrode 723 formed on the substrate 771. The electrode 723 has a region that overlaps with the semiconductor layer 742 via an insulating layer 772. The electrode 723 can function as a back gate electrode.

[0322] Alternatively, as shown in Figure 24(B1) for transistor 844 and Figure 24(B2) for transistor 845, the insulating layer 726 in the region that does not overlap with the electrode 746 may be completely removed. Alternatively, as shown in Figure 24(C1) for transistor 846 and Figure 24(C2) for transistor 847, the insulating layer 726 may be left in place.

[0323] In transistors 842 to 847, impurity regions can be formed in the semiconductor layer 742 in a self-aligned manner by introducing impurities 755 into the semiconductor layer 742 using electrodes 746 as a mask after forming electrodes 746. According to one aspect of the present invention, transistors with good electrical characteristics can be realized. Furthermore, according to one aspect of the present invention, semiconductor devices with a high degree of integration can be realized.

[0324] Figures 25(A1) to (C2) show cross-sectional views of transistors 842, 843, 844, 845, 846, and 847 in the channel width direction, respectively.

[0325] Transistors 843, 845, and 847 each have the S-channel structure described earlier. However, the system is not limited to this, and transistors 843, 845, and 847 do not necessarily have to have an S-channel structure.

[0326] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0327] (Embodiment 4) Electronic devices that can use a display device according to one aspect of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game consoles including portable ones, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio systems, digital audio players, etc.), photocopiers, facsimile machines, printers, printer-multifunction devices, automated teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in Figure 26.

[0328] Figure 26(A) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom lever 968, a lens 969, etc. By using a display device according to one embodiment of the present invention in the display unit 965, various images can be displayed.

[0329] Figure 26(B) shows a digital signage system having a large display unit 922. For example, it can be mounted on the side of a column 921. By using a display device according to one embodiment of the present invention in the display unit 922, a display with high display quality can be achieved.

[0330] Figure 26(C) shows a mobile phone, which includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone is equipped with a touch sensor on the display unit 952. All operations, such as making a phone call or entering text, can be performed by touching the display unit 952 with a finger or stylus. Furthermore, the housing 951 and the display unit 952 are flexible and can be bent as shown in the figure. By using a display device according to one embodiment of the present invention on the display unit 952, various images can be displayed.

[0331] Figure 26(D) shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information can be input and output using the touch panel function of the display unit 912. By using a display device according to one embodiment of the present invention in the display unit 912, various images can be displayed.

[0332] Figure 26(E) shows a television, which includes a housing 971, a display unit 973, operation keys 974, a speaker 975, a communication connection terminal 976, an optical sensor 977, etc. The display unit 973 is equipped with a touch sensor, allowing for input operations. By using a display device according to one embodiment of the present invention in the display unit 973, various images can be displayed.

[0333] Figure 26(F) shows an information processing terminal, which includes a housing 901, a display unit 902, a display unit 903, a sensor 904, etc. The display units 902 and 903 consist of a single display panel and are flexible. The housing 901 is also flexible and can be folded as shown in the figure, or it can be used in a flat shape like a tablet terminal. The sensor 904 can sense the shape of the housing 901, and for example, when the housing is bent, it can switch the display of the display units 902 and 903. By using a display device according to one aspect of the present invention in the display units 902 and 903, various images can be displayed.

[0334] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0335] 10: Pixel, 11: Pixel, 12: Pixel, 13: Pixel, 14: Pixel, 15: Pixel, 17: Pixel block, 18: Pixel block, 19: Pixel array, 20: Shift register, 21: Buffer circuit, 22: Shift register, 23: Buffer circuit, 24: Sensor, 25: Circuit, 31: Low driver, 32: Column driver, 33: Circuit, 34: Selection circuit, 101: Transistor, 102: Transistor, 103: Transistor, 104: Capacitive element, 105: Capacitive element, 106: Transistor, 107: Transistor, 110: Circuit block, 111: Transistor 112: Transistor, 113: Capacitive element, 114: EL element, 115: Transistor, 116: Capacitive element, 117: Liquid crystal element, 118: Transistor, 119: Transistor, 120: Circuit, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 215: Display unit, 221a: Scan line drive circuit, 231a: Signal line drive circuit, 232a: Signal line drive circuit, 241a: Common line drive circuit, 72 3: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Display unit, 903: Display unit, 90 4: Sensor, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Pillar, 922: Display unit, 951: Housing, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display unit, 966: Operation key, 967: Speaker, 968: Zoom lever, 969: Lens, 971: Housing, 973: Display unit, 974: Operation key, 975: Speaker, 976: Communication connection terminal, 977: Optical sensor, 4001: Circuit board,4005: Sealing material, 4006: Substrate, 4008: Liquid crystal layer, 4010: Transistor, 4011: Transistor, 4013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FPC, 4019: Anisotropic conductive layer, 4020: Capacitive element, 4021: Electrode, 4022: Transistor, 4023: Transistor, 4030: Electrode layer, 4031: Electrode layer, 4032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4042: Integrated circuit, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light-shielding layer, 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate, 4272b: FPC, 4273b: IC, 4510: partition, 4511: light-emitting layer, 4513: light-emitting element, 4514: filler,

Claims

[Claim 1] a plurality of capacitor elements, a plurality of transistors, and a display element; the plurality of capacitance elements are connected in series via wiring, one of the transistors is electrically connected to an electrode at one end of the plurality of capacitance elements connected in series; one of the transistors is electrically connected to the other end electrode of the plurality of capacitance elements connected in series; the display element is electrically connected to the other end electrode of the plurality of capacitance elements connected in series; The display device has one of the transistors electrically connected to the wiring.

Images