Transmission / Reception System and Transmission / Reception Method

Abstract

To secure an excellent communication quality in a data transmission using an LDPC code.SOLUTION: An LDPC coding is performed on the basis of a check matrix where a code length N is 17280 bits and a coding rate r is a 14 / 16 LDPC code. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table, and the check matrix initial value table is a table representing a position of one element of the information matrix for every 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using an LDPC code.SELECTED DRAWING: Figure 21

Description

Technical Field

[0001] The present technology relates to a transmission and reception system and a transmission and reception method, and particularly relates to a transmission and reception system and a transmission and reception method that can ensure good communication quality, for example, in data transmission using an LDPC code.

Background Art

[0002] The LDPC (Low Density Parity Check) code has high error correction ability and has been widely adopted in recent years in transmission systems such as DVB (Digital Video Broadcasting)-S.2, DVB-T.2, DVB-C.2 in Europe, etc., and ATSC (Advanced Television Systems Committee) 3.0 in the United States, etc. (see, for example, Non-Patent Document 1).

[0003] Recent research has shown that, similar to turbo codes, as the code length of the LDPC code is increased, performance approaching the Shannon limit can be obtained. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, it has good block error probability characteristics as a feature, and furthermore, it can be cited as an advantage that the so-called error floor phenomenon observed in the decoding characteristics of turbo codes and the like hardly occurs.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In data transmission using LDPC codes, for example, an LDPC code is used as a symbol of orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbol is mapped to a signal point of the orthogonal modulation and transmitted.

[0006] Data transmission using LDPC codes as described above is spreading worldwide, and it is required to ensure good communication (transmission) quality.

[0007] This technology has been made in view of such a situation, and in data transmission using LDPC codes, it enables good communication quality to be ensured.

Means for Solving the Problem

[0008] The first transmission device / transmission method of this technology includes an encoding unit / step that performs LDPC encoding based on a check matrix of an LDPC code with a code length N of 17,280 bits and a coding rate r of 13 / 16. The LDPC code includes information bits and parity bits. The check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits. The information matrix part is represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of the 1 elements of the information matrix part every 360 columns, 225 274 898 916 1020 1055 1075 1179 1185 1343 1376 1569 1828 1972 2852 2957 3183 548 602 628 928 1077 1474 1557 1598 1935 1981 2110 2472 2543 2594 2721 2884 2981 59 69 518 900 1158 1325 1367 1480 1744 2069 2119 2406 2757 2883 2914 2966 3232 1330 1369 1712 2133 2206 2487 2596 2606 2612 2666 2726 2733 2754 2811 2948 3030 391 542 689 748 810 1716 1927 2006 2296 2340 2357 2514 2797 2887 2896 3226 256 410 799 1126 1377 1409 1518 1619 1829 2037 2303 2324 2472 2475 2874 2992 862 1522 1905 809 842 945 561 1001 2857 2132 2592 2905 217 401 1894 11 30 1860 210 1188 2418 1372 2273 2455 407 2537 2962 939 2401 2677 2521 3077 3173 1374 2250 2423 23 188 1320 472 714 2144 2727 2755 2887 1814 2824 2852 148 1695 1845 595 1059 2702 1879 2480 2578 17 411 559 146 783 2154 951 1391 1979 1507 1613 3106 642 882 2356 1008 1324 3125 196 1794 2474 1129 1544 2931 765 1681 2591 1550 1936 3048 1596 1607 2794 156 1053 2926 1246 1996 3179 348 752 1943 is the transmission device / transmission method.

[0009] In the first transmission device and transmission method of the present technology, the code length N is 17,280 bits, and LDPC coding is performed based on the check matrix of the LDPC code with a coding rate r of 13 / 16. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, the information matrix part is represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of the 1 elements of the information matrix part every 360 columns, 225 274 898 916 1020 1055 1075 1179 1185 1343 1376 1569 1828 1972 2852 2957 3183 548 602 628 928 1077 1474 1557 1598 1935 1981 2110 2472 2543 2594 2721 2884 2981 59 69 518 900 1158 1325 1367 1480 1744 2069 2119 2406 2757 2883 2914 2966 3232 1330 1369 1712 2133 2206 2487 2596 2606 2612 2666 2726 2733 2754 2811 2948 3030 391 542 689 748 810 1716 1927 2006 2296 2340 2357 2514 2797 2887 2896 3226 256 410 799 1126 1377 1409 1518 1619 1829 2037 2303 2324 2472 2475 2874 2992 862 1522 1905 809 842 945 561 1001 2857 2132 2592 2905 217 401 1894 11 30 1860 210 1188 2418 1372 2273 2455 407 2537 2962 939 2401 2677 2521 3077 3173 1374 2250 2423 23 188 1320 472 714 2144 2727 2755 2887 1814 2824 2852 148 1695 1845 595 1059 2702 1879 2480 2578 17 411 559 146 783 2154 951 1391 1979 1507 1613 3106 642 882 2356 1008 1324 3125 196 1794 2474 1129 1544 2931 765 1681 2591 1550 1936 3048 1596 1607 2794 156 1053 2926 1246 1996 3179 348 752 1943 It has become.

[0010] The first receiving apparatus / receiving method of the present technology includes an encoding step of performing LDPC encoding based on a check matrix of an LDPC code with a code length N of 17,280 bits and a coding rate r of 13 / 16. The LDPC code includes information bits and parity bits. The check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits. The information matrix part is represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of the 1 elements of the information matrix part every 360 columns. 225 274 898 916 1020 1055 1075 1179 1185 1343 1376 1569 1828 1972 2852 2957 3183 548 602 628 928 1077 1474 1557 1598 1935 1981 2110 2472 2543 2594 2721 2884 2981 59 69 518 900 1158 1325 1367 1480 1744 2069 2119 2406 2757 2883 2914 2966 3232 1330 1369 1712 2133 2206 2487 2596 2606 2612 2666 2726 2733 2754 2811 2948 3030 391 542 689 748 810 1716 1927 2006 2296 2340 2357 2514 2797 2887 2896 3226 256 410 799 1126 1377 1409 1518 1619 1829 2037 2303 2324 2472 2475 2874 2992 862 1522 1905 809 842 945 561 1001 2857 2132 2592 2905 217 401 1894 11 30 1860 210 1188 2418 1372 2273 2455 407 2537 2962 939 2401 2677 2521 3077 3173 1374 2250 2423 23 188 1320 472 714 2144 2727 2755 2887 1814 2824 2852 148 1695 1845 595 1059 2702 1879 2480 2578 17 411 559 146 783 2154 951 1391 1979 1507 1613 3106 642 882 2356 1008 1324 3125 196 1794 2474 1129 1544 2931 765 1681 2591 1550 1936 3048 1596 1607 2794 156 1053 2926 1246 1996 3179 348 752 1943 A receiving apparatus / method comprising a decoding unit / step for decoding the LDPC code obtained from data transmitted by a transmission method.

[0011] In the first receiving apparatus and receiving method of the present technology, the LDPC code obtained from data transmitted by the first transmission method is decoded.

[0012] The second transmission device / transmission method of the present technology includes an encoding unit / step that performs LDPC encoding based on a check matrix of an LDPC code with a code length N of 17,280 bits and a coding rate r of 14 / 16. The LDPC code includes information bits and parity bits. The check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits. The information matrix part is represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of the 1 elements of the information matrix part every 360 columns. 337 376 447 504 551 864 872 975 1136 1225 1254 1271 1429 1478 1870 2122 58 121 163 365 515 534 855 889 1083 1122 1190 1448 1476 1635 1691 1954 247 342 395 454 479 665 674 1033 1041 1198 1300 1484 1680 1941 2096 2121 80 487 500 513 661 970 1038 1095 1109 1133 1416 1545 1696 1992 2051 2089 32 101 205 413 568 712 714 944 1329 1669 1703 1826 1904 1908 2014 2097 142 201 491 838 860 954 960 965 997 1027 1225 1488 1502 1521 1737 1804 453 1184 1542 10 781 1709 497 903 1546 1080 1640 1861 1198 1616 1817 771 978 2089 369 1079 1348 980 1788 1987 1495 1900 2015 27 540 1070 200 1771 1962 863 988 1329 674 1321 2152 807 1458 1727 844 867 1628 227 546 1027 408 926 1413 361 982 2087 1247 1288 1392 1051 1070 1281 325 452 467 1116 1672 1833 21 236 1267 504 856 2123 398 775 1912 1056 1529 1701 143 930 1186 553 1029 1040 303 653 1308 877 992 1174 1083 1134 1355 298 404 709 970 1272 1799 296 1017 1873 105 780 1418 682 1247 1867 is a transmission device / transmission method.

[0013] In the second transmission device and transmission method of the present technology, the code length N is 17,280 bits, and LDPC coding is performed based on the check matrix of the LDPC code with a coding rate r of 14 / 16. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, the information matrix part is represented by a check matrix initial value table, and the check matrix initial value table is a table representing the positions of the 1 elements of the information matrix part every 360 columns, 337 376 447 504 551 864 872 975 1136 1225 1254 1271 1429 1478 1870 2122 58 121 163 365 515 534 855 889 1083 1122 1190 1448 1476 1635 1691 1954 247 342 395 454 479 665 674 1033 1041 1198 1300 1484 1680 1941 2096 2121 80 487 500 513 661 970 1038 1095 1109 1133 1416 1545 1696 1992 2051 2089 32 101 205 413 568 712 714 944 1329 1669 1703 1826 1904 1908 2014 2097 142 201 491 838 860 954 960 965 997 1027 1225 1488 1502 1521 1737 1804 453 1184 1542 10 781 1709 497 903 1546 1080 1640 1861 1198 1616 1817 771 978 2089 369 1079 1348 980 1788 1987 1495 1900 2015 27 540 1070 200 1771 1962 863 988 1329 674 1321 2152 807 1458 1727 844 867 1628 227 546 1027 408 926 1413 361 982 2087 1247 1288 1392 1051 1070 1281 325 452 467 1116 1672 1833 21 236 1267 504 856 2123 398 775 1912 1056 1529 1701 143 930 1186 553 1029 1040 303 653 1308 877 992 1174 1083 1134 1355 298 404 709 970 1272 1799 296 1017 1873 105 780 1418 682 1247 1867 It is as follows.

[0014] The second receiving device / receiving method of the present technology includes an encoding step of performing LDPC encoding based on a check matrix of an LDPC code with a code length N of 17,280 bits and a coding rate r of 14 / 16. The LDPC code includes information bits and parity bits. The check matrix includes an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits. The information matrix part is represented by a check matrix initial value table, and the check matrix initial value table is a table that represents the positions of the 1 elements of the information matrix part every 360 columns, 337 376 447 504 551 864 872 975 1136 1225 1254 1271 1429 1478 1870 2122 58 121 163 365 515 534 855 889 1083 1122 1190 1448 1476 1635 1691 1954 247 342 395 454 479 665 674 1033 1041 1198 1300 1484 1680 1941 2096 2121 80 487 500 513 661 970 1038 1095 1109 1133 1416 1545 1696 1992 2051 2089 32 101 205 413 568 712 714 944 1329 1669 1703 1826 1904 1908 2014 2097 142 201 491 838 860 954 960 965 997 1027 1225 1488 1502 1521 1737 1804 453 1184 1542 10 781 1709 497 903 1546 1080 1640 1861 1198 1616 1817 771 978 2089 369 1079 1348 980 1788 1987 1495 1900 2015 27 540 1070 200 1771 1962 863 988 1329 674 1321 2152 807 1458 1727 844 867 1628 227 546 1027 408 926 1413 361 982 2087 1247 1288 1392 1051 1070 1281 325 452 467 1116 1672 1833 21 236 1267 504 856 2123 398 775 1912 1056 1529 1701 143 930 1186 553 1029 1040 303 653 1308 877 992 1174 1083 1134 1355 298 404 709 970 1272 1799 296 1017 1873 105 780 1418 682 1247 1867 A receiving apparatus / method comprising a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method described above.

[0015] In the second receiving apparatus and receiving method of the present technology, the LDPC code obtained from data transmitted by the second transmission method is decoded.

[0016] Note that the transmission apparatus and the receiving apparatus may be independent apparatuses or internal blocks constituting one apparatus.

Advantages of the Invention

[0017] According to the present technology, in data transmission using an LDPC code, good communication quality can be ensured.

[0018] Note that the effects described here are not necessarily limited, and any of the effects described in the present disclosure may be applicable.

Brief Description of the Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present technology will be described. Prior to that, the LDPC code will be described.

[0021] <LDPC code>

[0022] Note that the LDPC code is a linear code and does not necessarily have to be binary, but here it will be described as being binary.

[0023] The LDPC code is characterized in that the parity check matrix defining the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of "1"s in the elements of the matrix is very small (a matrix in which most elements are 0).

[0024] FIG. 1 is a diagram showing an example of the parity check matrix H of the LDPC code.

[0025] In the parity check matrix H of FIG. 1, the weight of each column (column weight) (the number of "1"s) (weight) is "3", and the weight of each row (row weight) is "6".

[0026] In encoding by an LDPC code (LDPC encoding), for example, a generator matrix G is generated based on a check matrix H, and an LDPC code (codeword) is generated by multiplying the generator matrix G by binary information bits.

[0027] Specifically, an encoding device that performs LDPC encoding first calculates a generator matrix G for which the equation GH T = 0 holds, between the transposed matrix H T of the check matrix H. Here, when the generator matrix G is a K×N matrix, the encoding device multiplies a bit sequence (vector u) of information bits consisting of K bits by the generator matrix G to generate a codeword c (= uG) consisting of N bits. The codeword (LDPC code) generated by this encoding device is received on the receiving side via a predetermined communication channel.

[0028] Decoding of an LDPC code is an algorithm proposed by Gallager called probabilistic decoding, and can be performed by a message-passing algorithm based on belief propagation on a so-called Tanner graph composed of variable nodes (also called message nodes) and check nodes. Hereinafter, variable nodes and check nodes will be simply referred to as nodes as appropriate.

[0029] FIG. 2 is a flowchart showing the procedure for decoding an LDPC code.

[0030] Note that hereinafter, as appropriate, a real value (received LLR) obtained by expressing the "0-likeness" of the value of the i-th code bit of an LDPC code (one codeword) received on the receiving side in terms of a log likelihood ratio will be referred to as a received value u 0i as well. Also, a message output from a check node will be denoted as u j , and a message output from a variable node will be denoted as v i .

[0031] First, in the decoding of the LDPC code, as shown in FIG. 2, in step S11, the LDPC code is received, and a message (check node message) u j is initialized to "0", and a variable k that takes an integer as a counter for the iterative process is initialized to "0", and the process proceeds to step S12. In step S12, based on the received value u 0i obtained by receiving the LDPC code, a message (variable node message) v i is obtained by performing the operation (variable node operation) shown in Equation (1), and further, based on this message v i a message u j is obtained by performing the operation (check node operation) shown in Equation (2).

[0032]

Equation

[0033]

Equation

[0034] Here, d v and d c in Equation (1) and Equation (2) are respectively arbitrarily selectable parameters indicating the number of "1"s in the vertical direction (column) and the horizontal direction (row) of the check matrix H. For example, in the case of an LDPC code ((3,6) LDPC code) for a check matrix H with a column weight of 3 and a row weight of 6 as shown in FIG. 1, d v = 3, d c = 6.

[0035] Note that in the variable node operation of Equation (1) and the check node operation of (2), respectively, since the message input from the branch (edge) (the line connecting the variable node and the check node) where the message is to be output is not the target of the operation, the range of the operation is from 1 to d v-1 or 1 to d c -1. Also, the check node operation of Equation (2) is actually a 2-input v 1 , v 2 for the function R(v 1 , v 2 ) defined by the output of 1 is performed by creating a table in advance and using it continuously (recursively) as shown in Equation (4).

[0036]

Number

[0037]

Number

[0038] In step S12, further, the variable k is incremented by only "1" and proceeds to step S13. In step S13, it is determined whether the variable k is greater than a predetermined number of decoding repetitions C. In step S13, if it is determined that the variable k is not greater than C, it returns to step S12, and the following similar processing is repeated.

[0039] Also, in step S13, if it is determined that the variable k is greater than C, it proceeds to step S14, and the message v i as the finally output decoding result is obtained by performing the operation shown in Equation (5) and output, and the decoding process of the LDPC code ends.

[0040]

Number

[0041] Here, the operation of Equation (5) is different from the variable node operation of Equation (1), and is performed using all the messages u j from all the branches connected to the variable node.

[0042] Figure 3 is a diagram showing an example of a check matrix H of a (3,6) LDPC code (code rate 1 / 2, code length 12).

[0043] In the check matrix H of Figure 3, as in Figure 1, the column weight is 3 and the row weight is 6, respectively.

[0044] Figure 4 is a diagram showing the Tanner graph of the check matrix H of Figure 3.

[0045] Here, in Figure 4, the check nodes are represented by plus signs "+", and the variable nodes are represented by equal signs "=". The check nodes and variable nodes correspond to the rows and columns of the check matrix H, respectively. The connections between the check nodes and variable nodes are edges, which correspond to the "1" of the elements of the check matrix.

[0046] That is, when the element in the j-th row and i-th column of the check matrix is 1, in Figure 4, the i-th variable node ("=" node) from the top and the j-th check node ("+" node) from the top are connected by an edge. The edge represents that the code bit corresponding to the variable node has the constraint condition corresponding to the check node.

[0047] In the Sum Product Algorithm, which is a decoding method for LDPC codes, variable node operations and check node operations are repeatedly performed.

[0048] Figure 5 is a diagram showing the variable node operation performed at the variable node.

[0049] At the variable node, the message v i corresponding to the edge to be calculated is obtained by the variable node operation of Equation (1) using the messages u 1 and u 2 from the remaining edges connected to the variable node and the received value u 0i . The messages corresponding to the other edges are obtained in the same way.

[0050] FIG. 6 is a diagram showing a check node operation performed at a check node.

[0051] Here, the check node operation of Expression (2) can be rewritten as Expression (6) using the relationship of the expression a × b = exp{ln(|a|) + ln(|b|)} × sign(a) × sign(b). However, sign(x) is 1 when x ≧ 0 and -1 when x < 0.

[0052]

Equation

[0053] When x ≧ 0, if the function φ(x) is defined by the expression φ(x) = ln(tanh(x / 2)), then the expression φ -1 (x) = 2tanh -1 (e -x ) holds, so Expression (6) can be transformed into Expression (7).

[0054]

Equation

[0055] At the check node, the check node operation of Expression (2) is performed according to Expression (7).

[0056] That is, at the check node, as shown in FIG. 6, the message u j corresponding to the branch to be calculated is obtained by the check node operation of Expression (7) using the messages v 1 , v 2 , v 3 , v 4 , v 5 from the remaining branches connected to the check node. Messages corresponding to other branches are obtained in the same way.

[0057] Note that the function φ(x) of Expression (7) is given by the expression φ(x) = ln((e x+1) / (e x -1)) and can be expressed as φ(x)=φ -1 (x) when x > 0. When implementing the functions φ(x) and φ -1 (x) in hardware, they may be implemented using a LUT (Look Up Table), but both use the same LUT.

[0058] <Configuration Example of Transmission System to which this Technology is Applied>

[0059] FIG. 7 is a diagram showing a configuration example of an embodiment of a transmission system (a system refers to a logically aggregated collection of a plurality of devices, and whether the devices of each configuration are in the same housing is not relevant) to which this technology is applied.

[0060] In FIG. 7, the transmission system is composed of a transmission device 11 and a reception device 12.

[0061] The transmission device 11 performs transmission (broadcast) (transmission) of, for example, a program of television broadcast. That is, the transmission device 11 encodes target data to be transmitted, such as image data and audio data as a program, into an LDPC code, and transmits it via a communication path 13 such as a satellite line, terrestrial wave, or cable (wired line).

[0062] The reception device 12 receives the LDPC code transmitted from the transmission device 11 via the communication path 13, decodes it into target data, and outputs it.

[0063] Here, the LDPC code used in the transmission system of FIG. 7 is known to exhibit extremely high performance in an AWGN (Additive White Gaussian Noise) communication path.

[0064] On the other hand, in communication path 13, burst errors and erasures may occur. For example, particularly when communication path 13 is a terrestrial wave, in an OFDM (Orthogonal Frequency Division Multiplexing) system, in a multipath environment where D / U (Desired to Undesired Ratio) is 0 dB (Undesired = the power of the echo is equal to the power of the Desired = main path), depending on the delay of the echo (a path other than the main path), the power of a specific symbol may become zero (erasure).

[0065] Also, in the case of flutter (a communication path where an echo with a Doppler frequency applied and a delay of 0 is added), when D / U is 0 dB, there may be a case where the power of the entire OFDM symbol at a specific time becomes zero (erasure) due to the Doppler frequency.

[0066] Furthermore, burst errors may occur due to the wiring situation from the receiving unit (not shown), such as an antenna that receives the signal from the transmitting device 11, to the receiving device 12 on the receiving device 12 side, and the instability of the power supply of the receiving device 12.

[0067] On the other hand, in the decoding of the LDPC code, as shown in FIG. 5, in the columns of the check matrix H, and thus in the variable nodes corresponding to the code bits of the LDPC code, since the variable node operation of equation (1) involving the addition of the received values u 0i ) of the code bits of the LDPC code is performed, if an error occurs in the code bits used for the variable node operation, the accuracy of the required message decreases.

[0068] In the decoding of LDPC codes, at the check nodes, since the check node operations of Equation (7) are performed using the messages obtained from the variable nodes connected to the check node, when the number of check nodes where a plurality of connected variable nodes (the code bits of the LDPC code corresponding thereto) simultaneously have errors (including erasures) increases, the decoding performance deteriorates.

[0069] That is, for example, when two or more of the variable nodes connected to a check node simultaneously become erased, the check node returns messages with equal probabilities of 0 and 1 to all the variable nodes. In this case, the check nodes that return messages with equal probabilities do not contribute to one decoding process (one set of variable node operations and check node operations). As a result, a larger number of repetitions of the decoding process are required, the decoding performance deteriorates, and furthermore, the power consumption of the receiving device 12 that decodes the LDPC code increases.

[0070] Therefore, in the transmission system of FIG. 7, it is possible to improve the resistance to burst errors and erasures while maintaining the performance in an AWGN communication channel (AWGN channel).

[0071] <Configuration Example of Transmission Device 11>

[0072] FIG. 8 is a block diagram showing a configuration example of the transmission device 11 of FIG. 7.

[0073] In the transmission device 11, one or more input streams as target data are supplied to a mode adaptation / multiplexer 111.

[0074] The mode adaptation / multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112.

[0075] The padding unit 112 performs necessary zero-padding (insertion of Null) on the data from the mode adaptation / multiplexer 111, and supplies the resulting data to the BB Scrambler 113.

[0076] The BB Scrambler 113 performs BB Scrambling on the data from the padding unit 112, and supplies the resulting data to the BCH encoder 114.

[0077] The BCH encoder 114 BCH-encodes the data from the BB Scrambler 113, and supplies the resulting data to the LDPC encoder 115 as LDPC target data to be LDPC-encoded.

[0078] The LDPC encoder 115 (encoding unit) performs LDPC encoding on the LDPC target data from the BCH encoder 114 according to, for example, a check matrix in which the parity matrix corresponding to the parity bits of the LDPC code has a dual diagonal structure, and outputs an LDPC code with the LDPC target data as information bits.

[0079] That is, the LDPC encoder 115 performs LDPC encoding to encode the LDPC target data into an LDPC code defined by a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, ATSC 3.0 (corresponding to the check matrix) or other LDPC codes, and outputs the resulting LDPC code.

[0080] Here, the LDPC codes defined in the DVB-S.2 and ATSC3.0 standards are IRA (Irregular Repeat Accumulate) codes, and the parity matrix (part or all) in the check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. Also, for IRA codes, see, for example, "Irregular Repeat-Accumulate Codes," H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000.

[0081] The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116.

[0082] The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the bit interleaving to a mapper 117.

[0083] The mapper 117 maps the LDPC code from the bit interleaver 116 to a signal point representing one symbol of quadrature modulation in units of one or more code bits (symbol units) of the LDPC code, and performs quadrature modulation (multi-value modulation).

[0084] That is, the mapper 117 maps the LDPC code from the bit interleaver 116 to a signal point determined by the modulation method for performing quadrature modulation of the LDPC code on a constellation that is the IQ plane defined by the I-axis representing the I component in phase with the carrier and the Q-axis representing the Q component orthogonal to the carrier, and performs quadrature modulation.

[0085] The number of signal points of the constellation used in the modulation method of the quadrature modulation performed by the mapper 117 is 2m When the number is m bits of the LDPC code, the mapper 117 maps the m-bit code bits of the LDPC code as a symbol (one symbol). From the bit interleaver 116, the LDPC code is in symbol units, 2 m is mapped to the signal point representing the symbol among the signal points of the individual signals.

[0086] Here, as the modulation method of the orthogonal modulation performed by the mapper 117, for example, the modulation methods defined in standards such as DVB-S.2 and ATSC 3.0, and other modulation methods, that is, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. are available. In the mapper 117, which modulation method is used for orthogonal modulation is set in advance according to, for example, the operation of the operator of the transmission device 11, etc.

[0087] The data obtained by the processing in the mapper 117 (the mapping result obtained by mapping the symbol to the signal point) is supplied to the Time Interleaver 118.

[0088] The time interleaver 118 performs time interleaving in symbol units (interleaving in the time direction) on the data from the mapper 117, and supplies the resulting data to the SISO / MISO encoder (SISO / MISO (Single Input Single Output / Multiple Input Single Output) encoder) 119.

[0089] The SISO / MISO encoder 119 performs space-time coding on the data from the time interleaver 118 and supplies it to the Frequency Interleaver 120.

[0090] The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on a symbol-by-symbol basis on the data from the SISO / MISO encoder 119 and supplies it to the Frame Builder & Resource Allocation 131.

[0091] On the other hand, control data (signalling) for transmission control such as, for example, BB Signalling (BB Header) is supplied to the BCH encoder 121.

[0092] The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114 and supplies the resulting data to the LDPC encoder 122.

[0093] The LDPC encoder 122 LDPC-encodes the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115 and supplies the resulting LDPC code to the mapper 123.

[0094] The mapper 123, in the same manner as the mapper 117, maps the LDPC code from the LDPC encoder 122 to signal points representing one symbol of quadrature modulation in units of one or more code bits of the LDPC code (symbol units) to perform quadrature modulation, and supplies the resulting data to the frequency interleaver 124.

[0095] The frequency interleaver 124 performs frequency interleaving on a symbol-by-symbol basis on the data from the mapper 123 in the same manner as the frequency interleaver 120 and supplies it to the Frame Builder & Resource Allocation 131.

[0096] The frame builder / resource allocator 131 inserts pilot symbols at the necessary positions of the data (symbols) from the frequency interleaver 120 and 124, and constructs a frame (for example, a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) composed of a predetermined number of symbols from the resulting data (symbols), and supplies it to the OFDM generation unit 132.

[0097] The OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder / resource allocator 131, and transmits it via the communication path 13 (Fig. 7).

[0098] Note that the transmission device 11 can be configured without providing some of the blocks illustrated in Fig. 8, such as the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124.

[0099] <Configuration example of the bit interleaver 116>

[0100] Fig. 9 is a block diagram showing a configuration example of the bit interleaver 116 in Fig. 8.

[0101] The bit interleaver 116 has a function of interleaving data, and is composed of a parity interleaver 23, a group-wise interleaver 24, and a block interleaver 25.

[0102] The parity interleaver 23 performs a parity interleaving that interleaves the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0103] The groupwise interleaver 24 performs groupwise interleaving on the LDPC code from the parity interleaver 23 and supplies the LDPC code after the groupwise interleaving to the block interleaver 25.

[0104] Here, in the groupwise interleaving, the LDPC code for one code is divided into 360-bit units equal to the parallel factor P described later from the beginning, and the 360 bits of one division are interleaved in bit group units by the LDPC code from the parity interleaver 23 as bit groups.

[0105] When performing groupwise interleaving, the error rate can be improved compared to the case where groupwise interleaving is not performed. As a result, good communication quality can be ensured in data transmission.

[0106] The block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the groupwise interleaver 24. For example, the LDPC code for one code is symbolized into m-bit symbols that are the units of mapping and supplied to the mapper 117 (FIG. 8).

[0107] Here, in the block interleaving, for example, columns as storage areas for storing a predetermined number of bits in the column (vertical) direction are arranged in the row (horizontal) direction by a number equal to the number of bits m of the symbol. The LDPC code from the groupwise interleaver 24 is written in the column direction and read in the row direction, so that the LDPC code is symbolized into m-bit symbols.

[0108] <Check Matrix of LDPC Code>

[0109] FIG. 10 is a diagram showing an example of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8.

[0110] The check matrix H has an LDGM (Low-Density Generation Matrix) structure, and for the code bits of the LDPC code, the information matrix H corresponding to the information bits A and the parity matrix H corresponding to the parity bits T are such that the equation H = [H A | H T (with the elements of the information matrix H A as the left-side elements and the elements of the parity matrix H T as the right-side elements) can represent the matrix).

[0111] Here, for the LDPC code of one codeword, the number of bits of the information bits and the number of bits of the parity bits among the code bits are respectively referred to as the information length K and the parity length M, and the number of bits of the code bits of one (one codeword) LDPC code is referred to as the code length N (= K + M).

[0112] For an LDPC code with a certain code length N, the information length K and the parity length M are determined by the coding rate. Also, the check matrix H is a matrix with M rows and N columns (an M×N matrix). And the information matrix H A is an M×K matrix, and the parity matrix H T is an M×M matrix.

[0113] FIG. 11 is a diagram showing an example of the parity matrix H of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8 T .

[0114] As the parity matrix H of the check matrix H used for LDPC encoding in the LDPC encoder 115 T , for example, a parity matrix H similar to the check matrix H of the LDPC code defined in standards such as DVB-T.2 can be adopted T .

[0115] The parity matrix H of the check matrix H of the LDPC code defined in standards such as DVB-T.2 TAs shown in Fig. 11, the elements of 1 form a staircase-structured matrix (lower bidiagonal matrix) where the elements are arranged in a staircase-like manner. The parity matrix H T has a row weight of 1 for the first row and 2 for all the remaining rows. Also, the column weight is 1 for the last column and 2 for all the remaining columns.

[0116] As described above, for the LDPC code with the parity matrix H T having a staircase structure, the inspection matrix H, it can be easily generated using the inspection matrix H.

[0117] That is, if the LDPC code (one codeword) is represented by the row vector c, and the column vector obtained by transposing the row vector is denoted as c T Let the information bit part of the row vector c, which is an LDPC code, be represented by the row vector A, and the parity bit part be represented by the row vector T.

[0118] In this case, the row vector c can be expressed as the equation c = [A|T] (a row vector with the elements of the row vector A on the left side and the elements of the row vector T on the right side) by the row vector A as the information bits and the row vector T as the parity bits.

[0119] The inspection matrix H and the row vector c = [A|T] as the LDPC code must satisfy the equation Hc T = 0. And for the row vector T as the parity bits that constitutes the row vector c = [A|T] satisfying the equation Hc T = 0, when the parity matrix H of the inspection matrix H = [H A |H T has the staircase structure shown in Fig. 11, it can be obtained sequentially (in order) by setting the elements of each row to 0 in order from the element in the first row of the column vector Hc T in the equation Hc T = 0. T That is, starting from the element in the first row of the column vector Hc in the equation Hc = 0, the elements of each row are set to 0 one by one.

[0120] FIG. 12 is a diagram for explaining a check matrix H of an LDPC code defined in a standard such as DVB-T.2.

[0121] Regarding the KX columns from the first column of the check matrix H of the LDPC code defined in a standard such as DVB-T.2, the column weight is X, for the subsequent K3 columns, the column weight is 3, for the subsequent M - 1 columns, the column weight is 2, and for the last column, the column weight is 1, respectively.

[0122] Here, KX + K3 + M - 1 + 1 is equal to the code length N.

[0123] FIG. 13 is a diagram showing the number of columns KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in a standard such as DVB-T.2.

[0124] In a standard such as DVB-T.2, LDPC codes with code lengths N of 64800 bits and 16200 bits are defined.

[0125] For the LDPC code with code length N of 64800 bits, 11 coding rates (nominal rates) of 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10 are defined, and for the LDPC code with code length N of 16200 bits, 10 coding rates of 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 are defined.

[0126] Hereinafter, the code length N of 64800 bits is also referred to as 64k bits, and the code length N of 16200 bits is also referred to as 16k bits.

[0127] Regarding the LDPC code, the error rate tends to be lower for the code bits corresponding to the columns with a larger column weight in the check matrix H.

[0128] In the check matrix H defined in standards such as DVB-T.2 shown in FIGS. 12 and 13, the column weight tends to be larger for the columns on the head side (left side). Therefore, for the LDPC code corresponding to the check matrix H, the leading code bits are more resistant to errors (have higher error tolerance), and the trailing code bits tend to be less resistant to errors.

[0129] <Parity interleaving>

[0130] Referring to FIGS. 14 to 16, the parity interleaving by the parity interleaver 23 in FIG. 9 will be described.

[0131] FIG. 14 is a diagram showing an example of a Tanner graph (a part) of the check matrix of an LDPC code.

[0132] As shown in FIG. 14, when a plurality of variable nodes (corresponding code bits) connected to the check node simultaneously become errors such as erasures, the check node returns messages with equal probabilities of 0 and 1 to all variable nodes connected to the check node. For this reason, when a plurality of variable nodes connected to the same check node simultaneously become erasures or the like, the decoding performance deteriorates.

[0133] By the way, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code, similar to the LDPC code defined in standards such as DVB-T.2, and the parity matrix H of the check matrix H T has a staircase structure as shown in FIG. 11.

[0134] FIG. 15 is a diagram showing an example of the Tanner graph corresponding to the parity matrix H T and the parity matrix H T which has a staircase structure as shown in FIG. 11.

[0135] A in FIG. 15 is the parity matrix H Tshows an example, and B in FIG. 15 shows the Tanner graph corresponding to the parity matrix H of A in FIG. 15 T The Tanner graph corresponding to the parity matrix H is shown in FIG. 15

[0136] The parity matrix H having a staircase structure T In each row, the elements of 1 are adjacent (except for the first row). Therefore, in the Tanner graph of the parity matrix H T In the Tanner graph of the parity matrix H T Two adjacent variable nodes corresponding to two adjacent columns of elements where the value of the parity matrix H is 1 are connected to the same check node

[0137] Therefore, when the parity bits corresponding to the above two adjacent variable nodes are simultaneously in error due to burst errors, erasures, etc., the check nodes connected to the two variable nodes (variable nodes for obtaining messages using parity bits) corresponding to the two parity bits in error return messages with equal probabilities of 0 and 1 to the variable nodes connected to the check nodes, resulting in deterioration of the decoding performance. And when the burst length (the number of bits of parity bits that are continuously in error) becomes large, the number of check nodes that return messages with equal probabilities increases, and the decoding performance further deteriorates

[0138] Therefore, in order to prevent the deterioration of the above-described decoding performance, the parity interleaver 23 (FIG. 9) performs a parity interleaving that interleaves the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits

[0139] FIG. 16 is a diagram showing the parity matrix H of the check matrix H corresponding to the LDPC code after the parity interleaving performed by the parity interleaver 23 of FIG. 9 T is a diagram showing the parity matrix H

[0140] Here, the information matrix H of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 AIt has a cyclic structure, similar to the information matrix of the check matrix H corresponding to the LDPC code defined in standards such as DVB-T.2.

[0141] The cyclic structure means that a certain column is identical to another column that has been cyclically shifted. For example, for every P columns, the positions of 1s in each row of the P columns are at positions that are cyclically shifted in the column direction by a predetermined value such as a value proportional to the value q obtained by dividing the first column of the P columns by the parity length M. Hereinafter, the P columns in the cyclic structure are appropriately referred to as parallel factors.

[0142] As the LDPC codes defined in standards such as DVB-T.2, as described in FIGS. 12 and 13, there are two types of LDPC codes with code lengths N of 64800 bits and 16200 bits. For either of the two types of LDPC codes, the parallel factor P is defined as 360, which is one of the divisors of the parity length M, excluding 1 and M.

[0143] Also, the parity length M is a non-prime value represented by the formula M = q×P = q×360, using different values q depending on the coding rate. Therefore, the value q is also another one of the divisors of the parity length M, excluding 1 and M, similar to the parallel factor P, and is obtained by dividing the parity length M by the parallel factor P (the product of P and q, which are divisors of the parity length M, is the parity length M).

[0144] As described above, for the parity interleaver 23, assuming the information length is K, an integer x satisfying 0 ≤ x < P, and an integer y satisfying 0 ≤ y < q, as a parity interleaving, the (K + qx + y + 1)-th code bit among the code bits of the N-bit LDPC code is interleaved to the position of the (K + Py + x + 1)-th code bit.

[0145] The (K + qx + y + 1)-th parity bit and the (K + Py + x + 1)-th parity bit are both parity bits after the (K + 1)-th bit, and thus, according to the parity interleaving, the positions of the parity bits of the LDPC code are shifted.

[0146] According to such parity interleaving, the variable nodes (corresponding parity bits) connected to the same check node are separated by the parallel factor P, that is, 360 bits here. Therefore, when the burst length is less than 360 bits, it is possible to avoid a situation where multiple variable nodes connected to the same check node simultaneously have errors, and as a result, the tolerance to burst errors can be improved.

[0147] Note that the LDPC code after the parity interleaving that interleaves the (K + qx + y + 1)-th parity bit to the position of the (K + Py + x + 1)-th parity bit matches the LDPC code of the check matrix (hereinafter also referred to as the transformed check matrix) obtained by performing a column replacement that replaces the (K + qx + y + 1)-th column of the original check matrix H with the (K + Py + x + 1)-th column.

[0148] Also, in the parity matrix of the transformed check matrix, as shown in FIG. 16, a pseudo-cyclic structure with P columns (360 columns in FIG. 16) as a unit appears.

[0149] Here, the pseudo-cyclic structure means a structure in which a part, except for a part, has a cyclic structure.

[0150] For the check matrix of the LDPC code defined in standards such as DVB-T.2, the transformed check matrix obtained by performing a column replacement corresponding to the parity interleaving has only one less element of 1 (it becomes an element of 0) in the upper right corner part of 360 rows × 360 columns (the shift matrix described later) of the transformed check matrix, and in this regard, it is not a (complete) cyclic structure but a pseudo-cyclic structure so to speak.

[0151] The conversion check matrix for the LDPC code output by the LDPC encoder 115 has a pseudo-cyclic structure, for example, similar to the conversion check matrix for the LDPC code defined in standards such as DVB-T.2.

[0152] Note that the conversion check matrix in FIG. 16 is a matrix obtained by performing column permutation corresponding to parity interleaving on the original check matrix H, and also performing row permutation (row permutation) so that the conversion check matrix is composed of the configuration matrices described later.

[0153] FIG. 17 is a flowchart for explaining the processing performed by the LDPC encoder 115, bit interleaver 116, and mapper 117 in FIG. 8.

[0154] The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101, encodes the LDPC target data into an LDPC code, supplies the LDPC code to the bit interleaver 116, and the process proceeds to step S102.

[0155] The bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115 in step S102, supplies the symbol obtained by the bit interleaving to the mapper 117, and the process proceeds to step S103.

[0156] That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0157] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 and supplies it to the block interleaver 25.

[0158] Block interleaver 25 performs block interleaving on the LDPC code after groupwise interleaving by groupwise interleaver 24, and supplies the resulting m-bit symbols to mapper 117.

[0159] In step S103, mapper 117 maps the symbols from block interleaver 25 to any one of the two signal points determined by the modulation method of the orthogonal modulation performed by mapper 117, performs orthogonal modulation, and supplies the resulting data to time interleaver 118. m

[0160] As described above, by performing parity interleaving and groupwise interleaving, the error rate when transmitting a plurality of code bits of an LDPC code as one symbol can be improved.

[0161] Here, in FIG. 9, for convenience of explanation, parity interleaver 23 which is a block for performing parity interleaving and groupwise interleaver 24 which is a block for performing groupwise interleaving are configured separately, but parity interleaver 23 and groupwise interleaver 24 can be integrally configured.

[0162] That is, both parity interleaving and groupwise interleaving can be performed by writing and reading code bits to / from memory, and can be represented by a matrix that converts the address for writing code bits (write address) into the address for reading code bits (read address).

[0163] ​Therefore, if a matrix obtained by multiplying a matrix representing a parity interleaving and a matrix representing a group-wise interleaving is obtained, by those matrices, by converting code bits, parity interleaving can be performed, and further, a result of group-wise interleaving the LDPC code after the parity interleaving can be obtained.

[0164] In addition to the parity interleaver 23 and the group-wise interleaver 24, the block interleaver 25 can also be integrally configured.

[0165] That is, the block interleaving performed by the block interleaver 25 can also be represented by a matrix that converts the write address of the memory storing the LDPC code into the read address.

[0166] Therefore, if a matrix obtained by multiplying a matrix representing a parity interleaving, a matrix representing a group-wise interleaving, and a matrix representing a block interleaving is obtained, by those matrices, parity interleaving, group-wise interleaving, and block interleaving can be performed collectively.

[0167] Note that one or both of the parity interleaving and the group-wise interleaving can be not performed.

[0168] <Configuration example of LDPC encoder 115>

[0169] FIG. 18 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG. 8.

[0170] Note that the LDPC encoder 122 of FIG. 8 is also configured in the same manner.

[0171] As described with reference to FIGS. 12 and 13, in standards such as DVB-T.2, LDPC codes with two code lengths N of 64800 bits and 16200 bits are defined.

[0172] For LDPC codes with a code length N of 64,800 bits, 11 coding rates of 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10 are defined. For LDPC codes with a code length N of 16,200 bits, 10 coding rates of 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 are defined (FIGS. 12 and 13).

[0173] The LDPC encoder 115 can perform encoding (error correction encoding) using LDPC codes with such coding rates for code lengths N of 64,800 bits and 16,200 bits, for example, according to a check matrix H prepared for each code length N and each coding rate.

[0174] Also, the LDPC encoder 115 can perform LDPC encoding according to a check matrix H of an LDPC code with a coding rate of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16, or any other arbitrary coding rate r for a code length N of 17,280 bits or any other arbitrary code length N.

[0175] The LDPC encoder 115 is composed of an encoding processing unit 601 and a storage unit 602.

[0176] The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generation unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616. It performs LDPC encoding on the LDPC target data supplied to the LDPC encoder 115 and supplies the resulting LDPC code to a bit interleaver 116 (FIG. 8).

[0177] That is, the coding rate setting unit 611 sets, for example, the code length N and coding rate r of the LDPC code, as well as other specific information for specifying the LDPC code, according to an operator's operation or the like.

[0178] The initial value table reading unit 612 reads out a check matrix initial value table, which will be described later and represents the check matrix of the LDPC code specified by the specific information set by the coding rate setting unit 611, from the storage unit 602.

[0179] The check matrix generation unit 613 generates a check matrix H based on the check matrix initial value table read by the initial value table reading unit 612 and stores it in the storage unit 602. For example, the check matrix generation unit 613 arranges the 1 elements of the information matrix H corresponding to the information length K (= code length N - parity length M) according to the code length N and coding rate r set by the coding rate setting unit 611 at a period of 360 columns (parallel factor P) in the column direction to generate the check matrix H and stores it in the storage unit 602. A The information bit reading unit 614 reads out (extracts) the information bits for the information length K from the LDPC target data supplied to the LDPC encoder 115.

[0180]

[0181] The encoding parity calculation unit 615 reads out the check matrix H generated by the check matrix generation unit 613 from the storage unit 602, and uses the check matrix H to calculate the parity bits for the information bits read by the information bit reading unit 614 based on a predetermined formula, thereby generating a codeword (LDPC code).

[0182] The control unit 616 controls each block constituting the encoding processing unit 601.

[0183] ​The memory unit 602 stores, for example, a plurality of check matrix initial value tables corresponding to a plurality of coding rates and the like shown in FIGS. 12 and 13 for each code length N such as 64,800 bits and 16,200 bits, a check matrix initial value table corresponding to each of coding rates of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 for a code length N of 17,280 bits, and a check matrix initial value table of a check matrix H of an LDPC code with an arbitrary code length N and an arbitrary coding rate r. Further, the memory unit 602 temporarily stores data necessary for the processing of the encoding unit 601.

[0184] FIG. 19 is a flowchart for explaining an example of the processing of the LDPC encoder 115 in FIG. 18.

[0185] In step S201, the coding rate setting unit 611 sets a code length N and a coding rate r for performing LDPC coding, and specific information for specifying other LDPC codes.

[0186] In step S202, the initial value table reading unit 612 reads out a predetermined check matrix initial value table specified by the code length N and the coding rate r, etc. as the specific information set by the coding rate setting unit 611, from the memory unit 602.

[0187] In step S203, the check matrix generation unit 613 obtains (generates) a check matrix H of an LDPC code with the code length N and the coding rate r set by the coding rate setting unit 611, using the check matrix initial value table read out by the initial value table reading unit 612 from the memory unit 602, and supplies it to the memory unit 602 for storage.

[0188] In step S204, the information bit reading unit 614 reads information bits of an information length K (= N × r) corresponding to the code length N and the coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, reads the check matrix H obtained by the check matrix generation unit 613 from the storage unit 602, and supplies it to the coding parity operation unit 615.

[0189] In step S205, the coding parity operation unit 615 sequentially operates the parity bits of the codeword c that satisfies Expression (8) using the information bits from the information bit reading unit 614 and the check matrix H.

[0190] Hc T =0 ···(8)

[0191] In Expression (8), c represents a row vector as a codeword (LDPC code), and c T represents the transpose of the row vector c.

[0192] Here, as described above, when the part of the information bits among the row vectors c as LDPC codes (one codeword) is represented by the row vector A and the part of the parity bits is represented by the row vector T, the row vector c can be represented by the expression c = [A|T] using the row vector A as the information bits and the row vector T as the parity bits.

[0193] The check matrix H and the row vector c = [A|T] as the LDPC code need to satisfy the expression Hc T =0, and the row vector T as the parity bits that constitutes the row vector c = [A|T] that satisfies such an expression Hc T =0, when the parity matrix H A |H T of the check matrix H = [H T has the staircase structure shown in FIG. 11, the column vector Hc in the expression Hc T =0 TIt can be sequentially obtained by setting the elements of each row to 0 in order from the elements of the first row.

[0194] The encoding parity calculation unit 615 obtains a parity bit T for the information bit A from the information bit reading unit 614, and outputs a codeword c = [A|T] represented by the information bit A and the parity bit T as the LDPC encoding result of the information bit A.

[0195] Thereafter, in step S206, the control unit 616 determines whether to end the LDPC encoding. In step S206, if it is determined not to end the LDPC encoding, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and hereinafter, the processes of steps S201 (or step S204) to S206 are repeated.

[0196] Also, in step S206, if it is determined to end the LDPC encoding, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the process.

[0197] For the LDPC encoder 115, a check matrix initial value table (representing a check matrix) of LDPC codes with various code lengths N and coding rates r can be prepared in advance. The LDPC encoder 115 can perform LDPC encoding for LDPC codes with various code lengths N and coding rates r using a check matrix H generated from the prepared check matrix initial value table.

[0198] <Example of the check matrix initial value table>

[0199] The check matrix initial value table is, for example, an information matrix H corresponding to the information length K according to the code length N and coding rate r of the LDPC code (the LDPC code defined by the check matrix H) of the check matrix H. AIt is a table that represents the positions of the 1 elements in (Figure 10) every 360 columns (parallel factor P), and is created in advance for each check matrix H with each code length N and each coding rate r.

[0200] That is, the check matrix initial value table represents, at least, the positions of the 1 elements in the information matrix H A every 360 columns (parallel factor P).

[0201] Also, in the check matrix H, there is a check matrix in which all of the parity matrix H T has a staircase structure, and a check matrix in which a part of the parity matrix H T has a staircase structure and the remaining part is a diagonal matrix (identity matrix).

[0202] Hereinafter, the expression method of the check matrix initial value table representing the check matrix in which a part of the parity matrix H T has a staircase structure and the remaining part is a diagonal matrix is also called the type A method. Also, the expression method of the check matrix initial value table representing the check matrix in which all of the parity matrix H T has a staircase structure is also called the type B method.

[0203] Also, the LDPC code for the check matrix represented by the check matrix initial value table of the type A method is also called the type A code, and the LDPC code for the check matrix represented by the check matrix initial value table of the type B method is also called the type B code.

[0204] The names "type A" and "type B" are names according to the ATSC 3.0 standard. For example, in ATSC 3.0, both type A codes and type B codes are adopted.

[0205] Note that in DVB-T.2, etc., type B codes are adopted.

[0206] Figure 20 is a diagram showing an example of the check matrix initial value table of the type B method.

[0207] That is, FIG. 20 shows an initial value table of a parity-check matrix (representing the parity-check matrix H) of a type B code with a code length N of 16,200 bits and a coding rate r of 1 / 4, which is defined in the DVB-T.2 standard.

[0208] The parity-check matrix generation unit 613 (FIG. 18) obtains the parity-check matrix H as follows using the initial value table of the parity-check matrix for the type B method.

[0209] FIG. 21 is a diagram for explaining a method of obtaining the parity-check matrix H from the initial value table of the parity-check matrix for the type B method.

[0210] That is, FIG. 21 shows an initial value table of a parity-check matrix of a type B code with a code length N of 16,200 bits and a coding rate r of 2 / 3, which is defined in the DVB-T.2 standard.

[0211] The initial value table of the parity-check matrix for the type B method is a table that represents the positions of all the 1 elements of the information matrix H corresponding to the information length K according to the code length N and the coding rate r of the LDPC code. A For each 360 columns (parallel factor P), the row numbers of the 1 elements in the 1 + 360×(i - 1)th column of the parity-check matrix H (with the row number of the first row of the parity-check matrix H being 0) are arranged as many as the column weight of the column having the 1 + 360×(i - 1)th column in the i-th row.

[0212] Here, since the parity matrix H corresponding to the parity length M of the parity-check matrix H for the type B method is determined in a staircase structure as shown in FIG. 15, if the information matrix H corresponding to the information length K can be obtained from the initial value table of the parity-check matrix, the parity-check matrix H can be obtained. T (FIG. 10) A (FIG. 10)

[0213] The number of rows k + 1 of the initial value table of the parity-check matrix for the type B method varies depending on the information length K.

[0214] The relationship of Equation (9) holds between the information length K and the number of rows k + 1 of the initial value table of the parity-check matrix.

[0215] K = (k + 1) × 360 ···(9)

[0216] Here, 360 in Equation (9) is the parallel factor P explained in FIG. 16.

[0217] In the inspection matrix initial value table of FIG. 21, 13 numerical values are arranged from the first row to the third row, and 3 numerical values are arranged from the fourth row to the (k + 1)-th row (the 30th row in FIG. 21).

[0218] Therefore, the column weight of the inspection matrix H obtained from the inspection matrix initial value table of FIG. 21 is 13 from the first column to the column of 1 + 360×(3 - 1) - 1, and 3 from the column of 1 + 360×(3 - 1) to the K-th column.

[0219] The first row of the inspection matrix initial value table of FIG. 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which indicates that in the first column of the inspection matrix H, the elements of the rows with row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are 1 (and the other elements are 0).

[0220] Also, the second row of the inspection matrix initial value table of FIG. 21 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108, which indicates that in the 361(=1 + 360×(2 - 1))-th column of the inspection matrix H, the elements of the rows with row numbers 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108 are 1.

[0221] As described above, the inspection matrix initial value table represents the positions of the 1 elements of the information matrix H A of the inspection matrix H every 360 columns.

[0222] For columns other than the column at position 1 + 360×(i - 1) of the check matrix H, that is, from the column at position 2 + 360×(i - 1) to the column at position 360×i, each column is obtained by cyclically shifting the element 1 in the column at position 1 + 360×(i - 1) determined by the check matrix initial value table downward (downward in the column) according to the parity length M in a periodic manner.

[0223] That is, for example, the column at position 2 + 360×(i - 1) is obtained by cyclically shifting the column at position 1 + 360×(i - 1) downward by M / 360 (= q), and the next column at position 3 + 360×(i - 1) is obtained by cyclically shifting the column at position 1 + 360×(i - 1) downward by 2×M / 360 (= 2×q) (the column at position 2 + 360×(i - 1) cyclically shifted downward by M / 360 (= q)).

[0224] Now, let the value in the j-th column (the j-th column from the left) of the i-th row (the i-th row from the top) of the check matrix initial value table be represented as h i,j and let the row number of the j-th 1 element in the w-th column of the check matrix H be represented as H w-j Then, for the w-th column which is a column other than the column at position 1 + 360×(i - 1) of the check matrix H, the row number H w-j of the 1 element can be obtained by Equation (10).

[0225] H w-j = mod{h i,j + mod((w - 1), P)×q, M) ···(10)

[0226] Here, mod(x, y) means the remainder when x is divided by y.

[0227] Also, P is the parallel factor described above, and in this embodiment, for example, like the standards of DVB - T.2 etc. and ATSC3.0, it is 360. Further, q is the value M / 360 obtained by dividing the parity length M by the parallel factor P (= 360).

[0228] The check matrix generation unit 613 (FIG. 18) identifies the row number of the element of 1 in the 1 + 360×(i - 1)-th column of the check matrix H using the check matrix initial value table.

[0229] Furthermore, the check matrix generation unit 613 (FIG. 18) determines the row number H of the element of 1 in the w-th column, which is a column other than the 1 + 360×(i - 1)-th column of the check matrix H, according to Expression (10), and generates a check matrix H in which the elements of the obtained row numbers are 1. w-j

[0230] FIG. 22 is a diagram showing the structure of the check matrix H of the type A method.

[0231] The check matrix of the type A method is composed of an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

[0232] The A matrix is the upper left matrix of the check matrix H, which is an M1-row K-column matrix represented by a predetermined value M1 and the information length K of the LDPC code = the code length N × the coding rate r.

[0233] The B matrix is a stepped matrix adjacent to the right of the A matrix, which is an M1-row M1-column matrix.

[0234] The C matrix is a matrix adjacent to the bottom of the A matrix and the B matrix, which is an (N - K - M1)-row (K + M1)-column matrix.

[0235] The D matrix is an identity matrix adjacent to the right of the C matrix, which is an (N - K - M1)-row (N - K - M1)-column matrix.

[0236] The Z matrix is a zero matrix (0 matrix) adjacent to the right of the B matrix, which is an M1-row (N - K - M1)-column matrix.

[0237] In the type A method check matrix H composed of the above A matrix to D matrix and Z matrix, a part of the A matrix and the C matrix constitutes the information matrix, and the remaining parts of the B matrix, the C matrix, the D matrix, and the Z matrix constitute the parity matrix.

[0238] ​Note that since the B matrix is a stepped matrix and the D matrix is an identity matrix, the parity matrix of the type A inspection matrix H has a part (the part of the B matrix) with a stepped structure and the remaining part (the part of the D matrix) is a diagonal matrix (identity matrix).

[0239] The A matrix and the C matrix have a cyclic structure for each column of the parallel factor P (for example, 360 columns), similar to the information matrix of the type B inspection matrix H. The type A inspection matrix initial value table represents the positions of the 1 elements of the A matrix and the C matrix every 360 columns.

[0240] Here, as described above, since a part of the A matrix and the C matrix constitutes the information matrix, it can be said that the type A inspection matrix initial value table representing the positions of the 1 elements of the A matrix and the C matrix every 360 columns represents at least the positions of the 1 elements of the information matrix every 360 columns.

[0241] Note that since the type A inspection matrix initial value table represents the positions of the 1 elements of the A matrix and the C matrix every 360 columns, it can also be said that it represents the positions of the 1 elements of a part of the inspection matrix (the remaining part of the C matrix) every 360 columns.

[0242] FIG. 23 is a diagram showing an example of the type A inspection matrix initial value table.

[0243] That is, FIG. 23 shows an example of the inspection matrix initial value table representing the inspection matrix H with a code length N of 35 bits and a coding rate r of 2 / 7.

[0244] The type A inspection matrix initial value table is a table representing the positions of the 1 elements of the A matrix and the C matrix for each parallel factor P. In the i-th row, the row numbers of the 1 elements in the (1 + P×(i - 1))-th column of the inspection matrix H (the row numbers with the row number of the first row of the inspection matrix H being 0) are arranged as many as the column weight of the (1 + P×(i - 1))-th column.

[0245] Here, for simplicity of explanation, assume that the parallel factor P is, for example, 5.

[0246] For the type A check matrix H, there are parameters M1, M2, Q1, and Q2.

[0247] M1 (Fig. 22) is a parameter that determines the size of the B matrix and takes a value that is a multiple of the parallel factor P. By adjusting M1, the performance of the LDPC code changes and is adjusted to a predetermined value when determining the check matrix H. Here, assume that 15, which is 3 times the parallel factor P = 5, is adopted as M1.

[0248] M2 (Fig. 22) takes the value M - M1 obtained by subtracting M1 from the parity length M.

[0249] Here, the information length K is N × r = 35 × 2 / 7 = 10, and the parity length M is N - K = 35 - 10 = 25. Therefore, M2 is M - M1 = 25 - 15 = 10.

[0250] Q1 is obtained according to the formula Q1 = M1 / P and represents the number of cyclic shifts (number of rows) in the A matrix.

[0251] That is, for columns other than the 1 + P×(i - 1) - th column of the A matrix of the type A check matrix H, that is, columns from the 2 + P×(i - 1) - th column to the P×i - th column, each column is arranged by cyclically shifting the 1 element of the 1 + P×(i - 1) - th column determined by the check matrix initial value table downward (downward in the column), and Q1 represents the number of cyclic shifts in the A matrix.

[0252] Q2 is obtained according to the formula Q2 = M2 / P and represents the number of cyclic shifts (number of rows) in the C matrix.

[0253] That is, for columns other than the column at position 1 + P×(i - 1) in the C matrix of the parity-check matrix H of type A, that is, from the column at position 2 + P×(i - 1) to the column at position P×i, each column is obtained by cyclically shifting the 1 element in the column at position 1 + P×(i - 1) determined by the parity-check matrix initial value table downward (in the downward direction of the column) periodically. Q2 represents the number of shifts of this cyclic shift in the C matrix.

[0254] Here, Q1 is M1 / P = 15 / 5 = 3, and Q2 is M2 / P = 10 / 5 = 2.

[0255] In the parity-check matrix initial value table of FIG. 23, three numerical values are arranged in the first and second rows, and one numerical value is arranged from the third row to the fifth row. According to such an arrangement of numerical values, the column weights of the A matrix and the C matrix of the parity-check matrix H obtained from the parity-check matrix initial value table of FIG. 23 are 3 from the column at position 1 = 1 + 5×(1 - 1) to the column at position 10 = 5×2, and 1 from the column at position 11 = 1 + 5×(3 - 1) to the column at position 25 = 5×5.

[0256] That is, the first row of the parity-check matrix initial value table of FIG. 23 is 2, 6, 18, which indicates that in the first column of the parity-check matrix H, the elements in the rows with row numbers 2, 6, and 18 are 1 (and the other elements are 0).

[0257] Here, in the present case, since the A matrix (FIG. 22) is a matrix of 15 rows and 10 columns (M1 rows and K columns), and the C matrix (FIG. 22) is a matrix of 10 rows and 25 columns (N - K - M1 rows and K + M1 columns), the rows with row numbers 0 to 14 of the parity-check matrix H are the rows of the A matrix, and the rows with row numbers 15 to 24 of the parity-check matrix H are the rows of the C matrix.

[0258] Therefore, among the rows with row numbers 2, 6, and 18 (hereinafter referred to as row #2, #6, and #18), row #2 and #6 are the rows of the A matrix, and row #18 is the row of the C matrix.

[0259] The second row of the inspection matrix initial value table in FIG. 23 is 2, 10, 19, which indicates that in the 6th (=1 + 5×(2 - 1)) column of the inspection matrix H, the elements in rows #2, #10, #19 are 1.

[0260] Here, in the 6th (=1 + 5×(2 - 1)) column of the inspection matrix H, among rows #2, #10, #19, rows #2 and #10 are rows of matrix A, and row #19 is a row of matrix C.

[0261] The third row of the inspection matrix initial value table in FIG. 23 is 22, which indicates that in the 11th (=1 + 5×(3 - 1)) column of the inspection matrix H, the element in row #22 is 1.

[0262] Here, in the 11th (=1 + 5×(3 - 1)) column of the inspection matrix H, row #22 is a row of matrix C.

[0263] Similarly, 19 in the fourth row of the inspection matrix initial value table in FIG. 23 indicates that in the 16th (=1 + 5×(4 - 1)) column of the inspection matrix H, the element in row #19 is 1, and 15 in the fifth row of the inspection matrix initial value table in FIG. 23 indicates that in the 21st (=1 + 5×(5 - 1)) column of the inspection matrix H, the element in row #15 is 1.

[0264] As described above, the inspection matrix initial value table represents the positions of the 1 elements of matrices A and C in the inspection matrix H every P = 5 columns in parallel.

[0265] For columns other than the 1 + 5×(i - 1)th column of matrices A and C in the inspection matrix H, that is, columns from the 2 + 5×(i - 1)th column to the 5×i th column, the 1 element in the 1 + 5×(i - 1)th column determined by the inspection matrix initial value table is cyclically shifted downward (in the downward direction of the column) periodically according to parameters Q1 and Q2.

[0266] That is, for example, in the A matrix, the column 2 + 5×(i - 1) is the column 1 + 5×(i - 1) cyclically shifted downward by Q1 (= 3), and the next column 3 + 5×(i - 1) is the column 1 + 5×(i - 1) cyclically shifted downward by 2×Q1 (= 2×3) (the column 2 + 5×(i - 1) cyclically shifted downward by Q1).

[0267] Also, for example, in the C matrix, the column 2 + 5×(i - 1) is the column 1 + 5×(i - 1) cyclically shifted downward by Q2 (= 2), and the next column 3 + 5×(i - 1) is the column 1 + 5×(i - 1) cyclically shifted downward by 2×Q2 (= 2×2) (the column 2 + 5×(i - 1) cyclically shifted downward by Q2).

[0268] FIG. 24 is a diagram showing the A matrix generated from the inspection matrix initial value table of FIG. 23.

[0269] In the A matrix of FIG. 24, according to the first row of the inspection matrix initial value table of FIG. 23, the elements of row #2 and #6 in the column 1 (= 1 + 5×(1 - 1)) are 1.

[0270] And for each column from the column 2 (= 2 + 5×(1 - 1)) to the column 5 (= 5 + 5×(1 - 1)), it is the column immediately preceding cyclically shifted downward by Q1 = 3.

[0271] Furthermore, in the A matrix of FIG. 24, according to the second row of the inspection matrix initial value table of FIG. 23, the elements of row #2 and #10 in the column 6 (= 1 + 5×(2 - 1)) are 1.

[0272] And for each column from the column 7 (= 2 + 5×(2 - 1)) to the column 10 (= 5 + 5×(2 - 1)), it is the column immediately preceding cyclically shifted downward by Q1 = 3.

[0273] FIG. 25 is a diagram showing the parity interleaving of the B matrix.

[0274] The check matrix generation unit 613 (FIG. 18) generates an A matrix using the check matrix initial value table, and arranges a B matrix with a staircase structure to the immediate right of the A matrix. Then, regarding the B matrix as a parity matrix, the check matrix generation unit 613 performs parity interleaving so that the adjacent 1 elements of the B matrix with a staircase structure are separated by a parallel factor P = 5 in the row direction.

[0275] FIG. 25 shows the A matrix and the B matrix after the parity interleaving of the B matrix in FIG. 24.

[0276] FIG. 26 is a diagram showing a C matrix generated from the check matrix initial value table in FIG. 23.

[0277] In the C matrix of FIG. 26, according to the first row of the check matrix initial value table in FIG. 23, the element of row #18 in the 1st (= 1 + 5×(1 - 1)) column of the check matrix H is 1.

[0278] And each column from the 2nd (= 2 + 5×(1 - 1)) column to the 5th (= 5 + 5×(1 - 1)) column of the C matrix is obtained by cyclically shifting the immediately preceding column downward by Q2 = 2.

[0279] Furthermore, in the C matrix of FIG. 26, according to the second row to the fifth row of the check matrix initial value table in FIG. 23, the elements of row #19 in the 6th (= 1 + 5×(2 - 1)) column, row #22 in the 11th (= 1 + 5×(3 - 1)) column, row #19 in the 16th (= 1 + 5×(4 - 1)) column, and row #15 in the 21st (= 1 + 5×(5 - 1)) column of the check matrix H are 1.

[0280] Then, each column from the 7(=2 + 5×(2 - 1))-th column to the 10(=5 + 5×(2 - 1))-th column, each column from the 12(=2 + 5×(3 - 1))-th column to the 15(=5 + 5×(3 - 1))-th column, each column from the 17(=2 + 5×(4 - 1))-th column to the 20(=5 + 5×(4 - 1))-th column, and each column from the 22(=2 + 5×(5 - 1))-th column to the 25(=5 + 5×(5 - 1))-th column is obtained by cyclically shifting the previous column downward by Q2 = 2.

[0281] The check matrix generation unit 613 (FIG. 18) generates a C matrix using the check matrix initial value table, and arranges the C matrix below the A matrix and the B matrix (after parity interleaving).

[0282] Furthermore, the check matrix generation unit 613 arranges a Z matrix to the immediate right of the B matrix, and arranges a D matrix to the immediate right of the C matrix to generate the check matrix H shown in FIG. 26.

[0283] FIG. 27 is a diagram showing the parity interleaving of the D matrix.

[0284] After generating the check matrix H in FIG. 26, the check matrix generation unit 613 regards the D matrix as a parity matrix, and performs (only for the D matrix) parity interleaving so that the elements of 1 in the odd rows and the next even rows of the D matrix of the identity matrix are separated by the parallel factor P = 5 in the row direction.

[0285] FIG. 27 shows the check matrix H after performing the parity interleaving of the D matrix for the check matrix H in FIG. 26.

[0286] The LDPC encoder 115 (the encoding parity operation unit 615 (FIG. 18) thereof) performs LDPC encoding (generation of LDPC codes), for example, using the check matrix H in FIG. 27.

[0287] Here, the LDPC code generated using the check matrix H in FIG. 27 is an LDPC code with parity interleaving. Therefore, for the LDPC code generated using the check matrix H in FIG. 27, there is no need to perform parity interleaving in the parity interleaver 23 (FIG. 9). That is, since the LDPC code generated using the check matrix H after performing parity interleaving on the D matrix is an LDPC code with parity interleaving, for such an LDPC code, the parity interleaving in the parity interleaver 23 is skipped.

[0288] FIG. 28 shows a check matrix H obtained by performing column permutation as parity deinterleaving to restore the parity interleaving on the B matrix, a part of the C matrix (the part of the C matrix arranged below the B matrix), and the D matrix of the check matrix H in FIG. 27.

[0289] In the LDPC encoder 115, LDPC encoding (generation of an LDPC code) can be performed using the check matrix H in FIG. 28.

[0290] When performing LDPC encoding using the check matrix H in FIG. 28, according to the LDPC encoding, an LDPC code without parity interleaving is obtained. Therefore, when performing LDPC encoding using the check matrix H in FIG. 28, parity interleaving is performed in the parity interleaver 23 (FIG. 9).

[0291] FIG. 29 shows a transformed check matrix H obtained by performing row permutation on the check matrix H in FIG. 27.

[0292] As will be described later, the transformed check matrix is a matrix represented by a combination of a P×P identity matrix, a quasi-identity matrix in which one or more of the 1s in the identity matrix become 0, a shift matrix obtained by cyclically shifting the identity matrix or the quasi-identity matrix, a sum matrix that is a sum of two or more of the identity matrix, the quasi-identity matrix, or the shift matrix, and a P×P zero matrix.

[0293] By using the transformation check matrix in the decoding of LDPC codes, in the decoding of LDPC codes, as will be described later, an architecture can be adopted that simultaneously performs P check node operations and variable node operations.

[0294] <New LDPC code>

[0295] In data transmission using LDPC codes, as one method for ensuring good communication quality, there is a method of using an LDPC code with good performance.

[0296] Hereinafter, a new LDPC code with good performance (hereinafter also referred to as the new LDPC code) will be described.

[0297] As the new LDPC code, for example, a type A code or a type B code corresponding to a check matrix H with a cyclic structure can be adopted, where the parallel factor P is 360, similar to DVB-T.2 or ATSC 3.0.

[0298] The LDPC encoder 115 (Figs. 8 and 18) can perform LDPC encoding into an LDPC code using a check matrix initial value table (the obtained check matrix H) of an LDPC code in which the code length N is longer than 64k bits, for example, 69120 bits, and the coding rate r is, for example, any one of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16.

[0299] Also, the LDPC encoder 115 can perform LDPC encoding into a new LDPC code using a check matrix initial value table (a check matrix H obtained therefrom) of a new LDPC code where the code length N is shorter than 64 k bits, for example, 17,280 bits (17 k bits), and the coding rate r is, for example, any one of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16.

[0300] When performing LDPC encoding into a new LDPC code with a code length N of 17,280 bits, a check matrix initial value table of the new LDPC code is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).

[0301] FIG. 30 is a diagram showing an example of a check matrix initial value table (of the type A method) representing a check matrix H of a type A code (hereinafter also referred to as a type A code with r = 2 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 2 / 16.

[0302] FIG. 31 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a type A code (hereinafter also referred to as a type A code with r = 3 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 3 / 16.

[0303] FIG. 32 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a type A code (hereinafter also referred to as a type A code with r = 4 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 4 / 16.

[0304] FIG. 33 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a type A code (hereinafter also referred to as a type A code with r = 5 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 5 / 16.

[0305] FIG. 34 is a diagram showing an example of an initial value table of a check matrix representing a check matrix H of a type A code (hereinafter also referred to as a type A code with r = 6 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 6 / 16.

[0306] FIG. 35 is a diagram showing an example of an initial value table of a check matrix representing a check matrix H of a type A code (hereinafter also referred to as a type A code with r = 7 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 7 / 16.

[0307] FIG. 36 is a diagram showing an example of an initial value table of a check matrix (in the type B method) representing a check matrix H of a type B code (hereinafter also referred to as a type B code with r = 7 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 7 / 16.

[0308] FIG. 37 is a diagram showing an example of an initial value table of a check matrix representing a check matrix H of a type B code (hereinafter also referred to as a type B code with r = 8 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 8 / 16.

[0309] FIG. 38 is a diagram showing an example of an initial value table of a check matrix representing a check matrix H of a type B code (hereinafter also referred to as a type B code with r = 9 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 9 / 16.

[0310] FIG. 39 is a diagram showing an example of an initial value table of a check matrix representing a check matrix H of a type B code (hereinafter also referred to as a type B code with r = 10 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 10 / 16.

[0311] FIG. 40 is a diagram showing an example of an initial value table of a check matrix representing a check matrix H of a type B code (hereinafter also referred to as a type B code with r = 11 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 11 / 16.

[0312] FIG. 41 is a diagram showing an example of an initial value table of a check matrix representing a type B code (hereinafter also referred to as a type B code with r = 12 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 12 / 16.

[0313] FIG. 42 is a diagram showing an example of an initial value table of a check matrix representing a type B code (hereinafter also referred to as a type B code with r = 13 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 13 / 16.

[0314] FIG. 43 is a diagram showing an example of an initial value table of a check matrix representing a type B code (hereinafter also referred to as a type B code with r = 14 / 16) as a new LDPC code with a code length N of 17,280 bits and a coding rate r of 14 / 16.

[0315] The new LDPC code has become an LDPC code with good performance.

[0316] Here, an LDPC code with good performance is an LDPC code obtained from an appropriate check matrix H.

[0317] An appropriate check matrix H is, for example, an LDPC code obtained from the check matrix H, with a low E s / N 0 or E b / N o (signal power to noise power ratio per bit) when transmitted, and satisfies a predetermined condition that makes the BER (bit error rate) (and FER (frame error rate)) smaller.

[0318] An appropriate check matrix H can be obtained, for example, by performing a simulation to measure the BER when an LDPC code obtained from various check matrices satisfying a predetermined condition is transmitted at a low E s / N o .

[0319] As predetermined conditions that an appropriate check matrix H should satisfy, for example, the analysis results obtained by an analysis method of the performance of a code called Density Evolution are good, there is no loop of elements of 1 called Cycle 4, and so on.

[0320] Here, information matrix H A In, as in Cycle 4, when elements of 1 are concentrated, it is known that the decoding performance of the LDPC code deteriorates. Therefore, it is desirable that the check matrix H does not have Cycle 4.

[0321] In the check matrix H, the minimum value of the length of the loop (loop length) composed of elements of 1 is called the girth. The fact that there is no Cycle 4 means that the girth is greater than 4.

[0322] Note that the predetermined conditions that an appropriate check matrix H should satisfy can be appropriately determined from viewpoints such as improvement of the decoding performance of the LDPC code and facilitation (simplification) of the decoding process of the LDPC code.

[0323] FIG. 44 and FIG. 45 are diagrams for explaining Density Evolution from which analysis results as predetermined conditions that an appropriate check matrix H should satisfy are obtained.

[0324] Density Evolution is an analysis method of a code that calculates the expected value of the error probability for the entire LDPC code (ensemble) with code length N = ∞ characterized by a degree sequence described later.

[0325] For example, on an AWGN channel, when the variance value of the noise is gradually increased from 0, the expected value of the error probability of a certain ensemble is initially 0, but when the variance value of the noise becomes equal to or greater than a certain threshold, it becomes non-zero.

[0326] According to density evolution, by comparing the threshold value of the variance of noise (hereinafter also referred to as the performance threshold) at which the expected value of the error probability becomes non-zero, the quality of the performance of the ensemble (the appropriateness of the check matrix) can be determined.

[0327] For a specific LDPC code, by determining the ensemble to which the LDPC code belongs and performing density evolution on the ensemble, the approximate performance of the LDPC code can be predicted.

[0328] Therefore, a good LDPC code can be found from among the LDPC codes belonging to an ensemble if a good ensemble is found.

[0329] Here, the above-mentioned degree sequence represents the proportion of variable nodes and check nodes with weights for each value with respect to the code length N of the LDPC code.

[0330] For example, a regular (3,6) LDPC code with a coding rate of 1 / 2 belongs to an ensemble characterized by a degree sequence in which the weight (column weight) of all variable nodes is 3 and the weight (row weight) of all check nodes is 6.

[0331] FIG. 44 shows a Tanner graph of such an ensemble.

[0332] In the Tanner graph of FIG. 44, there are only N variable nodes indicated by circles (○ marks) in the figure, and the number of check nodes indicated by squares (□ marks) in the figure is N / 2, which is equal to the multiplication value obtained by multiplying the code length N by the coding rate 1 / 2.

[0333] Three edges equal to the column weight are connected to each variable node. Therefore, there are a total of 3N edges connected to the N variable nodes.

[0334] Also, six branches equal to the row weight are connected to each check node. Therefore, there are a total of 3N branches connected to N / 2 check nodes.

[0335] Furthermore, in the Tanner graph of FIG. 44, there is one interleaver.

[0336] The interleaver randomly rearranges the 3N branches connected to N variable nodes, and connects each rearranged branch to any one of the 3N branches connected to N / 2 check nodes.

[0337] The number of rearrangement patterns for rearranging the 3N branches connected to N variable nodes in the interleaver is (3N)! (=(3N)×(3N - 1)×···×1). Therefore, the ensemble characterized by the degree sequence where all variable node weights are 3 and all check node weights are 6 is a set of (3N)! LDPC codes.

[0338] In simulations to find good LDPC codes (appropriate check matrices), a multi-edge type ensemble was used in density evolution.

[0339] In the multi-edge type, the interleaver through which the branches connected to variable nodes and the branches connected to check nodes pass is divided into multiple (multi edge), whereby the characterization of the ensemble is performed more precisely.

[0340] FIG. 45 shows an example of a Tanner graph of a multi-edge type ensemble.

[0341] In the Tanner graph of FIG. 45, there are two interleavers, a first interleaver and a second interleaver.

[0342] Also, in the Tanner graph of FIG. 45, there are only v1 variable nodes where the number of branches connected to the first interleaver is 1 and the number of branches connected to the second interleaver is 0, only v2 variable nodes where the number of branches connected to the first interleaver is 1 and the number of branches connected to the second interleaver is 2, and only v3 variable nodes where the number of branches connected to the first interleaver is 0 and the number of branches connected to the second interleaver is 2, respectively.

[0343] Furthermore, in the Tanner graph of FIG. 45, there are only c1 check nodes where the number of branches connected to the first interleaver is 2 and the number of branches connected to the second interleaver is 0, only c2 check nodes where the number of branches connected to the first interleaver is 2 and the number of branches connected to the second interleaver is 2, and only c3 check nodes where the number of branches connected to the first interleaver is 0 and the number of branches connected to the second interleaver is 3, respectively.

[0344] Here, regarding density evolution and its implementation, for example, it is described in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", S.Y.Chung, G.D.Forney, T.J.Richardson,R.Urbanke, IEEE Communications Leggers, VOL.5, NO.2, Feb 2001.

[0345] In the simulation for obtaining a new LDPC code (check matrix), an ensemble is found in which the performance threshold, which is the E b / N 0 (signal power-to-noise power ratio per bit) at which the BER starts to drop (decrease) is below a predetermined value, and from among the LDPC codes belonging to that ensemble, an LDPC code that reduces the BER when using one or more orthogonal modulations such as QPSK is selected as an LDPC code with good performance.

[0346] The new LDPC code (the parity-check matrix initial value table representing the parity-check matrix) was obtained through the above simulations.

[0347] Therefore, according to the new LDPC code, good communication quality can be ensured in data transmission.

[0348] FIG. 46 is a diagram for explaining the column weight of the parity-check matrix H of the type A code as the new LDPC code.

[0349] Regarding the parity-check matrix H of the type A code, as shown in FIG. 46, let the column weight of the first K1 columns of the A matrix and the C matrix be X1, the column weight of the subsequent K2 columns of the A matrix and the C matrix be X2, the column weight of the subsequent K3 columns of the A matrix and the C matrix be X3, and the column weight of the subsequent M1 columns of the C matrix be XM1, respectively.

[0350] Note that K1 + K2 + K3 is equal to the information length K, and M1 + M2 is equal to the parity length M. Therefore, K1 + K2 + K3 + M1 + M2 is equal to the code length N = 17280 bits.

[0351] Also, regarding the parity-check matrix H of the type A code, the column weight of the first M1 - 1 columns of the B matrix is 2, and the column weight of the M1-th column (the last column) of the B matrix is 1. Furthermore, the column weight of the D matrix is 1, and the column weight of the Z matrix is 0.

[0352] FIG. 47 is a diagram showing the parameters of the parity-check matrix H of the type A code (represented by the parity-check matrix initial value table) in FIGS. 30 to 35.

[0353] K, X1, K1, X2, K2, X3, K3, XM1, M1, M2 as the parameters of the parity-check matrix H of the type A code with r = 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16 are as shown in FIG. 47.

[0354] The parameters X1, K1, X2, K2, X3, K3, XM1, M1 (or M2) are set so that the performance of the LDPC code (e.g., error rate, etc.) is further improved.

[0355] FIG. 48 is a diagram for explaining the column weight of the check matrix H of the type B code as a new LDPC code.

[0356] Regarding the check matrix H of the type B code, as shown in FIG. 48, the column weight of the KX1 columns from the first column is X1, the column weight of the subsequent KX2 columns is X2, the column weight of the subsequent KX3 columns is X3, the column weight of the subsequent KX4 columns is X4, and the column weight of the subsequent KY1 columns is Y1, respectively.

[0357] Note that KX1 + KX2 + KX3 + KX4 + KY1 is equal to the information length K, and KX1 + KX2 + KX3 + KX4 + KY1 + M is equal to the code length N = 17280 bits.

[0358] Also, regarding the check matrix H of the type B code, among the last M columns, the column weight of M - 1 columns excluding the last column is 2, and the column weight of the last column is 1.

[0359] FIG. 49 is a diagram showing the parameters of the check matrix H of the type B code (represented by the check matrix initial value table) in FIGS. 36 to 43.

[0360] K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1 as the parameters of the check matrix H of the type B code with r = 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 are as shown in FIG. 49.

[0361] The parameters X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1 are set so that the performance of the LDPC code is further improved.

[0362] According to the new LDPC code, good BER / FER is achieved, and a capacity (communication channel capacity) close to the Shannon limit is achieved.

[0363] <Constellation>

[0364] Figs. 50 to 74 are diagrams showing examples of constellations that can be adopted in the transmission system of Fig. 7.

[0365] In the transmission system of Fig. 7, for example, for a MODCOD that is a combination of a modulation method (MODulation) and an LDPC code (CODe), the constellation used in that MODCOD can be set.

[0366] For one MODCOD, one or more constellations can be set.

[0367] Constellations include a UC (Uniform Constellation) in which the arrangement of signal points is uniform and a NUC (Non Uniform Constellation) in which the arrangement is not uniform.

[0368] Also, for the NUC, for example, there are constellations called 1D-NUC (1-dimensional (M 2 -QAM) non-uniform constellation) and constellations called 2D-NUC (2-dimensional (QQAM) non-uniform constellation), etc.

[0369] Generally, the BER is improved more by 1D-NUC than by UC, and further, the BER is improved more by 2D-NUC than by 1D-NUC.

[0370] For a modulation scheme with QPSK constellation, it will be UC. For modulation schemes with constellations such as 16QAM, 64QAM, 256QAM, etc., for example, UC or 2D-NUC can be adopted. For modulation schemes with constellations such as 1024QAM or 4096QAM, for example, UC or 1D-NUC can be adopted.

[0371] In the transmission system of FIG. 7, for example, constellations defined in ATSC3.0, DVB-C.2, etc., and other various constellations that can improve the error rate can be used.

[0372] That is, when the modulation scheme is QPSK, for each coding rate r of the LDPC code, for example, the same UC can be used.

[0373] Also, when the modulation scheme is 16QAM, 64QAM, or 256QAM, for each coding rate r of the LDPC code, for example, the same UC can be used. Furthermore, when the modulation scheme is 16QAM, 64QAM, or 256QAM, for example, different 2D-NUCs can be used for each coding rate r of the LDPC code.

[0374] Also, when the modulation scheme is 1024QAM or 4096QAM, for each coding rate r of the LDPC code, for example, the same UC can be used. Furthermore, when the modulation scheme is 1024QAM or 4096QAM, for example, different 1D-NUCs can be used for each coding rate r of the LDPC code.

[0375] Here, the UC of QPSK is also referred to as QPSK-UC, and the m UC of 2 m QAM is also referred to as 2 m QAM-UC. Also, the 1D-NUC and 2D-NUC of 2 m QAM are respectively referred to as 2 m QAM-1D-NUC and 2

[0376] The following describes some of the constellations defined in ATSC 3.0.

[0377] FIG. 50 is a diagram showing the coordinates of the signal points of QPSK-UC used for all the coding rates of the LDPC code defined in ATSC 3.0 when the modulation method is QPSK.

[0378] In FIG. 50, "Input Data cell y" represents a 2-bit symbol mapped to QPSK-UC, and "Constellation point z s " represents the coordinates of signal point z s . Note that the index s of signal point z s (similarly for the index q of signal point z q described later) represents the discrete time of the symbol (the time interval between one symbol and the next symbol).

[0379] In FIG. 50, the coordinates of signal point z s are represented in the form of complex numbers, and j represents the imaginary unit (√(-1)).

[0380] FIG. 51 is a diagram showing the coordinates of the signal points of 16QAM-2D-NUC used for the coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code defined in ATSC 3.0 when the modulation method is 16QAM.

[0381] In FIG. 51, similar to FIG. 50, the coordinates of signal point z s are represented in the form of complex numbers, and j represents the imaginary unit.

[0382] In FIG. 51, w#k represents the coordinates of the signal points in the first quadrant of the constellation.

[0383] In 2D-NUC, the signal points in the second quadrant of the constellation are arranged at positions where the signal points in the first quadrant are symmetrically moved with respect to the Q-axis, and the signal points in the third quadrant of the constellation are arranged at positions where the signal points in the first quadrant are symmetrically moved with respect to the origin. Then, the signal points in the fourth quadrant of the constellation are arranged at positions where the signal points in the first quadrant are symmetrically moved with respect to the I-axis.

[0384] Here, when the modulation method is 2 m QAM, taking m bits as one symbol, that one symbol is mapped to the signal point corresponding to that symbol.

[0385] The symbol of m bits can be represented by integer values from 0 to 2 m -1, but now, let b = 2 m / 4, then the symbol represented by integer values from 0 to 2 m -1, y(0), y(1), ···, y(2 m -1) can be classified into four groups: symbols y(0) to y(b - 1), y(b) to y(2b - 1), y(2b) to y(3b - 1), and y(3b) to y(4b - 1).

[0386] In FIG. 51, the suffix k of w#k takes integer values in the range from 0 to b - 1, and w#k represents the coordinates of the signal point corresponding to the symbol y(k) in the range of symbols y(0) to y(b - 1).

[0387] And the coordinates of the signal point corresponding to the symbol y(k + b) in the range of symbols y(b) to y(2b - 1) are represented by -conj(w#k), the coordinates of the signal point corresponding to the symbol y(k + 2b) in the range of symbols y(2b) to y(3b - 1) are represented by conj(w#k). Also, the coordinates of the signal point corresponding to the symbol y(k + 3b) in the range of symbols y(3b) to y(4b - 1) are represented by -w#k.

[0388] Here, conj(w#k) represents the complex conjugate of w#k.

[0389] For example, when the modulation method is 16QAM, for the symbols y(0), y(1), ···, y(15) with m = 4 bits, b = 2 4 / 4 = 4, and they are classified into four groups: symbols y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15).

[0390] Among the symbols y(0) to y(15), for example, symbol y(12) is the symbol y(k + 3b) = y(0 + 3×4) in the range of symbols y(3b) to y(4b - 1). Since k = 0, the coordinate of the signal point corresponding to symbol y(12) is -w#k = -w0.

[0391] Now, assuming that the coding rate r(CR) of the LDPC code is, for example, 9 / 15, according to FIG. 51, when the modulation method is 16QAM and the coding rate r is 9 / 15, w0 is 0.2386 + j0.5296. Therefore, the coordinate -w0 of the signal point corresponding to symbol y(12) is -(0.2386 + j0.5296).

[0392] FIG. 52 shows examples of the coordinates of the signal points of 1024QAM - 1D - NUC used for the coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code defined in ATSC3.0 when the modulation method is 1024QAM.

[0393] In FIG. 52, u#k represents the real part Re(z s ) and the imaginary part Im(z s ) of the complex number as the coordinate of the signal point of 1D - NUC, and is a component of the vector u = (u0, u1,..., u#V - 1) called the position vector. The number V of the components u#k of the position vector u is given by the formula V = √(2 s ) / 2. m ) / 2.

[0394] FIG. 53 is a diagram showing the relationship between the symbol y of 1024QAM and the position vector u (component u#k).

[0395] Now, the 10-bit symbol y of 1024QAM is represented from its leading bit (most significant bit) as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s and so on.

[0396] A in FIG. 53 represents the correspondence between the even-numbered 5 bits y 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s of the symbol y and u#k representing the real part Re(z s ) of the signal point z s corresponding to that symbol y.

[0397] B in FIG. 53 represents the correspondence between the odd-numbered 5 bits y 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s of the symbol y and u#k representing the imaginary part Im(z s ) of the signal point z s corresponding to that symbol y.

[0398] When the 10-bit symbol y = (y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ) of 1024QAM is, for example, (0,0,1,0,0,1,1,1,0,0), the odd-numbered 5 bits (y 0,s ,y 2,s, y 4,s , y 6,s , y 8,s ) is (0, 1, 0, 1, 0), and the even-numbered 5 bits (y 1,s , y 3,s , y 5,s , y 7,s , y 9,s ) is (0, 0, 1, 1, 0).

[0399] In A of FIG. 53, the even-numbered 5 bits (0, 0, 1, 1, 0) are associated with u11, and thus, the real part Re(z s ) of the signal point z corresponding to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) becomes u11. s

[0400] In B of FIG. 53, the odd-numbered 5 bits (0, 1, 0, 1, 0) are associated with u3, and thus, the imaginary part Im(z s ) of the signal point z corresponding to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) becomes u3. s

[0401] On the other hand, assuming that the coding rate r of the LDPC code is, for example, 6 / 15, according to FIG. 52 described above, for the 1D-NUC used when the modulation method is 1024QAM and the coding rate r(CR) of the LDPC code is 6 / 15, u3 is 0.1295 and u11 is 0.7196.

[0402] Therefore, the real part Re(z s ) of the signal point z corresponding to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) becomes u11 = 0.7196, and the imaginary part Im(z s ) becomes u3 = 0.1295. As a result, the coordinates of the signal point z corresponding to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) are represented as 0.7196 + j0.1295. s s

[0403] ​​​​Note that the signal points of 1D-NUC are arranged in a grid pattern on a straight line parallel to the I-axis or a straight line parallel to the Q-axis in the constellation. However, the intervals between the signal points are not constant. Also, when transmitting the signal points (the data mapped thereto), the average power of the signal points on the constellation can be normalized. The normalization is performed by taking the root mean square value of the absolute values of all the signal points (the coordinates) on the constellation as P ave If we represent it as such, the root mean square value P ave The square root √P of ave The reciprocal 1 / (√P ave ) can be multiplied by each signal point z s on the constellation to perform the normalization.

[0404] In the transmission system of FIG. 7, the constellation defined by ATSC 3.0 as described above can be used.

[0405] FIGS. 54 to 65 are diagrams showing the coordinates of the signal points of UC defined by DVB-C.2.

[0406] That is, FIG. 54 is a diagram showing the real part Re(z q ) of the coordinates of the signal points of QPSK-UC (UC of QPSK) defined by DVB-C.2. FIG. 55 is a diagram showing the imaginary part Im(z q ) of the coordinates of the signal points of QPSK-UC defined by DVB-C.2. q FIG. 56 is a diagram showing the real part Re(z q ) of the coordinates of the signal points of 16QAM-UC (UC of 16QAM) defined by DVB-C.2. FIG. 57 is a diagram showing the imaginary part Im(z

[0407] FIG. 56 shows the real part Re(z q ) of the coordinates of the signal points of 16QAM-UC (UC of 16QAM) defined by DVB-C.2. FIG. 57 shows the imaginary part Im(z q ) of the coordinates of the signal points of 16QAM-UC defined by DVB-C.2. q The imaginary part Im(z q ) of the coordinates of the signal points of 16QAM-UC defined by DVB-C.2.

[0408] Figure 58 shows the real part Re(z q ) of the signal point coordinates z of 64QAM-UC (UC of 64QAM) defined in DVB-C.2. Figure 59 shows the imaginary part Im(z q ) of the signal point coordinates z of 64QAM-UC defined in DVB-C.2. q q ) of the signal point coordinates z of 64QAM-UC defined in DVB-C.2.

[0409] Figure 60 shows the real part Re(z q ) of the signal point coordinates z of 256QAM-UC (UC of 256QAM) defined in DVB-C.2. Figure 61 shows the imaginary part Im(z q ) of the signal point coordinates z of 256QAM-UC defined in DVB-C.2. q q ) of the signal point coordinates z of 256QAM-UC defined in DVB-C.2.

[0410] Figure 62 shows the real part Re(z q ) of the signal point coordinates z of 1024QAM-UC (UC of 1024QAM) defined in DVB-C.2. Figure 63 shows the imaginary part Im(z q ) of the signal point coordinates z of 1024QAM-UC defined in DVB-C.2. q q ) of the signal point coordinates z of 1024QAM-UC defined in DVB-C.2.

[0411] Figure 64 shows the real part Re(z q ) of the signal point coordinates z of 4096QAM-UC (UC of 4096QAM) defined in DVB-C.2. Figure 65 shows the imaginary part Im(z q ) of the signal point coordinates z of 4096QAM-UC defined in DVB-C.2. q q ) of the signal point coordinates z of 4096QAM-UC defined in DVB-C.2.

[0412] Note that in Figures 54 to 65, y i,q is 2 m ​​​​It represents the (i + 1)-th bit from the beginning of an m-bit symbol of QAM (e.g., 2 bits in QPSK). Also, when transmitting the signal points (data mapped thereto) of UC, the average power of the signal points on the constellation can be normalized. The normalization is to take the root mean square value of the squares of the absolute values for all of the signal points (coordinates) on the constellation as P ave If we denote it as such, the root mean square value P ave The square root √P ave The reciprocal 1 / (√P ave ) can be used to multiply each signal point z q on the constellation.

[0413] In the transmission system of FIG. 7, the above-described UC defined in DVB-C.2 can be used.

[0414] That is, for the new LDPC codes (corresponding to the initial parity-check matrix tables) with a code length N of 17,280 bits and code rates r of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16 shown in FIGS. 30 to 43, the UC shown in FIGS. 54 to 65 can be used.

[0415] FIGS. 66 to 74 are diagrams showing examples of the coordinates of the signal points of the NUC that can be used for the new LDPC codes with a code length N of 17,280 bits and code rates r of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16 shown in FIGS. 30 to 43.

[0416] That is, FIG. 66 is a diagram showing an example of the coordinates of the signal points of 16QAM-2D-NUC that can be used for the new LDPC code.

[0417] FIG. 67 is a diagram showing an example of the coordinates of the signal points of 64QAM-2D-NUC that can be used for the new LDPC code.

[0418] Figures 68 and 69 are diagrams showing examples of the coordinates of the signal points of 256QAM-2D-NUC that can be used for the new LDPC code.

[0419] Note that Figure 69 is a figure following Figure 68.

[0420] In Figures 66 to 69, similar to Figure 51, the coordinates of the signal point z s are represented in the form of complex numbers, and j represents the imaginary unit.

[0421] In Figures 66 to 69, similar to Figure 51, w#k represents the coordinates of the signal points in the first quadrant of the constellation.

[0422] Here, as described in Figure 51, an m-bit symbol is represented by an integer value from 0 to 2 m -1, and when b = 2 m / 4, the symbols y(0), y(1), ···, y(2 m -1) represented by integer values from 0 to 2 m -1 can be classified into four groups: symbols y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

[0423] In Figures 66 to 69, similar to Figure 51, the suffix k of w#k takes an integer value in the range from 0 to b-1, and w#k represents the coordinates of the signal points corresponding to the symbol y(k) in the range of symbols y(0) to y(b-1).

[0424] Furthermore, in Figures 66 to 69, similar to Figure 51, the coordinates of the signal points corresponding to the symbol y(k + 3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

[0425] However, in FIG. 51, the coordinates of the signal points corresponding to the symbols y(k + b) in the range of the symbols y(b) to y(2b - 1) are represented by -conj(w#k), and the coordinates of the signal points corresponding to the symbols y(k + 2b) in the range of the symbols y(2b) to y(3b - 1) are represented by conj(w#k). However, in FIGS. 66 to 69, the sign of conj is reversed.

[0426] That is, in FIGS. 66 to 69, the coordinates of the signal points corresponding to the symbols y(k + b) in the range of the symbols y(b) to y(2b - 1) are represented by conj(w#k), and the coordinates of the signal points corresponding to the symbols y(k + 2b) in the range of the symbols y(2b) to y(3b - 1) are represented by -conj(w#k).

[0427] FIG. 70 is a diagram showing an example of the coordinates of the signal points of 1024QAM-1D-NUC that can be used for the new LDPC code.

[0428] That is, FIG. 70 shows the real part Re(z s of the complex number as the coordinates of the signal point z of 1024QAM-1D-NUC s ) and the imaginary part Im(z s ), and the relationship with the position vector u (component u#k) of.

[0429] FIG. 71 is a diagram showing the relationship between the symbol y of 1024QAM and the position vector u (component u#k) of FIG. 70.

[0430] That is, now, the 10-bit symbol y of 1024QAM is represented as y 0,s , y 1,s , y 2,s , y 3,s , y 4,s , y 5,s , y 6,s , y 7,s , y 8,s , y 9,s from its leading bit (most significant bit).

[0431] A in FIG. 71 represents the correspondence between the odd-numbered 5 bits y (starting from the beginning) of the 10-bit symbol y 0,s , y 2,s , y 4,s , y 6,s , y 8,s and the position vector u#k representing the real part Re(z s (of the coordinates) of the signal point z corresponding to that symbol y s ).

[0432] B in FIG. 71 represents the correspondence between the even-numbered 5 bits y of the 10-bit symbol y 1,s , y 3,s , y 5,s , y 7,s , y 9,s and the position vector u#k representing the imaginary part Im(z s (of the coordinates) of the signal point z corresponding to that symbol y s ).

[0433] When the 10-bit symbol y of 1024QAM is mapped to the signal point z of 1024QAM-1D-NUC defined in FIGS. 70 and 71 s , the method for obtaining the coordinates of the signal point z s is the same as that described in FIGS. 52 and 53, so the description is omitted.

[0434] FIG. 72 is a diagram showing an example of the coordinates of the signal points of 4096QAM-1D-NUC that can be used for the new LDPC code.

[0435] That is, FIG. 72 is a diagram showing the relationship between the real part Re(z s ) and the imaginary part Im(z s ) of the complex number as the coordinates of the signal point z of 4096QAM-1D-NUC s and the position vector u (u#k).

[0436] FIGS. 73 and 74 are diagrams showing the relationship between the symbol y of 4096QAM and the position vector u (the component u#k thereof) in FIG. 72.

[0437] That is, now, for a 12-bit symbol y of 4096QAM, starting from its leading bit (the most significant bit), y 0,s , y 1,s , y 2,s , y 3,s , y 4,s , y 5,s , y 6,s , y 7,s , y 8,s , y 9,s , y 10,s , y 11,s shall be represented as follows.

[0438] FIG. 73 shows the odd-numbered 6 bits y 0,s , y 2,s , y 4,s , y 6,s , y 8,s , y 10,s of a 12-bit symbol y and the position vector u#k representing the real part Re(z s ) of the signal point z s corresponding to that symbol y.

[0439] FIG. 74 shows the even-numbered 6 bits y 1,s , y 3,s , y 5,s , y 7,s , y 9,s , y 11,s of a 12-bit symbol y and the position vector u#k representing the imaginary part Im(z s ) of the signal point z s corresponding to that symbol y.

[0440] When a 12-bit symbol y of 4096QAM is mapped to the signal point z s of 4096QAM-1D-NUC defined in FIGS. 72 to 74, the method for obtaining the coordinates of that signal point z s is the same as that described in FIGS. 52 and 53, so the description is omitted.

[0441] When transmitting the signal points (data mapped thereto) of the NUCs in FIGS. 66 to 74, the average power of the signal points on the constellation can be normalized. The normalization is performed by taking the root mean square value of the absolute values of all of the (coordinates of the) signal points on the constellation as P ave and if we denote the root mean square value as P ave then the reciprocal 1 / (√P ave ) of the square root √P ave is multiplied by each signal point z s on the constellation. Also, in FIG. 53 described above, the odd-numbered bits of symbol y are associated with the position vector u#k representing the imaginary part Im(z s ) of signal point z s and the even-numbered bits of symbol y are associated with the position vector u#k representing the real part Re(z s ) of signal point z s . However, in FIGS. 71, 73, and 74, conversely, the odd-numbered bits of symbol y are associated with the position vector u#k representing the real part Re(z s ) of signal point z s and the even-numbered bits of symbol y are associated with the position vector u#k representing the imaginary part Im(z s ) of signal point z s .

[0442] <Block Interleaver 25>

[0443] FIG. 75 is a diagram for explaining the block interleaving performed by the block interleaver 25 of FIG. 9.

[0444] The block interleaving is performed by dividing the LDPC code of one codeword from its beginning into a part called part 1 and a part called part 2.

[0445] If we denote the length (number of bits) of part 1 as Npart1 and the length of part 2 as Npart2, then Npart1 + Npart2 is equal to the code length N.

[0446] Conceptually, in block interleaving, columns (vertical) in one direction are arranged in the row direction orthogonal to the column direction, with m columns equal to the number of bits of a symbol, where each column serves as a storage area for storing Npart1 / m bits. Each column is divided into small units of 360 bits, which is the parallel factor P, from top to bottom. This small unit of a column is also referred to as a column unit.

[0447] In block interleaving, as shown in FIG. 75, part 1 of the LDPC code of one codeword is written in the downward (column direction) from the top of the first column unit of a column, proceeding in the columns from left to right.

[0448] When the writing to the first column unit of the rightmost column is completed, as shown in FIG. 75, the process returns to the leftmost column, and the writing in the downward direction from the top of the second column unit of the column is performed in the columns from left to right. Subsequently, in the same manner, the writing of part 1 of the LDPC code of one codeword is carried out.

[0449] When the writing of part 1 of the LDPC code of one codeword is completed, as shown in FIG. 75, part 1 of the LDPC code is read out in units of m bits in the row direction from the first row of all m columns.

[0450] These m-bit units of part 1 are supplied as m-bit symbols from the block interleaver 25 to the mapper 117 (FIG. 8).

[0451] The reading of part 1 in units of m bits is sequentially performed toward the lower rows of the m columns. When the reading of part 1 is completed, part 2 is divided into units of m bits from the beginning and supplied as m-bit symbols from the block interleaver 25 to the mapper 117.

[0452] Therefore, Part 1 is symbolized while being interleaved, and Part 2 is sequentially segmented into m-bit units without being interleaved and then symbolized.

[0453] The length of the column Npart1 / m is a multiple of 360, which is the parallel factor P. The LDPC code of one codeword is divided into Part 1 and Part 2 so that Npart1 / m is a multiple of 360.

[0454] FIG. 76 shows examples of Part 1 and Part 2 of the LDPC code with a code length N of 69120 bits when the modulation schemes are QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM, respectively.

[0455] In FIG. 76, when the modulation scheme is 1024QAM, Part 1 is 68400 bits and Part 2 is 720 bits. When the modulation schemes are QPSK, 16QAM, 64QAM, 256QAM, and 4096QAM, in all cases, Part 1 is 69120 bits and Part 2 is 0 bits.

[0456] <Group-wise interleaving>

[0457] FIG. 77 is a diagram for explaining the group-wise interleaving performed by the group-wise interleaver 24 in FIG. 9.

[0458] In group-wise interleaving, as shown in FIG. 77, the LDPC code of one codeword is divided from its beginning into 360-bit units equal to the parallel factor P. The 360 bits of one such division are used as a bit group, and the LDPC code of one codeword is interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as the GW pattern).

[0459] Here, the (i + 1)-th bit group from the beginning when the LDPC code of one codeword is divided into bit groups is hereinafter also referred to as bit group i.

[0460] When the parallel factor P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (= 1800 / 360) bit groups of bit groups 0, 1, 2, 3, 4. Further, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (= 69120 / 360) bit groups of bit groups 0, 1, ···, 191. Also, for example, an LDPC code with a code length N of 17280 bits is divided into 48 (= 17280 / 360) bit groups of bit groups 0, 1, ···, 47.

[0461] Hereinafter, the GW pattern will be represented by an arrangement of numbers representing bit groups. For example, for an LDPC code with a code length N of 1800 bits and 5 bit groups 0, 1, 2, 3, 4, for example, the GW pattern 4, 2, 0, 3, 1 means interleaving (rearranging) the arrangement of bit groups 0, 1, 2, 3, 4 into the arrangement of bit groups 4, 2, 0, 3, 1.

[0462] For example, now, let the (i + 1)-th code bit from the beginning of an LDPC code with a code length N of 1800 bits be represented by x i as follows.

[0463] In this case, according to the group-wise interleaving of the GW pattern 4, 2, 0, 3, 1, the 1800-bit LDPC code {x 0 , x 1 ,..., x 1799} becomes {x 1440 , x 1441 ,..., x 1799 , {x 720 , x 721 ,..., x 1079 , {x 0 , x 1 ,..., x 359 , {x 1080 , x 1081 ,..., x 1439 , {x 360 , x 361 ,..., x 719are interleaved in the order of {...}.

[0464] The GW pattern can be set for each code length N of the LDPC code, for each coding rate r, for each modulation method, for each constellation, and further for each combination of two or more of the code length N, coding rate r, modulation method, and constellation.

[0465] <Example of GW Pattern for LDPC Code>

[0466] FIG. 78 is a diagram showing an example of a GW pattern for an LDPC code with a code length N of 69,120 bits.

[0467] According to the GW pattern of FIG. 78, the order of bit groups 0 to 191 of the 69,120-bit LDPC code is the bit group 191, 12, 188, 158, 173, 48, 75, 146, 113, 15, 51, 119, 132, 161, 91, 189, 142, 93, 120, 29, 156, 101, 100, 22, 165, 65, 98, 153, 127, 74, 39, 80, 38, 130, 148, 81, 13, 24, 125, 0, 174, 140, 124, 5, 68, 3, 104, 136, 63, 162, 106, 8, 25, 182, 178, 90, 96, 79, 168, 172, 128, 64, 69, 102, 45, 66, 86, 155, 163, 6, 152, 164, 108, 9, 111, 16, 177, 53, 94, 85, 72, 32, 147, 184, 117, 30, 54, 34, 70, 149, 157, 109, 73, 41, 131, 187, 185, 18, 4, 150, 92, 143, 14, 115, 20, 50, 26, 83, 36, 58, 169, 107, 129, 121, 43, 103, 21, 139, 52, 167, 19, 2, 40, 116, 181, 61, 141, 17, 33, 11, 135, 1, 37, 123, 180, 137, 77, 166, 183, 82, 23, 56, 88, 67, 176, 76, 35, 71, 105, 87, 78, 171, 55, 62, 44, 57, 97, 122, 112, 59, 27, 99, 84, 10, 134, 42, 118, 144, 49, 28, 126, 95, 7, 110, 186, 114, 151, 145, 175, 138, 133, 31, 179, 89, 46, 160, 170, 60, 154, 159, 47, 190 are interleaved in the order of.

[0468] <Configuration example of the receiving device 12>

[0469] FIG. 79 is a block diagram showing a configuration example of the receiving device 12 of FIG. 7.

[0470] The OFDM processing unit (OFDM operation) 151 receives the OFDM signal from the transmission device 11 (Fig. 7) and performs signal processing on the OFDM signal. The data obtained by the OFDM processing unit 151 performing signal processing is supplied to the frame management unit (Frame Management) 152.

[0471] The frame management unit 152 performs processing (frame interpretation) on the frame composed of the data supplied from the OFDM processing unit 151, and supplies the signal of the target data and the signal of the control data obtained as a result to the frequency deinterleavers (Frequency Deinterleaver) 161 and 153, respectively.

[0472] The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 in symbol units and supplies it to the demapper 154.

[0473] The demapper 154 demaps (decodes the signal point arrangement) and performs quadrature demodulation on the data (data on the constellation) from the frequency deinterleaver 153 based on the arrangement of signal points (constellation) defined by the quadrature modulation performed on the transmission device 11 side, and supplies the data (likelihood of the LDPC code) obtained as a result to the LDPC decoder 155.

[0474] The LDPC decoder 155 (decoding unit) performs LDPC decoding of the LDPC code from the demapper 154, and supplies the resulting LDPC target data (here, BCH code) to the BCH decoder 156.

[0475] The BCH decoder 156 performs BCH decoding of the LDPC target data from the LDPC decoder 155 and outputs the resulting control data (signaling).

[0476] On the one hand, the frequency deinterleaver 161 performs frequency deinterleaving on a symbol-by-symbol basis for the data from the frame management unit 152, and supplies it to the SISO / MISO decoder 162.

[0477] The SISO / MISO decoder 162 performs spatio-temporal decoding of the data from the frequency deinterleaver 161, and supplies it to the Time Deinterleaver 163.

[0478] The Time Deinterleaver 163 performs time deinterleaving on a symbol-by-symbol basis for the data from the SISO / MISO decoder 162, and supplies it to the Demapper 164.

[0479] The Demapper 164 demaps (decodes the signal point arrangement) and quadrature demodulates the data (data on the constellation) from the Time Deinterleaver 163 based on the arrangement of signal points (constellation) defined by the quadrature modulation performed on the transmission device 11 side, and supplies the resulting data to the Bit Deinterleaver 165.

[0480] The Bit Deinterleaver 165 performs bit deinterleaving on the data from the Demapper 164, and supplies the LDPC code (likelihood) which is the data after the bit deinterleaving to the LDPC decoder 166.

[0481] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the Bit Deinterleaver 165, and supplies the resulting LDPC target data (here, BCH code) to the BCH decoder 167.

[0482] The BCH decoder 167 performs BCH decoding of the LDPC target data from the LDPC decoder 155, and supplies the resulting data to the BB DeScrambler 168.

[0483] The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to the Null Deletion unit 169.

[0484] The Null Deletion unit 169 deletes the Null inserted by the padding 112 in FIG. 8 from the data from the BB descrambler 168 and supplies it to the Demultiplexer 170.

[0485] The Demultiplexer 170 separates each of the one or more streams (target data) multiplexed in the data from the Null Deletion unit 169, performs necessary processing, and outputs it as an Output stream.

[0486] Note that the receiving device 12 can be configured without providing a part of the blocks illustrated in FIG. 79. That is, for example, when the transmitting device 11 (FIG. 8) is configured without providing the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiving device 12 can be configured without providing the time deinterleaver 163, the SISO / MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153, which are the blocks corresponding to the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmitting device 11, respectively.

[0487] <Configuration example of the bit deinterleaver 165>

[0488] FIG. 80 is a block diagram showing a configuration example of the bit deinterleaver 165 in FIG. 79.

[0489] The bit deinterleaver 165 is composed of a block deinterleaver 54 and a group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols, which are the data from the demapper 164 (FIG. 79).

[0490] That is, the block deinterleaver 54 performs a block deinterleaving (a process reverse to the block interleaving) corresponding to the block interleaving performed by the block interleaver 25 in FIG. 9 on the symbol bits of the symbols from the demapper 164, that is, a block deinterleaving that returns the positions of the code bits (likelihoods) of the LDPC code rearranged by the block interleaving to their original positions, and supplies the resulting LDPC code to the groupwise deinterleaver 55.

[0491] The groupwise deinterleaver 55 performs a groupwise deinterleaving (a process reverse to the groupwise interleaving) corresponding to the groupwise interleaving performed by the groupwise interleaver 24 in FIG. 9 on the LDPC code from the block deinterleaver 54, that is, for example, a groupwise deinterleaving that rearranges the code bits of the LDPC code whose order has been changed in bit group units by the groupwise interleaving described in FIG. 77 in bit group units to return them to their original order.

[0492] Here, when a parity interleaving, a groupwise interleaving, and a block interleaving are performed on the LDPC code supplied from the demapper 164 to the bit deinterleaver 165, the bit deinterleaver 165 can perform all of a parity deinterleaving corresponding to the parity interleaving (a process reverse to the parity interleaving, that is, a parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by the parity interleaving to their original order), a block deinterleaving corresponding to the block interleaving, and a groupwise deinterleaving corresponding to the groupwise interleaving.

[0493] However, in the bit deinterleaver 165 of FIG. 80, a block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving and a groupwise deinterleaver 55 that performs groupwise deinterleaving corresponding to groupwise interleaving are provided, but a block that performs parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

[0494] Therefore, from the bit deinterleaver 165 (groupwise deinterleaver 55 thereof), the LDPC decoder 166 is supplied with an LDPC code in which block deinterleaving and groupwise deinterleaving are performed and parity deinterleaving is not performed.

[0495] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a conversion check matrix obtained by performing at least column permutation corresponding to parity interleaving on a type B check matrix H used by the LDPC encoder 115 of FIG. 8 for LDPC encoding, or a conversion check matrix (FIG. 29) obtained by performing row permutation on a type A check matrix (FIG. 27), and outputs the resulting data as the decoding result of the LDPC target data.

[0496] FIG. 81 is a flowchart for explaining the processing performed by the demapper 164, bit deinterleaver 165, and LDPC decoder 166 of FIG. 80.

[0497] In step S111, the demapper 164 demaps and quadrature demodulates the data (data on the constellation mapped to signal points) from the time deinterleaver 163, supplies it to the bit deinterleaver 165, and the process proceeds to step S112.

[0498] In step S112, the bit deinterleaver 165 performs deinterleaving (bit deinterleaving) of the data from the demapper 164, and the process proceeds to step S113.

[0499] That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbols) from the demapper 164, and supplies the resulting code bits of the LDPC code to the group-wise deinterleaver 55.

[0500] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, and supplies the resulting LDPC code (likelihood) to the LDPC decoder 166.

[0501] In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 using the parity-check matrix H that the LDPC encoder 115 in FIG. 8 used for LDPC encoding, that is, for example, using the transformed parity-check matrix obtained from the parity-check matrix H, and outputs the resulting data as the decoding result of the LDPC target data to the BCH decoder 167.

[0502] Note that also in FIG. 80, for the sake of convenience of explanation, similar to the case of FIG. 9, the block deinterleaver 54 that performs block deinterleaving and the group-wise deinterleaver 55 that performs group-wise deinterleaving are configured separately, but the block deinterleaver 54 and the group-wise deinterleaver 55 can be integrally configured.

[0503] Also, in the transmitter 11, when group-wise interleaving is not performed, the receiver 12 can be configured without providing the group-wise deinterleaver 55 that performs group-wise deinterleaving.

[0504] <LDPC decoding>

[0505] The LDPC decoding performed by the LDPC decoder 166 in FIG. 79 will be further described.

[0506] In the LDPC decoder 166 in FIG. 79, as described above, block deinterleaving and group-wise deinterleaving are performed on the LDPC code from the group-wise deinterleaver 55, and LDPC decoding of the LDPC code without parity deinterleaving is performed on the type B check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding. It is performed using a transformed check matrix obtained by performing at least column permutation corresponding to parity deinterleaving on the check matrix H, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the type A check matrix (FIG. 27).

[0507] Here, LDPC decoding using a transformed check matrix has been previously proposed, which can suppress the circuit scale and keep the operating frequency within a sufficiently achievable range while performing LDPC decoding (see, for example, Japanese Patent No. 4224777).

[0508] Therefore, first, with reference to FIGS. 82 to 85, the previously proposed LDPC decoding using a transformed check matrix will be described.

[0509] FIG. 82 is a diagram showing an example of the check matrix H of an LDPC code with a code length N of 90 and a coding rate of 2 / 3.

[0510] In FIG. 82 (similarly in FIGS. 83 and 84 described later), 0 is represented by a period (.).

[0511] In the check matrix H of FIG. 82, the parity matrix has a staircase structure.

[0512] FIG. 83 is a diagram showing the check matrix H' obtained by performing the row permutation of Equation (11) and the column permutation of Equation (12) on the check matrix H of FIG. 82.

[0513] Row replacement: the (6s + t + 1)-th row → the (5t + s + 1)-th row ···(11)

[0514] Column replacement: the (6x + y + 61)-th column → the (5y + x + 61)-th column ···(12)

[0515] However, in formulas (11) and (12), s, t, x, and y are integers in the ranges of 0 ≤ s < 5, 0 ≤ t < 6, 0 ≤ x < 5, and 0 ≤ t < 6, respectively.

[0516] According to the row replacement of formula (11), the 1st, 7th, 13th, 19th, and 25th rows, which have a remainder of 1 when divided by 6, are respectively replaced with the 1st, 2nd, 3rd, 4th, and 5th rows, and the 2nd, 8th, 14th, 20th, and 26th rows, which have a remainder of 2 when divided by 6, are respectively replaced with the 6th, 7th, 8th, 9th, and 10th rows, and so on for the replacement.

[0517] Also, according to the column replacement of formula (12), for the columns after the 61st column (parity matrix), the 61st, 67th, 73rd, 79th, and 85th columns, which have a remainder of 1 when divided by 6, are respectively replaced with the 61st, 62nd, 63rd, 64th, and 65th columns, and the 62nd, 68th, 74th, 80th, and 86th columns, which have a remainder of 2 when divided by 6, are respectively replaced with the 66th, 67th, 68th, 69th, and 70th columns, and so on for the replacement.

[0518] In this way, the matrix obtained by performing row and column replacements on the check matrix H in Figure 82 is the check matrix H' in Figure 83.

[0519] Here, even if row replacement of the check matrix H is performed, it does not affect the order of the code bits of the LDPC code.

[0520] Also, the column replacement of formula (12) corresponds to the parity interleaving where the (K + qx + y + 1)-th code bit is interleaved to the position of the (K + Py + x + 1)-th code bit, when the information length K is 60, the parallel factor P is 5, and the divisor q (= M / P) of the parity length M (here, 30) is 6.

[0521] Therefore, the check matrix H' in FIG. 83 is a transformed check matrix obtained by at least performing a column replacement in which the (K + qx + y + 1)-th column of the check matrix H in FIG. 82 (hereinafter, appropriately referred to as the original check matrix) is replaced with the (K + Py + x + 1)-th column.

[0522] When multiplying the LDPC code of the original check matrix H in FIG. 82 by the same replacement as in Equation (12) with respect to the transformed check matrix H' in FIG. 83, a zero vector is output. That is, assuming that the row vector obtained by performing the column replacement of Equation (12) on the row vector c as the LDPC code (one codeword) of the original check matrix H is represented as c', from the properties of the check matrix, Hc T is a zero vector, so H'c' T naturally becomes a zero vector as well.

[0523] From the above, the transformed check matrix H' in FIG. 83 is the check matrix of the LDPC code c' obtained by performing the column replacement of Equation (12) on the LDPC code c of the original check matrix H.

[0524] Therefore, by performing the column replacement of Equation (12) on the LDPC code c of the original check matrix H, decoding (LDPC decoding) the LDPC code c' after the column replacement using the transformed check matrix H' in FIG. 83, and performing the inverse replacement of the column replacement of Equation (12) on the decoding result, it is possible to obtain the same decoding result as when decoding the LDPC code of the original check matrix H using the check matrix H.

[0525] FIG. 84 is a diagram showing the transformed check matrix H' in FIG. 83 with intervals between the units of a 5×5 matrix.

[0526] In FIG. 84, the transformed check matrix H' is a 5×5 (=P×P) identity matrix that is the parallel factor P, a matrix in which one or more of the 1s in the identity matrix become 0 (hereinafter, appropriately referred to as a quasi-identity matrix), a matrix obtained by cyclically shifting the identity matrix or the quasi-identity matrix (hereinafter, appropriately referred to as a shift matrix), a sum of two or more of the identity matrix, the quasi-identity matrix, or the shift matrix (hereinafter, appropriately referred to as a sum matrix), and a combination of a 5×5 zero matrix.

[0527] The conversion check matrix H' in FIG. 84 can be said to be composed of a 5×5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a zero matrix. Therefore, these 5×5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, zero matrix) that make up the conversion check matrix H' are hereinafter appropriately referred to as constituent matrices.

[0528] For decoding an LDPC code of a check matrix represented by a P×P constituent matrix, an architecture that simultaneously performs P check node operations and variable node operations can be used.

[0529] FIG. 85 is a block diagram showing a configuration example of a decoding device that performs such decoding.

[0530] That is, FIG. 85 shows a configuration example of a decoding device that decodes an LDPC code using the conversion check matrix H' in FIG. 84 obtained by performing at least the column permutation of Expression (12) on the original check matrix H in FIG. 82.

[0531] The decoding device in FIG. 85 includes six FIFOs 300 1 to 300 6 constituting a branch data storage memory 300, a selector 301 for selecting FIFOs 300 1 to 300 6 a check node calculation unit 302, two cyclic shift circuits 303 and 308, eighteen FIFOs 304 1 to 304 18 constituting a branch data storage memory 304, a selector 305 for selecting FIFOs 304 1 to 304 18 a reception data memory 306 for storing reception data, a variable node calculation unit 307, a decoded word calculation unit 309, a reception data rearrangement unit 310, and a decoded data rearrangement unit 311.

[0532] First, a method of storing data in the branch data storage memories 300 and 304 will be described.

[0533] The memory 300 for storing branch data is composed of six FIFOs 300, which is the number obtained by dividing the number of rows 30 of the conversion check matrix H' in FIG. 84 by the number of rows of the constituent matrix (parallel factor P) 5. 1 or 300 6 FIFO 300 y (y = 1, 2, ···, 6) consists of a storage area with multiple stages. For each stage of the storage area, messages corresponding to five branches, which are the number of rows and columns of the constituent matrix (parallel factor P), can be read and written simultaneously. Also, the number of stages of the storage area of FIFO 300 y is the maximum number of 1s in the row direction of the conversion check matrix in FIG. 84, which is 9.

[0534] FIFO 300 1 In FIFO 300, data (messages v from variable nodes) corresponding to the positions of 1s from the first row to the fifth row of the conversion check matrix H' in FIG. 84 i ) are stored in a horizontally packed form (ignoring 0s) for each row. That is, if the j-th row and the i-th column are represented as (j, i), in the first-stage storage area of FIFO 300 1 , data corresponding to the positions of 1s in the 5×5 identity matrix from (1, 1) to (5, 5) of the conversion check matrix H' are stored. In the second-stage storage area, data corresponding to the positions of 1s in the shift matrix (a shift matrix obtained by cyclically shifting the 5×5 identity matrix three positions to the right) from (1, 21) to (5, 25) of the conversion check matrix H' are stored. Similarly, data are stored in the third to eighth-stage storage areas in association with the conversion check matrix H'. And in the ninth-stage storage area, data corresponding to the positions of 1s in the shift matrix (a shift matrix obtained by replacing the 1 in the first row of the 5×5 identity matrix with 0 and cyclically shifting one position to the left) from (1, 86) to (5, 90) of the conversion check matrix H' are stored.

[0535] FIFO 300 2 In FIFO 300, data corresponding to the positions of 1s from the sixth row to the tenth row of the conversion check matrix H' in FIG. 84 are stored. That is, in FIFO 300 2In the memory area of the first stage, data corresponding to the positions of 1s in the first shift matrix that constitutes the sum matrix from (6,1) to (10,5) of the conversion check matrix H' (the sum matrix that is the sum of the first shift matrix obtained by cyclically shifting the 5×5 identity matrix to the right by one position and the second shift matrix obtained by cyclically shifting it to the right by two positions) is stored. Also, in the memory area of the second stage, data corresponding to the positions of 1s in the second shift matrix that constitutes the sum matrix from (6,1) to (10,5) of the conversion check matrix H' is stored.

[0536] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is expressed in the form of a sum of a P×P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1s of the elements of the identity matrix become 0, or a plurality of shift matrices obtained by cyclically shifting the identity matrix or the quasi-identity matrix, the data corresponding to the positions of 1s in the identity matrix, quasi-identity matrix, or shift matrix with a weight of 1 (the message corresponding to the branch belonging to the identity matrix, quasi-identity matrix, or shift matrix) is stored in the same address (in the same FIFO among FIFO300 1 to 300 6 ).

[0537] Hereinafter, data is also stored in association with the conversion check matrix H' in the memory areas of the third to ninth stages.

[0538] FIFO300 3 to 300 6 also stores data in association with the conversion check matrix H' in the same manner.

[0539] The branch data storage memory 304 is composed of 18 FIFOs 304 obtained by dividing the number of columns 90 of the conversion check matrix H' by 5, which is the number of columns (parallel factor P) of the constituent matrix. 1 to 304 18 . FIFO304 x (x = 1, 2, ···, 18) consists of memory areas with a plurality of stages, and for each stage of the memory area, messages corresponding to five branches, which are the number of rows and columns (parallel factor P) of the constituent matrix, can be read and written simultaneously.

[0540] FIFO304 1 contains data (message u from the check node) corresponding to the positions of 1s from the first column to the fifth column of the transformation check matrix H' in FIG. 84 j ) are stored in a vertically packed form (ignoring 0s) for each column. That is, in the first storage area of FIFO304 1 , data corresponding to the positions of 1s in the 5×5 identity matrix from (1,1) to (5,5) of the transformation check matrix H' is stored. In the second storage area, data corresponding to the positions of 1s in the first shift matrix that constitutes the sum matrix (the sum matrix that is the sum of the first shift matrix obtained by cyclically shifting the 5×5 identity matrix one position to the right and the second shift matrix obtained by cyclically shifting it two positions to the right) from (6,1) to (10,5) of the transformation check matrix H' is stored. Also, in the third storage area, data corresponding to the positions of 1s in the second shift matrix that constitutes the sum matrix from (6,1) to (10,5) of the transformation check matrix H' is stored.

[0541] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is expressed in the form of a sum of a P×P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1s of the elements of the identity matrix become 0, or a plurality of shift matrices obtained by cyclically shifting the identity matrix or the quasi-identity matrix, the data corresponding to the positions of 1s in the identity matrix, quasi-identity matrix, or shift matrix with a weight of 1 (message corresponding to the branch belonging to the identity matrix, quasi-identity matrix, or shift matrix) is stored at the same address (the same FIFO among FIFO304 1 or 304 18 ).

[0542] Hereinafter, data is also stored in association with the transformation check matrix H' for the fourth and fifth storage areas. The number of stages of the storage area of this FIFO304 1 is 5, which is the maximum number of 1s in the row direction (Hamming weight) in the first column to the fifth column of the transformation check matrix H'.

[0543] FIFO304 2 and 3043 Similarly, data is stored in association with the transformed check matrix H', and the length (number of stages) of each is 5. FIFO304 4 or 304 12 Similarly, data is stored in association with the transformed check matrix H', and the length of each is 3. FIFO304 13 or 304 18 Similarly, data is stored in association with the transformed check matrix H', and the length of each is 2.

[0544] Next, the operation of the decoder shown in FIG. 85 will be described.

[0545] The branch data storage memory 300 includes six FIFOs 300 1 or 300 6 The five messages D311 supplied from the previous cyclic shift circuit 308 are stored in the FIFOs that store data according to the information (Matrix data) D312 indicating which row of the transformed check matrix H' shown in FIG. 84 they belong to. The FIFOs are FIFOs 300 1 or 300 6 The five messages D311 are selected from among them and sequentially stored in the selected FIFO. Also, when reading data, the branch data storage memory 300 reads five messages D300 1 from the FIFOs 300 1 sequentially and supplies them to the next-stage selector 301. After finishing reading the messages from the FIFOs 300 1 the branch data storage memory 300 reads the messages from the FIFOs 300 2 or 300 6 sequentially and supplies them to the selector 301.

[0546] The selector 301 selects five messages from the FIFO from which data is currently being read among the FIFOs 300 1 or 300 6 according to the select signal D301, and supplies them as the message D302 to the check node calculation unit 302.

[0547] The check node calculation unit 302 consists of five check node calculators 302 1 or 302 5 and performs a check node operation according to Equation (7) using the message D302 (D302 1 or D302 5 )(the message v in Equation (7) i ). The five messages D303 (D303 1 or D303 5 )(the message u in Equation (7) j ) obtained as a result of the check node operation are supplied to the cyclic shift circuit 303.

[0548] The cyclic shift circuit 303 cyclically shifts the five messages D303 1 or D303 5 obtained by the check node calculation unit 302 based on the information (Matrix data) D305 indicating how many times the corresponding branch has cyclically shifted the identity matrix (or quasi-identity matrix) that is the basis in the transformed parity-check matrix H', and supplies the result as the message D304 to the branch data storage memory 304.

[0549] The branch data storage memory 304 consists of 18 FIFOs 304 1 or 304 18 and stores data in the FIFO selected from among the FIFOs 304 1 or 304 18 according to the information D305 indicating which row of the transformed parity-check matrix H' the five messages D304 supplied from the previous cyclic shift circuit 303 belong to, and stores the five messages D304 in the selected FIFO in order. Also, when reading data, the branch data storage memory 304 reads the five messages D306 1 from the FIFO 304 1 in order and supplies them to the next-stage selector 305. After finishing reading the data from the FIFO 304 1 , the branch data storage memory 304 reads the data from the FIFO 304 2 or 304 18In order, messages are read out one by one and supplied to the selector 305.

[0550] The selector 305 selects five messages from the FIFO 304 1 or 304 18 from which the current data is being read out, according to the select signal D307, and supplies them as message D308 to the variable node calculation unit 307 and the decoded word calculation unit 309.

[0551] On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the check matrix H in FIG. 82 received through the communication path 13 by performing the column permutation of Equation (12), and supplies it as received data D314 to the received data memory 306. The received data memory 306 calculates and stores the received LLR (log-likelihood ratio) from the received data D314 supplied from the received data rearrangement unit 310, and supplies the received LLR in groups of five as received values D309 to the variable node calculation unit 307 and the decoded word calculation unit 309.

[0552] The variable node calculation unit 307 consists of five variable node calculators 307 1 or 307 5 and performs variable node operations according to Equation (1) using the message D308 (D308 1 or D308 5 )(message u in Equation (1) j ) supplied through the selector 305 and the five received values D309 (received value u in Equation (1) 0i ) supplied from the received data memory 306, and supplies the message D310 (D310 1 or D310 5 )(message v in Equation (1) i ) obtained as a result of the operation to the cyclic shift circuit 308.

[0553] The cyclic shift circuit 308 cyclically shifts the message D310 1 or D310 5Based on the information on how many cyclic shifts are made to the corresponding unit matrix (or quasi-unit matrix) that is the original in the transformed check matrix H', perform a cyclic shift, and supply the result as message D311 to the branch data storage memory 300.

[0554] By performing the above operations once, one decoding (variable node operation and check node operation) of the LDPC code can be performed. The decoding device in Fig. 85 decodes the LDPC code a predetermined number of times, and then obtains and outputs the final decoding result in the decoded word calculation unit 309 and the decoded data rearrangement unit 311.

[0555] That is, the decoded word calculation unit 309 consists of five decoded word calculators 309 1 or 309 5 and uses the five messages D308 (D308 1 or D308 5 ) (message u in Equation (5) j ) output by the selector 305 and the five received values D309 (received value u in Equation (5) 0i ) supplied from the received data memory 306. As the final stage of multiple decodings, based on Equation (5), calculate the decoding result (decoded word), and supply the resulting decoded data D315 to the decoded data rearrangement unit 311.

[0556] The decoded data rearrangement unit 311 rearranges the order of the decoded data D315 supplied from the decoded word calculation unit 309 by performing the inverse permutation of the column permutation in Equation (12), and outputs it as the final decoding result D316.

[0557] As described above, by performing one or both of row permutation and column permutation on the check matrix (original check matrix), and converting it into a check matrix (transformed check matrix) that can be represented by a combination of a P×P identity matrix, a sub-identity matrix in which one or more of the 1s of its elements become 0, a shift matrix obtained by cyclically shifting the identity matrix or the sub-identity matrix, a sum matrix that is a sum of a plurality of the identity matrix, the sub-identity matrix, or the shift matrix, and a P×P zero matrix, i.e., a combination of constituent matrices, it becomes possible to adopt an architecture for LDPC decoding that performs check node operations and variable node operations simultaneously for P at a time, where P is a number smaller than the number of rows or columns of the check matrix. When adopting an architecture that performs node operations (check node operations and variable node operations) simultaneously for P at a time, where P is a number smaller than the number of rows or columns of the check matrix, compared to the case of performing node operations simultaneously for a number equal to the number of rows or columns of the check matrix, the operating frequency can be suppressed within an achievable range, and multiple iterative decodings can be performed.

[0558] The LDPC decoder 166 that constitutes the receiving device 12 in FIG. 79 performs LDPC decoding, for example, in the same manner as the decoding device in FIG. 85, by performing check node operations and variable node operations simultaneously for P at a time.

[0559] That is, for the sake of simplicity in explanation, now assume that the check matrix of the LDPC code output by the LDPC encoder 115 that constitutes the transmitting device 11 in FIG. 8 is, for example, the check matrix H shown in FIG. 82, in which the parity matrix has a staircase structure. Then, in the parity interleaver 23 of the transmitting device 11, a parity interleaving that interleaves the (K + qx + y + 1)-th code bit to the position of the (K + Py + x + 1)-th code bit is performed with the information length K set to 60, the parallel factor P set to 5, and the divisor q (= M / P) of the parity length M set to 6.

[0560] As described above, this parity interleaving corresponds to the column permutation of Equation (12). Therefore, in the LDPC decoder 166, there is no need to perform the column permutation of Equation (12).

[0561] Therefore, in the receiving apparatus 12 of FIG. 79, as described above, from the group-wise deinterleaver 55, an LDPC code for which parity deinterleaving is not performed, that is, an LDPC code in a state where column permutation of Expression (12) has been performed, is supplied to the LDPC decoder 166. In the LDPC decoder 166, except for not performing the column permutation of Expression (12), the same processing as the decoding apparatus of FIG. 85 is performed.

[0562] That is, FIG. 86 is a diagram showing a configuration example of the LDPC decoder 166 of FIG. 79.

[0563] In FIG. 86, the LDPC decoder 166 is configured in the same manner as the decoding apparatus of FIG. 85 except that the received data rearrangement unit 310 of FIG. 85 is not provided. Except for not performing the column permutation of Expression (12), since the same processing as the decoding apparatus of FIG. 85 is performed, the description thereof is omitted.

[0564] As described above, since the LDPC decoder 166 can be configured without providing the received data rearrangement unit 310, the scale can be reduced compared to the decoding apparatus of FIG. 85.

[0565] Note that in FIGS. 82 to 86, for the sake of simplicity of explanation, the code length N of the LDPC code is 90, the information length K is 60, the parallel factor (the number of rows and columns of the parity check matrix) P is 5, and the divisor q (= M / P) of the parity length M is 6. However, each of the code length N, the information length K, the parallel factor P, and the divisor q (= M / P) is not limited to the above-described values.

[0566] That is, in the transmitting apparatus 11 of FIG. 8, for example, the LDPC encoder 115 outputs an LDPC code having a code length N of 64800, 16200, 69120, 17280, etc., an information length K of N - Pq (= N - M), a parallel factor P of 360, and a divisor q of M / P. The LDPC decoder 166 of FIG. 86 is applicable to performing LDPC decoding by simultaneously performing P check node operations and variable node operations on such an LDPC code.

[0567] Also, after decoding the LDPC code by the LDPC decoder 166, when the parity part of the decoding result is unnecessary and only the information bits of the decoding result are output, the LDPC decoder 166 can be configured without the decoding data rearrangement unit 311.

[0568] <Configuration example of block deinterleaver 54>

[0569] FIG. 87 is a diagram for explaining the block deinterleaving performed by the block deinterleaver 54 of FIG. 80.

[0570] In block deinterleaving, the order of the code bits of the LDPC code is restored (recovered) to the original order by performing the reverse process of the block interleaving of the block interleaver 25 described in FIG. 75.

[0571] That is, in block deinterleaving, for example, in the same manner as block interleaving, for m columns equal to the number of bits m of the symbol, by writing and reading the LDPC code, the order of the code bits of the LDPC code is restored to the original order.

[0572] However, in block deinterleaving, the writing of the LDPC code is performed in the order in which the LDPC code is read in block interleaving. Further, in block deinterleaving, the reading of the LDPC code is performed in the order in which the LDPC code is written in block interleaving.

[0573] That is, for part 1 of the LDPC code, as shown in FIG. 87, part 1 of the LDPC code in units of m-bit symbols is written in the row direction from the first row of all m columns. That is, the code bits of the LDPC code that are m-bit symbols are written in the row direction.

[0574] The writing of Part 1 in units of m bits is sequentially performed toward the rows below the m columns. When the writing of Part 1 is completed, as shown in FIG. 87, reading of Part 1 is performed in the downward direction from above the first column unit of the column, toward the columns in the left-to-right direction.

[0575] When the reading up to the rightmost column is completed, as shown in FIG. 87, it returns to the leftmost column, and reading of Part 1 is performed in the downward direction from above the second column unit of the column, toward the columns in the left-to-right direction. Subsequently, in the same manner, reading of Part 1 of the LDPC code of one symbol word is performed.

[0576] When the reading of Part 1 of the LDPC code of one symbol word is completed, for Part 2 which is in units of m-bit symbols, the m-bit symbol units are sequentially concatenated after Part 1. As a result, the LDPC code in symbol units is restored to the order of the code bits of the original LDPC code of one symbol word (the LDCP code before block interleaving).

[0577] <Another configuration example of bit deinterleaver 165>

[0578] FIG. 88 is a block diagram showing another configuration example of the bit deinterleaver 165 in FIG. 79.

[0579] In the figure, parts corresponding to those in the case of FIG. 80 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate below.

[0580] That is, the bit deinterleaver 165 in FIG. 88 is configured in the same manner as in the case of FIG. 80, except that a parity deinterleaver 1011 is newly provided.

[0581] In FIG. 88, the bit deinterleaver 165 is composed of a block deinterleaver 54, a group-wise deinterleaver 55, and a parity deinterleaver 1011, and performs bit deinterleaving of the code bits of the LDPC code from the demapper 164.

[0582] That is, the block deinterleaver 54 performs a block deinterleaving (a process inverse to the block interleaving) corresponding to the block interleaving performed by the block interleaver 25 of the transmission device 11 on the LDPC code from the demapper 164, that is, a block deinterleaving that returns the positions of the code bits swapped by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0583] The group-wise deinterleaver 55 performs a group-wise deinterleaving corresponding to the group-wise interleaving as the rearrangement process performed by the group-wise interleaver 24 of the transmission device 11 on the LDPC code from the block deinterleaver 54.

[0584] The LDPC code obtained as a result of the group-wise deinterleaving is supplied from the group-wise deinterleaver 55 to the parity deinterleaver 1011.

[0585] The parity deinterleaver 1011 performs a parity deinterleaving (a process inverse to the parity interleaving) corresponding to the parity interleaving performed by the parity interleaver 23 of the transmission device 11 on the code bits after the group-wise deinterleaving in the group-wise deinterleaver 55, that is, a parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by the parity interleaving to their original order.

[0586] The LDPC code obtained as a result of the parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.

[0587] Therefore, in the bit deinterleaver 165 of FIG. 88, the LDPC decoder 166 is supplied with an LDPC code in which block deinterleaving, group-wise deinterleaving, and parity deinterleaving have been performed, that is, an LDPC code obtained by LDPC encoding according to the check matrix H.

[0588] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the check matrix H that the LDPC encoder 115 of the transmission device 11 used for LDPC encoding.

[0589] That is, for the type B method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the check matrix H itself (of the type B method) that the LDPC encoder 115 of the transmission device 11 used for LDPC encoding, or a transformed check matrix obtained by performing at least column permutation corresponding to parity deinterleaving on the check matrix H. Also, for the type A method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a check matrix (FIG. 28) obtained by performing column permutation on the check matrix (FIG. 27) of the type A method that the LDPC encoder 115 of the transmission device 11 used for LDPC encoding, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the check matrix (FIG. 27) used for LDPC encoding.

[0590] Here, in FIG. 88, since the LDPC code obtained by LDPC encoding according to the check matrix H is supplied from the bit deinterleaver 165 (parity deinterleaver 1011 thereof) to the LDPC decoder 166, when performing LDPC decoding of the LDPC code using the type B check matrix H itself that the LDPC encoder 115 of the transmission device 11 used for LDPC encoding, or a check matrix (FIG. 28) obtained by performing column permutation on the type A check matrix (FIG. 27) used for LDPC encoding, the LDPC decoder 166 can be configured by, for example, a decoding device that performs LDPC decoding by a full serial decoding method that sequentially performs operations on messages (check node messages, variable node messages) one node at a time, or a decoding device that performs LDPC decoding by a full parallel decoding method that performs operations on messages simultaneously (in parallel) for all nodes.

[0591] Also, in the LDPC decoder 166, when performing LDPC decoding of the LDPC code using a transformed check matrix obtained by performing at least column permutation corresponding to parity interleaving on the type B check matrix H that the LDPC encoder 115 of the transmission device 11 used for LDPC encoding, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the type A check matrix (FIG. 27) used for LDPC encoding, the LDPC decoder 166 is a decoding device with an architecture that simultaneously performs P (or a divisor other than 1 of P) check node operations and variable node operations, and has a received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing the same column permutation as the column permutation for obtaining the transformed check matrix (parity interleaving) on the LDPC code, and can be configured by the decoding device (FIG. 85).

[0592] In FIG. 88, for the sake of convenience of explanation, the block deinterleaver 54 that performs block deinterleaving, the groupwise deinterleaver 55 that performs groupwise deinterleaving, and the parity deinterleaver 1011 that performs parity deinterleaving are each configured separately. However, two or more of the block deinterleaver 54, the groupwise deinterleaver 55, and the parity deinterleaver 1011 can be integrally configured in the same manner as the parity deinterleaver 23, the groupwise deinterleaver 24, and the block deinterleaver 25 of the transmission device 11.

[0593] <Configuration example of reception system>

[0594] FIG. 89 is a block diagram showing a first configuration example of a reception system to which the reception device 12 can be applied.

[0595] In FIG. 89, the reception system is composed of an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.

[0596] The acquisition unit 1101 acquires a signal including an LDPC code obtained by at least LDPC-encoding LDPC target data such as program image data and audio data, via a transmission path (communication path), not shown, such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, or other networks, and supplies it to the transmission path decoding processing unit 1102.

[0597] Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station via terrestrial waves, satellite waves, a CATV (Cable Television) network, etc., the acquisition unit 1101 is composed of a tuner, a STB (Set Top Box), etc. Also, when the signal acquired by the acquisition unit 1101 is transmitted by multicast like IPTV (Internet Protocol Television) from a web server, for example, the acquisition unit 1101 is composed of a network I / F (Interface) such as a NIC (Network Interface Card).

[0598] The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs transmission path decoding processing including at least processing for correcting errors occurring in the transmission path on the signal acquired by the acquisition unit 1101 via the transmission path, and supplies the resulting signal to the information source decoding processing unit 1103.

[0599] That is, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by at least performing error correction coding for correcting errors occurring in the transmission path, and the transmission path decoding processing unit 1102 performs transmission path decoding processing such as error correction processing on such a signal.

[0600] Here, examples of error correction coding include LDPC coding and BCH coding. Here, at least LDPC coding is performed as error correction coding.

[0601] Also, transmission path decoding processing may include demodulation of a modulation signal, etc.

[0602] The information source decoding processing unit 1103 performs information source decoding processing including at least processing for expanding the compressed information into the original information on the signal on which the transmission path decoding processing has been performed.

[0603] That is, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression encoding for compressing information in order to reduce the amount of data such as images and voices as information. In that case, the information source decoding processing unit 1103 performs information source decoding processing such as a process (expansion process) of expanding the compressed information into the original information on the signal subjected to the transmission path decoding processing.

[0604] Note that when the signal acquired by the acquisition unit 1101 via the transmission path is not subjected to compression encoding, the information source decoding processing unit 1103 does not perform a process of expanding the compressed information into the original information.

[0605] Here, examples of the expansion process include MPEG decoding and the like. In addition to the expansion process, the transmission path decoding process may include descrambling and the like.

[0606] In the receiving system configured as described above, in the acquisition unit 1101, for example, data such as images and voices is subjected to compression encoding such as MPEG encoding, and further, a signal subjected to error correction encoding such as LDPC encoding is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.

[0607] In the transmission path decoding processing unit 1102, for example, the same processing as that performed by the receiving device 12 is performed as the transmission path decoding processing on the signal from the acquisition unit 1101, and the resulting signal is supplied to the information source decoding processing unit 1103.

[0608] In the information source decoding processing unit 1103, information source decoding processing such as MPEG decoding is performed on the signal from the transmission path decoding processing unit 1102, and the resulting image or voice is output.

[0609] The receiving system of FIG. 89 as described above can be applied to, for example, a television tuner that receives television broadcasts as digital broadcasts.

[0610] Note that the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as one independent device (hardware (such as an IC (Integrated Circuit)), or a software module).

[0611] Also, regarding the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, or a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device.

[0612] FIG. 90 is a block diagram showing a second configuration example of a reception system to which the reception device 12 can be applied.

[0613] Note that in the figure, parts corresponding to those in FIG. 89 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate below.

[0614] The reception system of FIG. 90 is common with the case of FIG. 89 in that it has the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, and is different from the case of FIG. 89 in that the output unit 1111 is newly provided.

[0615] The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs sound, and outputs an image, sound, etc. as a signal output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs sound.

[0616] The reception system of FIG. 90 as described above can be applied to, for example, a TV (television receiver) that receives television broadcasts as digital broadcasts, a radio receiver that receives radio broadcasts, and the like.

[0617] In addition, when the signal acquired by the acquisition unit 1101 is not compression-encoded, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111.

[0618] FIG. 91 is a block diagram showing a third configuration example of a reception system to which the receiving device 12 can be applied.

[0619] In the figure, parts corresponding to those in FIG. 89 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate below.

[0620] The reception system in FIG. 91 is common to the case of FIG. 89 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.

[0621] However, the reception system in FIG. 91 is different from the case of FIG. 89 in that an information source decoding processing unit 1103 is not provided and a recording unit 1121 is newly provided.

[0622] The recording unit 1121 records (stores) the signal output by the transmission path decoding processing unit 1102 (for example, a TS packet of MPEG TS) in a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory.

[0623] The reception system in FIG. 91 as described above can be applied to a recorder or the like that records television broadcasts.

[0624] In FIG. 91, the reception system can be configured to include an information source decoding processing unit 1103, and the recording unit 1121 can record the signal after the information source decoding processing is performed by the information source decoding processing unit 1103, that is, the image and sound obtained by decoding.

[0625] <An Embodiment of a Computer>

[0626] Next, the above-described series of processes can be performed either by hardware or by software. When the series of processes is performed by software, the program constituting the software is installed in a general-purpose computer or the like.

[0627] Therefore, FIG. 92 shows a configuration example of an embodiment of a computer in which a program for executing the above-described series of processes is installed.

[0628] The program can be pre-recorded in a hard disk 705 or a ROM 703 as a recording medium built into the computer.

[0629] Alternatively, the program can be temporarily or permanently stored (recorded) in a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. Such a removable recording medium 711 can be provided as so-called package software.

[0630] In addition to installing the program from the removable recording medium 711 as described above into the computer, the program can be wirelessly transferred to the computer via an artificial satellite for digital satellite broadcasting from a download site, or can be transferred to the computer by wire via a network such as a LAN (Local Area Network) or the Internet. In the computer, the program transferred in such a manner is received by the communication unit 708 and installed in the built-in hard disk 705.

[0631] The computer incorporates a CPU (Central Processing Unit) 702. An input / output interface 710 is connected to the CPU 702 via a bus 701. When a command is input by a user operating an input unit 707 composed of a keyboard, a mouse, a microphone, etc. via the input / output interface 710, the CPU 702 executes a program stored in a ROM (Read Only Memory) 703 accordingly. Alternatively, the CPU 702 loads a program stored in a hard disk 705, a program transferred from a satellite or a network, received by a communication unit 708 and installed in the hard disk 705, or a program read from a removable recording medium 711 mounted on a drive 709 and installed in the hard disk 705 into a RAM (Random Access Memory) 704 and executes it. Thereby, the CPU 702 performs the processing according to the above-described flowchart or the processing performed according to the configuration of the above-described block diagram. Then, the CPU 702 outputs the processing result from an output unit 706 composed of an LCD (Liquid Crystal Display), a speaker, etc. via an input / output interface 710, transmits it from the communication unit 708, or records it in the hard disk 705 as necessary.

[0632] Here, in this specification, the processing steps for describing a program for causing a computer to perform various processes do not necessarily need to be processed in time series in the order described as a flowchart, and also include processes executed in parallel or individually (for example, parallel processing or object-based processing).

[0633] Also, the program may be processed by one computer or may be processed distributively by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.

[0634] Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0635] For example, the above-described new LDPC code (inspection matrix initial value table) and GW pattern can be used for satellite lines, terrestrial waves, cables (wired lines), and other communication paths 13 (FIG. 7). Further, the new LDPC code and GW pattern can also be used for data transmission other than digital broadcasting.

[0636] Note that the effects described in this specification are merely illustrative and not limiting, and there may be other effects.

Explanation of Signs

[0637] 11 Transmitting device, 12 Receiving device, 23 Parity interleaver, 24 Group-wise interleaver, 25 Block interleaver, 54 Block deinterleaver, 55 Group-wise deinterleaver, 111 Mode adaptation / multiplexer, 112 Padder, 113 BB scrambler, 114 BCH encoder, 115 LDPC encoder, 116 Bit interleaver, 117 Mapper, 118 Time interleaver, 119 SISO / MISO encoder, 120 Frequency interleaver, 121 BCH encoder, 122 LDPC encoder, 123 Mapper, 124 Frequency interleaver, 131 Frame builder / resource allocation unit 132 OFDM generation unit, 151 OFDM processing unit, 152 Frame management unit, 153 Frequency deinterleaver, 154 Demapper, 155 LDPC decoder, 156 BCH decoder, 161 Frequency deinterleaver, 162 SISO / MISO decoder, 163 Time deinterleaver, 164 Demapper, 165 Bit deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 Null deletion unit, 170 Demultiplexer, 300 Branch data storage memory, 301 Selector, 302 Check node calculation unit, 303 Cyclic shift circuit, 304 Branch data storage memory, 305 Selector, 306 Received data memory, 307 Variable node calculation unit, 308 Cyclic shift circuit, 309 Decoded word calculation unit, 310 Received data rearrangement unit, 311 Decoded data rearrangement unit, 601 Encoding processing unit, 602 Storage unit, 611 Encoding rate setting unit, 612 Initial value table reading unit, 613 Check matrix generation unit, 614 Information bit reading unit, 615 Encoded parity operation unit, 616 Control unit, 701 Bus, 702 CPU, 703 ROM, 704 RAM, 705 Hard disk, 706 Output unit, 707 Input unit, 708 Communication unit, 709 Drive, 710 Input / output interface, 711, Removable recording medium, 1001 Reverse swapping unit, 1002 Memory,1011 parity day interleaver, 1101 acquisition unit, 1101 transmission path decoding processing unit, 1103 information source decoding processing unit, 1111 output unit, 1121 recording unit,

Claims

1. A transmitting device including an encoding unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 14 / 16; A receiving device including a decoding unit that decodes the LDPC code; Equipped with The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix section is represented by a parity check matrix initial value table; The parity check matrix initial value table is a table representing the position of an element of 1 in the information matrix section for every 360 columns, 337 376 447 504 551 864 872 975 1136 1225 1254 1271 1429 1478 1870 2122 58 121 163 365 515 534 855 889 1083 1122 1190 1448 1476 1635 1691 1954 247 342 395 454 479 665 674 1033 1041 1198 1300 1484 1680 1941 2096 2121 80 487 500 513 661 970 1038 1095 1109 1133 1416 1545 1696 1992 2051 2089 32 101 205 413 568 712 714 944 1329 1669 1703 1826 1904 1908 2014 2097 142 201 491 838 860 954 960 965 997 1027 1225 1488 1502 1521 1737 1804 453 1184 1542 10 781 1709 497 903 1546 1080 1640 1861 1198 1616 1817 771 978 2089 369 1079 1348 980 1788 1987 1495 1900 2015 27 540 1070 200 1771 1962 863 988 1329 674 1321 2152 807 1458 1727 844 867 1628 227 546 1027 408 926 1413 361 982 2087 1247 1288 1392 1051 1070 1281 325 452 467 1116 1672 1833 21 236 1267 504 856 2123 398 775 1912 1056 1529 1701 143 930 1186 553 1029 1040 303 653 1308 877 992 1174 1083 1134 1355 298 404 709 970 1272 1799 296 1017 1873 105 780 1418 682 1247 1867 is Transmitting and receiving system.

2. A coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 14 / 16; a decoding step of decoding the LDPC code; Equipped with The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix section is represented by a parity check matrix initial value table; The parity check matrix initial value table is a table representing the position of an element of 1 in the information matrix section for every 360 columns, 337 376 447 504 551 864 872 975 1136 1225 1254 1271 1429 1478 1870 2122 58 121 163 365 515 534 855 889 1083 1122 1190 1448 1476 1635 1691 1954 247 342 395 454 479 665 674 1033 1041 1198 1300 1484 1680 1941 2096 2121 80 487 500 513 661 970 1038 1095 1109 1133 1416 1545 1696 1992 2051 2089 32 101 205 413 568 712 714 944 1329 1669 1703 1826 1904 1908 2014 2097 142 201 491 838 860 954 960 965 997 1027 1225 1488 1502 1521 1737 1804 453 1184 1542 10 781 1709 497 903 1546 1080 1640 1861 1198 1616 1817 771 978 2089 369 1079 1348 980 1788 1987 1495 1900 2015 27 540 1070 200 1771 1962 863 988 1329 674 1321 2152 807 1458 1727 844 867 1628 227 546 1027 408 926 1413 361 982 2087 1247 1288 1392 1051 1070 1281 325 452 467 1116 1672 1833 21 236 1267 504 856 2123 398 775 1912 1056 1529 1701 143 930 1186 553 1029 1040 303 653 1308 877 992 1174 1083 1134 1355 298 404 709 970 1272 1799 296 1017 1873 105 780 1418 682 1247 1867 is Sending and receiving methods.

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