Light-emitting diode display device and driving method thereof

Abstract

The present invention provides an LED display device including: a display panel including a number of pixels; a light emitting diode arranged in each of the number of pixels; a first transistor connected between the light emitting diode and a high potential voltage for emitting light, the first transistor being one of N-type and P-type; and a second transistor connected between the light emitting diode and a low potential voltage for emitting light, the second transistor being the other of N-type and P-type.

Description

Technical Field

[0001] The present invention relates to a light emitting diode display device, and more particularly to a light emitting diode display device including a pixel having an N-type transistor and a P-type transistor, and a driving method thereof.

Background Art

[0002] An organic light emitting diode display device or a micro light emitting diode display device can save manufacturing costs by configuring a pixel with one type of transistor out of an N-type transistor and a P-type transistor. However, there is a problem that there is room for characteristic changes due to changes in the power supply voltage and other restrictions on other operations.

[0003] FIG. 1 is a drawing illustrating one pixel of an organic light emitting diode display device according to a conventional first example, and FIG. 2 is a waveform diagram illustrating signals used in the organic light emitting diode display device according to the conventional first example.

[0004] As illustrated in FIG. 1, one pixel P of an organic light emitting diode display device according to a conventional first example includes P-type first to seventh transistors M1 to M7, a first capacitor C1, and a light emitting diode Del.

[0005] The first transistor M1 switches the connection between the high potential voltage EVDD and the first capacitor C1 and the second and fourth transistors M2 and M4 by the emission signal EM, and the second transistor M2 switches the connection between the data signal DATA and the first and fourth transistors M1 and M4 by the N-th gate signal GATE(N).

[0006] The third transistor M3 switches the connection between the first capacitor C1, the fourth and fifth transistors M4, M5, and the initialization voltage VINT and the seventh transistor M7 by the (N - 1)-th gate signal GATE(N - 1). The fourth transistor M4 switches the connection between the first and second transistors M1, M2 and the fifth and sixth transistors M5, M6 by the voltage at the connection node of the first capacitor C1, the third and fifth transistors M3, M5.

[0007] The fifth transistor M5 switches the connection between the first capacitor C1, the third and fourth transistors M3, M4 and the fourth and sixth transistors M4, M6 by the N-th gate signal GATE(N). The sixth transistor M6 switches the connection between the fourth and fifth transistors M4, M5 and the light-emitting diode Del by the light-emitting signal EM.

[0008] The seventh transistor M7 switches the connection between the initialization voltage VINT, the third transistor M3 and the light-emitting diode Del by the N-th gate signal GATE(N).

[0009] The first electrode of the first capacitor C1 is connected to the high-potential voltage EVDD and the first transistor M1. The second electrode of the first capacitor C1 is connected to the third, fourth and fifth transistors M3, M4, M5.

[0010] The positive electrode of the light-emitting diode Del is connected to the sixth and seventh transistors M6, M7. The negative electrode of the light-emitting diode Del is connected to the low-potential voltage EVSS.

[0011] As shown in FIG. 2, the data signal DATA has a valid interval for each frame. The (N - 1)th gate signal GATE(N - 1) has a low level during the initialization interval Tin corresponding to the valid interval of the previous frame of the data signal DATA. The Nth gate signal GATE(N) has a low level during the sensing and programming interval Tsp corresponding to the valid interval of the current frame of the data signal DATA. The emission signal EM has a low level during the emission interval Tem corresponding to after the valid interval of the next frame of the data signal DATA.

[0012] Accordingly, during the initialization interval Tin, the third transistor M3 is turned on and the initialization voltage VINT is charged to the first capacitor C1.

[0013] During the sensing and programming interval Tsp, the second transistor M2 is turned on and the data signal DATA is applied to the source of the fourth transistor M4. The fifth transistor M5 is turned on and the data signal DATA and the threshold voltage of the fourth transistor M4 are charged to the first capacitor C1. The seventh transistor M7 is turned on and the initialization voltage VINT is applied to the light emitting diode Del.

[0014] During the emission interval Tem, the first transistor M1 is turned on and the high potential voltage EVDD is applied to the source of the fourth transistor M4. The sixth transistor M6 is turned on and the current corresponding to the data signal DATA is supplied to the light emitting diode Del, and the light emitting diode Del emits light corresponding to the data signal DATA.

[0015] However, since the pixel P operates with reference to the high potential voltage EVDD, when there is a variation in the high potential voltage EVDD supplied to each pixel P of the display panel, the current flowing through the fourth transistor M4, which is a driving transistor, changes, and the luminance of the light displayed by each pixel P can be changed, and the overall luminance characteristics can be changed depending on the average luminance of the display panel and the video form.

[0016] Such non-uniformity in emission luminance may not be easily recognized by a user in a single display panel. However, when two or more display panels are connected to form a single large display system, such as in a tiled display device, there is a problem in that the luminance difference between the display panels appears as a defect that is recognized by the user in the form of planar non-uniformity.

[0017] FIG. 3 is a drawing illustrating one pixel of an organic light-emitting diode display device according to a conventional second example.

[0018] As shown in FIG. 3, one pixel P of an organic light-emitting diode display device according to a conventional second example includes N-type first to third transistors M1 to M3, a first capacitor C1, and a light-emitting diode Del.

[0019] The gate of the first transistor M1, the source of the second transistor M2, and the first electrode of the first capacitor C1 are connected to each other to form a first node N1. The source of the first transistor M1, the source of the third transistor M3, the second electrode of the first capacitor C1, and the anode of the light-emitting diode Del are connected to each other to form a second node N2.

[0020] The first transistor M1 switches the connection between the high-potential voltage EVDD and the second node N2 according to the voltage of the first node N1, and the second transistor M2 switches the connection between the data signal DATA and the first node N1 according to the gate signal GATE.

[0021] The third transistor M3 switches the connection between the reference voltage VREF and the second node N2 according to the reference signal REF.

[0022] The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode of the first capacitor C1 is connected to the second node N2.

[0023] The anode of the light-emitting diode Del is connected to the second node N2, and the cathode of the light-emitting diode Del is connected to the low-potential voltage EVSS.

[0024] Accordingly, between the intervals in which the gate signal GATE and the reference signal REF each have a high level, the second transistor M2 is turned on and the data signal DATA is applied to the first node N1, the third transistor M3 is turned on and the reference voltage VREF is applied to the second node N2, and the data signal DATA and the reference voltage VREF are input to the first and second electrodes of the first capacitor C1, respectively.

[0025] Between the intervals in which the gate signal GATE and the reference signal REF each have a low level, the second and third transistors M2 and M3 are each turned off and the voltage of the first node N1 is boosted to correspond to the threshold voltage, but the degree of boosting varies depending on the level of the low potential voltage EVSS and luminance unevenness may occur.

[0026] That is, when fluctuations occur in the low potential voltage EVSS supplied to each pixel P of the display panel, the current flowing through the first transistor M1, which is a driving transistor, changes and the luminance of the light displayed by each pixel P can be changed, and the overall luminance characteristics can be changed depending on the average luminance and video form of the display panel.

[0027] Such unevenness in emission luminance may not be easily recognized by the user in a single display panel, but when two or more display panels are connected to form a single large display system such as a tiled display device, there is a problem that the luminance difference between the display panels appears as a defect that is recognized by the user in the form of planar unevenness.

[0028] FIG. 4 is a drawing illustrating a conventional large display system.

[0029] As shown in FIG. 4, the conventional large display system includes a number of light emitting diode display panels arranged in a 3*3 matrix in the first to third panel rows PR1 to PR3 and the first to third panel columns PC1 to PC3.

[0030] When the current of the driving transistor changes due to fluctuations in the high potential voltage EVDD or the low potential voltage EVSS, although non-uniformity in emission luminance may not be recognized in a single light-emitting diode display panel, in a large number of two-dimensionally tiled light-emitting diode display panels, non-uniformity in emission luminance may be recognized as a defect such as planar non-uniformity.

Summary of the Invention

Problems to be Solved by the Invention

[0031] The present invention has been devised to solve the above problems, and by connecting a current source transistor and a source follower transistor to the positive electrode and the negative electrode of the light-emitting diode, respectively, a uniform current is supplied to the light-emitting diode even when the power supply voltage fluctuates, and the object is to provide a light-emitting diode display device and a driving method thereof in which the uniformity of emission luminance is improved.

[0032] And, the present invention aims to provide a light-emitting diode display device and a driving method thereof in which the defective detection ability in the manufacturing process is improved, defects are easily repaired, and manufacturing costs are reduced by connecting test transistors to the positive electrode and the negative electrode of the light-emitting diode.

Means for Solving the Problems

[0033] To achieve the above object, the present invention provides a light-emitting diode display device including a display panel including a large number of pixels; light-emitting diodes arranged in each of the large number of pixels; at least one current source connected between the light-emitting diode and a light-emitting high potential voltage or between the light-emitting diode and a light-emitting low potential voltage; and a control circuit unit that supplies a control signal to the at least one current source.

[0034] And, the at least one current source may include a first transistor that is connected between the light-emitting diode and the light-emitting high potential voltage and is one of an N-type and a P-type, and a second transistor that is connected between the light-emitting diode and the light-emitting low potential voltage and is the other of the N-type and the P-type.

[0035] Further, the control circuit unit may include a latch connected between a digital high potential voltage and a digital low potential voltage and generating first and second output signals using video data and a programming signal; and a level shifter connected between a pin high potential voltage and a pin low potential voltage and generating third and fourth output signals for switching the first and second transistors respectively using the first and second output signals.

[0036] The latch includes a P-type first digital transistor that switches the transmission of the first output signal by the programming signal; an N-type second digital transistor that switches the transmission of the video data by the programming signal; an N-type third digital transistor that switches the transmission of the digital low potential voltage by a reset signal; a P-type fourth digital transistor that switches the transmission of the digital high potential voltage by the first output signal or the digital low potential voltage; an N-type fifth digital transistor that switches the transmission of the digital low potential voltage by the first output signal or the digital low potential voltage; a P-type sixth digital transistor that switches the transmission of the digital high potential voltage by the second output signal; and an N-type seventh digital transistor that switches the transmission of the digital low potential voltage by the second output signal. The level shifter may include a P-type eighth digital transistor that switches the transmission of the pin high potential voltage by the third output signal; an N-type ninth digital transistor that switches the transmission of the pin low potential voltage by the first output signal; a P-type tenth digital transistor that switches the transmission of the pin high potential voltage by the fourth output signal; and an N-type eleventh digital transistor that switches the transmission of the pin low potential voltage by the fourth output signal.

[0037] The control circuit unit is also connected between the pin high potential voltage and the pin low potential voltage, and includes an integrated level shifter that generates first and second output signals for switching the first and second transistors respectively using video data, a programming signal, and a light emission signal. The integrated level shifter includes an N-type first digital transistor that switches the transmission of the first output signal according to the light emission signal; a P-type second digital transistor that switches the transmission of the first output signal according to the programming signal; an N-type third digital transistor that switches the transmission of the video data according to the programming signal; a P-type fourth digital transistor that switches the transmission of the pin high potential voltage according to the first output signal or the video data; an N-type fifth digital transistor that switches the transmission of the pin low potential voltage according to the first output signal or the video data; a P-type sixth digital transistor that switches the transmission of the pin high potential voltage according to the light emission signal; a P-type seventh digital transistor that switches the transmission of the pin high potential voltage according to the second output signal; and an N-type eighth digital transistor that switches the transmission of the pin low potential voltage according to the second output signal.

[0038] The light emitting diode display device further includes a third transistor connected between the positive and negative electrodes of the light emitting diode. The first and third transistors may be N-type, and the second transistor may be P-type.

[0039] The control circuit unit may also include an N-type fourth transistor that switches the connection between the first data signal and the gate of the first transistor according to a first programming signal; an N-type fifth transistor that switches the connection between the second data signal and the source of the first transistor according to a second programming signal; and a first capacitor connected between the gate and the source of the first transistor.

[0040] The control circuit unit may include an N-type fourth transistor that switches the connection between the first data signal and the gate of the first transistor by a programming signal; an N-type fifth transistor that switches the connection between the second data signal and the source of the first transistor by the programming signal; and a first capacitor connected between the gate and the source of the first transistor.

[0041] Alternatively, the control circuit unit may include an N-type fourth transistor that switches the connection between the data signal and the gate of the first transistor by a programming signal; an N-type fifth transistor that switches the connection between the reference signal and the source of the first transistor by a sense signal; and a first capacitor connected between the gate of the first transistor and the drain of the fifth transistor.

[0042] The control circuit unit is connected between the pin high potential voltage and the pin low potential voltage, and includes a level shifter that generates first and second output signals using first and second video data, a programming signal, and an enable signal; and a latch that is connected between the pin high potential voltage and the pin low potential voltage and generates third and fourth output signals for switching the first and second transistors using the first and second output signals. The level shifter includes a first digital transistor that switches the connection between the pin high potential voltage and the drain of a third digital transistor by the first output signal; a second digital transistor that switches the connection between the pin high potential voltage and the drain of a fourth digital transistor by the second output signal; a third digital transistor that switches the connection between the drain of the first digital transistor and the drain of a ninth digital transistor by the first output signal; a fourth digital transistor that switches the connection between the drain of the second digital transistor and the drain of the ninth digital transistor by the second output signal; a fifth digital transistor that switches the connection between the drain of the first digital transistor and the drain of the ninth digital transistor by the voltage of the first electrode of a first capacitor; a sixth digital transistor that switches the connection between the drain of the second digital transistor and the drain of the ninth digital transistor by the voltage of the first electrode of a second capacitor; a seventh digital transistor that switches the connection between the first video data and the gate of the fifth digital transistor by the programming signal; an eighth digital transistor that switches the connection between the second video data and the gate of the sixth digital transistor by the programming signal; a ninth digital transistor that switches the connection between the sources of the third to sixth digital transistors and the pin low potential voltage by the enable signal; the first capacitor connected between the source of the seventh digital transistor and the pin low potential voltage; and the second capacitor connected between the source of the eighth digital transistor and the pin low potential voltage can be included.

[0043] Further, the control circuit unit includes a level shifter connected between the pin high potential voltage and the pin low potential voltage, which generates an output signal using video data, a programming signal, and a precharge signal; and a latch connected between the pin high potential voltage and the pin low potential voltage, which generates third and fourth output signals for switching the first and second transistors respectively using the output signal. The level shifter includes a first digital transistor that switches the connection between the pin high potential voltage and the drain of a third digital transistor by the precharge signal; a second digital transistor that switches the connection between the pin high potential voltage and the drain of a fourth digital transistor by the voltage of the first electrode of the second capacitor; a third digital transistor that switches the connection between the drain of the first digital transistor and the drain of a sixth digital transistor by the precharge; a fourth digital transistor that switches the connection between the drain of the second digital transistor and the pin low potential voltage by the voltage of the first electrode of the second capacitor; a fifth digital transistor that switches the connection between the video data and the gate of the sixth digital transistor by the programming signal; a sixth digital transistor that switches the connection between the source of the third digital transistor and the pin low potential voltage by the voltage of the first electrode of the first capacitor; a first capacitor connected between the source of the fifth digital transistor and the pin low potential voltage; and a second capacitor connected between the gate of the second digital transistor and the pin low potential voltage.

[0044] And, the at least one current source includes a first transistor which is one of N-type and P-type and is connected between the light emitting diode and the light emitting high potential voltage. The light emitting diode display device further includes a third transistor connected between the positive electrode of the light emitting diode and the test voltage, and the negative electrode of the light emitting diode may be connected to the light emitting low potential voltage.

[0045] Further, the control circuit unit may include a latch connected between a digital high potential voltage and a digital low potential voltage and generating first and second output signals using video data and a programming signal; and a level shifter connected between a pin high potential voltage and a pin low potential voltage and generating a third output signal for switching the first transistor using the first and second output signals.

[0046] And the control circuit unit may include an integrated level shifter connected between a pin high potential voltage and a pin low potential voltage and generating a first output signal for switching the first transistor using video data, a programming signal, and a light emission signal.

[0047] Further, the control circuit unit may include an N-type fourth transistor that switches the connection between a first data signal and the gate of the first transistor by a first programming signal; an N-type fifth transistor that switches the connection between a second data signal and the source of the first transistor by a second programming signal; and a first capacitor connected between the gate and the source of the first transistor.

[0048] And the control circuit unit may include an N-type fourth transistor that switches the connection between a first data signal and the gate of the first transistor by a programming signal; an N-type fifth transistor that switches the connection between a second data signal and the source of the first transistor by the programming signal; and a first capacitor connected between the gate and the source of the first transistor.

[0049] Further, the control circuit unit may include an N-type fourth transistor that switches the connection between a data signal and the gate of the first transistor by a programming signal; an N-type fifth transistor that switches the connection between a reference signal and the source of the first transistor by a sense signal; and a first capacitor connected between the gate of the first transistor and the drain of the fifth transistor.

[0050] The control circuit unit includes a latch connected between a digital high potential voltage and a digital low potential voltage and generating first and second output signals using video data and a programming signal; an N-type fourth transistor that switches the connection between the first output signal and the source of the first transistor by a reference signal; an N-type fifth transistor that switches the connection between the second output signal and the gate of the first transistor by the reference signal; a P-type sixth transistor that switches the connection between the light emission high potential voltage and the source of the first transistor by a first light emission signal; an N-type seventh transistor that switches the connection between the drain of the first transistor and the anode of the light emitting diode by a second light emission signal; and a first capacitor connected between the gate and the source of the first transistor.

[0051] The control circuit unit also includes a latch connected between a digital high potential voltage and a digital low potential voltage and generating first and second output signals using video data and a programming signal; an N-type fourth transistor that switches the connection between the first output signal and the gate of the first transistor by a reference signal; an N-type fifth transistor that switches the connection between the second output signal and the source of the first transistor by the reference signal; a P-type sixth transistor that switches the connection between the light emission high potential voltage and the drain of the first transistor by a first light emission signal; an N-type seventh transistor that switches the connection between the source of the first transistor and the anode of the light emitting diode by a second light emission signal; and a first capacitor connected between the gate and the source of the first transistor.

Advantages of the Invention

[0052] According to the present invention, by connecting a current source transistor and a source follower transistor to the anode and the cathode of the light emitting diode respectively, even when the power supply voltage fluctuates, a uniform current is supplied to the light emitting diode, and the uniformity of the light emission luminance is improved.

[0053] And, by connecting a test transistor to the positive and negative electrodes of the light-emitting diode, the present invention has the effect of improving the defect detection ability in the manufacturing process, facilitating the repair of defects, and reducing the manufacturing cost.

Brief Description of the Drawings

[0054]

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Modes for Carrying Out the Invention

[0055] Hereinafter, specific contents of the present invention will be described in detail with reference to the accompanying drawings.

[0056] FIG. 5 is a drawing illustrating a light-emitting diode display device according to the 1st embodiment of the present invention, and FIG. 6 is a drawing illustrating a pixel of the light-emitting diode display device according to the 1st embodiment of the present invention.

[0057] As illustrated in FIGS. 5 and 6, a light-emitting diode display device 110 according to the 1st embodiment of the present invention includes a timing control unit 120, a gate driving unit 130, a data driving unit 140, and a display panel 160.

[0058] The timing control unit 120 receives inputs of a video signal IMS and a number of timing signals DE, HSY, VSY, CLK from an external system such as a TV system or a graphic card, generates video data RGB, a gate control signal GCS, and a data control signal DCS, supplies the generated gate control signal GCS to the gate driving unit 130, and supplies the generated video data RGB and data control signal DCS to the data driving unit 140.

[0059] The gate driving unit 130 generates a number of switching signals such as a gate signal (gate voltage), a sensing signal, and a light emitting signal by using a gate control signal GCS, and supplies the generated number of switching signals to the display panel 160.

[0060] The data driving unit 140 converts video data RGB into data signals (data voltages) by using a data control signal DCS, and supplies the converted data signals to the display panel 160 through data wirings DL.

[0061] The display panel 160 displays an image by using the gate signal and the data signal. For this purpose, the display panel 160 includes a gate wiring GL and a data wiring DL that cross each other to define a pixel P, and a latch (digital storage element) 172, a level shifter 174, first and second transistors M1, M2, and a light emitting diode Del formed in each pixel P.

[0062] The latch 172 of the control circuit unit that supplies a control signal to the current source receives inputs of video data RGB, a programming signal PGM, and a reset signal RS, and outputs first and second output signals by using a digital high potential voltage VCC and a digital low potential voltage VSS, where the first and second output signals can be signals inverted with respect to each other.

[0063] In other embodiments, the reset signal RS can be omitted.

[0064] The level shifter 174 of the control circuit unit that supplies a control signal to the current source receives inputs of the first and second output signals, and outputs third and fourth output signals by using a pin high potential voltage PVDD and a pin low potential voltage PVSS, where the third and fourth output signals can be signals inverted with respect to each other.

[0065] The first transistor M1, which operates as a first current source 182 to cause a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high potential voltage EVDD and the light-emitting diode Del by a third output signal, and the second transistor M2 switches the connection between the light-emitting diode Del and the light-emitting low potential voltage EVSS by a fourth output signal.

[0066] The first transistor M1 has an N type (negative type). The gate of the first transistor M1 is connected to the third output signal of the level shifter 174 to form a first node N1. The drain of the first transistor M1 is connected to the light-emitting high potential voltage EVDD, and the source of the first transistor M1 is connected to the positive electrode of the light-emitting diode Del to form a second node N2.

[0067] The second transistor M2, which operates as a second current source 184 to cause a constant current to flow through the light-emitting diode Del, has a P type (positive type). The source of the second transistor M2 is connected to the negative electrode of the light-emitting diode Del to form a third node N3. The gate of the second transistor M2 is connected to the fourth output signal of the level shifter 174 to form a fourth node N4, and the drain of the second transistor M2 is connected to the light-emitting low potential voltage EVSS.

[0068] The first and second transistors M1, M2 and the light-emitting diode Del constitute the light-emitting portion of each pixel P.

[0069] In such a pixel P, the current level of the light-emitting diode Del is determined by the voltages of the first and fourth nodes N1, N4 and the operating characteristics (L-I-V characteristics) of the light-emitting diode Del.

[0070] That is, the voltage condition in the steady state is expressed as the following formula (1).

[0071] V(N1)-V(N4)=Vgs(M1)+V(Del)+Vsg(M2) --- Formula (1)

[0072] V(N1) is the voltage of the first node N1, V(N4) is the voltage of the fourth node N4, Vgs(M1) is the voltage difference between the gate and the source of the first transistor M1, V(Del) is the voltage difference between the anode and the cathode of the light-emitting diode Del, and Vgs(M2) is the voltage difference between the source and the gate of the second transistor M2.

[0073] When solving Equation (1) for the voltages of the first to fourth nodes N1 to N4, it is expressed as the following Equation (2).

[0074] V(N1) - V(N4) = {V(N1) - V(N2)} + {V(N2) - V(N3)} + {V(N3) - V(4)} --- Equation (2)

[0075] V(N2) is the voltage of the second node N2, and V(N3) is the voltage of the fourth node N4.

[0076] Therefore, since the current level of the light-emitting diode Del is determined by the voltages of the first and fourth nodes N1 and N4 and the operating characteristics of the light-emitting diode Del regardless of the light-emitting high-potential voltage EVDD and the light-emitting low-potential voltage EVSS, when there is no voltage drop due to the DC bypass current in the level shifter 174, the current flowing through the light-emitting diode Del is constant regardless of the brightness of the video.

[0077] That is, when the level shifter 174 outputs the third and fourth output signals using the first and second signals of the latch 172 to which the digital storage concept is applied, the DC bypass current in the level shifter 174 can be prevented. In this case, if the brightness of the video does not exceed the limit value (if the first and second transistors M1 and M2 operating as source followers for light emission operate in the saturation region), the light-emitting diode Del can emit light with a constant brightness.

[0078] Here, the video data RGB input to the latch 172 has a digital type of digital voltage level.

[0079] As described above, in the pixel P of the light-emitting diode display device 110 according to the first embodiment of the present invention, the latch 172 outputs first and second output signals at a constant DC voltage level so that flicker or the like does not occur, and the level shifter 174 applies third and fourth signals necessary for light emission to the gates of the first and fourth transistors M1 and M4, so that a constant current can flow through the light-emitting diode Del regardless of the fluctuations in the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS.

[0080] When the pixel P includes light-emitting diodes Del that emit red light, green light, and blue light, by adjusting the aspect ratios of the first and second transistors M1 and M2, a current reflecting the operating characteristic differences of the red, green, and blue light-emitting diodes Del can be made to flow through the light-emitting diodes Del.

[0081] The latch 172 and the level shifter 174 can be composed of a number of transistors, which will be described with reference to the drawings.

[0082] FIG. 7 is a drawing illustrating a pixel of the light-emitting diode display device according to the first embodiment of the present invention, and FIG. 8 is a waveform diagram illustrating signals used in the pixel of the light-emitting diode display device according to the first embodiment of the present invention, which will be described with reference to both FIGS. 5 and 6.

[0083] As shown in FIG. 7, the pixel P of the light-emitting diode display device 110 according to the first embodiment of the present invention includes a latch 172, a level shifter 174, first and second transistors M1 and M2, and a light-emitting diode Del. The latch 172 includes first to seventh digital transistors Q1 to Q7, the level shifter 174 includes eighth to eleventh digital transistors Q8 to Q11, and the first and second transistors M1 and M2 and the light-emitting diode Del constitute a light-emitting portion.

[0084] The first, fourth, sixth, eighth, and tenth digital transistors Q1, Q4, Q6, Q8, and Q10 are of P-type, and the second, third, fifth, seventh, ninth, and eleventh digital transistors Q2, Q3, Q5, Q7, Q9, and Q11 are of N-type.

[0085] The first digital transistor Q1 switches the connection between the first output signal and the gates of the fourth and fifth digital transistors Q4 and Q5 by a programming signal PGM which is a signal for inputting video data RGB to the latch 172, and the second digital transistor Q2 switches the connection between the video data RGB and the gates of the fourth and fifth digital transistors Q4 and Q5 by the programming signal PGM.

[0086] The third digital transistor Q3 switches the connection between the digital low potential voltage VSS and the gates of the fourth and fifth digital transistors Q4 and Q5 by a reset signal RS which is a signal for resetting the latch 172.

[0087] In other embodiments, the reset signal RS and the third digital transistor Q3 may be omitted.

[0088] The fourth digital transistor Q4 switches the connection between the digital high potential voltage VCC and the second output signal by the first output signal or the digital low potential voltage VSS, and the fifth digital transistor Q5 switches the connection between the digital low potential voltage VSS and the second output signal by the first output signal or the digital low potential voltage VSS.

[0089] The sixth digital transistor Q6 switches the connection between the digital high potential voltage VCC and the first output signal by the second output signal, and the seventh digital transistor Q7 switches the connection between the digital low potential voltage VSS and the second output signal by the second output signal.

[0090] The eighth digital transistor Q8 switches the connection between the pin high potential voltage PVDD and the fourth output signal by the third output signal, and the ninth digital transistor Q9 switches the connection between the pin low potential voltage PVSS and the fourth output signal by the first output signal.

[0091] The tenth digital transistor Q10 switches the connection between the pin high potential voltage PVDD and the third output signal by the fourth output signal, and the eleventh digital transistor Q11 switches the connection between the pin low potential voltage PVSS and the third output signal by the 2 output signal.

[0092] Here, the pin high potential voltage PVDD and the pin low potential voltage PVSS can have voltage levels such that the necessary current flows through the first and second transistors M1, M2 responsible for light emission and the light emitting diode Del, so that the first and second transistors M1, M2 operate in the saturation region and the source follower can operate normally.

[0093] For example, the pin high potential voltage PVDD can be a value greater than the digital high potential voltage VCC and less than the light emission high potential voltage EVDD.

[0094] As shown in FIG. 8, the video data RGB has a valid section for each frame, the reset signal RS has a high level during the reset section Trs corresponding to the valid section of the current frame of the video data RGB, and the programming signal PGM has a high level during the programming section Tpg corresponding to the valid section of the current frame of the video data RGB.

[0095] Accordingly, during the reset section Trs, the first and second output signals of the latch 172 become low (0) and high (1) respectively and are input to the level shifter 174, and the third and fourth output signals of the level shifter 174 become low (0) and high (1) respectively and are transmitted to the first and fourth nodes N1, N4. As a result, the first and second transistors M1, M2 are turned off respectively and the light emitting diode Del does not emit light.

[0096] During the programming period Tpg, the first and second output signals of the latch 172 become high (1) and low (0) respectively and are input to the level shifter 174. The third and fourth output signals of the level shifter 174 become high (1) and low (0) respectively and are transmitted to the first and fourth nodes N1, N4. As a result, the first and second transistors M1, M2 are turned on respectively and the light emitting diode Del emits light.

[0097] That is, the period between the rising point of the reset period Trs and the rising point of the programming period Tpg becomes a non-light emitting period Tne in which the light emitting diode Del does not emit light, and the period between the rising point of the programming period Tpg and the rising point of the reset period Trs of the next frame becomes a light emitting period Tem in which the light emitting diode Del emits light.

[0098] As described above, in the light emitting diode display device 110 according to the first embodiment of the present invention, the first and second transistors M1, M2 are connected to the positive and negative electrodes of the light emitting diode Del respectively, and the latch 172 which is a digital storage element that outputs the first and second output signals of a certain DC voltage level and the level shifter 174 that outputs the third and fourth output signals of the voltage level required for light emission are used to switch the first and second transistors M1, M2, so that a constant current can flow through the light emitting diode Del regardless of the fluctuations of the light emitting high potential voltage EVDD and the light emitting low potential voltage EVSS. As a result, the uniformity of the light emitting luminance can be improved.

[0099] In other embodiments, the reset period may not be used, which will be described with reference to the drawings.

[0100] FIG. 9 is a waveform diagram showing the signals used for the pixel of the light emitting diode display device according to the second embodiment of the present invention, and the description of the same parts as those in the first embodiment is omitted.

[0101] As shown in FIG. 9, the video data RGB has a valid interval for each frame, the reset signal RS has a low level, and the programming signal PGM has a high level during a programming interval Tpg corresponding to the valid interval of the current frame of the video data RGB.

[0102] Accordingly, during the programming interval Tpg, the first and second output signals of the latch 172 become high (1) and low (0), respectively, and are input to the level shifter 174. The third and fourth output signals of the level shifter 174 become high (1) and low (0), respectively, and are transmitted to the first and fourth nodes N1, N4. As a result, the first and second transistors M1, M2 are turned on respectively, and the light emitting diode Del emits light.

[0103] That is, the interval between the rising point of the programming interval Tpg and the rising point of the programming interval Tpg of the next frame becomes a light emitting interval Tem in which the light emitting diode Del emits light.

[0104] As described above, in the light emitting diode display device according to the second embodiment of the present invention, the first and second transistors M1, M2 are connected to the positive and negative electrodes of the light emitting diode Del respectively, and the first and second transistors M1, M2 are switched by using the latch 172 and the level shifter 174, so that a constant current can flow through the light emitting diode Del regardless of the fluctuations of the light emitting high potential voltage EVDD and the light emitting low potential voltage EVSS. As a result, the uniformity of the light emitting luminance can be improved.

[0105] In other embodiments, both ends of the light emitting diode may be connected to test transistors to perform defect detection and repair, which will be described with reference to the drawings.

[0106] FIG. 10 is a drawing showing a pixel of a light emitting diode display device according to a third embodiment of the present invention, and descriptions of the same parts as those in the first and second embodiments are omitted.

[0107] As shown in FIG. 10, the pixel P of the light-emitting diode display device according to the third embodiment of the present invention includes a latch 172, a level shifter 174, first, second, and third transistors M1, M2, M3, and a light-emitting diode Del. The latch 172 includes first to seventh digital transistors Q1 to Q7, the level shifter 174 includes eighth to eleventh digital transistors Q8 to Q11, and the first, second, and third transistors M1, M2, M3 and the light-emitting diode Del constitute a light-emitting unit.

[0108] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high-potential voltage EVDD and the light-emitting diode Del by the third output signal. The second transistor M2, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting diode Del and the light-emitting low-potential voltage EVSS by the fourth output signal. The third transistor M3 switches the connection between the positive and negative electrodes of the light-emitting diode Del by the test signal TE.

[0109] The gate of the N-type first transistor M1 is connected to the third output signal of the level shifter 174 to form a first node N1. The drain of the first transistor M1 is connected to the light-emitting high-potential voltage EVDD, and the source of the first transistor M1 is connected to the positive electrode of the light-emitting diode Del to form a second node N2.

[0110] The source of the P-type second transistor M2 is connected to the negative electrode of the light-emitting diode Del to form a third node N3. The gate of the second transistor M2 is connected to the fourth output signal of the level shifter 174 to form a fourth node N4, and the drain of the second transistor M2 is connected to the light-emitting low-potential voltage EVSS.

[0111] The drain and source of the N-type third transistor M3 are connected to the second and third nodes N2 and N3, respectively, and the gate of the third transistor M3 is connected to the test signal TE.

[0112] The light-emitting diode display device according to the third embodiment of the present invention can operate in a display mode and a test mode.

[0113] In the display mode, the third transistor M3 is turned off, the light-emitting diode Del emits light, and the light-emitting diode display device displays an image.

[0114] In the test mode, the third transistor M3 is turned on, the light-emitting diode Del does not emit light, and defects of the first to eleventh digital transistors Q1 to Q11 of the latch 172 and the level shifter 174 and the first and second transistors M1 and M2 are detected using the video data RGB, the reset signal RS, and the programming signal PGM.

[0115] Here, when the light-emitting diode Del is not connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light-emitting diode Del.

[0116] When the light-emitting diode Del is connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on so that the voltage difference between the second and third nodes N2 and N3 is smaller than the light emission threshold voltage of the light-emitting diode Del to detect the normal operation of elements other than the light-emitting diode Del.

[0117] As described above, in the light-emitting diode display device according to the third embodiment of the present invention, the first and second transistors M1 and M2 are respectively connected to the positive and negative electrodes of the light-emitting diode Del, and the first and second transistors M1 and M2 are switched using the latch 172 and the level shifter 174, so that a constant current can flow through the light-emitting diode Del regardless of fluctuations in the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS, and as a result, the uniformity of the light emission luminance can be improved.

[0118] Then, by connecting the third transistor M3 to the positive and negative electrodes of the light-emitting diode Del and turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0119] In the third embodiment of FIG. 10, an example is given in which the second transistor M2 is connected between the negative electrode of the light-emitting diode Del and the light-emitting low-potential voltage EVSS. However, in other embodiments, the second transistor M2 may be omitted and the negative electrode of the light-emitting diode Del may be directly connected to the light-emitting low-potential voltage EVSS. In this case, the level shifter 174 outputs the third output signal and does not output the fourth output signal, and the source of the third transistor M3 may be connected to the test voltage TM instead of the third node N3, which will be described in detail with reference to FIGS. 14 and 15.

[0120] In other embodiments, the latch and the level shifter may be configured by a single level shifter, which will be described with reference to the drawings.

[0121] FIG. 11 is a drawing illustrating a pixel of a light-emitting diode display device according to a fourth embodiment of the present invention, and FIG. 12 is a waveform diagram illustrating signals used in the pixel of the light-emitting diode display device according to the fourth embodiment of the present invention. Descriptions of the same parts as in the first to third embodiments are omitted.

[0122] As shown in FIG. 11, the pixel P of the light-emitting diode display device according to the fourth embodiment of the present invention includes an integrated level shifter 176, first and second transistors M1 and M2, and a light-emitting diode Del. The first and second transistors M1 and M2 and the light-emitting diode Del constitute a light-emitting unit.

[0123] The integrated level shifter 176 of the control circuit unit that supplies the control signal to the current source receives the inputs of the video data RGB, the programming signal PGM, and the light-emitting signal EM, and outputs the first and second output signals using the pin high-potential voltage PVDD and the pin low-potential voltage PVSS. The first and second output signals may be signals inverted from each other.

[0124] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high-potential voltage EVDD and the light-emitting diode Del by the first output signal, and the second transistor M2, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting diode Del and the light-emitting low-potential voltage EVSS by the second output signal.

[0125] The first transistor M1 has an N type (negative type). The gate of the first transistor M1 is connected to the first output signal of the integrated level shifter 176 to form a first node N1. The drain of the first transistor M1 is connected to the light-emitting high-potential voltage EVDD, and the source of the first transistor M1 is connected to the anode of the light-emitting diode Del to form a second node N2.

[0126] The second transistor M2 has a P type (positive type). The source of the second transistor M2 is connected to the cathode of the light-emitting diode Del to form a third node N3. The gate of the second transistor M2 is connected to the second output signal of the integrated level shifter 176 to form a fourth node N4, and the drain of the second transistor M2 is connected to the light-emitting low-potential voltage EVSS.

[0127] The integrated level shifter 176 includes first to eighth digital transistors Q1 to Q8.

[0128] The second, fourth, sixth, and seventh digital transistors Q2, Q4, Q6, and Q7 have a P type, and the first, third, fifth, and eighth digital transistors Q1, Q3, Q5, and Q8 have an N type.

[0129] The first digital transistor Q1 switches the connection between the first output signal and the gates of the fourth and fifth digital transistors Q4 and Q5 by the light-emitting signal EM, and the second digital transistor Q2 switches the connection between the first output signal and the gates of the fourth and fifth digital transistors Q4 and Q5 by the programming signal PGM.

[0130] The third digital transistor Q3 switches the connection between the video data RGB and the gates of the fourth and fifth digital transistors Q4 and Q5 by the programming signal PGM.

[0131] The fourth digital transistor Q4 switches the connection between the pin high potential voltage PVDD and the second output signal by the first output signal or the video data RGB, and the fifth digital transistor Q5 switches the connection between the pin low potential voltage PVSS and the second output signal by the first output signal or the video data RGB.

[0132] The sixth digital transistor Q6 switches the connection between the pin high potential voltage PVDD and the second output signal by the emission signal EM, the seventh digital transistor Q7 switches the connection between the pin high potential voltage PVDD and the first output signal by the second output signal, and the eighth digital transistor Q8 switches the connection between the pin low potential voltage PVSS and the first output signal by the second output signal.

[0133] Here, the pin high potential voltage PVDD and the pin low potential voltage PVSS can have voltage levels such that the necessary current flows through the first and second transistors M1 and M2 responsible for light emission and the light emitting diode Del, so that the first and second transistors M1 and M2 operate in the saturation region and the source follower can operate normally.

[0134] For example, the pin high potential voltage PVDD can be a value smaller than the light emission high potential voltage EVDD.

[0135] And by adjusting the aspect ratios of the first to eighth digital transistors Q1 to Q8, the integrated level shifter 176 can perform all the functions of changing the voltage of the video data RGB at the levels of the pin high potential voltage PVDD and the pin low potential voltage PVSS and storing the video data RGB.

[0136] As shown in FIG. 12, the video data RGB has a valid interval for each frame, the emission signal EM has a low level during the non-storage interval Tns corresponding to the valid interval of the current frame of the video data RGB, and the programming signal PGM has a high level during the programming interval Tpg corresponding to the valid interval of the current frame of the video data RGB.

[0137] Accordingly, during the non-storage interval Tns, the first and second output signals of the integrated level shifter 176 become low (0) and high (1) respectively and are transmitted to the first and fourth nodes N1, N4. As a result, the first and second transistors M1, M2 are turned off respectively and the light emitting diode Del does not emit light.

[0138] During the programming interval Tpg, the first and second output signals of the integrated level shifter 176 become high (1) and low (0) respectively and are transmitted to the first and fourth nodes N1, N4. As a result, the first and second transistors M1, M2 are turned on respectively and the light emitting diode Del emits light.

[0139] That is, the interval between the falling point of the non-storage interval Tns and the rising point of the programming interval Tpg becomes the non-light emitting interval Tne where the light emitting diode Del does not emit light, and the interval between the rising point of the programming interval Tpg and the falling point of the non-storage interval Tns of the next frame becomes the light emitting interval Tem where the light emitting diode Del emits light.

[0140] And during the interval when the emission signal EM has a high level and the programming signal PGM has a low level, the video data RGB is stored in the integrated level shifter 176.

[0141] As described above, in the light-emitting diode display device according to the fourth embodiment of the present invention, the first and second transistors M1 and M2 are respectively connected to the positive and negative electrodes of the light-emitting diode Del, and the first and second transistors M1 and M2 are switched using the integrated level shifter 176, so that a constant current can flow through the light-emitting diode Del regardless of the fluctuations in the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS. As a result, the uniformity of the light-emitting luminance can be improved.

[0142] In other embodiments, both ends of the light-emitting diode may be connected to test transistors to perform defect detection and repair, which will be described with reference to the drawings.

[0143] FIG. 13 is a drawing showing a pixel of the light-emitting diode display device according to the fifth embodiment of the present invention, and descriptions of the same parts as those in the first to fourth embodiments are omitted.

[0144] As shown in FIG. 13, the pixel P of the light-emitting diode display device according to the fifth embodiment of the present invention includes an integrated level shifter 176, first, second, and third transistors M1, M2, M3, and a light-emitting diode Del. The integrated level shifter 176 includes first to eighth digital transistors Q1 to Q8, and the first, second, and third transistors M1, M2, M3, and the light-emitting diode Del constitute a light-emitting unit.

[0145] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high potential voltage EVDD and the light-emitting diode Del by the first output signal. The second transistor M2, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting diode Del and the light-emitting low potential voltage EVSS by the second output signal. The third transistor M3 switches the connection between the positive and negative electrodes of the light-emitting diode Del by the test signal TE.

[0146] The gate of the N-type first transistor M1 is connected to the first output signal of the integrated level shifter 176 to form a first node N1. The drain of the first transistor M1 is connected to the light-emitting high potential voltage EVDD, and the source of the first transistor M1 is connected to the anode of the light-emitting diode Del to form a second node N2.

[0147] The source of the P-type second transistor M2 is connected to the cathode of the light-emitting diode Del to form a third node N3. The gate of the second transistor M2 is connected to the second output signal of the integrated level shifter 176 to form a fourth node N4, and the drain of the second transistor M2 is connected to the light-emitting low potential voltage EVSS.

[0148] The drain and source of the N-type third transistor M3 are connected to the second and third nodes N2 and N3 respectively, and the gate of the third transistor M3 is connected to the test signal TE.

[0149] The light-emitting diode display device according to the fifth embodiment of the present invention can operate in a display mode and a test mode.

[0150] In the display mode, the third transistor M3 is turned off and the light-emitting diode Del emits light, and the light-emitting diode display device displays an image.

[0151] In the test mode, the third transistor M3 is turned on and the light-emitting diode Del does not emit light, and defects of the first to eighth digital transistors Q1 to Q8 of the integrated level shifter 176 and the first and second transistors M1 and M2 are detected using the video data RGB, the programming signal PGM, and the light-emitting signal EM.

[0152] Here, if the light-emitting diode Del is not connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light-emitting diode Del.

[0153] When the light-emitting diode Del is connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 is turned on so that the voltage difference between the second and third nodes N2 and N3 is smaller than the light-emitting threshold voltage of the light-emitting diode Del, and the normal operation of elements other than the light-emitting diode Del can be detected.

[0154] As described above, in the light-emitting diode display device according to the fifth embodiment of the present invention, the first and second transistors M1 and M2 are respectively connected to the positive and negative electrodes of the light-emitting diode Del, and the first and second transistors M1 and M2 are switched by using the integrated level shifter 176, so that a constant current can flow through the light-emitting diode Del regardless of the fluctuations of the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS. As a result, the uniformity of the light-emitting luminance can be improved.

[0155] Then, the third transistor M3 is connected to the positive and negative electrodes of the light-emitting diode Del, and by turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0156] In other embodiments, the second transistor M2 may be omitted and the negative electrode of the light-emitting diode Del may be directly connected to the light-emitting low potential voltage EVSS, and this will be described with reference to the drawings.

[0157] FIG. 14 is a drawing illustrating a pixel of a light-emitting diode display device according to the sixth embodiment of the present invention, and FIG. 15 is a waveform diagram illustrating signals used in the pixel of the light-emitting diode display device according to the sixth embodiment of the present invention. Descriptions of the same parts as in the first to fifth embodiments are omitted.

[0158] As shown in FIG. 14, the pixel P of the light-emitting diode display device according to the sixth embodiment of the present invention includes an integrated level shifter 176, first and third transistors M1 and M3, and a light-emitting diode Del, and the first and third transistors M1 and M3 and the light-emitting diode Del constitute a light-emitting portion.

[0159] The integrated level shifter 176 of the control circuit unit that supplies a control signal to the current source includes first to eighth digital transistors Q1 to Q8, receives inputs of video data RGB, a programming signal PGM, and a light emission signal EM, and outputs a first output signal using a pin high potential voltage PVDD and a pin low potential voltage PVSS.

[0160] The first transistor M1 that operates as a current source to allow a constant current to flow through the light emitting diode Del switches the connection between the light emission high potential voltage EVDD and the light emitting diode Del by the first output signal, and the third transistor M3 switches the connection between the positive electrode of the light emitting diode Del and the test voltage TM by the test signal TE.

[0161] The gate of the N-type first transistor M1 is connected to the first output signal of the integrated level shifter 176 to form a first node N1, the drain of the first transistor M1 is connected to the light emission high potential voltage EVDD, and the source of the first transistor M1 is connected to the positive electrode of the light emitting diode Del to form a second node N2.

[0162] The drain and source of the N-type third transistor M3 are connected to the second node N2 and the test voltage TM, respectively, and the gate of the third transistor M3 is connected to the test signal TE.

[0163] The light emitting diode display device according to the sixth embodiment of the present invention can operate in a display mode and a test mode.

[0164] In the display mode, the third transistor M3 is turned off, the light emitting diode Del emits light, and the light emitting diode display device displays an image.

[0165] In the test mode, the third transistor M3 is turned on, the light emitting diode Del does not emit light, the second node N2 is initialized to the test voltage TM to prevent it from decreasing below a specific voltage, or the characteristics of the first transistor M1 or the light emitting diode Del can be measured.

[0166] As shown in FIG. 15, in the test mode of the light-emitting diode display device, the video data RGB has a test data section, the emission signal EM has a low level during a non-preservation section Tns corresponding to the test data section of the video data RGB, the programming signal PGM has a high level during a programming section Tpg corresponding to the test data section of the video data RGB, and the test signal TE has a high level during a test section Tts corresponding to the next frame of the video data RGB.

[0167] Accordingly, during the non-preservation section Tns, the first output signal of the integrated level shifter 176 becomes low (0) and is transmitted to the first node N1, and the gate of the first transistor M1 is initialized.

[0168] During the programming section Tpg, the first output signal of the integrated level shifter 176 becomes high (1) and is transmitted to the first node N1, and the gate of the first transistor M1 reflects the pixel state.

[0169] During the test section Tts, the test signal TE becomes high (1), the third transistor M3 is turned on, the test voltage TM is transmitted to the second node N2 which is the source of the first transistor M1, and the characteristic change of the first transistor M1 or the light-emitting diode Del is detected.

[0170] As described above, in the light-emitting diode display device according to the sixth embodiment of the present invention, by connecting the first transistor M1 to the positive electrode of the light-emitting diode Del and switching the first transistor M1 using the integrated level shifter 176, a constant current can flow through the light-emitting diode Del regardless of the fluctuations in the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS, and as a result, the uniformity of the light-emitting luminance can be improved.

[0171] Then, by connecting the third transistor M3 to the positive electrode of the light-emitting diode Del and turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0172] In other embodiments, a current source and a source follower can be connected to the positive and negative electrodes of the light-emitting diode, respectively, which will be described with reference to the drawings.

[0173] FIG. 16 is a drawing showing the light-emitting portion of a pixel of a light-emitting diode display device according to a seventh embodiment of the present invention, and descriptions of the same parts as those in the first to sixth embodiments are omitted.

[0174] As shown in FIG. 16, the light-emitting portion of the pixel P of the light-emitting diode display device according to the seventh embodiment of the present invention includes N-type first, third to fifth transistors M1, M3 to M5, an N-type second transistor M2, a first capacitor C1, and a light-emitting diode Del.

[0175] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high potential voltage EVDD and the light-emitting diode Del according to the voltage of the first node N1. The second transistor M2, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting diode Del and the light-emitting low potential voltage EVSS according to the voltage of the third node N3. The third transistor M3 switches the connection between the positive and negative electrodes of the light-emitting diode Del according to the test signal TE.

[0176] The fourth transistor M4 of the control circuit unit that supplies a control signal to the current source switches the connection between the first data signal DATA1 and the first node N1 according to the first programming signal PGM1. The fifth transistor M5 of the control circuit unit that supplies a control signal to the current source switches the connection between the second data signal DATA2 and the second node N2 according to the second programming signal PGM2.

[0177] The first transistor M1 has an N-type (negative type), the gate of the first transistor M1 is connected to the first node N1, the drain of the first transistor M1 is connected to the light-emitting high potential voltage EVDD, and the source of the first transistor M1 is connected to the second node N2.

[0178] The second transistor M2 has a P-type (positive type), the gate of the second transistor M2 is connected to the light-emitting signal EM, the source of the second transistor M2 is connected to the third node N3, and the drain of the second transistor M2 is connected to the light-emitting low potential voltage EVSS.

[0179] The third transistor M3 has an N-type, the gate of the third transistor M3 is connected to the test signal TE, the drain of the third transistor M3 is connected to the second node N2, and the source of the third transistor M3 is connected to the third node N3.

[0180] The fourth transistor M4 has an N-type, the gate of the fourth transistor M4 is connected to the first programming signal PGM1, the drain of the fourth transistor M4 is connected to the first data signal DATA1, and the source of the fourth transistor M4 is connected to the first node N1.

[0181] The fifth transistor M5 has an N-type, the gate of the fifth transistor M5 is connected to the second programming signal PGM2, the drain of the fifth transistor M5 is connected to the second data signal DATA2, and the source of the fifth transistor M5 is connected to the second node N2.

[0182] The first and second electrodes of the first capacitor C1 of the control circuit unit that supplies the control signal to the current source are connected to the first and second nodes N1 and N2, respectively.

[0183] The positive and negative electrodes of the light-emitting diode Del are connected to the second and third nodes N2 and N3, respectively.

[0184] The gate of the first transistor M1, the source of the fourth transistor M4, and the first electrode of the first capacitor C1 constitute the first node N1. The source of the first transistor M1, the drain of the third transistor M3, the source of the fifth transistor M5, the second electrode of the first capacitor C1, and the anode of the light-emitting diode Del constitute the second node N2. The source of the second transistor M2, the source of the third transistor M3, and the cathode of the light-emitting diode Del constitute the third node N3.

[0185] The light-emitting diode display device according to the seventh embodiment of the present invention can operate in a display mode and a test mode.

[0186] In the display mode, the third transistor M3 is turned off and the light-emitting diode Del emits light, and the light-emitting diode display device displays an image.

[0187] In the test mode, the third transistor M3 is turned on and the light-emitting diode Del does not emit light, and defects of the first to fifth transistors M1 to M5 are detected using the first and second data signals DATA1, DATA2, the first and second programming signals PGM1, PGM2, and the emission signal EM.

[0188] Here, when the light-emitting diode Del is not connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light-emitting diode Del.

[0189] When the light-emitting diode Del is connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on so that the voltage difference between the second and third nodes N2 and N3 is smaller than the light emission threshold voltage of the light-emitting diode Del to detect the normal operation of elements other than the light-emitting diode Del.

[0190] As described above, in the light-emitting diode display device according to the seventh embodiment of the present invention, the first and second transistors M1 and M2 are connected to the positive and negative electrodes of the light-emitting diode Del, respectively, and the fourth and fifth transistors M4 and M5 are used to operate the first and second transistors M1 and M2 as a current source and a source follower, respectively. As a result, a constant current can flow through the light-emitting diode Del regardless of the fluctuations in the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS, and thus the uniformity of the light-emitting luminance can be improved.

[0191] Then, a third transistor M3 is connected to the positive and negative electrodes of the light-emitting diode Del, and by turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0192] In the seventh embodiment of FIG. 16, an example is given in which the second transistor M2 is connected between the negative electrode of the light-emitting diode Del and the light-emitting low potential voltage EVSS. However, in other embodiments similar to FIGS. 14 and 15, the second transistor M2 may be omitted and the negative electrode of the light-emitting diode Del may be directly connected to the light-emitting low potential voltage EVSS. In this case, the source of the third transistor M3 may be connected to the test voltage TM instead of the third node N3.

[0193] In other embodiments, the fourth and fifth transistors can be switched by one signal, which will be described with reference to the drawings.

[0194] FIG. 17 is a drawing showing the light-emitting portion of a pixel of a light-emitting diode display device according to the eighth embodiment of the present invention, and FIG. 18 is a waveform diagram showing the signals used in the light-emitting portion of a pixel of a light-emitting diode display device according to the eighth embodiment of the present invention. Descriptions of the same parts as those in the first to seventh embodiments are omitted.

[0195] As shown in FIG. 17, the light-emitting portion of the pixel P of the light-emitting diode display device according to the eighth embodiment of the present invention includes N-type first, third to fifth transistors M1, M3 to M5, an N-type second transistor M2, a first capacitor C1, and a light-emitting diode Del.

[0196] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high potential voltage EVDD and the light-emitting diode Del according to the voltage of the first node N1. The second transistor M2, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting diode Del and the light-emitting low potential voltage EVSS according to the voltage of the third node N3. The third transistor M3 switches the connection between the positive and negative electrodes of the light-emitting diode Del according to the test signal TE.

[0197] The fourth transistor M4 of the control circuit unit that supplies a control signal to the current source switches the connection between the first data signal DATA1 and the first node N1 according to the programming signal PGM. The fifth transistor M5 of the control circuit unit that supplies a control signal to the current source switches the connection between the second data signal DATA2 and the second node N2 according to the programming signal PGM.

[0198] The first transistor M1 has an N-type (negative type). The gate of the first transistor M1 is connected to the first node N1. The drain of the first transistor M1 is connected to the light-emitting high potential voltage EVDD. The source of the first transistor M1 is connected to the second node N2.

[0199] The second transistor M2 has a P-type (positive type). The gate of the second transistor M2 is connected to the light-emitting signal EM. The source of the second transistor M2 is connected to the third node N3. The drain of the second transistor M2 is connected to the light-emitting low potential voltage EVSS.

[0200] The third transistor M3 has an N-type, the gate of the third transistor M3 is connected to the test signal TE, the drain of the third transistor M3 is connected to the second node N2, and the source of the third transistor M3 is connected to the third node N3.

[0201] The fourth transistor M4 has an N-type, the gate of the fourth transistor M4 is connected to the programming signal PGM, the drain of the fourth transistor M4 is connected to the first data signal DATA1, and the source of the fourth transistor M4 is connected to the first node N1.

[0202] The fifth transistor M5 has an N-type, the gate of the fifth transistor M5 is connected to the programming signal PGM, the drain of the fifth transistor M5 is connected to the second data signal DATA2, and the source of the fifth transistor M5 is connected to the second node N2.

[0203] The first and second electrodes of the first capacitor C1 of the control circuit unit that supplies the control signal to the current source are connected to the first and second nodes N1 and N2, respectively.

[0204] The positive and negative electrodes of the light emitting diode Del are connected to the second and third nodes N2 and N3, respectively.

[0205] The gate of the first transistor M1, the source of the fourth transistor M4, and the first electrode of the first capacitor C1 constitute the first node N1, the source of the first transistor M1, the drain of the third transistor M3, the source of the fifth transistor M5, the second electrode of the first capacitor C1, and the positive electrode of the light emitting diode Del constitute the second node N2, and the source of the second transistor M2, the source of the third transistor M3, and the negative electrode of the light emitting diode Del constitute the third node N3.

[0206] The light emitting diode display device according to the eighth embodiment of the present invention can operate in a display mode and a test mode.

[0207] In the display mode, the third transistor M3 is turned off and the light emitting diode Del emits light, and the light emitting diode display device displays an image.

[0208] In the test mode, the third transistor M3 is turned on and the light emitting diode Del does not emit light, and defects of the first to fifth transistors M1 to M5 are detected using the first and second data signals DATA1, DATA2, the programming signal PGM, and the light emission signal EM.

[0209] Here, when the light emitting diode Del is not connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light emitting diode Del.

[0210] When the light emitting diode Del is connected between the second and third nodes N2 and N3 after the manufacturing process, the third transistor M3 can be turned on so that the voltage difference between the second and third nodes N2 and N3 is smaller than the light emission threshold voltage of the light emitting diode Del to detect the normal operation of elements other than the light emitting diode Del.

[0211] As shown in FIG. 18, the first data signal DATA1 has a valid section for each frame, the second data signal DATA2 has a low level, the light emission signal EM has a high level during the non-light emission section Tne corresponding to the valid section of the current frame of the first data signal DATA1 and has a low level during the light emission section Tem other than the non-light emission section Tne, and the programming signal PGM has a high level during the programming section Tpg corresponding to the valid section of the current frame of the first data signal DATA1.

[0212] Accordingly, during the non-light emission section Tne, the second transistor M2 is turned off and the light emitting diode Del does not emit light.

[0213] During the programming period Tpg, the fourth and fifth transistors M4 and M5 are turned on, and the first and second data signals DATA1 and DATA2 are transmitted to the first and second nodes N1 and N2, respectively. As a result, the voltage difference between the first and second data signals DATA1 and DATA2 is stored in the first capacitor C1.

[0214] During the light emission period Tem, the first transistor M1 is turned on by the voltage difference between the first and second data signals DATA1 and DATA2 of the first capacitor C1 and operates as a current source that supplies a constant current. The second transistor M2 is turned on and operates as a source follower through which a constant current flows. Accordingly, the light emitting diode Del emits light with uniform luminance by a constant current regardless of fluctuations in the light emission high potential voltage EVDD and the light emission low potential voltage EVSS.

[0215] As described above, in the light emitting diode display device according to the eighth embodiment of the present invention, the first and second transistors M1 and M2 are connected to the positive and negative electrodes of the light emitting diode Del, respectively, and the fourth and fifth transistors M4 and M5 are used to operate the first and second transistors M1 and M2 as a current source and a source follower, respectively. Thus, a constant current can flow through the light emitting diode Del regardless of fluctuations in the light emission high potential voltage EVDD and the light emission low potential voltage EVSS, and as a result, the uniformity of the light emission luminance can be improved.

[0216] Then, by connecting the third transistor M3 to the positive and negative electrodes of the light emitting diode Del and turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0217] In the eighth embodiment of FIG. 17, an example was given in which the second transistor M2 is connected between the negative electrode of the light-emitting diode Del and the light-emitting low-potential voltage EVSS. However, in other embodiments, the second transistor M2 may be omitted and the negative electrode of the light-emitting diode Del may be directly connected to the light-emitting low-potential voltage EVSS. In this case, the source of the third transistor M3 may be connected to the test voltage TM instead of the third node N3.

[0218] In other embodiments, the voltage of the second electrode of the first capacitor can be fixed, which will be described with reference to the drawings.

[0219] FIG. 19 is a drawing showing the light-emitting part of a pixel of a light-emitting diode display device according to the ninth embodiment of the present invention, and FIG. 20 is a waveform diagram showing the signals used in the light-emitting part of a pixel of a light-emitting diode display device according to the ninth embodiment of the present invention. Descriptions of the same parts as in the first to eighth embodiments are omitted.

[0220] As shown in FIG. 19, the light-emitting part of the pixel P of the light-emitting diode display device according to the ninth embodiment of the present invention includes N-type first, third to fifth transistors M1, M3 to M5, an N-type second transistor M2, a first capacitor C1, and a light-emitting diode Del.

[0221] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting high-potential voltage EVDD and the light-emitting diode Del according to the voltage of the first node N1. The second transistor M2, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the light-emitting diode Del and the light-emitting low-potential voltage EVSS according to the voltage of the third node N3. The third transistor M3 switches the connection between the positive and negative electrodes of the light-emitting diode Del according to the test signal TE.

[0222] The fourth transistor M4 of the control circuit unit that supplies a control signal to the current source switches the connection between the data signal DATA and the first node N1 by the programming signal PGM, and the fifth transistor M5 of the control circuit unit that supplies a control signal to the current source switches the connection between the reference signal REF and the second node N2 by the sense signal SE.

[0223] The first transistor M1 has an N-type (negative type), the gate of the first transistor M1 is connected to the first node N1, the drain of the first transistor M1 is connected to the light-emitting high potential voltage EVDD, and the source of the first transistor M1 is connected to the second node N2.

[0224] The second transistor M2 has a P-type (positive type), the gate of the second transistor M2 is connected to the light-emitting signal EM, the source of the second transistor M2 is connected to the third node N3, and the drain of the second transistor M2 is connected to the light-emitting low potential voltage EVSS.

[0225] The third transistor M3 has an N-type, the gate of the third transistor M3 is connected to the test signal TE, the drain of the third transistor M3 is connected to the second node N2, and the source of the third transistor M3 is connected to the third node N3.

[0226] The fourth transistor M4 has an N-type, the gate of the fourth transistor M4 is connected to the programming signal PGM, the drain of the fourth transistor M4 is connected to the data signal DATA, and the source of the fourth transistor M4 is connected to the first node N1.

[0227] The fifth transistor M5 has an N-type, the gate of the fifth transistor M5 is connected to the sense signal SE, the drain of the fifth transistor M5 is connected to the reference signal REF and the second electrode of the first capacitor, and the source of the fifth transistor M5 is connected to the second node N2.

[0228] The first electrode of the first capacitor C1 of the control circuit unit that supplies a control signal to the current source is connected to the first node N1, and the second electrode of the first capacitor C1 is connected to the reference signal REF and the drain of the fifth transistor M5.

[0229] The positive and negative electrodes of the light-emitting diode Del are connected to the second and third nodes N2 and N3, respectively.

[0230] The gate of the first transistor M1, the source of the fourth transistor M4, and the first electrode of the first capacitor C1 constitute the first node N1. The source of the first transistor M1, the drain of the third transistor M3, the source of the fifth transistor M5, and the positive electrode of the light-emitting diode Del constitute the second node N2. The source of the second transistor M2, the source of the third transistor M3, and the negative electrode of the light-emitting diode Del constitute the third node N3.

[0231] The light-emitting diode display device according to the ninth embodiment of the present invention can operate in a display mode and a test mode.

[0232] In the display mode, the third transistor M3 is turned off and the light-emitting diode Del emits light, and the light-emitting diode display device displays an image.

[0233] In the test mode, the third transistor M3 is turned on and the light-emitting diode Del does not emit light, and defects of the first to fifth transistors M1 to M5 are detected using the data signal DATA, the sense signal SE, the programming signal PGM, and the emission signal EM.

[0234] Here, when the light-emitting diode Del is not yet connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light-emitting diode Del.

[0235] When the light-emitting diode Del is connected between the second and third nodes N2 and N3 during the manufacturing process, the third transistor M3 is turned on so that the voltage difference between the second and third nodes N2 and N3 becomes smaller than the light-emitting threshold voltage of the light-emitting diode Del, and the normal operation of elements other than the light-emitting diode Del can be detected.

[0236] As shown in FIG. 20, the data signal DATA has a valid section for each frame, the light-emitting signal EM has a high level during the non-light-emitting section Tne corresponding to the valid section of the current frame of the data signal DATA and a low level during the light-emitting section Tem other than the non-light-emitting section Tne, the programming signal PGM has a high level during the programming section Tpg corresponding to the valid section of the current frame of the data signal DATA, and the sense signal SE has a high level during the sense section SE corresponding to the valid section of the current frame of the data signal DATA.

[0237] Accordingly, during the non-light-emitting section Tne, the second transistor M2 is turned off and the light-emitting diode Del does not emit light.

[0238] During the programming section Tpg, the fourth transistor M4 is turned on and the data signal DATA is transmitted to the first node N1, and the voltage of the second electrode of the first capacitor C1 is kept constant by the reference signal REF. As a result, the voltage difference between the data signal DATA and the reference signal REF is stored in the first capacitor C1.

[0239] During the sense section SE, the fifth transistor M5 is turned on and the reference signal REF is transmitted to the second node N2. As a result, the positive electrode of the light-emitting diode Del is initialized and characteristics such as the moving picture response time are improved.

[0240] During the light-emitting period Tem, the first transistor M1 is turned on by the data signal DATA of the first capacitor C1 and operates as a source follower through which a constant current flows, and the second transistor M2 is turned on and operates as a source follower through which a constant current flows. Accordingly, the light-emitting diode Del emits light of uniform luminance with a constant current regardless of fluctuations in the light-emitting high-potential voltage EVDD and the light-emitting low-potential voltage EVSS.

[0241] Here, the current of the light-emitting diode Del is determined by the voltage difference between the first and second transistors M1 and M2 operating as source followers. When the pixel P includes the light-emitting diode Del that emits red light, green light, and blue light, by adjusting the aspect ratios of the first and second transistors M1 and M2, a current reflecting the difference in operating characteristics of the red, green, and blue light-emitting diodes Del can be made to flow through the light-emitting diode Del.

[0242] As described above, in the light-emitting diode display device according to the ninth embodiment of the present invention, the first and second transistors M1 and M2 are connected to the positive and negative electrodes of the light-emitting diode Del, respectively, and the fourth and fifth transistors M4 and M5 are used to cause the first and second transistors M1 and M2 to operate as source followers, respectively, so that a constant current can flow through the light-emitting diode Del regardless of fluctuations in the light-emitting high-potential voltage EVDD and the light-emitting low-potential voltage EVSS, and as a result, the uniformity of the light-emitting luminance can be improved.

[0243] Then, by connecting the third transistor M3 to the positive and negative electrodes of the light-emitting diode Del and turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0244] In the ninth embodiment of FIG. 19, an example was given in which the second transistor M2 is connected between the negative electrode of the light-emitting diode Del and the light-emitting low-potential voltage EVSS. However, in other embodiments, the second transistor M2 may be omitted and the negative electrode of the light-emitting diode Del may be directly connected to the light-emitting low-potential voltage EVSS. In this case, the source of the third transistor M3 may be connected to the test voltage TM instead of the third node N3.

[0245] In other embodiments, each pixel can be composed of a latch and a light-emitting portion, which will be described with reference to the drawings.

[0246] FIG. 21 is a drawing showing the pixel of the light-emitting diode display device according to the tenth embodiment of the present invention, and FIG. 22 is a waveform diagram showing the signals used in the pixel of the light-emitting diode display device according to the tenth embodiment of the present invention. The description of the same parts as those in the first to ninth embodiments will be omitted.

[0247] As shown in FIG. 21, the pixel P of the light-emitting diode display device according to the tenth embodiment of the present invention includes a latch 172 and a light-emitting portion 178. The latch 172 includes the first to seventh digital transistors Q1 to Q7, and the light-emitting portion 178 includes the first, third, fourth to seventh transistors M1, M3, M4 to M7, the first capacitor C1, and the light-emitting diode Del.

[0248] The latch 172, the fourth to seventh transistors M4 to M7, and the first capacitor C1 constitute a control circuit portion that supplies a control signal to the first transistor M1, which is a current source. The first, fourth, and sixth digital transistors Q1, Q4, and Q6 are of P type, the second, third, fifth, and seventh digital transistors Q2, Q3, Q5, and Q7 are of N type, the first and sixth transistors M1 and M6 are of P type, and the third to fifth and seventh transistors M3 to M5 and M7 are of N type.

[0249] The first digital transistor Q1 switches the connection between the first output signal and the gates of the fourth and fifth digital transistors Q4 and Q5 by a programming signal PGM which is a signal for inputting video data RGB to the latch 172. The second digital transistor Q2 switches the connection between the video data RGB and the gates of the fourth and fifth digital transistors Q4 and Q5 by the programming signal PGM.

[0250] The third digital transistor Q3 switches the connection between the digital low potential voltage VSS and the gates of the fourth and fifth digital transistors Q4 and Q5 by a reset signal RS which is a signal for resetting the latch 172.

[0251] In other embodiments, the reset signal RS and the third digital transistor Q3 can be omitted.

[0252] The fourth digital transistor Q4 switches the connection between the digital high potential voltage VCC and the second output signal by the first output signal or the digital low potential voltage VSS. The fifth digital transistor Q5 switches the connection between the digital low potential voltage VSS and the second output signal by the first output signal or the digital low potential voltage VSS.

[0253] The sixth digital transistor Q6 switches the connection between the digital high potential voltage VCC and the first output signal by the second output signal. The seventh digital transistor Q7 switches the connection between the digital low potential voltage VSS and the second output signal by the second output signal.

[0254] The first transistor M1 which operates as a current source to allow a constant current to flow through the light emitting diode Del switches the connection between the sixth transistor M6 and the seventh transistor M7 by the voltage of the first node N1. The third transistor M3 switches the connection between the drain of the seventh transistor M7 and the test voltage TM by the test signal TE.

[0255] The gate of the first transistor M1 is connected to the second electrode of the first capacitor C1 and the fifth transistor M5 to form a first node N1. The source of the first transistor M1 is connected to the first electrode of the first capacitor C1 and the sixth transistor M6. The drain of the first transistor M1 is connected to the third transistor M3 and the seventh transistor M7 to form a second node N2.

[0256] The fourth transistor M4 switches the connection between the first output signal and the first electrode of the first capacitor C1 according to the reference signal RF. The fifth transistor M5 switches the connection between the second output signal and the first node N1 according to the reference signal RF.

[0257] The sixth transistor M6 switches the connection between the light-emitting high potential voltage EVDD and the first transistor M1 according to the first light-emitting signal EM1. The seventh transistor M7 switches the connection between the first transistor M1 and the light-emitting diode Del according to the second light-emitting signal EM2.

[0258] The first electrode of the first capacitor C1 is connected to the first transistor M1, the fourth transistor M4, and the sixth transistor M6. The second electrode of the first capacitor C1 is connected to the first node N1.

[0259] The positive electrode of the light-emitting diode Del is connected to the seventh transistor M7. The negative electrode of the light-emitting diode Del is connected to the light-emitting low potential voltage EVSS.

[0260] The light-emitting diode display device according to the tenth embodiment of the present invention can operate in a display mode and a test mode.

[0261] In the display mode, the third transistor M3 is turned off, the light-emitting diode Del emits light, and the light-emitting diode display device displays an image.

[0262] In the test mode, the third transistor M3 is turned on, the light-emitting diode Del does not emit light, the second node N2 is initialized with the test voltage TM to prevent it from decreasing below a specific voltage, or the characteristics of the first transistor M1 or the light-emitting diode Del can be measured.

[0263] Here, if it is before the light-emitting diode Del is connected to the second node N2 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light-emitting diode Del.

[0264] If it is after the light-emitting diode Del is connected to the second node N2 during the manufacturing process, the third transistor M3 can be turned on so that the voltage difference between the second and third nodes N2, N3 is smaller than the light emission threshold voltage of the light-emitting diode Del to detect the normal operation of elements other than the light-emitting diode Del.

[0265] As shown in FIG. 22, the third digital transistor Q3 is turned on by a high-level reset signal RS between the first and second timings T1, T2, and the gates of the fourth and fifth digital transistors Q4, Q5 are reset to the digital low potential voltage VSS.

[0266] Video data RGB is input to the latch 172 by a high-level programming signal PGM between the third and fourth timings T3, T4, and the first and second output signals are output from the latch 172.

[0267] The seventh transistor M7 is turned off by a low-level second light emission signal EM2 between the fifth and tenth timings T5, T10, and the sixth transistor M6 is turned off by a high-level first light emission signal EM1 at the sixth and ninth timings T6, T9, and the light-emitting diode Del is in a non-light-emitting state.

[0268] Between the seventh and eighth timings T7 and T8, the fourth and fifth transistors M4 and M5 are turned on by a high-level reference signal RF, and the first and second output signals of the latch 172 are transmitted to the source and gate of the first transistor M1, respectively.

[0269] At the ninth and tenth timings T9 and T10, the sixth and seventh transistors M6 and M7 are turned on respectively, and the light-emitting diode Del enters a light-emitting state. Accordingly, the first transistor M1 is turned on by the second output signal of the first capacitor C1 and operates as a source follower through which a constant current flows, and the light-emitting diode Del emits light of uniform luminance with a constant current regardless of fluctuations in the light-emitting high-potential voltage EVDD and the light-emitting low-potential voltage EVSS.

[0270] Here, the current of the light-emitting diode Del is determined by the voltage difference between the first transistor M1 operating as a source follower and the light-emitting low-potential voltage EVSS. When the pixel P includes a light-emitting diode Del that emits red light, green light, and blue light, by adjusting the aspect ratio of the first transistor M1, a current reflecting the difference in operating characteristics of the red, green, and blue light-emitting diodes Del can be made to flow through the light-emitting diode Del.

[0271] As described above, in the light-emitting diode display device according to the tenth embodiment of the present invention, the first transistor M1 is connected to the positive electrode of the light-emitting diode Del, and the fourth and fifth transistors M4 and M5 are used to operate the first transistor M1 as a source follower, so that a constant current can flow through the light-emitting diode Del regardless of fluctuations in the light-emitting high-potential voltage EVDD and the light-emitting low-potential voltage EVSS, and as a result, the uniformity of the light-emitting luminance can be improved.

[0272] Then, by connecting the third transistor M3 to the positive electrode of the light-emitting diode Del and turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0273] In other embodiments, the N-type first transistor M1 can be connected to the fourth transistor T4, which will be described with reference to the drawings.

[0274] FIG. 23 is a drawing illustrating a pixel of a light-emitting diode display device according to the 11th embodiment of the present invention. Descriptions of the same parts as those in the 1st to 10th embodiments are omitted.

[0275] As shown in FIG. 23, the pixel P of the light-emitting diode display device according to the 11th embodiment of the present invention includes a latch 172 and a light-emitting unit 178. The latch 172 includes first to seventh digital transistors Q1 to Q7, and the light-emitting unit 178 includes first, third to seventh transistors M1, M3 to M7, a first capacitor C1, and a light-emitting diode Del.

[0276] The latch 172, the fourth to seventh transistors M4 to M7, and the first capacitor C1 constitute a control circuit unit that supplies a control signal to a current source. The first, fourth, and sixth digital transistors Q1, Q4, and Q6 are of P-type, the second, third, fifth, and seventh digital transistors Q2, Q3, Q5, and Q7 are of N-type, and the configuration and operation of the latch 172 of each pixel P of the light-emitting diode display device according to the 11th embodiment are the same as those of the latch 172 of each pixel P of the light-emitting diode display device according to the 10th embodiment.

[0277] The sixth transistor M6 is of P-type, and the first, third to fifth, and seventh transistors M1, M3 to M5, and M7 are of N-type.

[0278] The first transistor M1, which operates as a current source to allow a constant current to flow through the light-emitting diode Del, switches the connection between the sixth transistor M6 and the seventh transistor M7 according to the voltage of the first node N1, and the third transistor M3 switches the connection between the drain of the seventh transistor M7 and the test voltage TM according to the test signal TE.

[0279] The gate of the first transistor M1 is connected to the first electrode of the first capacitor C1 and the fourth transistor M4 to form a first node N1. The drain of the first transistor M1 is connected to the sixth transistor M6, and the source of the first transistor M1 is connected to the second electrode of the first capacitor C1, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 to form a second node N2.

[0280] The fourth transistor M4 switches the connection between the first output signal and the first node N1 by a reference signal RF, and the fifth transistor M5 switches the connection between the second output signal and the second node N2 by a reference signal RF.

[0281] The sixth transistor M6 switches the connection between the light-emitting high-potential voltage EVDD and the first transistor M1 by a first light-emitting signal EM1, and the seventh transistor M7 switches the connection between the first transistor M1 and the light-emitting diode Del by a second light-emitting signal EM2.

[0282] The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode of the first capacitor C1 is connected to the second node N2.

[0283] The positive electrode of the light-emitting diode Del is connected to the seventh transistor M7, and the negative electrode of the light-emitting diode Del is connected to the light-emitting low-potential voltage EVSS.

[0284] The light-emitting diode display device according to the eleventh embodiment of the present invention can operate in a display mode and a test mode.

[0285] In the display mode, the third transistor M3 is turned off and the light-emitting diode Del emits light, and the light-emitting diode display device displays an image.

[0286] In the test mode, the third transistor M3 is turned on, the light-emitting diode Del does not emit light, the second node N2 is initialized with the test voltage TM to prevent it from decreasing below a specific voltage, or the characteristics of the first transistor M1 or the light-emitting diode Del can be measured.

[0287] Here, when the light-emitting diode Del is not yet connected to the second node N2 during the manufacturing process, the third transistor M3 can be turned on to detect the normal operation of elements other than the light-emitting diode Del.

[0288] When the light-emitting diode Del is connected to the second node N2 during the manufacturing process, the third transistor M3 can be turned on so that the voltage difference between the second and third nodes N2, N3 is smaller than the light emission threshold voltage of the light-emitting diode Del to detect the normal operation of elements other than the light-emitting diode Del.

[0289] The light-emitting diode display device according to the 11th embodiment of the present invention operates according to the waveform diagram of FIG. 22.

[0290] As described above, in the light-emitting diode display device according to the 11th embodiment of the present invention, the first transistor M1 is connected to the positive electrode of the light-emitting diode Del, and the fourth and fifth transistors M4, M5 are used to make the first transistor M1 operate as a source follower, so that a constant current can flow through the light-emitting diode Del regardless of the fluctuations in the light emission high potential voltage EVDD and the light emission low potential voltage EVSS. As a result, the uniformity of the light emission luminance can be improved.

[0291] Then, by connecting the third transistor M3 to the positive electrode of the light-emitting diode Del and turning on the third transistor M3, defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.

[0292] In other embodiments, a current source can be arranged at one of the positive and negative electrodes of the light-emitting diode, which will be described with reference to the drawings.

[0293] FIG. 24 and FIG. 25 are diagrams showing pixels of the light-emitting diode display device according to the 12th and 13th embodiments of the present invention, respectively. Explanation of the same parts as those in the 1st to 11th embodiments is omitted.

[0294] As shown in FIG. 24, a pixel P of the light-emitting diode display device according to the 12th embodiment of the present invention includes a latch 172, a level shifter 174, a current source 182, and a light-emitting diode Del. The latch 172 and the level shifter 174 constitute a control circuit unit that supplies a control signal to the current source 182, and the current source 182 and the light-emitting diode Del constitute a light-emitting unit.

[0295] The latch 172 receives inputs of video data RGB, a programming signal PGM, and a reset signal RS, and outputs first and second output signals using a digital high-potential voltage VCC and a digital low-potential voltage VSS. The first and second output signals can be signals inverted from each other.

[0296] In other embodiments, the reset signal RS can be omitted.

[0297] The level shifter 174 receives inputs of the first and second output signals, and outputs third and fourth output signals using a pin high-potential voltage PVDD and a pin low-potential voltage PVSS. The third and fourth output signals can be signals inverted from each other.

[0298] The current source 182 receives an input of at least one of the third and fourth output signals, is connected to the positive electrode of the light-emitting diode Del, and causes a constant current to flow through the light-emitting diode Del using at least one of the third and fourth output signals.

[0299] For example, the latch 172 and the level shifter 174 include a number of transistors, and the current source 182 can include transistors and capacitors.

[0300] When the level shifter 174 outputs third and fourth output signals by using first and second signals of the latch 172 to which the digital storage concept is applied, a DC bypass current in the level shifter 174 can be prevented, and the light emitting diode Del can emit light with a constant luminance.

[0301] Here, the video data RGB input to the latch 172 has a digital type of digital voltage level.

[0302] As illustrated in FIG. 25, a pixel P of the light emitting diode display device according to the 13th embodiment of the present invention includes a latch 172, a level shifter 174, a current source 184, and a light emitting diode Del. The latch 172 and the level shifter 174 constitute a control circuit unit that supplies a control signal to the current source 184, and the current source 184 and the light emitting diode Del constitute a light emitting unit.

[0303] The latch 172 receives inputs of video data RGB, a programming signal PGM, and a reset signal RS, and outputs first and second output signals by using a digital high potential voltage VCC and a digital low potential voltage VSS, but the first and second output signals can be signals inverted from each other.

[0304] In other embodiments, the reset signal RS can be omitted.

[0305] The level shifter 174 receives inputs of the first and second output signals, and outputs third and fourth output signals by using a pin high potential voltage PVDD and a pin low potential voltage PVSS, but the third and fourth output signals can be signals inverted from each other.

[0306] The current source 184 receives an input of at least one of the third and fourth output signals, is connected to the negative electrode of the light emitting diode Del, and allows a constant current to flow through the light emitting diode Del by using at least one of the third and fourth output signals.

[0307] For example, the latch 172 and the level shifter 174 include a number of transistors, and the current source 182 can include transistors and capacitors.

[0308] When the level shifter 174 outputs third and fourth output signals using the first and second signals of the latch 172 to which the digital storage concept is applied, direct current bypass current in the level shifter 174 can be prevented, and the light emitting diode Del can emit light with a constant luminance.

[0309] Here, the video data RGB input to the latch 172 has a digital type of digital voltage level.

[0310] Thus, in the pixel P of the light emitting diode display device according to the 12th and 13th embodiments of the present invention, the latch 172 outputs first and second output signals at a constant direct current voltage level so that flicker or the like does not occur, and the level shifter 174 applies at least one of the third and fourth output signals required for light emission to the current sources 182 and 184, so that a constant current can flow through the light emitting diode Del regardless of fluctuations in the light emission high potential voltage EVDD and the light emission low potential voltage EVSS.

[0311] In other embodiments, the output signal of the level shifter can be stored in the latch and then supplied to the current source, which will be described with reference to the drawings.

[0312] FIG. 26 is a drawing illustrating a pixel of a light emitting diode display device according to the 14th embodiment of the present invention, FIG. 27 is a drawing illustrating a level shifter of a pixel of a light emitting diode display device according to the 14th embodiment of the present invention, and FIG. 28 is a waveform diagram illustrating signals used in the level shifter of a pixel of a light emitting diode display device according to the 14th embodiment of the present invention. Descriptions of the same parts as those in the 1st to 13th embodiments are omitted.

[0313] As shown in FIG. 26, the pixel P of the light-emitting diode display device according to the 14th embodiment of the present invention includes a level shifter 174, a latch 172, first and second current sources 182, 184, and a light-emitting diode Del. The level shifter 174 and the latch 172 constitute a control circuit section that supplies control signals to the first and second current sources 182, 184, and the first and second current sources 182, 184 and the light-emitting diode Del constitute a light-emitting section.

[0314] The level shifter 174 receives inputs of video data RGB, a programming signal PGM, and a reset signal RS, and outputs at least one of first and second output signals using a pin high-potential voltage PVDD and a pin low-potential voltage PVSS, where the first and second output signals can be signals inverted with respect to each other.

[0315] In other embodiments, the reset signal RS can be omitted.

[0316] The latch 172 receives an input of at least one of the first and second output signals, and outputs at least one of third and fourth output signals using a pin high-potential voltage PVDD and a pin low-potential voltage PVSS, where the third and fourth output signals can be signals inverted with respect to each other.

[0317] The first current source 182 receives an input of the third output signal, is connected to the positive electrode of the light-emitting diode Del, and uses the third output signal to cause a constant current to flow through the light-emitting diode Del.

[0318] The second current source 184 receives an input of the fourth output signal, is connected to the negative electrode of the light-emitting diode Del, and uses the fourth output signal to cause a constant current to flow through the light-emitting diode Del.

[0319] For example, the level shifter 174 and the latch 172 can include a number of transistors, and the first and second current sources 182, 184 can include transistors and capacitors.

[0320] Here, the video data RGB input to the level shifter 174 has a digital type of digital voltage level.

[0321] As shown in FIG. 27, the level shifter 174 of the pixel P of the light-emitting diode display device according to the 14th embodiment of the present invention includes first to ninth digital transistors Q1 to Q9, and first and second capacitors C1, C2.

[0322] The first and second digital transistors Q1, Q2 have a P-type, and the third to ninth digital transistors Q3 to Q9 have an N-type.

[0323] The first digital transistor Q1 switches the connection between the pin high potential voltage PVDD and the drain of the third digital transistor Q3 by the first output signal LSO1, and the second digital transistor Q2 switches the connection between the pin high potential voltage PVDD and the drain of the fourth digital transistor Q4 by the second output signal LSO2.

[0324] The third digital transistor Q3 switches the connection between the drain of the first digital transistor Q1 and the drain of the ninth digital transistor Q9 by the first output signal LSO1, and the fourth digital transistor Q4 switches the connection between the drain of the second digital transistor Q2 and the drain of the ninth digital transistor Q9 by the second output signal LSO2.

[0325] The fifth digital transistor Q5 switches the connection between the drain of the first digital transistor Q1 and the drain of the ninth digital transistor Q9 by the voltage of the first electrode of the first capacitor C1, and the sixth digital transistor Q6 switches the connection between the drain of the second digital transistor Q2 and the drain of the ninth digital transistor Q9 by the voltage of the first electrode of the second capacitor C2.

[0326] The seventh digital transistor Q7 switches the connection between the first video data RGB1 and the gate of the fifth digital transistor Q5 by a programming signal PGM which is a signal for inputting the first and second video data RGB1 and RGB2 to the level shifter 174, and the eighth digital transistor Q8 switches the connection between the second video data RGB2 and the gate of the sixth digital transistor Q6 by the programming signal PGM.

[0327] The ninth digital transistor Q9 switches the connection between the sources of the third to sixth digital transistors Q3 to Q6 and the pin low potential voltage PVSS by an enable signal LSE which is a signal for activating the output of the level shifter 174.

[0328] The first capacitor C1 is connected between the source of the seventh digital transistor Q7 and the pin low potential voltage PVSS, and the second capacitor C2 is connected between the source of the eighth digital transistor Q8 and the pin low potential voltage PVSS.

[0329] As shown in FIG. 28, the first and second video data RGB1 and RGB2 each have a valid section for each frame, the programming signal PGM has a high level during a programming section Tpg corresponding to the valid section of the current frame of the first and second video data RGB1 and RGB2, and the enable signal LSE has a high level during an output enable section Toe.

[0330] Accordingly, the seventh and eighth digital transistors Q7 and Q8 are turned on during the programming section Tpg, and the first and second video data RGB1 and RGB2 are stored in the first and second capacitors C1 and C2 respectively, and then valid first and second output signals LSO1 and LSO2 are output respectively during the output enable section Toe.

[0331] Although not shown in the figure, after storing the first and second output signals LSO1 and LSO2, the latch 172 can supply them to the light emitting diode Del at an appropriate timing.

[0332] FIG. 29 is a drawing illustrating a level shifter of a pixel of a light emitting diode display device according to a 15th embodiment of the present invention, and FIG. 30 is a waveform diagram illustrating signals used in the level shifter of the pixel of the light emitting diode display device according to the 15th embodiment of the present invention. The description will be made with reference to FIG. 26 together.

[0333] As shown in FIG. 29, the level shifter 174 of the pixel P of the light emitting diode display device according to the 15th embodiment of the present invention includes first to sixth digital transistors Q1 to Q6, and first and second capacitors C1 and C2.

[0334] The first and second digital transistors Q1 and Q2 are of P type, and the third to sixth digital transistors Q3 to Q6 are of N type.

[0335] The first digital transistor Q1 switches the connection between the pin high potential voltage PVDD and the drain of the third digital transistor Q3 by the precharge signal PCG, and the second digital transistor Q2 switches the connection between the pin high potential voltage PVDD and the drain of the fourth digital transistor Q4 by the voltage of the first electrode of the second capacitor C2.

[0336] The third digital transistor Q3 switches the connection between the drain of the first digital transistor Q1 and the drain of the sixth digital transistor Q6 by the precharge signal PCG, and the fourth digital transistor Q4 switches the connection between the drain of the second digital transistor Q2 and the pin low potential voltage PVSS by the voltage of the first electrode of the second capacitor C2.

[0337] The fifth digital transistor Q5 switches the connection between the video data RGB and the gate of the sixth digital transistor Q6 by the programming signal PGM, and the sixth digital transistor Q6 switches the connection between the source of the third digital transistor Q2 and the pin low potential voltage PVSS by the voltage of the first electrode of the first capacitor C1.

[0338] The first capacitor C1 is connected between the source of the fifth digital transistor Q5 and the pin low potential voltage PVSS, and the second capacitor C2 is connected between the gate of the second digital transistor Q2 and the pin low potential voltage PVSS.

[0339] The output signal LSO is output from a node between the drain of the second digital transistor Q2 and the drain of the fourth digital transistor Q4.

[0340] As shown in FIG. 30, the video data RGB has a valid section for each frame, the precharge signal PCG has a low level during a precharge section Tpc preceding the valid section of the current frame of the video data RGB, and the programming signal PGM has a high level during a programming section Tpg corresponding to the valid section of the current frame of the video data RGB.

[0341] Accordingly, the first digital transistor Q1 is turned on during the precharge section Tpc and the pin high potential voltage PVDD is stored in the second capacitor C2, the fifth digital transistor Q5 is turned on during the programming section Tpg and the video data RGB is stored in the first capacitor C1, and a valid output signal LSO is output.

[0342] Although not shown, after the latch 172 stores the output signal LSO, it can supply the light emitting diode Del at an appropriate timing.

[0343] As described above, in the pixel P of the light emitting diode display device according to the 14th and 15th embodiments of the present invention, the level shifter 174 outputs one of the first and second output signals using the video data RGB, the programming signal PGM, and the reset signal RS, and the latch 172 applies at least one of the third and fourth output signals necessary for light emission to the current sources 182 and 184, so that a constant current can flow through the light emitting diode Del regardless of fluctuations in the light emission high potential voltage EVDD and the light emission low potential voltage EVSS.

[0344] In other embodiments, the current source can be disposed at one of the anode and the cathode of the light emitting diode, which will be described with reference to the drawings.

[0345] FIG. 31 and FIG. 32 are diagrams illustrating pixels of a light emitting diode display device according to the 16th and 17th embodiments of the present invention, respectively. Descriptions of the same parts as those in the 1st to 15th embodiments are omitted.

[0346] As shown in FIG. 31, a pixel P of a light emitting diode display device according to the 16th embodiment of the present invention includes a level shifter 174, a latch 172, a current source 184, and a light emitting diode Del. The level shifter 174 and the latch 172 constitute a control circuit unit that supplies a control signal to the current source 184, and the current source 184 and the light emitting diode Del constitute a light emitting unit.

[0347] The level shifter 174 receives inputs of video data RGB, a programming signal PGM, and a reset signal RS, and outputs at least one of first and second output signals using a pin high potential voltage PVDD and a pin low potential voltage PVSS. The first and second output signals can be signals inverted from each other.

[0348] In other embodiments, the reset signal RS can be omitted.

[0349] The latch 172 receives an input of at least one of the first and second output signals, and outputs at least one of third and fourth output signals using a pin high potential voltage PVDD and a pin low potential voltage PVSS. The third and fourth output signals can be signals inverted from each other.

[0350] The current source 184 receives an input of at least one of the third and fourth output signals, is connected to the cathode of the light emitting diode Del, and causes a constant current to flow through the light emitting diode Del using at least one of the third and fourth output signals.

[0351] For example, the level shifter 174 and the latch 172 include a number of transistors, and the current source 184 can include transistors and capacitors.

[0352] Here, the video data RGB input to the level shifter 174 has a digital type of digital voltage level.

[0353] As shown in FIG. 32, the pixel P of the light-emitting diode display device according to the 17th embodiment of the present invention includes a level shifter 174, a latch 172, a current source 182, and a light-emitting diode Del. The level shifter 174 and the latch 172 constitute a control circuit unit that supplies a control signal to the current source, and the current source 182 and the light-emitting diode Del constitute a light-emitting unit.

[0354] The level shifter 174 receives inputs of video data RGB, a programming signal PGM, and a reset signal RS, and outputs at least one of a first and a second output signal using a pin high potential voltage PVDD and a pin low potential voltage PVSS, where the first and second output signals can be signals inverted from each other.

[0355] In other embodiments, the reset signal RS can be omitted.

[0356] The latch 172 receives an input of at least one of the first and second output signals, and outputs at least one of a third and a fourth output signal using a pin high potential voltage PVDD and a pin low potential voltage PVSS, where the third and fourth output signals can be signals inverted from each other.

[0357] The current source 182 receives an input of at least one of the third and fourth output signals, is connected to the positive electrode of the light-emitting diode Del, and uses at least one of the third and fourth output signals to allow a constant current to flow through the light-emitting diode Del.

[0358] For example, the level shifter 174 and the latch 172 include a number of transistors, and the current source 182 can include transistors and capacitors.

[0359] Here, the video data RGB input to the level shifter 174 has a digital type of digital voltage level.

[0360] Thus, in the pixel P of the light-emitting diode display device according to the 16th and 17th embodiments of the present invention, the level shifter 174 outputs one of the first and second output signals using the video data RGB, the programming signal PGM, and the reset signal RS, and the latch 172 applies at least one of the third and fourth output signals necessary for light emission to the current sources 182 and 184, so that a constant current can flow through the light-emitting diode Del regardless of the fluctuations in the light-emitting high potential voltage EVDD and the light-emitting low potential voltage EVSS.

[0361] Although the preferred embodiments of the present invention have been described above with reference thereto, those skilled in the relevant technical field will understand that the present invention can be variously modified and changed without departing from the technical idea and scope of the present invention described in the following claims.

Claims

1. A display panel including a plurality of pixels; Light-emitting diodes respectively disposed for each of the plurality of pixels; At least one current source connected between the light-emitting diode and a light-emitting high potential voltage and between the light-emitting diode and a light-emitting low potential voltage; A control circuit unit for supplying a control signal to the at least one current source, wherein the at least one current source includes a first transistor which is connected between the light-emitting diode and the light-emitting high potential voltage and is one of an N-type and a P-type; and a second transistor which is connected between the light-emitting diode and the light-emitting low potential voltage and is the other of the N-type and the P-type; wherein the control circuit unit includes a latch connected between a digital high potential voltage and a digital low potential voltage, and generating first and second output signals by using video data and a programming signal; and a level shifter connected between a pin high potential voltage and a pin low potential voltage, and generating third and fourth output signals for respectively switching the first and second transistors by using the first and second output signals. A light-emitting diode display device.

2. The latch includes a first P-type digital transistor for switching the transmission of the first output signal by the programming signal; a second N-type digital transistor for switching the transmission of the video data by the programming signal; a fourth P-type digital transistor for switching the transmission of the digital high potential voltage by the first output signal or the digital low potential voltage; a fifth N-type digital transistor for switching the transmission of the digital low potential voltage by the first output signal or the digital low potential voltage; a sixth P-type digital transistor for switching the transmission of the digital high potential voltage by the second output signal; and a seventh N-type digital transistor for switching the transmission of the digital low potential voltage by the second output signal. The level shifter includes an eighth P-type digital transistor for switching the transmission of the pin high potential voltage by the third output signal; a ninth N-type digital transistor for switching the transmission of the pin low potential voltage by the first output signal; and a tenth P-type digital transistor for switching the transmission of the pin high potential voltage by the fourth output signal; An N-type first digital transistor that switches the transmission of the pin low potential voltage by the second output signal, and the like. The light-emitting diode display device according to claim 1.

3. A display panel having a plurality of pixels, Light-emitting diodes arranged in each of the plurality of pixels, At least one current source connected between the light-emitting diode and the light-emitting high potential voltage and between the light-emitting diode and the light-emitting low potential voltage, A control circuit unit that supplies a control signal to the at least one current source, and the like. The at least one current source, A first transistor that is connected between the light-emitting diode and the light-emitting high potential voltage and is one of an N-type and a P-type, A second transistor that is connected between the light-emitting diode and the light-emitting low potential voltage and is the other one of the N-type and the P-type, and the like. The control circuit unit, An integrated level shifter that is connected between a pin high potential voltage and a pin low potential voltage and generates first and second output signals for switching the first and second transistors respectively using video data, a programming signal, and a light-emitting signal. The integrated level shifter, An N-type first digital transistor that switches the transmission of the first output signal by the light-emitting signal, A P-type second digital transistor that switches the transmission of the first output signal by the programming signal, An N-type third digital transistor that switches the transmission of the video data by the programming signal, A P-type fourth digital transistor that switches the transmission of the pin high potential voltage by the first output signal or the video data, An N-type fifth digital transistor that switches the transmission of the pin low potential voltage by the first output signal or the video data, A P-type sixth digital transistor that switches the transmission of the pin high potential voltage by the light-emitting signal, A P-type seventh digital transistor that switches the transmission of the pin high potential voltage by the second output signal, An N-type eighth digital transistor that switches the transmission of the pin low potential voltage by the second output signal, and the like. Light-emitting diode display device.

4. A display panel having a plurality of pixels, Light-emitting diodes arranged in each of the plurality of pixels, At least one current source connected between the light-emitting diode and the light-emitting high-potential voltage and between the light-emitting diode and the light-emitting low-potential voltage; A control circuit unit that supplies a control signal to the at least one current source; A third transistor connected between the positive and negative electrodes of the light-emitting diode; The at least one current source includes: A first transistor, which is one of an N-type and a P-type, connected between the light-emitting diode and the light-emitting high-potential voltage; A second transistor, which is the other of the N-type and the P-type, connected between the light-emitting diode and the light-emitting low-potential voltage; A light-emitting diode display device, wherein the first and third transistors are N-type and the second transistor is P-type.

5. An N-type fourth transistor that switches the connection between the first data signal and the gate of the first transistor by a first programming signal; An N-type fifth transistor that switches the connection between the second data signal and the source of the first transistor by a second programming signal; A first capacitor connected between the gate and the source of the first transistor; The light-emitting diode display device according to claim 4.

6. An N-type fourth transistor that switches the connection between the first data signal and the gate of the first transistor by a programming signal; An N-type fifth transistor that switches the connection between the second data signal and the source of the first transistor by the programming signal; A first capacitor connected between the gate and the source of the first transistor; The light-emitting diode display device according to claim 4.

7. An N-type fourth transistor that switches the connection between the data signal and the gate of the first transistor by a programming signal; An N-type fifth transistor that switches the connection between the reference signal and the source of the first transistor by a sense signal; Further including a first capacitor connected between the gate of the first transistor and the drain of the fifth transistor; The light-emitting diode display device according to claim 4.

8. A display panel having a plurality of pixels; Light-emitting diodes arranged in each of the plurality of pixels; At least one current source connected between the light-emitting diode and the light-emitting high-potential voltage and between the light-emitting diode and the light-emitting low-potential voltage; A control circuit unit that supplies a control signal to the at least one current source, The at least one current source, A first transistor that is connected between the light-emitting diode and the light-emitting high potential voltage and is one of N-type and P-type, A second transistor that is connected between the light-emitting diode and the light-emitting low potential voltage and is the other one of the N-type and P-type, The control circuit unit, A level shifter that is connected between the pin high potential voltage and the pin low potential voltage and generates first and second output signals using first and second video data, a programming signal, and an enable signal, A latch that is connected between the pin high potential voltage and the pin low potential voltage and generates third and fourth output signals for switching the first and second transistors using the first and second output signals, The level shifter, A first digital transistor that switches the connection between the pin high potential voltage and the drain of a third digital transistor by the first output signal, A second digital transistor that switches the connection between the pin high potential voltage and the drain of a fourth digital transistor by the second output signal, The third digital transistor that switches the connection between the drain of the first digital transistor and the drain of a ninth digital transistor by the first output signal, The fourth digital transistor that switches the connection between the drain of the second digital transistor and the drain of the ninth digital transistor by the second output signal, A fifth digital transistor that switches the connection between the drain of the first digital transistor and the drain of the ninth digital transistor by the voltage of the first electrode of a first capacitor, A sixth digital transistor that switches the connection between the drain of the second digital transistor and the drain of the ninth digital transistor by the voltage of the first electrode of a second capacitor, A seventh digital transistor that switches the connection between the first video data and the gate of the fifth digital transistor by the programming signal, An eighth digital transistor that switches the connection between the second video data and the gate of the sixth digital transistor by the programming signal, The ninth digital transistor that switches the connection between the source of the third to sixth digital transistors and the pin low potential voltage by the enable signal; The first capacitor connected between the source of the seventh digital transistor and the pin low potential voltage; The second capacitor connected between the source of the eighth digital transistor and the pin low potential voltage, and includes: A light emitting diode display device. **Claim 9**: A display panel having a plurality of pixels; Light emitting diodes arranged in each of the plurality of pixels; At least one current source connected between the light emitting diode and the light emitting high potential voltage and between the light emitting diode and the light emitting low potential voltage; A control circuit unit that supplies a control signal to the at least one current source, and includes: The at least one current source is A first transistor that is connected between the light emitting diode and the light emitting high potential voltage and is one of an N-type and a P-type; A second transistor that is connected between the light emitting diode and the light emitting low potential voltage and is the other of the N-type and the P-type, and includes: The control circuit unit is A level shifter that is connected between the pin high potential voltage and the pin low potential voltage and generates an output signal using video data, a programming signal, and a precharge signal; A latch that is connected between the pin high potential voltage and the pin low potential voltage and generates third and fourth output signals that switch the first and second transistors using the output signal, and includes: The level shifter is A first digital transistor that switches the connection between the pin high potential voltage and the drain of the third digital transistor by the precharge signal; A second digital transistor that switches the connection between the pin high potential voltage and the drain of the fourth digital transistor by the voltage of the first electrode of the second capacitor; The third digital transistor that switches the connection between the drain of the first digital transistor and the drain of the sixth digital transistor by the precharge signal; The fourth digital transistor that switches the connection between the drain of the second digital transistor and the pin low potential voltage by the voltage of the first electrode of the second capacitor; The connection between the video data and the gate of the sixth digital transistor is switched by the programming signal The fifth digital transistor for A sixth digital transistor that switches the connection between the source of the third digital transistor and the pin low potential voltage according to the voltage of the first electrode of the first capacitor; A first capacitor connected between the source of the fifth digital transistor and the pin low potential voltage; A second capacitor connected between the gate of the second digital transistor and the pin low potential voltage, and including; A light emitting diode display device.

10. A display panel including a large number of pixels; Light emitting diodes arranged respectively for the large number of pixels; At least one current source connected between the light emitting diode and the light emitting high potential voltage; A control circuit unit that supplies a control signal to the at least one current source; A third transistor connected between the positive electrode of the light emitting diode and the test voltage, and including; The at least one current source is Connected between the light emitting diode and the light emitting high potential voltage, and includes a first transistor which is one of an N-type and a P-type; The negative electrode of the light emitting diode is connected to the light emitting low potential voltage; A light emitting diode display device.

11. The control circuit unit is A latch connected between a digital high potential voltage and a digital low potential voltage, and generating first and second output signals by using video data and a programming signal; A level shifter connected between a pin high potential voltage and a pin low potential voltage, and generating a third output signal for switching the first transistor by using the first and second output signals, and including; The light emitting diode display device according to Claim 10.

12. The control circuit unit includes an integrated level shifter connected between a pin high potential voltage and a pin low potential voltage, and generating a first output signal for switching the first transistor by using video data, a programming signal, and a light emitting signal; The light emitting diode display device according to Claim 10.

13. An N-type fourth transistor that switches the connection between the first data signal and the gate of the first transistor by a first programming signal; An N-type fifth transistor that switches the connection between the second data signal and the source of the first transistor by a second programming signal; Further including a first capacitor connected between the gate and the source of the first transistor; The light emitting diode display device according to Claim 10.

14. An N-type fourth transistor that switches the connection between the first data signal and the gate of the first transistor by a programming signal; An N-type fifth transistor that switches the connection between the second data signal and the source of the first transistor by the programming signal; A first capacitor connected between the gate and the source of the first transistor, further comprising: The light-emitting diode display device according to claim 10.

15. An N-type fourth transistor that switches the connection between the data signal and the gate of the first transistor by a programming signal; An N-type fifth transistor that switches the connection between the reference signal and the source of the first transistor by a sense signal; A first capacitor connected between the gate of the first transistor and the drain of the fifth transistor, further comprising: The light-emitting diode display device according to claim 10.

16. An N-type fourth transistor that switches the connection between the first output signal and the source of the first transistor by a reference signal; An N-type fifth transistor that switches the connection between the second output signal and the gate of the first transistor by the reference signal; A P-type sixth transistor that switches the connection between the light-emitting high-potential voltage and the source of the first transistor by a first light-emitting signal; An N-type seventh transistor that switches the connection between the drain of the first transistor and the positive electrode of the light-emitting diode by a second light-emitting signal; A first capacitor connected between the gate and the source of the first transistor, further comprising: The control circuit unit is connected between a digital high-potential voltage and a digital low-potential voltage, and includes a latch that generates first and second output signals using video data and a programming signal. The light-emitting diode display device according to claim 10.

17. An N-type fourth transistor that switches the connection between the first output signal and the gate of the first transistor by a reference signal; An N-type fifth transistor that switches the connection between the second output signal and the source of the first transistor by the reference signal; A P-type sixth transistor that switches the connection between the light-emitting high-potential voltage and the drain of the first transistor by a first light-emitting signal; An N-type seventh transistor that switches the connection between the source of the first transistor and the anode of the light-emitting diode by the second light-emitting signal, A first capacitor connected between the gate of the first transistor and the source of the first transistor, and further includes, The control circuit unit is connected between a digital high potential voltage and a digital low potential voltage, and includes a latch that generates first and second output signals using video data and a programming signal, The light-emitting diode display device according to claim 10.

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