Control device and control system

Abstract

To achieve compatibility that has high real time capability, yet allows executing an existing application program, when updating a control device.SOLUTION: The control device comprises an arithmetic processing device that executes a binary, a memory, a first cache that is provided inside of the arithmetic processing device, an I / O module, a second cache that holds a portion of the data processed by the I / O module, together with address information, and a transfer control unit. The transfer control unit exercises control for transferring the data held in the second cache to the memory with the timing at which the I / O module accesses the second cache, and making the data reflected in the memory, and exercises control for transferring the data held in the first cache to the second cache via the memory with the timing at which the binary executed by the arithmetic processing device accesses the designated address of the I / O module, and making the data reflected in the I / O module.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a control device and a control system that execute control arithmetic processing such as sensing data.

Background Art

[0002] In social infrastructure fields such as water treatment, plants, FA (Factory Automation), steel, and power generation, various control systems controlled by control devices have been put into practical use. For example, in water and sewage treatment, factories, steel mills, power generation plants, etc., a control system having a plurality of control devices connected to a main machine is responsible for processing. This control device executes control arithmetic processing in a CPU (Central Processing Unit) using sensing data input from the outside, and performs control by outputting a control command to the main machine as control data (signal).

[0003] In order to perform such control, there are cases where the arithmetic processing must be completed within the time of the control cycle defined in the control system, and input / output must be performed on the I / O (Input / Output). If it is not output within the time, the system may not operate normally, losses may occur, and the state of the system may become unstable. Therefore, the control device in such a control system is required to speed up the access between the CPU and the I / O.

[0004] On the other hand, such a control system often operates for decades or more. Therefore, even when updated to a new control device using the latest semiconductor and general-purpose OS (Operating System), it is required to have compatibility to execute the same application program that has been operating conventionally.

[0005] Patent Document 1 discloses a programmable controller including a storage unit that stores firmware and a control program executed by a programmable controller to be simulated, and hardware information necessary to simulate the hardware of the programmable controller to be simulated, and a controller emulator unit that emulates the operation of the hardware in the programmable controller to be simulated based on the hardware information. This controller emulator unit executes the firmware and the control program on the emulated hardware, and the firmware and the hardware information in the storage unit can be changed according to the programmable controller to be simulated.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, the programmable controller described in Patent Document 1 has a configuration in which the input / output of I / O is made to operate compatibly by an emulator that causes an application program executed by a programmable controller to be simulated to be executed on another programmable controller. When this arithmetic unit accesses I / O, it is necessary to access the I / O via a compatible I / O address assigned to the memory-mapped I / O area. Therefore, there is a problem that the latency (waiting time) for accessing I / O from the arithmetic unit becomes large, making it difficult to realize real-time compatible operation.

[0008] In view of the above situation, when updating a control device that executes control arithmetic processing of a control system, a mechanism that can realize compatibility to execute an existing application program while having high real-time performance has been desired.

Means for Solving the Problems

[0009] To solve the above problems, a control device according to one aspect of the present invention includes an arithmetic processing unit that executes binary, a memory that temporarily records data required for the processing of the arithmetic processing unit, a first cache provided in the arithmetic processing unit that holds a part of the data recorded in the memory, an I / O module that performs input / output processing on an external device, a bus interface that communicates with a bus connected to the I / O module, a second cache that holds a part of the data processed by the I / O module together with address information, and a transfer control unit that transfers data between the memory and the second cache. The transfer control unit transfers the data held in the second cache to the memory at the timing when the I / O module accesses the second cache, and performs control to reflect the data in the memory. When the binary is executed by the arithmetic processing unit, the arithmetic processing unit At the timing of accessing the specified address of the I / O module, the data held in the first cache is transferred to the second cache via the memory, and control is performed to reflect the data in the I / O module.

Effect of the Invention

[0010] According to at least one aspect of the present invention, when updating a control device that executes control arithmetic processing of a control system, it is possible to provide a mechanism that realizes compatibility for executing an existing application program while having high real-time performance. Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0012] Hereinafter, examples of embodiments for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, the same reference numerals are given to the same components or components having substantially the same functions, and redundant explanations are omitted.

[0013] <First Embodiment> First, the control system according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 8.

[0014] FIG. 1 is a diagram showing a configuration example of a control device 1A according to the first embodiment of the present invention. As shown in FIG. 1, the control device 1A includes a general-purpose CPU 1, a memory 2, a transfer control unit 3, an I / O cache 4, a bus interface 5, a bus 20, and an I / O module 21 connected to the bus 20.

[0015] The general-purpose CPU 1 (an example of an arithmetic processing unit) includes a memory map 6 composed of a virtual address 7 and a physical address 8. The address for accessing the memory map 6 is associated with a CPU cache 10 (an example of a first cache). In this control device 1A, a general-purpose OS 60 operates, and an emulator 61 operating on the general-purpose OS 60 causes an application program 62 to operate. As the general-purpose OS 60, for example, Windows (registered trademark), Linux (registered trademark), etc. can be used. The application program 62 is data in binary format (hereinafter referred to as "binary data"). The emulator 61 may be an emulation method for executing binary or an interpreter method for interpreting and executing the machine language of the application program one instruction at a time. The binary is defined in a data format executable by the general-purpose CPU 1. The I / O module 21 inputs sensing data from sensors or the like provided in the control system and outputs a control signal to the actuator. The I / O module 21 may be a programmable I / O with built-in microcontroller that enables program control, or an I / O module that has only a basic relay (conversion) function with input and output signal lines connected. The memory 2 temporarily holds data required for the processing of the general-purpose OS 60, the emulator 61, or the application program 62. The transfer control unit 3 controls data transfer between the memory 2 and the I / O cache 4. The I / O cache 4 (an example of a second cache) holds a part of the data processed by the I / O module 21 connected to the bus 20 via the bus interface 5 together with the address information.

[0016] Thus, in the arithmetic processing unit (general-purpose CPU 1), the first operating system (general-purpose OS 60) operates. The arithmetic processing unit executes an emulator or interpreter that executes binary including the address information of the I / O module.

[0017] Here, the memory map 6 of the control device 1A will be described with reference to FIG. 2. FIG. 2 is a diagram showing a configuration example of the memory map 6 of the control device 1A. The left side of Figure 2 shows an example of the memory space 11 assuming a microcontroller used in the control device of a conventionally operating control system. The memory space 11 uses the area from the leading "0x0000_0000" to "0xEFFF_FFFC" at an address represented by 32 bits. This area is all associated with the physical address 9. The areas indicated by I / O-1 starting from the address "0x1000_0000" and I / O-2 starting from the address "0x6000_0000" are areas where access from the microcontroller of the control system to the I / O module 21 is executed as memory-mapped I / O, and correspond one-to-one with the physical address.

[0018] On the other hand, the right side of Figure 2 shows an example of the memory space 12 assuming the general-purpose CPU 1 used in the control device 1A of the new control system. In the memory space 12, the area from "0x0000_0000" to "0xEFFF_FFFC" of the memory space 11 in the conventional control system is made to correspond to the virtual address 7. Thereby, without changing the address information to which the application program of the conventional control system has accessed the memory, it becomes possible to access the memory space 12 of the general-purpose CPU 1 of the new control system.

[0019] Here, the areas indicated by I / O-1 and I / O-2 are areas where access from the microcontroller of the conventional control system to the I / O module 21 is executed as memory-mapped I / O. However, since the areas indicated by I / O-1 and I / O-2 are different from the addresses of the I / O module 21 assigned by the general-purpose CPU 1, it is not possible to access the I / O module 21 only by making it correspond to the virtual address 7. Therefore, only the areas corresponding to I / O-1 and I / O-2 are converted from the virtual address 7 to the physical address 8 and made to correspond to the areas executed as memory-mapped I / O.

[0020] In this way, in the control device 1A, among the virtual address spaces of the memory assigned by the arithmetic processing unit (general-purpose CPU 1), the space accessed by the I / O module is assigned a physical address, and the I / O module accesses the first cache (CPU cache 10).

[0021] [Configuration of Transfer Control Unit] FIG. 3 is a diagram showing a configuration example of the transfer control unit 3 of the control device 1A. As shown in FIG. 3, the transfer control unit 3 includes a memory interface 30, a transmission unit 32, a reception unit 35, and an I / O cache interface 31.

[0022] The transmission unit 32 includes an update data transmission determination unit 34 and an update data transmission unit 33. The update data transmission determination unit 34 periodically checks with the I / O cache interface 31 whether there is update data in the I / O cache 4, and the I / O cache interface 31 returns to the update data transmission determination unit 34 whether there is update data. When there is update data, the update data transmission determination unit 34 receives the update data together with the reply on the presence or absence of the update data from the I / O cache interface 31. Next, the update data transmission determination unit 34 determines at a fixed period whether it is the timing to transmit the update data to the update data transmission unit 33. When the determination timing matches the transmissible timing, it is determined as the transmission timing and the process of transmitting the update data to the update data transmission unit 33 is performed. The update data transmission determination unit 34 receives a data update trigger signal (such as a periodic signal or an interrupt signal) together with the update data of the I / O module 21 from the I / O cache interface 31, and outputs the update data to the update data transmission unit 33 at the timing when the trigger signal becomes enabled. Note that the update data transmission determination unit 34 has a function of holding the previous update data (previous value). When the update data received from the I / O cache interface 31 is not new data compared with the previous value, the update data is not transmitted to the update data transmission unit 33.

[0023] When the update data transmission unit 33 outputs update data to the memory interface 30 as a write access to the memory 2, the memory interface 30 coordinates read access and write access and writes the update data to the memory 2.

[0024] In addition, the reception unit 35 includes a data reception unit 36 and an I / O data reflection unit 37. At the timing when a write access request from the memory 2 is transmitted to the transfer control unit 3, the data reception unit 36 receives write data from the memory 2 via the memory interface 30. Then, the data reception unit 36 outputs the received write data to the I / O data reflection unit 37. When the I / O data reflection unit 37 outputs the write data to the I / O cache interface 31, the I / O cache interface 31 performs access arbitration and writes the write data to the I / O cache 4. Since basically read processing and write processing cannot be executed simultaneously, access arbitration determines which processing is to be executed first.

[0025] [Configuration of I / O Cache] FIG. 4 is a diagram showing a configuration example of the I / O cache 4 of the control device 1A. As shown in FIG. 4, the I / O cache 4 includes a cache memory 40 and a cache control unit 41.

[0026] The cache memory 40 is configured to hold a plurality of pairs of tags and data. Tags n (in this example, n = 1 to 8) respectively correspond to data n. For example, a tag indicates unique address information generated from the address information of data. Well-known general techniques can be used to generate a tag from the address information of data.

[0027] When the tag corresponding to the address information output to the cache memory 40 matches the tag held in the cache memory 40, the cache control unit 41 outputs the corresponding data as a cache hit. When the tag corresponding to the address information output to the cache memory 40 does not match the held tag, a cache miss occurs.

[0028] This cache control unit 41 includes an address extraction unit 42, a tag determination unit 43, an I / O update control unit 44, and a memory update control unit 45. The I / O update control unit 44 and the memory update control unit 45 are functions that are newly added according to the present invention and do not exist in the prior art. The address extraction unit 42 is connected to a bus composed of dozens of signal lines. For example, the bus is configured by combining an address bus for transmitting address information, a data bus for transmitting the main body of data, and a control bus for transmitting control signals such as timing.

[0029] The address extraction unit 42 generates a tag based on the address information for the bus access included in the data input from the bus interface 5 and outputs it to the tag determination unit 43. When the tag corresponding to the tag generated by the address extraction unit 42 is not held in the cache memory 40, the tag determination unit 43 regards it as a cache miss and updates the tag and data in the cache memory 40. That is, when there is a cache miss, the tag determination unit 43 generates a tag with the acquired bus address information and registers a new tag and input data pair in the cache memory 40. When the content held in the cache memory 40 is updated due to a cache miss, the memory update control unit 45 transmits the updated content of the cache memory 40 to the transfer control unit 3 to request data update.

[0030] Also, when write data is transmitted from the transfer control unit 3 to the I / O cache 4, the address extraction unit 42 generates a tag and outputs it to the tag determination unit 43. When the corresponding tag is held in the cache memory 40 (cache hit), the tag determination unit 43 updates the data associated with the corresponding tag in the cache memory 40. When the corresponding tag is not held (cache miss), the tag determination unit 43 updates the tag and data in the cache memory 40. When the content held in the cache memory 40 is updated due to a cache miss, the I / O update control unit 44 transmits the updated content of the cache memory 40 to the I / O module 21 via the bus interface 5 to request data update.

[0031] When updating the content of this cache memory 40, if there is an unused area in the cache memory 40, the unused area may be used. If there is no unused area, a replacement algorithm such as LRU (Least Recently Used) may be used.

[0032] As described above, in the control device 1A, the second cache (I / O cache 4) includes a cache memory and a cache control unit that determines whether corresponding data is held in the cache memory based on a tag generated from an address in an access from a transfer control unit or an I / O module. When the corresponding data is not held in the cache memory, the cache control unit is configured to transmit the data to the transfer control unit or the I / O module and request an update of the data.

[0033] [Configuration of Bus Interface] FIG. 5 is a diagram showing a configuration example of the bus interface 5 of the control device 1A. As shown in FIG. 5, the bus interface 5 includes an input I / O processing unit 51 and an output I / O processing unit 52, and is connected to the bus 20 via a bus signal line 53 in which a transmission direction and a reception direction are set. An I / O module 21 is connected to the bus 20 via a bus signal line 54 in which a transmission direction and a reception direction are set.

[0034] When the I / O module 21 transmits data to the bus 20 via the bus signal line 54, the input I / O processing unit 51 of the bus interface 5 receives the data via the bus signal line 53 and performs predetermined processing. Thereafter, the input I / O processing unit 51 transmits the data to the I / O cache 4. When the I / O cache 4 transmits data to the bus interface 5, the output I / O processing unit 52 transmits the data to the bus 20 via the bus signal line 53, and the I / O module 21 receives the data via the bus signal line 54.

[0035] [Operation Example When the Present Invention is Not Applied] FIG. 6 is a timing chart showing an example of the operation of the control device when accessing from the general-purpose CPU 1 of the control device to the I / O module 21 without applying the present invention. The control device without applying the present invention corresponds to, for example, a configuration in which the transfer control unit 3 and the I / O cache 4 are deleted from the configuration of the control device 1A.

[0036] The uppermost row "general-purpose CPU 1" in the timing chart 2A shown in FIG. 6 represents the access transaction generated by the general-purpose CPU 1. Here, there are a read transaction from when the general-purpose CPU 1 outputs a read request (denoted as RR) until the read data (denoted as RD) is returned, and a write transaction from when the general-purpose CPU 1 outputs a write request (denoted as WR) until the write acknowledgment (denoted as WA) is returned.

[0037] The second row from the top "CPU cache 10" in the timing chart 2A represents the data held in the CPU cache 10. The third row from the top "memory 2" in the timing chart 2A represents the data held in the memory 2. The fourth row from the top "bus I / F 5" in the timing chart 2A represents the access transaction occurring at the bus interface 5. Here, there are RR and RD, and WR and WA. The lowermost row "I / O module 21" in the timing chart 2A represents the access transaction occurring at the I / O module 21. Here, there are RR and RD, and WR and WA.

[0038] In a control device to which the present invention is not applied, when a read request RR is output from the general-purpose CPU 1 to the I / O module 21, the read request RR is transmitted to the I / O module 21 via the bus interface 5, and the I / O module 21 outputs read data RD. The read data RD output by the I / O module 21 is transmitted to the general-purpose CPU 1 via the bus interface 5. At this time, the read access time from when the general-purpose CPU 1 generates a read access request (read request RR) until the read data RD is returned to the general-purpose CPU 1 is denoted as "t ir ".

[0039] Also, when a write request WR is output from the general-purpose CPU 1 to the I / O module 21, the write request WR is transmitted to the I / O module 21 via the bus interface 5, and writing (write processing) of write data (not shown) to the I / O module 21 is executed. When the write processing is completed, the I / O module 21 outputs a write acknowledge WA (positive response). The write acknowledge WA output by the I / O module 21 is transmitted to the general-purpose CPU 1 via the bus interface 5. At this time, the write access time from when the general-purpose CPU 1 generates a write request WR until the write acknowledge WA is returned to the general-purpose CPU 1 is denoted as "t iw ".

[0040] [Operation example when the present invention is applied] (Without write error) On the other hand, FIG. 7 is a timing chart showing an example of the operation of the control device 1A when accessing from the general-purpose CPU 1 to the I / O module 21 in the control device 1A according to the first embodiment of the present invention (without write error).

[0041] The rows in the first, second, third, sixth, and seventh stages from the top of the timing chart 2B shown in FIG. 7 are the same as those described in FIG. 6. The "Transfer Control Unit 3" in the fourth row from the top of Timing Chart 2B represents the access transactions generated by the Transfer Control Unit 3. Here, there is an update request (denoted as UR) to update the content of the I / O cache 4 to the memory 2. The "I / O Cache 4" in the fifth row from the top of Timing Chart 2B represents the data held in the I / O cache 4. Here, there are transfer data (denoted as TD) and a write request WR.

[0042] When a transfer request (denoted as TR) occurs in the I / O module 21, the updated content of the I / O module 21 is held as transfer data TD in the I / O cache 4 via the bus interface 5.

[0043] When the Transfer Control Unit 3 generates an update request UR for the I / O cache 4 and the content of the I / O cache 4 has been updated with the transfer data TD, the Transfer Control Unit 3 sends TD from the I / O cache 4 to the memory 2. Then, TD is transferred from the memory 2 to the CPU cache 10, and the content of the CPU cache 10 is updated with TD.

[0044] Here, when a read request RR is generated from the general-purpose CPU 1 to the I / O module 21, since the updated content of the I / O module 21 is held as TD in the CPU cache 10, TD in the CPU cache 10 is sent to the general-purpose CPU 1 to complete the read access. At this time, the read access time from when the general-purpose CPU 1 generates the read request RR until the read data (transfer data TD) is returned is denoted as "t" cr ".

[0045] Also, when a write request WR is output from the general-purpose CPU 1 to the I / O module 21, when the WR is held in the CPU cache 10, a write acknowledgment WA is returned from the CPU cache 10 to the general-purpose CPU 1. Also, the WR in the CPU cache 10 is reflected in the memory 2, and the WR is held in the I / O cache 4 by an update request UR to the memory 2 from the transfer control unit 3. The WR is written to the I / O module 21 via the bus interface 5, and the WA from the I / O module 21 is held in the I / O cache 4 via the bus interface 5. At this time, the write access time from when the general-purpose CPU 1 generates the write request WR until the write acknowledgment WA is returned is denoted as "t cw」 as shown.

[0046] Here, in the control device to which the present invention is not applied, as shown in the timing chart 2A of FIG. 6, when accessing the I / O module 21 from the general-purpose CPU 1, it is always necessary to access the I / O module 21 via the bus interface 5. Therefore, both the read access time t ir and the write access time t iw have large latencies.

[0047] On the other hand, in the control device 1A (FIG. 1) to which the present invention is applied as shown in the timing chart 2B of FIG. 7, when accessing the I / O module 21 from the general-purpose CPU 1, the data to be obtained by accessing the I / O module 21 is held in the CPU cache 10. Therefore, the latency is only the time required for access from the general-purpose CPU 1 to the CPU cache 10, and the read access time t cr and the write access time t cw are respectively much smaller compared to the read access time t ir and the write access time t iw when the present invention is not applied.

[0048] Thus, in the write access from the general-purpose CPU 1 to the I / O module 21, since data write failures are extremely rare, by immediately responding with a write acknowledgment WA from the CPU cache 10 on the premise that there are no data write failures, the latency of the compatible access from the general-purpose CPU 1 to the I / O module 21 can be suppressed.

[0049] (With write error) By the way, in the operation example at the time of the write access in FIG. 7, on the premise that no write error occurs anywhere on the path from the general-purpose CPU 1 to the I / O module 21, a write acknowledgment WA was output from the CPU cache 10 before the write was completed. However, it cannot be asserted that the possibility of a write error, such as the write not being performed or the write time exceeding the allowable time (timeout), is zero. Therefore, an example of the operation at the time of write access when a write error occurs will be described with reference to FIG. 8.

[0050] FIG. 8 is a timing chart 2B1 showing another example of the operation of the control device 1A (with a write error) when accessing from the general-purpose CPU 1 to the I / O module 21 in the control device 1A. In the write access on the right side of FIG. 8, when a write request WR is output from the general-purpose CPU 1 to the I / O module 21, the point where the write request WA is written to the I / O module 21 is the same as the operation at the time of the write access on the right side of FIG. 7.

[0051] Here, assume that data writing fails in the I / O module 21. In the example of FIG. 8, although data writing fails in the I / O module 21, the bus interface 5 outputs a write acknowledge WA to the I / O cache 4. If the I / O cache 4 cannot receive the write acknowledge WA from the bus interface 5 before the allowable time elapses after receiving the write request WR, it is determined that data writing has failed in the I / O module 21. The causes of the write failure in the I / O module 21 are assumed to be various, such as being unable to write to the I / O module 21 or the write time exceeding the allowable time.

[0052] Then, the bus interface 5 outputs an error signal Werror indicating a write failure as the write acknowledge WA to the I / O cache 4. When the content of the I / O cache 4 is updated with the error signal Werror, the transfer control unit 3 transmits the error signal Werror held in the I / O cache 4 to the memory 2. As a result, the error signal Werror is transferred from the memory 2 to the CPU cache 10, and the content of the CPU cache 10 is updated with the error signal Werror. The general-purpose CPU 1 can recognize that a write error has occurred in the I / O module 21 based on the error signal Werror held in the CPU cache 10.

[0053] Note that the method of notifying a write failure is not limited to the method of determining a timeout in the I / O cache 4 shown in the example of FIG. 7. For example, when writing fails in the I / O module 21, the I / O module 21 itself may output the error signal Werror. Alternatively, the general-purpose CPU 1 may output a request for confirming the success or failure of writing in the I / O module 21 after outputting a write request.

[0054] As described above, the control device according to the first embodiment of the present invention includes an arithmetic processing unit (e.g., general-purpose CPU 1) that executes binaries (e.g., application program 62, emulator 61, general-purpose OS 60, etc.), a memory that temporarily records data required for the processing of the arithmetic processing unit, a first cache (e.g., CPU cache 10) provided in the arithmetic processing unit that holds a part of the data recorded in the memory, an I / O module that performs input / output processing with respect to external devices, a bus interface that communicates with a bus connected to the I / O module, a second cache (e.g., I / O cache 4) that holds a part of the data processed by the I / O module together with address information, and a transfer control unit that transfers data between the memory and the second cache. The transfer control unit transfers the data held in the second cache to the memory at the timing when the I / O module accesses the second cache, and performs control to reflect the data in the memory. When the binary is executed by the arithmetic processing unit, the arithmetic processing unit At the timing of accessing the designated address of the I / O module, it is configured to transfer the data held in the first cache to the second cache via the memory and perform control to reflect the data in the I / O module.

[0055] According to the control device according to the first embodiment described above, in implementing a control system by adopting a general-purpose CPU and a general-purpose OS, it is possible to suppress the latency of compatible access to the I / O module when operating a conventional application program. Thereby, it is possible to provide a control device that realizes compatible operation while ensuring real-time performance. More specifically, in this embodiment, on a general-purpose architecture (for example, a PC), an application program (existing) of a different architecture and an I / O module are made to operate compatibly without modification, and the access latency from the general-purpose CPU to the I / O module and the access latency from the I / O module to the general-purpose CPU are suppressed. As a result, when updating the control device that executes the control arithmetic processing of the control system, it is possible to provide a mechanism that realizes compatibility that can execute an existing application program while having high real-time performance. Therefore, it is possible to reduce the redesign man-hours and respond to the replacement demand from off-the-shelf products at low cost.

[0056] Hereinafter, the second to fifth embodiments will be described. Even if each component included in the control device 1A according to the first embodiment is not shown in each control device according to the second to fifth embodiments, it is considered that each component included in the control device 1A is also included in the control device according to each embodiment.

[0057] <Second Embodiment> Next, the control device according to the second embodiment of the present invention will be described with reference to FIG. 9. FIG. 9 is a diagram showing a configuration example of a control device 1B according to the second embodiment of the present invention. As shown in FIG. 9, the control device 1B is different from the control device 1A in FIG. 1 in that a real-time OS 63 operating in the I / O module 21 is added.

[0058] In the I / O module 21, a real-time OS 63 (the second operating system) operates. This real-time OS 63 is configured to guarantee the worst-case response time, unlike the general-purpose OS 60 (the first operating system). Therefore, the I / O module 21 performs processes such as accessing the bus 20 at a timing independent of the general-purpose CPU 1, resulting in a configuration with enhanced programmability.

[0059] According to the control device according to the second embodiment, even when the response performance and latency deteriorate due to an increase in the load of the general-purpose OS while an application program is operating with the general-purpose OS operating on the general-purpose CPU, the I / O module can operate safely in real time. For example, even when a stop signal for the control system cannot be received from the general-purpose CPU 1 for some reason, the I / O module 21 can stop the control system within the worst-case response time by the real-time OS 63.

[0060] <The Third Embodiment> Next, a control device according to the third embodiment of the present invention will be described with reference to FIG. 10. FIG. 10 is a diagram showing a configuration example of a control device 1C according to the third embodiment of the present invention. As shown in FIG. 10, the control device 1C is different from the control device 1A in FIG. 1 in that a physical address register 80 is added.

[0061] The physical address register 80 is a register that holds the value 81 of the physical address 8 corresponding to the access space of the I / O module 21 in the memory map 6 of the general-purpose CPU 1. The value 81 of the physical address 8 is transferred to the physical address register 80 by a device driver 64 (program) implemented in the general-purpose OS 60 and held in the physical address register 80. The update data transmission unit 33 (FIG. 3) of the transfer control unit 3 reads the value 81 of the physical address 8 from the physical address register 80 and performs data transfer to the general-purpose CPU 1 using the value 81 of the physical address 8 of the I / O module 21 that can be recognized by the general-purpose OS 60.

[0062] In this way, the control device 1C includes a register (physical address register 80) that holds an address value obtained by converting a virtual address for accessing the I / O module into a physical address from among the virtual address spaces of the memory, and a device driver program that transfers the converted address value to the transfer control unit.

[0063] According to the control device according to the third embodiment, when a general-purpose OS operating on a general-purpose CPU adopts a virtual memory system, by passing the physical address information required when accessing from the I / O module to the general-purpose OS to the transfer control unit, it becomes possible to access efficiently. For example, conventionally, the I / O module side used the value of the physical address determined at the beginning, but according to this embodiment, it is also possible to cope with changes in the physical address that occur during the operation of the control system.

[0064] Note that in the third embodiment, an example in which a device driver program is used to transfer the address value to the physical address register has been shown, but a dedicated signal line for transfer may be implemented. For example, the physical address register and the transfer control unit may be connected by a dedicated signal line.

[0065] <Fourth Embodiment> Next, a control device according to a fourth embodiment of the present invention will be described with reference to FIGS. 11 to 14. FIG. 11 is a diagram showing a configuration example of a control device 1D according to the fourth embodiment of the present invention. As shown in FIG. 11, the control device 1D is different from the control device 1A in FIG. 1 in that a second I / O module 22 is added separately from the I / O module 21.

[0066] FIG. 12 is a diagram showing a configuration example of the bus interface 15 of the control device 1D. The bus interface 15 shown in FIG. 12 is different from the bus interface 5 shown in FIG. 5 in the first embodiment in that a priority determination mode register 56 and a priority determination unit 57 are added.

[0067] The priority determination mode register 56 is a register that stores an algorithm (rule) for determining which I / O module to prioritize when multiple I / O modules are connected to the bus 20 and access requests may occur simultaneously. For example, in the case where I / O module 21 and I / O module 22 generate access requests simultaneously, there are cases where I / O module 21 is always prioritized, cases where I / O module 22 is always prioritized, cases where the priority order is alternately changed in a round-robin manner, and so on.

[0068] The priority determination unit 57 transmits the access request of I / O module 21 or I / O module 22 input to the input I / O processing unit 51 to the I / O cache 4 according to the content of the algorithm (the value of the mode register) stored in the priority determination mode register 56.

[0069] In this way, in the control device 1D, there are multiple I / O modules, and the bus interface has a mode register (priority determination mode register 56) that stores an algorithm for determining the priorities of the multiple I / O modules. Then, the bus interface performs control to arbitrate and determine the access priorities of the multiple I / O modules according to the above algorithm, and as a result of the arbitration, the access of the I / O module determined to have a higher priority is configured to be reflected in the second cache (I / O cache 4).

[0070] [Example when the present invention is not applied] FIG. 13 is a timing chart showing an example of the operation of a control device when the present invention is not applied in the case of accessing two I / O modules 21 and 22 from the general-purpose CPU 1 of the control device. Here, the control device when the present invention is not applied corresponds to a configuration in which, for example, the transfer control unit 3 and the I / O cache 4 are deleted from the configuration of the control device 1A.

[0071] The first, second, third, and fourth rows from the top of the timing chart 2C shown in FIG. 13 are as described in FIG. 6, and the "I / O module 21" in the fifth row corresponds to the row of the I / O module 21 (example of the first I / O module) in FIG. 6. Here, there are a read request RR1 and read data RD1. The "I / O module 22" at the bottommost row of the timing chart 2C represents the access transaction that occurs in the I / O module 22 (example of the second I / O module). Here, there are a read request RR2 and read data RD2.

[0072] In a control device to which the present invention is not applied, when a read request RR1 is output from the general-purpose CPU 1 to the I / O module 21, a read access from the general-purpose CPU 1 is performed in the same manner as the description of the timing chart 2A in FIG. 6. At this time, the time from when the general-purpose CPU 1 generates a read access request (read request RR1) until the read data RD1 is returned is represented as "t" ir ".

[0073] Also, when a read request RR2 is output from the general-purpose CPU 1 to the I / O module 22, a read access from the general-purpose CPU 1 is performed in the same manner as the description of the timing chart 2A in FIG. 6. At this time, the time from when the general-purpose CPU 1 generates a read access request (read request RR2) until the read data RD2 is returned is also "t" ir ".

[0074] [Operation example when the present invention is applied] On the other hand, FIG. 14 is a timing chart showing an example of the operation of the control device 1D when accessing the I / O modules 21 and 22 from the general-purpose CPU 1 in the control device 1D according to the fourth embodiment of the present invention. In the example of FIG. 14, it is assumed that the I / O module 21 has a higher priority.

[0075] The first, second, third, fourth, fifth, seventh, and eighth rows from the top of the timing chart 2D shown in FIG. 14 are as described in FIGS. 7 and 13. The sixth row from the top of the 2D timing chart, "Bus I / F15", represents the access transactions occurring at bus interface 15. Here, there are transfer requests TR1 and TR2.

[0076] When a transfer request TR1 occurs in the I / O module 21, the updated content of the I / O module 21 is held as transfer data TD1 in the I / O cache 4 via the bus interface 5. Similarly, when a transfer request TR2 occurs in the I / O module 22, the updated content of the I / O module 22 is held as transfer data TD2 in the I / O cache 4 via the bus interface 5.

[0077] When the transfer control unit 3 generates an update request UR for the I / O cache 4, if the content of the I / O cache 4 has been updated with transfer data TD1 and TD2, the transfer control unit 3 sends TD1 and TD2 from the I / O cache 4 to the memory 2. Then, TD1 and TD2 are transferred from the memory 2 to the CPU cache 10, and the content of the CPU cache 10 is updated with TD1 and TD2.

[0078] Here, when a read request RR1 is generated from the general-purpose CPU1 to the I / O module 21, since the updated content of the I / O module 21 is held as TD1 in the CPU cache 10, TD1 of the CPU cache 10 is sent to the general-purpose CPU1 to complete the read access. At this time, the time from when the general-purpose CPU1 generates the read request RR1 until the read data (transfer data TD1) is returned is represented as "t" cr ".

[0079] Also, when a read request RR2 is generated from the general-purpose CPU1 to the I / O module 22, since the updated content of the I / O module 22 is held as TD2 in the CPU cache 10, TD2 of the CPU cache 10 is sent to the general-purpose CPU1 to complete the read access. At this time, the time from when the general-purpose CPU1 generates the read request RR2 until the read data (transfer data TD2) is returned is also "t"cr It becomes "".

[0080] Here, in the control device to which the present invention is not applied, as shown in the timing chart 2C of FIG. 13, when accessing two I / O modules 21 and 22 from the general-purpose CPU 1, it is always necessary to access each of the I / O modules 21 and 22 via the bus interface 5. Therefore, the latency of the read access time t ir becomes large.

[0081] On the other hand, in the control device 1D (FIG. 11) to which the present invention is applied, as shown in the timing chart 2D of FIG. 14, when accessing two I / O modules 21 and 22 from the general-purpose CPU 1, the data to be obtained by accessing each of the I / O modules 21 and 22 is collectively held in the CPU cache 10. Therefore, the latency is only the time required for access from the general-purpose CPU 1 to the CPU cache 10, and the read access time t cr is significantly smaller than the read access time t ir when the present invention is not applied. Also, the general-purpose CPU 1 can preferentially obtain the transfer data TD1 of the I / O module 21.

[0082] As described above, according to the control device according to the fourth embodiment, in the implementation of the control system by adopting the general-purpose CPU and the general-purpose OS, even when a conventional application program is operated on a plurality of I / O modules, the latency of the compatible access can be suppressed. Thereby, it is possible to provide a control device that realizes compatible operation while guaranteeing real-time performance. In the fourth embodiment, an example in which there are two I / O modules has been described, but the configuration may include three or more I / O modules.

[0083] <Fifth Embodiment> Next, the control device according to the fifth embodiment of the present invention will be described with reference to FIGS. 15 to 16. FIG. 15 is a diagram showing a configuration example of a transfer control unit 13 in a control device according to a fifth embodiment of the present invention. As shown in FIG. 15, the transfer control unit 13 is different in that a flag setting unit 74 and a state determination unit 70 in a transmission unit 32E are added as compared with the transfer control unit 3 described with reference to FIG. 3 in the first embodiment. This transfer control unit 13 can be applied to the control devices 1A to 1D according to the first to fourth embodiments. Each control device is assumed to execute periodic processing.

[0084] The flag setting unit 74 in the transmission unit 32E sets a flag whose value is updated when the general-purpose CPU 1 accesses the data transmitted from the I / O module 21 to the general-purpose CPU 1. This flag is, for example, 1-bit data. For example, when the I / O module 21 causes an access to the general-purpose CPU 1 (for example, the time T shown in FIG. 16 0 , time T 1 ), a flag “0” indicating the start of access is generated. Then, if the flag is “0”, it may be set that there is no access from the general-purpose CPU 1, and if the flag is “1”, there is access from the general-purpose CPU 1.

[0085] The state determination unit 70 includes a threshold time register 73, a flag determination unit 71, and an abnormality determination unit 72. The threshold time register 73 is a register that stores a threshold time (threshold value) that serves as a determination criterion for the I / O module 21 to shift to safety control when there is no response from the general-purpose CPU 1 to the I / O module 21 for a certain period of time in a control device that performs periodic processing. The flag determination unit 71 determines whether or not the flag set when an access occurs from the I / O module 21 by the flag setting unit 74 is updated depending on the presence or absence of access from the general-purpose CPU 1. For example, each time there is an access from the general-purpose CPU 1, the subscript increases from [F0] (no access) to [F1], [F2], ···. In the abnormality determination unit 72, when the state in which it is determined by the flag determination unit 71 that the flag is not updated exceeds the threshold time set in the threshold time register 73, it is determined that an abnormality has occurred in the control device, and an abnormality signal 76 is output to the I / O module 21.

[0086] FIG. 16 is a timing chart showing an example of the operation of a control device including a transfer control unit 13 according to the fifth embodiment. FIG. 16 shows an example of the operation of the control device when the general-purpose CPU 1 is abnormal. In the figure, time T 0 and time T 1 interval, time T 1 and time T 2 interval respectively indicate the interval (period) of the minimum guaranteed operation time.

[0087] The first, second, third, sixth, and seventh rows from the top of the timing chart 2E in FIG. 16 are as described with reference to FIG. 7. The "transfer control unit 13" in the fourth row from the top of the timing chart 2E represents the access transaction generated by the transfer control unit 13. Here, there are an update request UR for updating the content of the I / O cache 4 to the memory 2, a safety request (denoted as SR) for requesting the I / O module 21 to transition to safety control, and transfer data TD.

[0088] When a transfer request TR occurs in the I / O module 21, the updated content of the I / O module 21 is held in the I / O cache 4 as transfer data TD via the bus interface 5. When an update request UR for the I / O cache 4 is generated in the transfer control unit 13, if the content of the I / O cache 4 has been updated with TD, the transfer control unit 13 transmits TD from the I / O cache 4 to the memory 2. At this time, a flag [F0] indicating that the general-purpose CPU 1 has not accessed this data (TD) is added to TD and held in the memory 2 by the flag setting unit 74 (FIG. 15). Then, the content of the CPU cache 10 is updated to TD[F0].

[0089] Here, in the transfer control unit 13, the abnormality determination unit 72 determines that there is an abnormality in the general-purpose CPU 1 when the flag [F0] of the target TD in the memory 2 is not updated during the time set by the threshold time register 73 from the time T 0 (that is, when there is no access from the general-purpose CPU 1). In response to the determination result of the abnormality determination unit 72, the transfer control unit 13 transfers the safety request SR to the memory 2 and acquires the transfer data TD[F0] from the memory 2. Then, the transfer control unit 13 transmits the transfer data TD[F0] acquired from the memory 2 and the abnormality signal 76 output by the abnormality determination unit 72 to the bus interface 5. Then, the I / O module 21 that has received the abnormality signal 76 from the bus interface 5 shifts to safety control.

[0090] Next, when a read request RR is generated from the general-purpose CPU 1 to the I / O module 21 at the time T 1 , the updated content of the I / O module 21 is held in the CPU cache 10 as TD[F0]. Therefore, the general-purpose CPU 1 changes the flag [F0] of TD[F0] in the CPU cache 10 to [F1] and reads TD[F1] from the CPU cache 10. Also, TD[F1] is transmitted from the CPU cache 10 to the memory 2. In this way, the TD[F1] with the updated flag is reflected in the CPU cache 10 and the memory 2, and the read access of the general-purpose CPU 1 is completed.

[0091] As described above, in the control device according to the fifth embodiment of the present invention, the transfer control unit has a threshold time register that holds a threshold time for determining the presence or absence of access from the arithmetic processing unit (general-purpose CPU 1) to the I / O module within a certain period of time. Then, the transfer control unit sets a flag indicating the start of access at the time when the I / O module generates access to the arithmetic processing unit, and when it is determined that the time from the time when the I / O module generates access to the arithmetic processing unit to the time when the arithmetic processing unit refers to the flag exceeds the threshold time, controls to output an abnormality signal indicating an abnormality of the control device to the I / O module. The I / O module shifts to safety control when it receives the abnormality signal.

[0092] According to the control device according to the fifth embodiment described above, in the implementation of the control system by adopting a general-purpose CPU and a general-purpose OS, even when a response cannot be returned to the I / O module within a predetermined response time, such as when the load on the general-purpose CPU is high, the state of the flag is determined and safety control is performed on the I / O module. Thereby, it is possible to provide a highly safe control device while ensuring real-time performance.

[0093] <Implementation Example> Next, an implementation example applying the control devices 1A to 1D according to the first to fifth embodiments described so far will be described with reference to FIG. 17.

[0094] FIG. 17 is a diagram showing a configuration example of an implementation example of the control devices 1A to 1D according to the first to fifth embodiments. The control device 200 shown in FIG. 17 is configured by inserting various modules into a plurality of slots 221, 222, etc. connected to a backplane 220 (mounting substrate). A CPU module 210, which is a device equipped with a general-purpose CPU 1, a memory 2, a transfer control unit 3, and an I / O cache 4, and I / O modules 211, 212 are mounted on the backplane 220, respectively. The CPU module 210 and the I / O modules 211, 212 are each equipped with an interface for connecting to other devices. In general, a power supply module is also required when implementing such a control device, but the description of the power supply module is omitted in the example of FIG. 17.

[0095] As shown in each embodiment, by adopting a configuration in which a module equipped with a general-purpose CPU 1 (for example, the CPU module 210) and a module equipped with an I / O control function (for example, the I / O modules 211, 212) are connected, the control device can be configured in various forms.

[0096] Furthermore, by adopting the same connection interface as the conventional control device for the backplane or the like, while using the conventional module as it is, it is possible to connect to a new module employing the general-purpose CPU 1 and realize partial function expansion. Also, since partial function expansion can be realized, it becomes possible to gradually expand the functions of the control system.

[0097] Note that the number of installed CPU modules, I / O modules, etc. in each embodiment is not limited to the numbers described above, and can be expanded and implemented in any number.

[0098] Next, Application Examples 1 to 4 in which the control devices 1A to 1D according to the first to fifth embodiments are applied to the control of various facilities such as a water treatment system will be described with reference to FIGS. 18 to 21. The control system has one or more of the above-described control devices, and operates sensors and control devices (actuators, switchboards, various facilities, main and auxiliary machines of power generation facilities, etc.).

[0099] <Application Example 1> FIG. 18 is a diagram showing a configuration example of Application Example 1 when the control devices 1A to 1D are applied to a water treatment system. The water treatment system 1000 controls and monitors the control devices 400 and 401 connected to the control network 601 by the monitoring device 500 and the cloud server 501 connected to the information network 600.

[0100] The control device 400 controls the high-voltage panel 800 and the low-voltage panel 801 from the PI / O device 700 and the PI / O device 701 via the field bus 602, respectively. The control device 401 adjusts the amount of water sent out by the pump 802 and the blower 803 via the sequencer 702. Also, the water quality information obtained by the water quality meter 804 and the field image data captured by the camera 805 are collected by the sequencer 703 and acquired by the control device 401. These control devices 400 and control device 401 are connected via the control network 601 and share data. The control devices 1A to 1D can be applied to the control devices 400 and 401 to realize a water treatment system that requires scalability and real-time compatibility.

[0101] Here, in order to perform water treatment efficiently, the CPU module 300 of the control device 400 and the CPU module 301 of the control device 401 adopt a general-purpose CPU 1 and a general-purpose OS 60, and are configured to enable data sharing between devices via a control network 601.

[0102] On the other hand, since the control device 400 controls the conventional PI / O devices 700 and 701 connected to the high-voltage panel 800 and the low-voltage panel 801 via the field bus 602, it is necessary to perform compatible operation with the conventional input / output processing. In addition, since the control device 401 controls the conventional sequencer 702 connected to the pump 802 and the blower 803, it is necessary to perform compatible operation with the conventional output processing. Further, since the control device 401 controls the conventional sequencer 703 that controls the water quality meter 804 and the camera 805, it is necessary to perform compatible operation with the conventional input processing.

[0103] Therefore, in the water treatment system 1000 having the configuration shown in FIG. 18, in order to achieve both high versatility and scalability and compatibility with conventional processing, the control devices 400 and 401 to which the control device according to each embodiment of the present invention is applied are used. Furthermore, the CPU modules 300 and 301 using the general-purpose CPU 1 (FIG. 17) execute compatible operation by binary emulation, and the I / O modules 900, 901, and 902 execute transfer processing so that the general-purpose CPU can access data of various devices with low latency. Thereby, a water treatment system that requires versatility, scalability, and real-time compatibility can be realized.

[0104] <Application Example 2> FIG. 19 is a diagram showing a configuration example of Application Example 2 when the control devices 1A to 1D are applied to the hot rolling facility of a steel control system. The steel control system 1010 controls and monitors the control devices 410, 411, and 412 by means of a monitoring terminal 510 connected to a control network 610. The steel heated in the heating furnace 811 is fed into the hot rolling facility 810. The temperature of the heating furnace 811 obtained by the temperature sensor 710 is acquired by the control device 400.

[0105] The control device 410 controls the PI / O device 711 and adjusts the rotational speed of the rough rolling mill 812. The control device 411 controls the PI / O device 712 and adjusts the rotational speed and tension of the finishing rolling mill 813. The temperature of the cooling facility 814 obtained by the temperature sensor 713 is acquired by the control device 412. The control device 412 controls the PI / O device 714 and adjusts the rotational speed and direction of the coiler 815. By applying the control devices 1A to 1D to the control devices 410 to 412, a steel control system that requires extensibility and real-time compatibility can be realized.

[0106] Here, in order to refine high-quality steel plates, the CPU modules 310 of the control device 410, the CPU module 311 of the control device 411, and the CPU module 312 of the control device 412 each adopt a general-purpose CPU 1 and a general-purpose OS 60, and are configured such that the monitoring terminal 510 can acquire the state of the hot rolling facility 810 via the control network 610.

[0107] On the other hand, since the control device 410 controls the conventional PI / O device 711 connected to the rough rolling mill 812, it is necessary to perform compatible operation with the conventional input / output processing. Also, since the control device 411 controls the conventional PI / O device 712 connected to the finishing rolling mill 813, it is necessary to perform compatible operation with the conventional input / output processing. Furthermore, since the control device 412 controls the conventional PI / O device 714 connected to the coiler 815, it is necessary to perform compatible operation with the conventional input / output processing.

[0108] Therefore, in the steel control system 1010 shown in FIG. 19, in order to achieve both high versatility and extensibility and compatibility with conventional processing, a configuration is adopted in which the control devices 410 to 412 to which the control devices according to the embodiments of the present invention are applied are used. Furthermore, the CPU modules 310, 311, and 312 using the general-purpose CPU 1 (Fig. 17) perform compatible operations by binary emulation, and the I / O modules 910, 911, and 912 execute transfer processing so that the general-purpose CPU 1 can access the data of various devices with low latency. Thereby, a steel control system that requires versatility, expandability, and real-time compatibility can be realized.

[0109] <Application Example 3> Fig. 20 is a diagram showing a configuration example of Application Example 3 when the control devices 1A to 1D are applied to the FA system. The FA system 1020 controls and monitors the control device 420 by the monitoring terminal 520 connected to the information network 620. The products placed on the belt conveyor 820 are photographed by the camera 821, and the shape data is processed by the PLC 720. The PLC 721 controls the picking robot 822 and arranges it at a predetermined position. The belt conveyor 820 rotates at a predetermined speed by the conveyor motor 823 controlled by the PLC 722, and the painting robot 824 controlled by the PLC 723 paints the surface of the product. By applying the control devices 1A to 1D to the control device 420, an FA system that requires expandability and real-time compatibility can be realized.

[0110] Here, in this FA system, a plurality of PLCs 720 to 723 necessary for controlling the belt conveyor 820 are collectively controlled by the control device 420. Therefore, in order to perform high-quality painting, it is necessary for the control device 420 to perform high-performance and real-time processing. Therefore, the control device 420 of the FA system 1020 shown in FIG. 20 is configured to connect a CPU module 320 employing a general-purpose CPU 1 and a general-purpose OS 60, and I / O modules 920 and 921 via a backplane. High-performance processing is executed by the CPU module 320, and the processing result is transmitted from the I / O module 920 to the PLCs 720 and 721 in real time while compatible with the processing timing to perform distributed control. Similarly, the processing result is transmitted from the I / O module 921 to the PLCs 722 and 723 in real time while compatible with the processing timing to perform distributed control.

[0111] Furthermore, the CPU module 320 using the general-purpose CPU 1 (FIG. 17) executes a compatible operation by binary emulation, and the I / O modules 920 and 921 execute a transfer process so that the general-purpose CPU 1 can access the data of various devices with low latency. Thereby, an FA system that requires versatility, expandability, and real-time compatibility can be realized.

[0112] <Application Example 4> FIG. 21 is a diagram showing a configuration example of Application Example 4 when the control devices 1A to 1D are applied to a power generation control system. In the power generation control system 1030, overall power generation control and monitoring are performed by a monitoring terminal 530 connected to the control network 630. In this power generation control system 1030, control data due to the pressing of switch 831 is transmitted to control device 730 via electric control panel 830, and the power generation control system is activated. When the power generation control system is activated, control device 732 controls boiler control panel 834 that controls burning boiler 835, and control device 731 monitors the rotational speed of rotating turbine 833 via turbine control panel 832. Control devices 730 to 732 perform overall control by transmitting the states of these devices to monitoring terminal 530 via control network 630. By applying control devices 1A to 1D to control devices 730 to 732, a power generation control system that requires scalability and real-time compatibility can be realized.

[0113] Here, in order to safely perform efficient power generation considering the environment, CPU module 330 of control device 730, CPU module 331 of control device 731, and CPU module 332 of control device 732 each adopt general-purpose CPU 1 and general-purpose OS 60, and are configured to enable data sharing of switch 831, turbine 833, and boiler 835 via control network 630.

[0114] On the other hand, since control device 730 controls conventional electric control panel 830 connected to switch 831, it is necessary to perform compatible operation with conventional input processing. Also, since control device 731 controls conventional turbine control panel 832 connected to turbine 833, it is necessary to perform compatible operation with conventional input / output processing. Furthermore, since control device 732 controls conventional boiler control panel 834 connected to boiler 835, it is necessary to perform compatible operation with conventional input / output processing.

[0115] Therefore, functions that require versatility are respectively executed by CPU modules 330, 331, and 332, and functions that require real-time compatibility are respectively executed by I / O modules 930, 931, and 932. Furthermore, the CPU modules 330, 331, and 332 using the general-purpose CPU 1 (FIG. 17) perform compatible operations by binary emulation, and the I / O modules 930, 931, and 932 perform transfer processing so that the general-purpose CPU 1 can access the data of various devices with low latency. Thereby, a power generation control system that requires versatility, expandability, and real-time compatibility can be realized.

[0116] Note that the application examples of the control device and the control system according to each embodiment are not limited to the above-described application examples 1 to 4. The control system of each embodiment can be used in various systems such as, for example, an elevator control system, a railway control system, an automobile control system, and a construction machine control system.

[0117] When using the control devices (for example, control devices 1A to 1D) according to the embodiments of the present invention described above in a control system that employs a general-purpose CPU or a general-purpose OS and that makes the binary emulation of the application programs of the conventional control system operate compatibly, by controlling to transfer the data of the I / O module from the I / O module to the CPU cache of the general-purpose CPU, the latency of the process of accessing from the general-purpose CPU to the I / O module can be suppressed. As a result, it becomes possible to provide an application execution platform with high compatibility and real-time performance. Here, the real-time performance means that the process is completed within a determined response time, and high real-time performance indicates a short response time.

[0118] Thereby, in a control system that controls social infrastructure or the like, it becomes easy to realize a control device that has high versatility and expandability and guarantees the real-time performance of the I / O processing of the conventional module. Thereby, a control system that can be partially and gradually expanded from a conventional control system to a control system with high versatility and expandability can be realized.

[0119] Note that the present invention is not limited to the above-described embodiments, and it goes without saying that various other application examples and modification examples can be adopted as long as they do not depart from the gist of the present invention described in the claims. For example, the above-described embodiments have described the configurations of the control device and the control system in detail and specifically for the purpose of explaining the present invention clearly, and are not necessarily limited to those having all the components described. Also, it is possible to replace a part of the configuration of one embodiment with the components of another embodiment. Further, it is possible to add the components of another embodiment to the configuration of one embodiment. Also, it is possible to add, replace, or delete other components with respect to a part of the configuration of each embodiment.

[0120] Further, each of the above configurations, functions, processing units, etc. may be realized in hardware by designing a part or all of them, for example, by an integrated circuit. As the hardware, a processor device in a broad sense such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) may be used.

[0121] Also, each of the above configurations, functions, processing units, etc. may be realized in software by a processor provided in a computer interpreting and executing a program that realizes each function. Information such as a program, table, and file that realizes each function can be placed in a recording device such as a memory, hard disk, SSD (Solid State Drive), or a recording medium such as an IC card or non-volatile memory. Also, the cloud can be utilized for storing this information.

[0122] Also, in each of the above-described embodiments, the control lines and information lines show those considered necessary for the explanation, and not necessarily all the control lines and information lines are shown on the product. In practice, it may be considered that almost all components are interconnected.

Explanation of Reference Numerals

[0123] 1A, 1B, 1C, 1D, 200, 400, 401, 410, 411, 412, 420, 730, 731, 732... control devices, 1... general-purpose CPU, 2... memory, 3, 16... transfer control units, 4... I / O cache, 5, 15... bus interfaces, 6... memory map, 7... virtual address, 8, 9... physical addresses, 10... CPU cache, 20... bus, 21, 22, 211, 212... I / O modules, 30... memory interface, 31... I / O cache interface, 32, 32E... transmission units, 33... updated data transmission unit, 34... updated data transmission determination unit, 35... reception unit, 36... data reception unit, 37... I / O data reflection unit, 40... cache memory, 41... cache control unit, 42... address extraction unit, 43... tag determination unit, 44... I / O update control unit, 45... memory update control unit, 51... input I / O processing unit, 52... output I / O processing unit, 56... priority determination mode register, 57... priority determination unit, 60... general-purpose OS, 61... emulator, 62... application program, 63... real-time OS, 64... device driver, 70... state determination unit, 71... flag determination unit, 72... abnormality determination unit, 73... threshold time register, 74... flag setting unit, 80... physical address register, 210... CPU module

Claims

1. a processor for executing the binary; A memory for temporarily recording data required for processing by the arithmetic processing device; a first cache provided in the arithmetic processing device and configured to hold a portion of the data recorded in the memory; an I / O module for performing input / output processing for an external device; a bus interface for communicating with a bus connected to the I / O module; a second cache that holds a portion of data processed by the I / O module together with address information; a transfer control unit that transfers data between the memory and the second cache; The transfer control unit At a timing when the I / O module accesses the second cache, the data held in the second cache is transferred to the memory, and the data is reflected in the memory; When the binary is executed by the arithmetic processing device, data held in the first cache is transferred to the second cache via the memory at a timing when the arithmetic processing device accesses a specified address of the I / O module, and the data is reflected in the I / O module; A first operating system runs on the processing unit, and the processing unit executes an emulator or an interpreter that executes the binary including the address information of the I / O module; A space to be accessed by the I / O module is allocated to a physical address from a virtual address space of the memory allocated by the arithmetic processing unit, and the I / O module accesses the first cache; the second cache includes a cache memory and a cache control unit that determines whether or not corresponding data is held in the cache memory based on a tag generated from an address in an access from the transfer control unit or the I / O module; When the corresponding data is not held in the cache memory, the cache control unit transmits the data to the transfer control unit or the I / O module to request an update of the data; A second operating system with a guaranteed worst-case response time runs in the I / O module, and the I / O module accesses the bus at a timing independent of the first operating system. Control device.

2. a register for storing an address value obtained by converting a virtual address for accessing the I / O module into a physical address in a virtual address space of the memory; a device driver program for transferring the converted address value to the transfer control unit; Further comprising The control device according to claim 1 .

3. There are a plurality of the I / O modules, the bus interface has a mode register that stores an algorithm for determining the priority of the plurality of I / O modules; The bus interface performs control to arbitrate and determine the priority of accesses of the plurality of I / O modules using the algorithm, and reflects the access of the I / O module determined to have a high priority as a result of the arbitration in the second cache. The control device according to claim 1 .

4. A processor for executing binaries; A memory for temporarily recording data required for processing by the arithmetic processing device; a first cache provided in the arithmetic processing device and configured to hold a portion of the data recorded in the memory; an I / O module for performing input / output processing for an external device; a bus interface for communicating with a bus connected to the I / O module; a second cache that holds a portion of data processed by the I / O module together with address information; a transfer control unit that transfers data between the memory and the second cache; The transfer control unit At a timing when the I / O module accesses the second cache, the data held in the second cache is transferred to the memory, and the data is reflected in the memory; When the binary is executed by the arithmetic processing device, data held in the first cache is transferred to the second cache via the memory at a timing when the arithmetic processing device accesses a specified address of the I / O module, and the data is reflected in the I / O module; A first operating system runs on the processing unit, and the processing unit executes an emulator or an interpreter that executes the binary including the address information of the I / O module; A space to be accessed by the I / O module is allocated to a physical address from a virtual address space of the memory allocated by the arithmetic processing unit, and the I / O module accesses the first cache; the second cache includes a cache memory and a cache control unit that determines whether or not corresponding data is held in the cache memory based on a tag generated from an address in an access from the transfer control unit or the I / O module; When the corresponding data is not held in the cache memory, the cache control unit transmits the data to the transfer control unit or the I / O module to request an update of the data; There are a plurality of the I / O modules, the bus interface has a mode register that stores an algorithm for determining the priority of the plurality of I / O modules; The bus interface performs control to arbitrate and determine the priority of accesses of the plurality of I / O modules using the algorithm, and reflects the access of the I / O module determined to have a high priority as a result of the arbitration in the second cache. Control device.

5. A processor for executing binaries; A memory for temporarily recording data required for processing by the arithmetic processing device; a first cache provided in the arithmetic processing device and configured to hold a portion of the data recorded in the memory; an I / O module for performing input / output processing for an external device; a bus interface for communicating with a bus connected to the I / O module; a second cache that holds a portion of data processed by the I / O module together with address information; a transfer control unit that transfers data between the memory and the second cache; The transfer control unit At a timing when the I / O module accesses the second cache, the data held in the second cache is transferred to the memory, and the data is reflected in the memory; When the binary is executed by the arithmetic processing device, data held in the first cache is transferred to the second cache via the memory at a timing when the arithmetic processing device accesses a specified address of the I / O module, and the data is reflected in the I / O module; the transfer control unit has a threshold time register for holding a threshold time for determining whether or not the arithmetic processing unit accesses the I / O module within a certain period of time; the transfer control unit sets a flag indicating an access start at a time when the I / O module generates an access to the arithmetic processing device, and when it determines that a time from a time when the I / O module generates an access to the arithmetic processing device to a time when the arithmetic processing device refers to the flag exceeds the threshold time, outputs an abnormality signal indicating an abnormality of a control device to the I / O module; The I / O module transitions to safety control upon receiving the abnormality signal. Control device.

6. The control device according to any one of claims 1 to 5, The control device operates the sensor and the control device. Control system.

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