Power line design changes for reducing vertical band crosstalk

Abstract

Techniques for providing uniform brightness across a computing device display, such as an active matrix organic light emitting diode (AMOLED) display. In some examples, the computing device display may include a hole in an active area of ​​the display that may be used for a camera, a button, or some other function. The hole may cause a non-uniform voltage drop in a power supply mesh in a region of the active area near the hole. The power supply mesh may provide electrical energy to elements of the display. Techniques of this disclosure include portions of the power supply mesh that are not connected to a voltage supply bus to ensure a uniform voltage drop across the active area of ​​the display.

Description

Background Art

[0001] Background A computing device may include a display panel that forms an image. The display panel may include an active area defined by an array of pixels each including one or more light-emitting elements configured to generate light using electrical energy. In some examples, the display panel may include a gap between the contour of the display panel and the contour of the display active area. This gap may be referred to as a bezel. The pixels may receive electrical energy from a power supply bus to generate light.

Summary of the Invention

Means for Solving the Problems

[0002] Summary Generally, the present disclosure describes a display panel such as an active matrix organic light emitting diode (AMOLED) display panel that achieves uniform luminance. The pixels of the AMOLED display may receive electrical energy via a power supply mesh composed of traces of columns and rows. The column traces may be coupled to a voltage supply bus located at a first edge of the display panel and may receive electrical energy from this bus. In some examples, the display panel may include a window (e.g., a hole) defined by a window boundary within the active area of the display panel that can be used for a camera, a button, or some other function. The window may cause a non-uniform voltage drop in the power supply mesh in the region of the active area near the hole (e.g., the region between the window and the first edge of the display panel). Such a non-uniform voltage drop may cause distortion in the displayed image, which may be undesirable.

[0003] According to one or more aspects of the present disclosure, one or more of the column traces may be disconnected, e.g., may not be directly connected to a voltage supply bus. For example, a subset of column traces that intersect a window may not be connected to the voltage supply bus. Instead, a subset of column traces that are not connected to the voltage supply bus may receive electrical energy from the voltage supply bus via a circuit including other column traces and row traces. In this way, the present disclosure enables a uniform voltage drop across the active area of the display device.

[0004] In one example, the present disclosure describes a device comprising a display panel, the display panel comprising a plurality of pixel circuits arranged within a matrix, the matrix including a window that does not include pixel circuits. The display panel further comprises a voltage supply bus disposed at an edge of the display panel and a voltage supply grid configured to transmit electrical signals from the voltage supply bus to the plurality of pixel circuits. The voltage supply grid includes a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces being connected to the voltage supply bus and a second subset of the plurality of column traces not being connected to the voltage supply bus, the second subset of column traces including at least column traces aligned with the window. The display panel further comprises one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces.

[0005] In another example, the present disclosure describes a method of constructing a device comprising a display panel, the method comprising the steps of a plurality of pixel circuits arranged within a matrix displaying an image, the matrix including windows that do not include pixel circuits. The method further comprises the steps of a voltage supply bus transmitting an electrical signal to a first subset of a plurality of column traces, the first subset of column traces transmitting an electrical signal to a plurality of row traces, and a plurality of row circuits transmitting an electrical signal to a second subset of a plurality of column traces. The second subset of column traces includes at least the column traces aligned with the windows, and the plurality of column traces and the plurality of row traces form a voltage supply grid. The method further comprises the step of transmitting an electrical signal to a plurality of pixel circuits by the voltage supply grid.

[0006] Details of one or more examples of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6

Figure 7

[0008] Detailed Description FIG. 1 is a conceptual diagram showing an exemplary computing device having a display panel including a window in an active area. As shown by the example of FIG. 1, display panel 100 may include a display panel active area 102, which area may include rounded corner regions 104 and 122. Display panel 100 may be included in a computing device. Examples of such computing devices include, but are not limited to, mobile phones, camera devices, smart displays, tablet computers, laptop computers, desktop computers, gaming systems, media players, e-book readers, television platforms, vehicle infotainment systems or head units, or wearable computing devices (e.g., computerized watches, head-mounted devices such as VR / AR headsets, computerized glasses, computerized gloves). Examples of display panel 100 include, but are not limited to, liquid crystal displays (LCDs), light emitting diode (LED) displays, organic light emitting diode (OLED) displays, active matrix organic light emitting diode (“AMOLED”) displays, micro LED displays, or similar monochrome or color displays capable of outputting visual information to a user of display panel 100.

[0009] As shown by the example of FIG. 1, the display panel active area 102 may include a first end side 106, a second end side 108, a first side 110, and a second side 112. The rounded corner region 104 may be located on or near the first end side 106 of the display panel active area 102. For example, as shown in FIG. 1, the rounded corner region 104 may be located between the first end side 106 and the second side 112. The example of FIG. 1 shows a display panel having a first end side 106, a second end side 108, a first side 110, and a second side 112, but it is clear that the technology of the present disclosure may also be applied to display panels having different geometric shapes. For example, the technology of the present disclosure is applicable to round display panels and display panels having three or more end sides and / or three or more side sides. Further, the example of FIG. 1 shows a rounded corner region 104 located between the first end side 106 and the second side 112, but it is clear that the technology of the present disclosure may also be applied to rounded corner regions located between another end side and another side of the display panel. For example, the rounded corner region may be located between the first end side and the first side of the display panel, between the second end side and the first side of the display panel, and / or between the second end side and the second side of the display panel.

[0010] The display panel may include a window 114 defined by a window boundary 116. The window 114 may provide a space for a sensor such as a camera, a button, a light sensor, or some other component. The window 114 may be located at any location within the display panel active area 102, for example, near the center of the first side 110, as shown in the example of FIG. 1. In other examples, the window 114 may be located near one of the corners at the center of the display panel active area 102, including near a foldable section (not shown in FIG. 1) of the display panel active area 102, or at any other location.

[0011] One or more regions of the display panel active area 102 may be defined with reference to the window 114 (e.g., one or more regions such as regions 120 and 124 may be defined to be aligned with the window 114). Region 120 may extend from window 114 to the first end side 106 and the second end side 108. Region 124 may extend from window 114 to the first side 110 and the second side 112. Region 126 may be described, in the example of FIG. 1, as being between the region 120 aligned with the window 114 and the edge of the display panel 100 proximate to the window 114, e.g., the first side 110. Region 128 may be described as a symmetrically disposed region proximate to the side of the display panel 100 far from the window 114, e.g., side 112. Similar to region 120, regions 126 and 128 may extend from the first end side 106 to the second end side 108.

[0012] As will be discussed in more detail below, the display panel active area 102 may include an array of pixel circuits divided into rows and columns. The operation of the pixel circuits of the present disclosure may be controlled using electrical signals relayed through a plurality of traces (e.g., pixel circuit traces or other conductive paths) built into the display panel 100. The voltage supply bus may follow perpendicular to the columns of the pixel circuits, and each of the column traces may be directly connected to the voltage supply bus. However, the pixel circuit traces directly connected to the voltage supply bus need to occupy a large area in the rounded corner region 104. Generally, in order to accommodate these pixel circuit traces directly connected to the voltage supply bus, the display panel bezel size including the bezel size in the rounded corner region 104 may be increased, and / or the display corner curvature may be changed. However, increasing the display panel bezel size and / or changing the display corner curvature may be undesirable (e.g., for aesthetic considerations).

[0013] In some examples, one or more column traces may be disconnected from the voltage supply bus, for example, in region 120, near the curved region 104, or in other areas. If one or more column traces are not directly connected to the voltage supply bus, an electrical signal from the voltage supply bus may move through one or more row traces and the interconnects between the row traces and the column traces. In some examples, changing the path of the electrical signal in this way can avoid non-uniform luminance in some areas between, for example, region 126 and region 120.

[0014] For simplicity of explanation, in the present disclosure, a "column" or column trace may be described as extending from edge 106 to edge 108 and substantially parallel to sides 110 and 112. A "row" or row trace may be described as extending from side 110 to side 112, substantially parallel to edges 106 and 108, and substantially perpendicular to the columns. However, rows and columns are merely examples for explaining the technology of the present disclosure. The user may rotate the display panel 100 at any angle, in which case a column may be considered a column even if it is not vertical, and a row may be considered a row even if it is not horizontal.

[0015] FIG. 2 is a diagram showing an enlarged example of a display panel according to one or more techniques of the present disclosure. The display panel 200 is an example of the display panel 100 described above in connection with FIG. 1. Edge 206 is an example of the first edge 106, the first side 210 is an example of the first side 110, the second side 212 is an example of the second side 112, and the rounded corner region 204 is an example of the rounded corner region 104 depicted in FIG. 1.

[0016] As shown by the example of FIG. 2, the display panel 200 may include a plurality of pixel circuits 242 and a voltage supply bus 234. The example of FIG. 2 shows pixel circuits 242 divided into three regions 230A, 230B, and 230C. Together, the pixel circuits 230 may constitute the display panel active area 202. The pixel circuits 230 are arranged in a plurality of columns and may receive power via a plurality of column traces 232A and 232B collectively referred to as column traces 232. The pixel circuits in region 230B may receive power from column trace 232A connected (e.g., directly) to voltage supply bus 234. In the example of FIG. 2, the pixel circuits in regions 230A and 230C may receive power from column traces that are disconnected (e.g., not directly connected) from voltage supply bus 234. In other examples, one or more column traces in regions 230A and / or 230C may be connected to voltage supply bus 234, such as column trace 232C. In the present disclosure, the subset of column traces 232A connected to voltage supply bus 234 may be described as a first subset of the plurality of column traces. The subset of column traces 232B not directly connected to voltage supply bus 234 may be described as a second subset of the plurality of column traces. Column trace 232B may be indirectly connected to voltage supply bus 234 via one or more row traces and interconnects.

[0017] In the example of FIG. 2, voltage supply bus 234 may define a length 236 extending along a first subset 232A of column traces connected to voltage supply bus 234. In other words, in some examples, column trace 232C may not be connected to voltage supply bus 234, and length 238 of voltage supply bus 234 may be removed. Removing the unnecessary portion of voltage supply bus 234 provides advantages such as providing space in the bezel region of the rounded corner region, e.g., region 204, for other structures (e.g., signal / power lines, integrated row driver circuits, etc.) and desirably reducing the bezel size of the display panel.

[0018] The pixel circuits 230 are also arranged in a plurality of rows 240. In some examples, the pixel circuits are directly coupled to the column traces and receive power directly from the column traces. In other examples, the plurality of rows of pixel circuits may receive power via a plurality of row traces (not shown in FIG. 2) on a layer separate from the layer of the column traces. In some examples, the plurality of row traces make electrical connections between the column traces.

[0019] FIG. 3A is a schematic diagram showing an exemplary pixel circuit that may be arranged in a matrix of pixel circuits. Pixel circuit 342 is an example of pixel circuit 242 among the plurality of pixel circuits in display panel 200 described above in connection with FIG. 2.

[0020] The pixel circuit 342 of circuit 300 may include an OLED 312. The cathode of the OLED 312 is connected to the reference line Vss 314, and the anode of the OLED 312 is connected to the output terminal of transistor T1 308. T1 308 is depicted as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) in the example of FIG. 3A, but in other examples, it may be implemented by another type of switch. T1 308 may control the current I OLED 310 to the OLED 312 from a column trace that supplies power Vdd 332. The column trace having voltage Vdd 332 is an example of column traces 232A and 232B described above in connection with FIG. 2. In other examples, the pixel circuit 342 may receive power from a row trace in one of the rows 240 described above in connection with FIG. 2. The column traces and row traces of the display panel are a power supply mesh that can supply electrical energy to lighting elements, such as the OLED 312 of pixel circuit 342. In the present disclosure, the power supply mesh may also be referred to as a voltage supply grid, which can transmit electrical signals from a voltage supply bus, such as voltage supply bus 234 depicted in FIG. 2, to a plurality of pixel circuits. The electrical signals are power signals used by the plurality of pixel circuits for light emission.

[0021] The gate of T1 308 is connected to the output terminal of transistor T2 316 and to Vdd 332 through capacitor Cst 306. The input terminal of transistor T2 316 is connected to data [k] 302 and is controlled by scan [N] 304 connected to the gate of T2 316.

[0022] FIG. 3B is a schematic diagram showing an exemplary column trace of a voltage supply bus having a trace between interconnects of column traces modeled as resistors. Voltage supply bus 334 is an example of voltage supply bus 234 described above in connection with FIG. 2. Column trace 333 of FIG. 3B is an example of one of column traces 232A connected to the voltage supply bus. The portion of the column trace connecting each pixel circuit in the column may cause a voltage drop, which in the example of FIG. 3B is modeled as a 10 ohm (10Ω) resistor. Note that the values depicted in FIG. 3B are merely values selected for purposes of illustration. In other examples, the values may be different from those shown in FIG. 3B. An exemplary 1 milliampere (mA) current may cause a voltage drop of 1 millivolt (mV) between each pixel circuit.

[0023] FIGS. 4A - 4C are conceptual diagrams showing an exemplary display panel having a voltage supply matrix including windows that may interrupt one or more traces of the voltage supply matrix. Display panel 400 is an example of display panel 100 and / or 200 described above in connection with FIGS. 1 and 2.

[0024] As described with respect to FIG. 1, in the examples of FIGS. 4A and 4B, display panel active area 402 may include a first end side 406, a second end side 408, a first side 410, and a second side 412. The display panel may include a window 414 defined by window boundary 416. Window 414 may be located, for example, anywhere within display panel active area 402 near the center of first side 410 as shown in the example of FIG. 4. In other examples, window 414 may be located at other locations within active area 402.

[0025] The display panel active area 402, the first end side 406, the second end side 408, the first side 410, the second side 412, the window 414 defined by the window boundary 416, and the column trace 432 are, respectively, examples of the display panel active area 102 and / or 202, the first end side 106 and / or 206, the second end side 108, the first side 110 and / or 210, the second side 112 and / or 212, the window 114, and the column trace 232 described above in connection with FIGS. 1 and 2. Therefore, the characteristics and functions of the display panel active area 402, the first end side 406, the second end side 408, the first side 410, the second side 412, the window 414, and the column trace 432 may be similar or identical to the characteristics and functions of the display panel active area 102 and / or 202, the first end side 106 and / or 206, the second end side 108, the first side 110 and / or 210, the second side 112 and / or 212, the window 114, and the column trace 232, respectively.

[0026] The display panel 400 may also include a plurality of pixel circuits including lighting elements configured to emit light, as described above in connection with FIG. 3. The pixel circuits (not shown in FIGS. 4A-4C) may be located at one or more interconnects 450 between a column trace 432 of a plurality of column traces of the voltage supply grid of the display panel 400 and a row trace 452 of a plurality of row traces, as shown in FIGS. 4B and 4C. As described above in connection with FIG. 2, the column trace 432 may be connected to a voltage supply bus 434. The voltage supply bus 434 may be connected to a power supply connection Vdd454 to a power source (not shown in FIGS. 4A-4C) of a computing device including the display panel 400. The interconnect 450 may conduct an electrical signal from the voltage supply bus through the column trace 432 to the row trace 452. In the column trace 432 not connected to the voltage supply bus 434, the interconnect 450 may conduct an electrical signal to the isolated column trace 432 through the row trace 452. In this way, the pixel circuit may receive power through either or both of the row trace 452 and the column trace 432 of the voltage supply grid.

[0027] In some examples, the row trace 452 may be on a layer separate from the layer of the column trace 432. The layer of the column trace 432 may be electrically insulated from the layer of the row trace 452, except for the interconnect 450. In some examples, the horizontal Vdd line, e.g., the row trace 452, may have a relatively high sheet resistance compared to the column trace 432. The vertical Vdd line, e.g., the column trace 432, may have a relatively low sheet resistance compared to the row trace 452. The reference layer, e.g., Vss314 described above in connection with FIG. 3, may be a third layer electrically insulated from both the layer of the row trace 452 and the layer of the column trace 432.

[0028] One or more regions of the display panel active area 402 may be defined with reference to the window 414. For example, regions such as regions 420 and 424 may be aligned with the window 414. Region 420 aligned with the window 414 may extend from the window to the first side 406 and the second side 408. As described above in connection with FIG. 3B, the column trace 432 may have a voltage drop, for example, starting from a connection to a voltage supply bus near the short side 406 and extending along the column trace to each pixel circuit extending to the side 408. For region 458 that may extend from the voltage supply bus to the window 414 within region 420, the voltage drop for each pixel or interconnect 450 may be as shown for column trace 333 in FIG. 3. For region 456 that may be within region 420 between the interruption in the column trace caused by the window 414 and the side 408, the electrical signal may first move along one or more row traces 452 through one or more of the interconnects 450, for example, in region 424, before reconnecting to the column trace through the interconnect 450, and thus reach the column trace in region 456. Accordingly, the voltage of each pixel circuit in region 456 may be different compared to adjacent pixels along the same row located in region 427. Region 427 may include the column trace 432 from the window 414 to the side 412. Since the voltages of pixel circuits in different regions may be different, the display may be performed differently in each region. For example, the light emitted by the pixel circuit in region 427 and the identically programmed pixel circuit in region 456 may be different.

[0029] In the examples of FIGS. 4A and 4B, region 426 is between region 420 and an edge of display panel 400 proximate to window 414, such as first side 410. In some examples, column traces 432 in region 426 may be connected to a voltage supply bus and thus can have a voltage drop pattern similar to column traces 432 in regions 427 and 458. However, column traces 432 in region 456 are not directly connected to the voltage supply bus but receive power from one or more row traces 452 and interconnects 450, so column traces 432 in region 456 can have a different voltage drop pattern. In some examples, processing circuitry (not shown in FIGS. 4A - 4C) for a device using display panel 400 may execute complex algorithms to compensate for different performance in different regions.

[0030] In addition to non - uniform luminance caused by discontinuities in column traces 432 in region 420 due to window 414, display panel 400 may also suffer from pixel crosstalk. Some exemplary types of pixel crosstalk can include electrical or optical crosstalk. For example, pixel crosstalk may be caused by either or both electrical or optical coupling between adjacent pixels in active area 402 of the display matrix. Electrical crosstalk may be caused by lateral current through a common layer, and optical crosstalk may be caused by light leakage through non - addressed pixels. In some examples, pixel crosstalk may reduce the contrast ratio and impede the color gamut of a computing device display.

[0031] Other categories of the crosstalk OLED display panel 400 may include "bright crosstalk" and "dark crosstalk". In the present disclosure, bright crosstalk refers to a phenomenon in which the lit OLEDs in a row with many black (turned-off) pixels (OLEDs) tend to light up brighter than the lit OLEDs in a row with few black (turned-off) pixels (OLEDs). Dark crosstalk refers to the opposite of bright crosstalk, that is, a phenomenon in which the lit OLEDs in a row with many black (turned-off) pixels (OLEDs) tend to light up darker than the lit OLED in a row with few black (turned-off) pixels (OLEDs).

[0032] Bright crosstalk may be caused by the difference in the sink current of each row of the OLED display panel 400. Dark crosstalk may be caused by the difference in the amount of associated parasitic capacitance according to the display data for each row, for example, the display data received via the data [k]302 described above in relation to FIG. 3. The parasitic capacitance associated with the OLED of the pixel circuit, for example, OLED312, may be larger when the OLED is not lit than when the OLED is lit because the conductive OLED can reduce the associated parasitic capacitance. The total parasitic capacitance of a row with many unlit OLEDs may be larger than that of a row with few unlit OLEDs. Since a row with a larger parasitic capacitance has a larger time constant (R-C time constant), it takes time to drive the OLEDs in a row with a larger time constant.

[0033] In the example of FIG. 4B, region 428 is a symmetrically arranged region that is close to a side of display panel 400, e.g., side 412, and far from window 414. In some examples, region 428 may be symmetric with region 426, and thus may include approximately the same number of column traces 432 as in region 426. When the column traces in region 426 are directly connected to the voltage supply bus and the column traces in region 428 are directly connected to the voltage supply bus, the pixel circuits connected to those column traces may have similar voltage drop characteristics to each other, as well as characteristics similar to column traces 432 in region 427. In other examples, region 428 may be symmetric with both regions 420 and 426. Developing a compensation algorithm to provide uniform luminance for display panel 400 having a number of different regions and to reduce crosstalk is complex and may result in a long development time for testing, development, verification, and production. In some examples, one or more column traces may be disconnected from the voltage supply bus, e.g., in region 458, region 428, or other areas. As described above in connection with FIGS. 1 and 2, when one or more column traces are disconnected, electrical signals from the voltage supply bus can move through one or more row traces and the interconnects between the row and column traces. In some examples, changing the path of the electrical signals in this way can avoid non-uniform luminance in some areas.

[0034] FIGS. 5A - 5C are conceptual diagrams showing an exemplary voltage supply grid having a subset of column traces aligned with windows not connected to the voltage supply bus. Display panel 500 is an example of display panels 100, 200, and 400 described above in connection with FIGS. 1, 2, and 4, and may have the same functions and characteristics unless otherwise specified.

[0035] An example of a display panel 500 as shown in FIGS. 5A and 5B includes a window 514, an active area 502 having regions 520, 556, 558, and 528, and a power supply connection Vdd554. As described above in connection with FIG. 4, region 520 includes a subset of column traces 532B aligned with window 514. In contrast to FIG. 4, as described above in connection with FIG. 2, column traces 532B are a subset of column traces that do not connect directly to voltage supply bus 534. Column traces 532A in regions 526 and 527 connect directly to voltage supply bus 534. In display panel 500, by disconnecting column traces 532B in region 520 from voltage supply bus 534, the portion of column traces 532B in region 558 can be similar to the column traces in region 556. As described above in connection with FIG. 4, the column traces in region 558 are also within region 520 and are located between window 514 and voltage supply bus 534 at side 506. The column traces in region 556 are within region 520 and are located between window 514 and side 508. In both regions 556 and 558, the column traces can receive power from voltage supply bus 534 via one or more row traces 552 and interconnects (not shown in FIGS. 5A - 5C), so the column traces in region 558 may have voltage drop characteristics similar to those of the column traces in region 556. Thus, the technology of the present disclosure for display panel 500 can improve luminance uniformity compared to the display panel 400 described above in connection with FIG. 4. In other words, in contrast to display panel 400, display panel 500 can have fewer areas with different voltage drop characteristics, so less complexity can be achieved to compensate for differences in active area 502. The technology of the present disclosure can also reduce the problem of crosstalk and can help improve luminance uniformity.

[0036] In some examples, the display panel 500 may further include column traces 532B in an area 528 that is not directly connected to the voltage supply bus 534 but is indirectly connected to the voltage supply bus 534 via one or more row traces and interconnects. Similar to the area 428 described above in connection with FIG. 4, the area 528 is symmetrically disposed with respect to the area 520 and is an area that is close to the side 512 and far from the window 514. In the display panel 500, since the area 528 is symmetric to the area 520, it includes approximately the same number of column traces 532B as in the area 520. The column traces 532B in both the areas 520 and 528 are in a subset of the column traces that are not directly connected to the voltage supply bus 534. Therefore, the pixel circuits connected to the column traces 532B can have similar voltage drop characteristics in both the areas 520 and 528, and thus can contribute to the luminance uniformity in the active area 502.

[0037] Similarly, the column traces 532A in the area 560 may be symmetric to the column traces 532A in the area 526, for example, a subset of the column traces that are directly connected to the voltage supply bus 534 and are disposed close to the side of the display panel 500. Therefore, both the subset 532A and the subset 532B of the column traces along the side 510 may have characteristics similar to those of the column traces along the side 512. The pixel circuits connected to these column traces in the areas 526, 520, 528, and 560 can have similar voltage drop characteristics to each other, and thus can contribute to a uniform light intensity for the active area 502.

[0038] FIGS. 6A - 6C are conceptual diagrams showing an exemplary voltage supply grid having a subset of column traces in a corner area of a display not connected to a voltage supply bus. The display panel 600 is an example of the display panels 100, 200, 400 described above in connection with FIGS. 1, 2, and 4 and may have the same functions and characteristics unless otherwise specified.

[0039] An example of a display panel 600 as shown in FIGS. 6A and 6B includes an active area 602, and has a window 614, regions 620, 656, 658, and 628, and a power supply connection Vdd654 on an edge 606, on the side opposite to edge 608. As described above in connection with FIG. 5, region 620 includes a subset of column traces 632B aligned with window 614. In contrast to FIG. 4, as described above in connection with FIG. 2, column traces 632B are a subset of column traces that do not connect directly to voltage supply bus 634. Column traces 632A in regions 626 and 627 connect directly to voltage supply bus 634. As described above in connection with FIG. 5, in display panel 600, by not connecting column traces 632B in region 620 to voltage supply bus 634, the portion of column traces 632B in region 658 can be similar to the column traces in region 656. Thus, in both regions 656 and 658, the column traces can receive power from voltage supply bus 634 via one or more row traces 652 and interconnects (not shown in FIGS. 6A - 6C), so that the column traces within region 658 can have voltage drop characteristics similar to those of the column traces within region 656.

[0040] In addition, in display panel 600, a subset of column traces 632B disconnected from voltage supply bus 634 may include those column traces in region 626. Similar to regions 426 and 526 described above in connection with FIGS. 4 and 5, region 626 includes column traces located between the column traces aligned with window 414 in region 620 and side 610 of display panel 600 proximate to window 614. However, in contrast to the column traces in regions 426 and 526, column traces 632B in region 626 are included in a subset of a plurality of column traces not connected to voltage supply bus 634.

[0041] As described above with reference to FIG. 4, the technology of the present disclosure regarding the display panel 600 can improve the luminance uniformity as compared with the display panel 400. In other words, in contrast to the display panel 400, the display panel 600 can have fewer areas with different voltage drop characteristics, so that the complexity can be reduced to compensate for the difference in the active area 602. Also, by disconnecting the column traces in the area 626, the area of the display panel 600 having different voltage drop characteristics is reduced as compared with the display panel 500. Similar to the display panel 500, the technology of the present disclosure as described with reference to FIGS. 6A to 6C can also reduce the problem of crosstalk and can help improve the luminance uniformity.

[0042] As described above with reference to FIG. 5C, in some examples, the display panel 600 may also disconnect the column trace 532B in the area 528. The area 628 is disposed symmetrically with respect to the combined areas 626 and 620 and is an area close to the side 612 and far from the window 614. In the display panel 500, since the area 528 is symmetric with the area 520, it includes approximately the same number of column traces 532B as in the area 520. As described above, the column traces 632B in the areas 620, 626, and 628 are a subset of the column traces that are not directly connected to the voltage supply bus 534. Therefore, the pixel circuits connected to the column traces 532B can have similar voltage drop characteristics in the areas 620, 626, and 628, which can contribute to the luminance uniformity in the active area 602.

[0043] In the examples of FIGS. 6A and 6C, the portion of the voltage supply bus 634 indicated by 670 does not connect to any column traces. Thus, the voltage supply bus 634 need not extend towards side 610 or side 612 beyond the last connected column trace 632A. In some examples, the portion 670 of the voltage supply bus 634 may be removed from the corner region, which can help reduce the display corner bezel width. In some examples, removing the portion 670 can provide space near other signal lines, or near the rounded corner regions for other components. In other words, the portion 670 proximate to a column trace aligned with window 614, e.g., a column trace among a plurality of column traces located between the column trace in region 620 and side 610 of the display panel proximate to window 614, may be removed from the voltage supply bus 634. Without the portions 670 near side 610 and near side 612, the voltage supply bus 634 defines a length that extends along a subset of the column traces 632A that connect to the voltage supply bus 634.

[0044] FIG. 7 is a flowchart illustrating an exemplary operation of a display device of the present disclosure. The blocks of FIG. 7 are described from the perspective of FIGS. 5A-5C unless otherwise noted.

[0045] As seen in the example of FIG. 7, for example, a plurality of pixel circuits arranged within a matrix as shown in FIG. 2 may be configured to display an image on the active area 502 of the display panel 500 (700). The image may include colors, text, control features, graphical user interface elements, etc. The matrix of pixel circuits may include a window 514 that does not include pixel circuits. As described above, the window 514 may be included so that a sensor such as a camera can capture light through the display panel 500.

[0046] The voltage supply bus 534 may transmit an electrical signal, e.g., power, to a subset 532A of column traces connected to the voltage supply bus 534 (705). As described above in connection with FIG. 4, the subset 532A of column traces may further conduct the electrical signal to other pixel circuits via the interconnect 450 and the row traces 452 (710). In other words, the voltage supply grid of the display panel 500 may comprise a plurality of layers and may conduct electrical signals to a plurality of pixel circuits (715).

[0047] The present disclosure may also be illustrated by the following examples. Example 1 A device comprising a display panel, the display panel comprising a plurality of pixel circuits arranged in a matrix, the matrix including a window that does not include pixel circuits, the display panel further comprising a voltage supply bus disposed at an edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid including a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces being connected to the voltage supply bus, a second subset of the plurality of column traces not being connected to the voltage supply bus, the second subset of column traces including at least column traces aligned with the window, the display panel further comprising one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces.

[0048] Example 2 The device of Example 1, wherein the second subset of column traces further includes column traces located between column traces aligned with the window and an edge of the display panel proximate to the window among the plurality of column traces.

[0049] Example 3 The device of Example 2, wherein the voltage supply bus defines a length extending along the first subset of column traces.

[0050] Example 4 In Example 2, a part of the voltage supply bus that is close to the column traces located between the column traces aligned with the window and the edge of the display panel close to the window is removed.

[0051] Example 5 In Example 1, the second subset of column traces includes column traces symmetrically arranged close to the side of the display panel far from the window among the plurality of column traces.

[0052] Example 6 In Example 1, the electrical signal is a power signal used by a plurality of pixel circuits to emit light.

[0053] Example 7 In Example 1, the device further includes a camera configured to capture an image through the window.

[0054] Example 8 In Example 1, the voltage supply grid includes a first layer and a second layer. The first layer includes a plurality of column traces, and the second layer includes a plurality of row traces.

[0055] Example 9 In Example 8, the first layer defines a first sheet resistance, the second layer defines a second sheet resistance, and the first sheet resistance is less than the second sheet resistance.

[0056] Example 10 In Example 8, the first layer is electrically insulated from the second layer except for one or more interconnects between the column traces among the plurality of column traces and the row traces among the plurality of row traces.

[0057] Example 11 A method of configuring a device comprising a display panel, the method comprising the steps of: a plurality of pixel circuits arranged within a matrix displaying an image, the matrix including a window that does not include pixel circuits; the method further comprising the steps of: a voltage supply bus transmitting an electrical signal to a first subset of a plurality of column traces; the first subset of column traces transmitting an electrical signal to a plurality of row traces; a plurality of row circuits transmitting an electrical signal to a second subset of the plurality of column traces, the second subset of column traces including at least column traces aligned with the window; the plurality of column traces and the plurality of row traces forming a voltage supply grid; the method further comprising the step of the voltage supply grid transmitting the electrical signal to the plurality of pixel circuits.

[0058] Example 12 The method of Example 11, further comprising a camera capturing one or more images through the window.

[0059] Example 13 The method of Example 11, wherein the first subset of column traces is directly connected to the voltage supply bus and the second subset of column traces is not directly connected to the voltage supply bus.

[0060] Various examples of the present disclosure have been described. These and other examples are included in the following claims.

Claims

1. A device comprising a display panel, wherein the display panel comprises a plurality of pixel circuits arranged within a matrix, the matrix including windows that do not contain pixel circuits, and the display panel further comprising a voltage supply bus disposed at a first edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid including a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces being directly connected to the voltage supply bus, a second subset of the plurality of column traces including all column traces aligned with the window, the second subset of the plurality of column traces including a first portion between the first edge and the window and a second portion between a second edge opposite the first edge and the window, neither the first portion nor the second portion of the second subset of the plurality of column traces being directly connected to the voltage supply bus, and the display panel further comprising one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces, the second subset of the plurality of column traces being indirectly connected to the voltage supply bus via the first subset of the plurality of column traces and the row traces.

2. The device according to claim 1, wherein the second subset of the plurality of column traces further includes column traces located between the column traces aligned with the window and the edge of the display panel proximate to the window among the plurality of column traces.

3. The device according to claim 1 or 2, wherein the voltage supply bus defines a length extending along the first subset of the plurality of column traces.

4. The device according to any one of claims 1 to 3, wherein a part of the voltage supply bus proximate to a column trace located between the column traces aligned with the window and the edge of the display panel proximate to the window among the plurality of column traces is removed. **Claim 5**: The device according to any one of claims 1 to 4, wherein the second subset of the plurality of column traces includes column traces symmetrically disposed close to a side of the display panel far from the window among the plurality of column traces. **Claim 6** The device according to any one of claims 1 to 5, wherein the electrical signal is a power signal used by the plurality of pixel circuits to emit light. **Claim 7** The device according to any one of claims 1 to 6, further comprising a camera configured to capture an image through the window. **Claim 8** The voltage supply grid includes a first layer and a second layer, the first layer includes the plurality of column traces, the second layer includes the plurality of row traces, The device according to any one of claims 1 to 7. **Claim 9** The first layer defines a first sheet resistance, the second layer defines a second sheet resistance, the first sheet resistance is less than the second sheet resistance. The device according to claim 8. **Claim 10** The device according to claim 8 or 9, wherein the first layer is electrically insulated from the second layer except for the one or more interconnects between the column traces among the plurality of column traces and the row traces among the plurality of row traces. **Claim 11**: A device comprising a display panel, wherein the display panel comprises a plurality of pixel circuits arranged in a matrix, the matrix includes a window not including pixel circuits, and the display panel further comprises a voltage supply bus disposed at an edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid includes a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces is connected to the voltage supply bus, a second subset of the plurality of column traces is not connected to the voltage supply bus, the second subset of the plurality of column traces includes at least column traces aligned with the window, the second subset of the plurality of column traces further includes column traces located between the column traces aligned with the window and an edge of the display panel close to the window among the plurality of column traces, and the display panel further A device comprising one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces.

12. A device comprising a display panel, wherein the display panel comprises a plurality of pixel circuits arranged in a matrix, the matrix includes windows that do not include pixel circuits, and the display panel further comprises a voltage supply bus disposed at an edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid includes a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces is connected to the voltage supply bus, a second subset of the plurality of column traces is not connected to the voltage supply bus, the second subset of the plurality of column traces includes at least column traces aligned with the windows, the voltage supply bus defines a length extending along the first subset of the plurality of column traces, and the display panel further comprises one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces.

13. A device comprising a display panel, wherein the display panel comprises a plurality of pixel circuits arranged in a matrix, the matrix includes windows that do not include pixel circuits, and the display panel further comprises a voltage supply bus disposed at an edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid includes a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces is connected to the voltage supply bus, a second subset of the plurality of column traces is not connected to the voltage supply bus, the second subset of the plurality of column traces includes at least column traces aligned with the windows, a portion of the voltage supply bus proximate to a column trace located between the column trace aligned with the window and an edge of the display panel proximate to the window among the plurality of column traces is removed, and the display panel further A device comprising one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces. **Claim 14**: A device comprising a display panel, wherein the display panel comprises a plurality of pixel circuits arranged in a matrix, the matrix includes windows that do not contain pixel circuits, and the display panel further comprises a voltage supply bus disposed at an edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid includes a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces is connected to the voltage supply bus, a second subset of the plurality of column traces is not connected to the voltage supply bus, the second subset of the plurality of column traces includes at least column traces aligned with the windows, the second subset of the plurality of column traces includes column traces symmetrically disposed adjacent to a side of the display panel far from the windows among the plurality of column traces, and the display panel further comprises one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces. **Claim 15**: A device comprising a display panel, wherein the display panel comprises a plurality of pixel circuits arranged in a matrix, the matrix includes windows that do not contain pixel circuits, and the display panel further comprises a voltage supply bus disposed at an edge of the display panel, and a voltage supply grid configured to transmit an electrical signal from the voltage supply bus to the plurality of pixel circuits, the voltage supply grid includes a plurality of column traces and a plurality of row traces, a first subset of the plurality of column traces is connected to the voltage supply bus, a second subset of the plurality of column traces is not connected to the voltage supply bus, the second subset of the plurality of column traces includes at least column traces aligned with the windows, and further the voltage supply grid includes a first layer and a second layer, the first layer comprises the plurality of column traces, the second layer comprises the plurality of row traces, the first layer defines a first sheet resistance, The second layer defines a second sheet resistance, the first sheet resistance is less than the second sheet resistance, the display panel further comprises, a device comprising one or more interconnects between a column trace of the plurality of column traces and a row trace of the plurality of row traces.

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