Quantum Controller High-Speed Pass Interface

Abstract

Techniques are provided that allow for the routing of qubit data. For example, one or more embodiments described herein may include a computer-implemented method for training a quantum controller fast-path interface that can control qubit data routing. The computer-implemented method may include training, by a system operably coupled to a processor, the quantum controller fast-path interface to route qubit data bits between the quantum controller and a condition engine by adjusting delay values ​​such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.

Description

Technical Field

[0001] The present disclosure relates to quantum controller fast path interfaces, and more specifically, to routing qubit information between one or more quantum controllers and a conditional engine via a quantum controller fast path interface characterized by a direct register-to-register transfer pattern.

Background Art

[0002] In a quantum computing system, it has been considered preferable to deploy a hardware path for routing qubit information to the controllers of other qubits in a given network of qubits, preferably as quickly as possible. This communication of qubit data to other qubit controllers enables efficient conditional operations to be applied to those qubits. This has various potential applications in the quantum computing world, including topics such as forcing a known state on a qubit and qubit teleportation, among others. However, typical implementations of qubit data routing interfaces utilize asynchronous boundaries and extra header information for authenticating qubit data, which may not be preferable for system operation as qubits continuously degrade while data transfer is occurring.

Summary of the Invention

[0003] The following presents an overview in order to provide a basic understanding of one or more embodiments of the present invention. This overview is not intended to identify key or critical elements or to define any scope of either particular embodiments or the scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, a computer-implemented method, an apparatus, or a computer program product, or a combination thereof, for routing qubit data is described.

[0004] According to one embodiment, a computer-implemented method is provided. The computer-implemented method may include training a quantum controller high-speed path interface for routing qubit data bits between a quantum controller and a conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized directly by an inter-register transfer pattern by a system operably coupled to a processor. An advantage of such a computer-implemented method may be training the interface to reduce data transfer latency.

[0005] In some examples, the computer-implemented method may further include selecting, by the system, a delay value that can stabilize the mesochronous clock domain by shifting a delay device of the quantum controller high-speed path interface. An advantage of such a computer-implemented method may be that it can utilize a built-in conditional method for training the interface rather than relying on hardware components.

[0006] According to one embodiment, a computer program product is provided for routing qubit data bits between a quantum controller and a conditional engine. The computer program product may include a computer-readable storage medium having embodied program instructions. The program instructions are executable by a processor to cause the processor to train a quantum controller high-speed path interface by adjusting a delay value such that a mesochronous clock domain of the quantum controller high-speed path interface is characterized by a direct register-to-register transfer pattern.

[0007] In some examples, the computer program product may further cause the processor to execute, by the processor, to appraise the stability of the mesochronous clock domain in the delay value with respect to a target wire of the quantum controller high-speed path interface. An advantage of such a computer program product may be that quantum data bits can be centered from domain edges so as to be positioned outside of setup and hold time windows.

[0008] According to one embodiment, a system is provided. The system may include a quantum controller high-speed path interface capable of routing the qubit data packet between a quantum controller and a conditional engine via a packet transfer protocol in which source information is inferred from a data position within the qubit data packet. An advantage of such a system may be that qubit data traffic can be routed with low latency taking into account qubit degradation.

[0009] In some examples of the system, the qubit data packet may consist of a pairing of a data position and a valid qubit. An advantage of such a system may be that it is possible to utilize data packets that do not require overhead information for authentication of qubit data. BRIEF DESCRIPTION OF THE DRAWINGS

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DETAILED DESCRIPTION OF THE INVENTION

[0020] The following detailed description is exemplary only and is not intended to limit embodiments, or applications or uses of embodiments, or combinations thereof. Further, it is not intended to be constrained by any representation or suggested information presented in the above Background section or Summary section of the invention, or the Detailed Description of the Invention section.

[0021] Here, one or more embodiments will be described with reference to the drawings. Throughout, like reference numerals are used to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, in various instances, it will be apparent that one or more embodiments may be practiced without these specific details.

[0022] Considering issues related to other implementations of qubit information routing, the present disclosure can be implemented to generate solutions to one or more of these issues via a trainable quantum controller high-speed path interface that can utilize one or more continuous packet transfer protocols. Advantageously, one or more embodiments described herein can consider a quantum controller high-speed path interface that can be trained to exhibit data transfer characteristics similar to direct register-to-register transfers. Further, the interface can be implemented using one or more continuous packet transfer approaches. Thereby, qubit data can be routed between registers without utilizing overhead bits conventionally used to identify the start and end of data packets. Further, the interface can identify data source information without using conventional overhead bits based on bit positions within the data packet.

[0023] Various embodiments of the present invention can be directed to a computer processing system, a computer implemented method, an apparatus or a computer program product, or a combination thereof, that facilitates efficient, effective, and autonomous (e.g., without direct human guidance) qubit information routing. For example, one or more embodiments described herein can contemplate a quantum controller high speed pass interface that can route qubit information between one or more quantum controllers (e.g., the lowest level quantum controllers) and a conditional engine. The one or more quantum controllers can stimulate one or more qubits, and the conditional engine can perform one or more Boolean operations on the one or more qubits and route the results back to an endpoint. In various embodiments, the interface can be implemented using a continuous packet transfer approach, where data packets containing only qubit data positions and qubit validity can be continuously transferred between the controller and the conditional engine. Further, the boundaries of the data packets can be established via one or more training algorithms incorporated within the interface.

[0024] A computer processing system, a computer-implemented method, an apparatus, or a computer program product, or a combination thereof, utilizes hardware or conditional software or a combination thereof to solve a highly technical problem (e.g., qubit information routing) that cannot be performed as a set of non-abstract mental activities by humans. Also, one or more embodiments described herein can constitute a technical improvement over conventional qubit information routing via a quantum controller high-speed path interface that utilizes an embedded training algorithm to define the boundaries of data packets. Additionally, various embodiments described herein can show a technical improvement over conventional qubit information routing via a quantum controller high-speed path interface that utilizes a continuous packet transfer protocol to transfer data between registries without including overhead bits to authenticate qubit data.

[0025] Furthermore, one or more of the embodiments described herein can have practical applications by establishing an interface between a quantum controller and a conditional engine that can be characterized by an inter-register transfer pattern. For example, the various embodiments described herein can utilize an embedded training algorithm to define a data packet boundary for implementation in a continuous packet transfer protocol that can identify data source information based on bit positions within a data packet. One or more of the embodiments described herein can control one or more delay routines within one or more receiving chips based on mesochronous clock domain stability. Thereby, one or more of the embodiments can center edge data bits from a stable clock domain to place data bits outside of the setup and hold windows of the received clock. For example, the various embodiments described herein can control the delay routines of an interface to align data patterns across wires, or maximize timing margins to minimize the risk of data slips that can occur due to device variations or temperature changes or combinations thereof, or combinations thereof.

[0026] FIG. 1 shows a block diagram of an exemplary and non-limiting interface 100 that can route qubit information between one or more quantum controller architecture blocks 102 and a conditional engine architecture block 104. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. Aspects of the systems (e.g., interface 100, etc.), apparatus, or processes in various embodiments of the present invention can comprise one or more machine-executable components embodied in one or more machines (e.g., embodied in one or more computer-readable media (singular or plural) associated with one or more machines). Such components can cause a machine to perform the described operations when executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.).

[0027] One or more quantum controller architecture blocks 102 may include one or more quantum controllers 106 operably coupled to one or more transmission chips 108 and receive chips 110. In various embodiments, one or more quantum controllers 106 can be operably coupled to one or more qubits. Exemplary qubit technologies can include, but are not limited to, trapped ion qubits or superconducting qubits or combinations thereof. For example, if the qubit is a trapped ion qubit, multiple ions can serve as qubits and as one or more traps that hold the ions at specific positions. Further, a laser or microwave source targeting one or more of the ions affects the quantum state of the ions and a laser that cools the ions or enables measurement or a combination thereof, or one or more photon detectors that measure the state of the ions, or a combination thereof. In another example, a superconducting qubit (e.g., a superconducting quantum interference device “SQUID”) can be a lithographically defined electronic circuit that, when cooled to millikelvin temperatures, can exhibit quantized energy levels (e.g., due to quantized states of charge or flux). The superconducting qubit can be Josephson junction-based, such as a transmon qubit or the like, or a combination thereof. Also, the superconducting qubit can be compatible with microwave control electronics and can be utilized with gate-based technology or integrated cryogenic control. Additional exemplary qubit technologies can include, but are not limited to, photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically gated or electrically gated), topological qubits, combinations thereof, or the like, or combinations thereof.As described herein, the term "superconducting" can characterize materials that exhibit superconducting properties at or below a superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). Additionally, those skilled in the art will recognize that other superconductor materials (e.g., hydride superconductors such as lithium / magnesium hydride alloys) can be used in the various embodiments described herein.

[0028] One or more quantum controllers 106 can stimulate one or more qubits, output results from such stimulation, or a combination thereof. In various embodiments, one or more quantum controllers 106 can transmit qubit data resulting from the stimulation of one or more qubits to the conditional engine architecture block 104. For example, one or more quantum controllers 106 can transmit qubit data via one or more transmission chips 108. One or more transmission chips 108 of the one or more quantum controller architecture blocks 102 can be operably coupled to one or more receiving chips 110 of the conditional engine architecture block 104. For example, one or more transmission chips 108 of the one or more quantum controller architecture blocks 102 can be operably coupled to one or more receiving chips 110 of the conditional engine architecture block 104 via one or more transmission wire buses 112. Further, one or more transmission chips 108 can include a high-speed pass transmission logic circuit layer 113 that can direct one or more continuous packet transfer protocols utilized to direct qubit data from one or more quantum controllers 106 to the conditional engine architecture block 104.

[0029] In addition, one or more quantum controllers 106 can stimulate one or more qubits according to one or more commands received via one or more receiving chips 110. In various embodiments, the one or more commands can be generated by a conditional engine architecture block 104. As shown in FIG. 1, one or more receiving chips 110 of one or more quantum controller architecture blocks 102 can be operably coupled to one or more transmission chips 108 of a conditional engine architecture block 104. For example, one or more receiving chips 110 of one or more quantum controller architecture blocks 102 can be operably coupled to one or more transmission chips 108 of a conditional engine architecture block 104 via one or more transmission wire buses 112.

[0030] The conditional engine architecture block 104 can include one or more conditional engines 116 operably coupled to one or more transmission chips 108 or receive chips 110 or combinations thereof. As shown in FIG. 1, the conditional engine architecture block 104 can be operably coupled to a plurality of quantum controller architecture blocks 102 via interface 100. Although two quantum controller architecture blocks 102 are shown in FIG. 1, the architecture of interface 100 is not so limited, and embodiments including more than two quantum controller architecture blocks 102 may be envisioned. In various embodiments, the conditional engine 116 can generate one or more commands that direct the operation of one or more quantum controllers 106 based on received qubit data. For example, one or more conditional engines 116 can perform one or more Boolean operations or conversions or combinations thereof based on qubit data transmitted by one or more quantum controller architecture blocks 102 and received via one or more receive chips 110 of the conditional engine architecture block 104. For example, one or more conditional engines 116 can control one or more conditional operations between quantum controllers 106 to perform various applications, such as forcing qubits to a known state or qubit teleportation or combinations thereof.

[0031] In addition, interface 100 may include a common clock source generated from oscillator reference 118. As shown in FIG. 1, common oscillator reference 118 may be operably coupled to both one or more quantum controller architecture blocks 102 and condition engine architecture blocks 104. For example, the transmit clock and receive clock of transmit chip 108 and receive chip 110 of interface 100 may be derived from the common clock of oscillator reference 118. In various embodiments, the common clock may pass through phase - locked loop network 120 to generate a plurality of selectable clocks via glitch - less clock multiplexer 122. Glitch - less clock multiplexer 122 may derive the clock signal of one or more condition engines 116, transmit chip 108, or receive chip 110 of condition engine architecture block 104, or a combination thereof.

[0032] The conditional engine architecture block 104 may further include one or more embedded processors 124 that can utilize one or more training components 126 to execute one or more algorithms for training the interface 100. One or more of the embedded processors 124, training components 126, or combinations thereof may be operably coupled to one or more programmable registers 128 included within the receive chip 110 of the conditional engine architecture block 104. The one or more programmable registers 128 may control one or more delay elements 130 positioned along one or more data paths established by the interface 100. Exemplary delay elements 130 may include, but are not limited to, variable digital delay elements, serial chains of digital buffers (e.g., having stages of a serial chain coupled to a multiplexer), analog circuits, combinations thereof, or the like, or combinations thereof. Further, one or more receive chips 110 of the conditional engine architecture block 104 may include one or more receive logic circuit layers 132 that can transmit qubit data values to the programmable crossbar multiplexer 134.

[0033] In various embodiments, qubit data can be broadcast from one or more quantum controllers 106 and incorporated into the high-speed pass transmission logic circuit layer 113 of the transmission chip 108 of the quantum controller of the architecture block 102. As further described herein, the transmission logic circuit layer 113 can include one or more free-running data pointers 114 or mask fields 115 or combinations thereof. In various embodiments, one or more free-running data pointers 114 can select which qubit data and qubit valid pairs are transmitted on one or more transmission wire buses 112 in each clock cycle. Also, in various embodiments, one or more mask fields 115 can set or clear valid bits in a data packet or combinations thereof, where the bits can be set when received on a corresponding channel of the quantum controller 106 and can be cleared when a routing scheme rotation activates a routing scheme for allocating one or more wires to a given qubit data. The qubit data can further be multiplexed to the number of configurable wires within the transmission wire bus 112. The transmission wire bus 112 can include wires bundled into a packet start pulse for alignment with the receiving logic circuit layer 132 of the corresponding receiving chip 110 and parity signal wires for protecting the qubit data signal, qubit valid signal, or packet start signal or combinations thereof.

[0034] The receive logic circuit layer 132 of the receive chip 110 of the conditional engine architecture block 104 can transmit qubit data to the programmable crossbar multiplexer 134, where the data can be mapped to the receive buffer of the conditional engine 116. In various embodiments, the receive logic circuit layer 132 can also include one or more free-running data pointers 114. Each receive chip 110 can be paired with a respective transmission chip 108, such that one or more free-running data pointers 114 of the receive logic circuit layer 132 can be synchronized with the free-running data pointers 114 of the paired transmission logic circuit layer 113. Synchronization is performed by the training component 126 and can be achieved via one or more training algorithms or computer-implemented methods or combinations thereof further described herein. The receive logic circuit layer 132 can have the same understanding of the number of wires in the transmission wire bus 112 and the number of qubits of the quantum controller 106 coupled to the paired transmission chip 108.

[0035] In various embodiments, the routing of data signals can be matched external to the field programmable gate array ( "FPGA") device to generate minimum skew. The transmission chip 108 or receive chip 110 or combinations thereof that directly drive or receive the transmission wire bus 112 or combinations thereof can be restricted to special I / O buffer registers to minimize internal data skew on the interface 100. Timing constraints can be utilized in an attempt to minimize clock skew to these same registers.

[0036] As shown in FIG. 1, the transmission and reception clocks of the transmission chip 108 and the reception chip 110 are both derived from a common oscillator reference 118 and can pass through the PLL network 120 to generate a plurality of clocks selectable via the glitchless clock multiplexer 122. The selected clocks on the transmission chip 108 and the reception chip 110 can be frequency-matched only if the same frequency is selected via the register selection bits. Although the clocks can be frequency-matched, they cannot be transmitted together with the qubit data, so the interface 100 can be a mesochronous clock interface between the transmission chip 108 and the reception chip 110 that drives and receives the transmission wire bus 112.

[0037] Even if the skew of the transmission wire bus 112 can be matched at all stages including driving and receiving the register, the delay element 130 can be introduced into the data path together with the programmable register 128, thereby enabling the training component 126 to train the data path. As a result, the qubit data bits are centered outside the setup and hold windows of the reception clock from the edge of the mesochronous clock domain. Further, the training component 126 can ensure that the data pattern of the qubit data bits is aligned with the other wires of the transmission wire bus 112. In various embodiments, the training component 126 can select the delay value for the delay element 130 to maximize the timing margin and minimize the risk of future bit slips that may occur due to mismatches caused by component deformation or temperature changes.

[0038] Figures 2-6 illustrate block diagrams of exemplary and non-limiting training component 126 that can execute one or more training algorithms to render the data transfer pattern of the interface to appear as a direct register-to-register transfer, in accordance with various embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. In various embodiments, training component 126 can train interface 100 prior to one or more qubit data transfers between one or more quantum controllers 106 and condition engine 116. For example, training component 126 can interact with programmable register 128 to observe wire data or shift one or more delay elements 130 or a combination thereof.

[0039] As shown in FIG. 2, the training component 126 can include a wire selection component 202. In various embodiments, the wire selection component 202 can select the first wire of the transmission wire bus 112 targeted for training. The data path associated with the selected wire can be controlled by the training component 126 via the operation of one or more delay elements 130. For example, the training component 126 can identify a delay value executed by a programmable register 128 that controls the delay element 130. The training component 126 can analyze each of the various delay routines available for the selected wire by varying the delay value associated with the delay element 130 (e.g., each delay routine can be associated with a respective delay value). In various embodiments, the wire selection component 202 can also designate a wire of each transmission wire bus 112 as a reference wire. For example, the first wire of the transmission wire bus 112 selected by the wire selection component 202 can be considered as a reference wire when training the target transmission wire bus 112.

[0040] As shown in FIG. 3, the training component 126 can further include a domain stability component 302. In various embodiments, the domain stability component 302 can assess the mesochronous clock domain stability of the wire selected in the current delay routine of the data path. 1 or more embodiments, the domain stability component 302 can determine whether the transfer pattern associated with the current delay routine is shown as a stable single register stage between the respective transmission chip 108 and the receiving chip 110. For example, the domain stability component 302 can identify 1 or more patterns by analyzing the string of qubit data bits transmitted by the transmission chip 108. Further, the string pattern characterizing the stable single register stage can be pre-specified by the domain stability component 302. If the string of qubit data bits received by the receiving chip 110 matches the pre-specified pattern, the domain stability component 302 can determine that the mesochronous clock domain stability associated with the current delay value of the delay element 130 is a stable single register transfer level (“RTL”) stage. For example, the programmable register 128 can be a shift register, the pre-specified pattern can be a pre-specified stage of the shift register, and the domain stability component 302 can determine whether the received qubit data string is within the pre-specified shift register stage. If the current delay routine is not characterized by a stable single register stage transfer pattern, the training component 126 can proceed to analyze other delay routines or the wires of the transmission wire bus 112 or a combination thereof.

[0041] In various embodiments, the domain stability component 302 can determine whether the mesochronous clock domain stability is characterized by a stable single register - to - register stage pattern by analyzing the observed data transfer pattern of the wire multiple times. For example, the domain stability component 302 can analyze the data transfer pattern hundreds of times by turning the pattern from the transmitting side on and off. By repeatedly analyzing the data transfer pattern of the current delay routine, the domain stability component 302 can increase the reliability of pattern determination.

[0042] As shown in FIG. 4, the training component 126 can also include a domain region component 402. In various embodiments, the domain region component 402 can track the stable domain region of the mesochronous clock. If the domain stability component 302 determines that the currently evaluated delay routine is a stable single register - to - register stage, the domain region component 402 can then determine whether the selected wire is the reference wire or is aligned with the reference wire. For example, if the selected wire is not the reference wire, the domain region component 402 can cross - reference the qubit data of the selected wire and the qubit data of the reference wire to ensure that the selected wire and the reference wire are in alignment. If the selected wire is neither the reference wire nor aligned with the reference wire, the training component 126 can proceed to analyze other delay routines or the wires of the transmission wire bus 112 or a combination thereof.

[0043] If the selected wire is the reference wire, or if the selected wire is aligned with the reference wire, the domain region component 402 can further determine whether the delay routine achieves a known stable region of the mesochronous clock domain. If the selected wire and the delay routine are within a known stable region, the domain region component 402 can increase the size of each region. For example, the domain region component 402 can increase the size of the region by a specified value (e.g., increase the size of the region by 1). If the selected wire and the delay routine are not within a known stable region, the domain region component 402 can track a new region of the mesochronous clock domain. In various embodiments, the domain region component 402 can thereby track the domain stability associated with each delay routine (e.g., each delay value) of the selected wire. For example, the domain region component 402 can generate a table of the stable delay regions of the selected wire, where the boundaries of the stable regions can be determined by the presence of one or more unstable delay values.

[0044] As shown in FIG. 5, the training component 126 can additionally include a delay value component 502. In various embodiments, the delay value component 502 can determine whether any other delay routines of the selected wire to be evaluated exist. For example, the delay value component 502 can determine whether any delay values of the delay elements 130 that have not yet been evaluated during the training of the selected wire exist. If there are available delay routines for the selected wire that are yet to be evaluated, the delay value component 502 can, in accordance with the above characteristics, establish an alternative delay routine that can be further evaluated by the domain stability component 302 or the domain region component 402 or a combination thereof by increasing the current delay value.

[0045] As shown in FIG. 6, the training component 126 can further include a centering component 602. In various embodiments, the centering component 602 that places a selected wire within the largest stable region of the mesochronous clock domain can select a delay value and thereby select a delay routine. For example, once all available delay routines for a selected wire have been evaluated, the centering component 602 can select the delay value that achieves the largest stable region. Further, the centering component 602 can center the selected wire within the active clock edge of the region such that the qubit data bit is outside of a restrictive time window. For example, the centering component 602 can center the selected wire from the edge of the largest stable clock region such that the qubit data bit is outside of the setup and hold time windows. Further, the training component 126 can repeat the above-described features or operations or combinations thereof using each wire of the target transmission wire bus 112.

[0046] FIG. 7 shows a flowchart of an exemplary and non-limiting training algorithm 700 that can be executed by the training component 126 according to one or more embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. The various stages of the training algorithm 700 are executed by the training component 126 and can be associated with the components of the training component 126 in accordance with the features or operations or combinations thereof described herein.

[0047] At 702, the training algorithm 700 can include a step of selecting (e.g., via the wire selection component 202) the wires of the transmission wire bus 112 targeted for training. At 704, the training algorithm 700 can include a step of assessing mesochronous domain stability at the currently evaluated delay value. For example, the training component 126 can observe the qubit data being transferred on the selected wire having the current delay value. The delay value can take into account one or more delay elements 130 positioned along the data path and can be implemented by the programmable register 128 in the direction of the training component 126.

[0048] At 706, the training algorithm 700 can include a step of determining whether the transfer pattern of the selected wire having the current delay value is shown as a stable single register - to - register stage between chips (e.g., between the transmission chip 108 of the quantum controller architecture block 102 and the receiving chip 110 of the conditional engine architecture block 104). As described herein, in various embodiments, the domain stability component 302 can determine whether the observed qubit data bit string is characterized by a predefined pattern associated with a single RTL stage. If the observed pattern indicates a stable single register - to - register stage, the training algorithm 700 can proceed to step 708. If the observed pattern does not indicate a stable single register - to - register stage, the training algorithm 700 can proceed to step 710.

[0049] In 708, the training algorithm 700 can include a step of determining whether the selected wire is the reference wire. In various embodiments, the domain stability component 302 can specify a wire from the targeted transmission wire bus 112 as the reference wire. For example, the first wire of the targeted transmission wire bus 112 selected for training can be specified as the reference wire. If the selected wire is the reference wire, the training algorithm 700 can proceed to step 712. If the selected wire is not the reference wire, the training algorithm 700 can proceed to step 714.

[0050] In 714, the training algorithm 700 can include a step of determining whether the selected wire is aligned with the reference wire. For example, the observed qubit data of the selected wire can be cross-referenced (e.g., via the domain region component 402) with a snapshot of the qubit data transferred along the reference wire to determine whether the selected wire and the reference wire are aligned. If the selected wire and the reference wire are aligned, the training algorithm 700 can proceed to step 712. If the selected wire and the reference wire are not aligned, the training algorithm 700 can proceed to step 710.

[0051] At 712, the training algorithm 700 can include a stage of determining whether the delay routine is already in the stable region. For example, the domain region component 402 can track the stable region associated with the selected wire via one or more region tracking tables of the stable delay region, where the boundaries of the stable region can be determined by the presence of one or more unstable delay values. If it is determined that the delay routine is within the known stable region, the training algorithm 700 can proceed to stage 716. If the delay routine is not within the known stable region, the training algorithm 700 can proceed to stage 718.

[0052] At 716, the training algorithm 700 can include a stage of increasing the size of the current region. For example, the domain region component 402 can increase the size of the known stable region by a specified value (e.g., by a value of 1). At 718, the training algorithm 700 can include a stage of tracking a new stable region. For example, the domain region component 402 can update the region tracking table associated with the selected wire to reflect an increase in the size of the region or the presence of a new stable region or a combination thereof. The training algorithm 700 can proceed from stage 716 or stage 718 to stage 710.

[0053] At 710, the training algorithm 700 can include a stage of determining whether there are more delay values to be evaluated for the selected wire. For example, the delay value component 502 can check whether all the available delay values of the delay element 130 have been evaluated by the training component 126 with respect to the selected wire. For example, the delay value component 502 can refer to a table constructed by the domain region component 402 to check the previously evaluated delay values and compare these delay values with a list of delay values available for execution by the programmable register 128 with respect to the delay element 130. If there are additional delay values to be evaluated, the training algorithm 700 can proceed to stage 720. If there are no additional available delay values to be evaluated, the training algorithm 700 can proceed to stage 722.

[0054] At 720, the training algorithm 700 can include a stage of increasing the delay value. For example, the delay value component 502 can increase the delay value by a specified value for a delay value that has not yet been evaluated by the training component 126 for the selected wire. As shown in FIG. 7, once the delay value is increased to a new delay value, the training algorithm 700 can evaluate the transfer pattern or domain stability or a combination thereof associated with the new delay value by repeating stages 706 - 718. At 722, the training algorithm 700 can include a stage of selecting the delay value associated with the largest stable region. For example, the centering component 602 can identify the largest region associated with the evaluated delay value by considering the region tracking table constructed by the domain region component 402. In various embodiments, the training algorithm 700 can further, at 722, include a stage of centering the qubit data bits and the delay routine of the selected wire within the received clock domain from the active clock edge. For example, the qubit data bits can be centered from the rising and falling edges of the largest region. Thereby, the qubit data bits can be positioned outside the setup and hold time windows at each edge. For example, if the largest region has a boundary defined by a size of 300 with a minimum delay value of 100 and a maximum delay value of 400, the centering component 602 can select a delay value of 250 for the selected wire.

[0055] In one or more embodiments, the training algorithm 700 can be repeated for each wire of the target transmission wire bus 112 of the interface 100, for each transmission wire bus 112, or for both. For example, the built-in training component 126 can train the interface 100 by performing steps 702-722 for each wire of one or more transmission wire buses 112.

[0056] FIG. 8 shows an exemplary and non - limiting diagram of a continuous packet transfer protocol 800 that can be utilized by interface 100 according to one or more embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. In various embodiments, interface 100 can utilize an exemplary and continuous packet transfer protocol 800 following training executed by an embedded training component 126. As shown in FIG. 8, according to the continuous packet transfer protocol 800, data packets containing only qubit data positions and qubit validities can be continuously transferred between one or more transmission chips 108 of a quantum controller architecture block 102 and a receiving chip 110 of a conditional engine architecture block 104. The boundaries of the data packets can be established during training executed by the training component 126 (e.g., during training executed according to a training algorithm 700). When qubit data becomes available, the continuous packet transfer protocol 800 can hold the data until the next data packet arrives, insert new bits of qubit data (e.g., new qubit measurements) along with qubit validities, and then transmit the packet to the receiving chip 110. Thereby, overhead bits are not required to identify the start and end of the data packet, and source information can be inferred from the bit positions within the data packet. Advantageously, the continuous packet transfer protocol 800 can enable data transfer during the runtime of interface 100 to be executed with low latency so as to overcome qubit degradation that occurs during transfer.

[0057] In one or more embodiments, the continuous packet transfer protocol can be implemented by the transmission logic circuit layer 113 of the transmission chip 108 of the quantum controller of the architecture block 102 in conjunction with the reception logic circuit layer 132 of the reception chip 110 of the conditional engine architecture block 104. Further, the inter-chip transmission wire bus 112 can include "k + 1" wires (e.g., wire 0, wire 1, wire 2 to wire "k") as shown in FIG. 8, where the total number of wires is a positive even integer. The transmission logic circuit layer 113 can be routed through a plurality of routing schemes that indicate wire assignments through a mask of which qubit numbers were sent out via a free-running pointer in the current cycle. Additionally, the transmission logic circuit layer 113 can set a transmission qubit valid vector based on reception from the associated quantum controller 106 acquisition channel. Further, the transmission qubit valid vector can be cleared during transmission of the conditional engine architecture block 104. The reception logic circuit layer 132 can have the same understanding as the transmission logic circuit layer 113 regarding rotation of the routing scheme. Further, the reception logic circuit layer 132 can process, cycle by cycle, the pair of the currently incoming qubit data and validity on the wires of the transmission wire bus 112 and transfer the pair to the conditional engine 116 according to the conditional assignment mapping.

[0058] As shown in FIG. 8, the continuous packet transfer protocol 800 can include a plurality of cycles (e.g., up to "x" cycles, including cycle "n"). Using each cycle, the continuous packet transfer protocol 800 can allocate the wires used to transmit the pair of qubit data and validity by utilizing different routing schemes. The number of cycles can be configured based on the number of pairs of qubit data and validity broadcast from the quantum controller 106. As long as both the transmission logic circuit layer 113 and the reception logic circuit layer 132 are set to the same rotation of the routing scheme and cycle count, the qubit authentication information can be inferred based on the wire used to transfer the data, the current cycle count, or the qubit data bit position within the data package, or a combination thereof.

[0059] If the quantum controller 106 controls the number of qubits "q" and the number of wires "i" of the transmission wire bus 112 is greater than or equal to twice the number of qubits "q" (e.g., 2×q≦i), the qubit data from each qubit can be routed to the same wire (e.g., wire 0) in each cycle (e.g., this is because there are at least enough wires for each qubit data and qubit validity coming from the quantum controller 106). However, if the number of wires "i" is less than twice the number of qubits "q" (e.g., 2×q>i), the transmission logic circuit layer 113 and the reception logic circuit layer 132 rotate through a plurality of routing schemes, and as a result, perform wire allocation alternately for each cycle, thereby transmitting all available pairs of qubit data and validity without authenticating overhead information, or without strictly dedicated wires, or both.

[0060] For example, an array "a" containing packet data can be defined according to Equation 1 below.

Number

Number

[0061] FIG. 8 shows an exemplary routing scheme rotation that modifies wire assignments using each clock cycle. For example, during cycle 0 of the continuous packet transfer protocol 800, qubit data from qubit 0 can be routed to wire 0, qubit valid from qubit 0 can be routed to wire 1, qubit data from qubit 1 can be routed to wire 2, and so on. For example, cycle 0 can follow the routing scheme such that qubit valid routed to wire "k" is from qubit ((k + 1) / 2) - 1 (e.g., for wire 1, "k" is equal to 1, and thus, as shown, qubit valid from qubit 0 is routed to wire 1), and qubit data from the same qubit is routed to the previous wire in the index (e.g., qubit data from qubit 0 is routed to wire 0).

[0062] In the next cycle, the continuous packet transfer protocol 800 can rotate to a new routing scheme such that the wires have different qubit assignments. For example, during cycle 1 of the continuous packet transfer protocol 800, qubit data from qubit 1 can be routed to wire 0, qubit valid from qubit 1 can be routed to wire 1, qubit data from qubit 3 can be routed to wire 2, qubit valid from qubit 3 can be routed to wire 3, and so on. For example, cycle 1 can follow a routing scheme such that qubit valid routed to wire "k" is from qubit ((k + 1) / 2)*2 - 1 (e.g., for wire 3, "k" is equal to 3, and thus qubit valid from qubit 3 is routed to wire 3), and qubit data from the same qubit is routed to the previous wire (e.g., qubit data from qubit 3 is routed to wire 2).

[0063] During exemplary cycle 0, the data packets of qubits 0 and 2 are available as qubit data, and the validity of both qubits is assigned to wires (e.g., wires 0-1 and 4-5). However, during exemplary cycle 1, the data packets of qubits 0 and 2 are not available, because the routing scheme utilized during cycle 1 does not assign wires to the qubit data and validity of these qubits. Thus, the qubit data and validity become available from qubits 0 and 2, and the pairing of the qubit data and validity can be forced by transmission logic circuit layer 113 to wait for a cycle that utilizes a routing scheme having available data packets for the pairing of the qubit data and validity of qubit 0 or 2 or a combination thereof. For example, the pairing of the available qubit data and validity from qubit 0 or 2 or a combination thereof can be forced to wait until exemplary cycle 0, or another cycle having available data packets is active in the rotation of the routing scheme.

[0064] Since the continuous packet transfer protocol 800 rotates through the routing scheme, the rotation protocol can loop to eventually return to the first routing scheme, and the continuous packet transfer protocol 800 can rotate through the routing scheme again once. For example, FIG. 8 shows that the routing scheme of exemplary cycle "n" is the same as the first rotation scheme of exemplary cycle 0, whereby at cycle "n", the continuous packet transfer protocol 800 can start repeating the rotation protocol. For example, the routing scheme of exemplary cycle "n + 1" can be the same as the routing scheme of exemplary cycle 1.

[0065] FIG. 9 shows a flowchart of an exemplary and non-limiting computer-implemented method 900 that can be utilized to train interface 100 according to one or more embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. In various embodiments, computer-implemented method 900 can be utilized by training component 126 via execution of training algorithm 700.

[0066] At 902, computer-implemented method 900 can include assessing, by a system (e.g., interface 100) operably coupled to a processor (e.g., embedded processor 124), the stability of a mesochronous clock domain at one or more delay values for a target wire (e.g., included within transmission wire bus 112) of a quantum controller high-speed path interface (e.g., interface 100) (e.g., via domain stability component 302). At 904, computer-implemented method 900 can include determining, by the mesochronous clock domain is characterized by a stable direct register transfer pattern at one or more delay values (e.g., via domain stability component 302).

[0067] At 906, computer-implemented method 900 can include the system (e.g., interface 100) determining whether the target wire is the reference wire or aligned with the reference wire (e.g., via domain region component 402). For example, domain region component 402 can specify one or more of the wires of transmission wire bus 112 as the reference wire. Further, if the target wire is not the reference wire, domain region component 402 can determine whether the target wire is aligned with the reference wire. At 908, computer-implemented method 900 can include the system (e.g., interface 100) identifying the boundaries of a plurality of stable regions of the mesochronous clock domain (e.g., via domain region component 402 or delay value component 502 or a combination thereof). For example, domain region component 402 can track various stable and unstable regions associated with evaluated delay values via a region tracking table according to various embodiments described herein. At 910, computer-implemented method 900 can include the system (e.g., interface 100) selecting a delay value centered from the active clock edge of the largest stable region (e.g., via centering component 602).

[0068] The present invention can be a system, method, or computer program product, or a combination thereof, integrated at any possible level of technical detail. The computer program product can include computer-readable storage media (s) having computer-readable program instructions for causing a processor to execute aspects of the present invention. A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing, but is not limited thereto. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as raised structures within grooves in which instructions are recorded, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0069] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing devices, or may be downloaded from an external computer or an external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0070] The computer-readable program instructions for performing the operations of the present invention can be in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in object-oriented programming languages such as Smalltalk® and C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partially executed on the user's computer as a stand-alone conditional package, partially executed on the user's computer and partially on a remote computer, or entirely executed on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to implement aspects of the present invention, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute the computer-readable program instructions by personalizing the electronic circuit using the state information of the computer-readable program instructions.

[0071] Aspects of the invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0072] These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram and / or combinations thereof. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, or other device to function in a particular manner, such that the storage medium having instructions stored therein comprises an article of manufacture including instructions for implementing the function / act specified in one or more blocks of the flowchart and / or block diagram and / or combinations thereof.

[0073] Alternatively, the computer-readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram and / or combinations thereof.

[0074] Flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram can represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks can be performed in an order different from that noted in the drawings. For example, two blocks shown in succession can, in fact, be executed substantially simultaneously, or the blocks can be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams or flowchart diagrams, or both, and combinations of blocks in the block diagrams or flowchart diagrams can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0075] To provide additional context for the various embodiments described herein, FIGS. 10 and the following description are intended to provide a general description of a suitable computing environment 1000 in which the various embodiments described herein can be implemented. The embodiments have been described above in the general context of computer-executable instructions that can be executed on one or more computers, but one of ordinary skill in the art will recognize that the embodiments can also be implemented in combination with other program modules or as a conditional combination with hardware, or both.

[0076] Generally, a program module includes routines, programs, components, data structures, etc. that perform a particular task or implement a particular abstract data type. Further, those skilled in the art will understand that the inventive method can be implemented using a single-processor or multi-processor computer system, a minicomputer, a mainframe computer, a mono Internet of Things (「IoT」) device, a distributed computing system, and other computer system configurations including a personal computer, a handheld computing device, or a microprocessor-based electronic device or a programmable consumer electronic device, etc., where each of these can be operably coupled to one or more associated devices.

[0077] The illustrated embodiments of the embodiments herein can also be implemented in a distributed computing environment where a particular task is performed by a remote processing device linked through a communication network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components can be executed from a memory that includes, consists of, or both is and consists of one or more distributed memory units. As used herein, the terms 「memory」 and 「memory unit」 are interchangeable. Further, one or more embodiments described herein can execute the code of computer-executable components in a distributed manner, e.g., multiple processors can operate in combination or jointly to execute code from one or more distributed memory units. As used herein, the term 「memory」 can include a single memory or memory unit at one location, or multiple memories, or a single memory or memory unit at one or more locations in memory units.

[0078] A computing device can typically include various media, where the two terms are used herein as being distinct from each other as follows: a computer-readable storage medium, a machine-readable storage medium, or a communication medium, or a combination thereof. A computer-readable storage medium or a machine-readable storage medium can be any available storage medium that can be accessed by a computer and includes both volatile and non-volatile media, and both removable and non-removable media. By way of example, and without limitation, a computer-readable storage medium or a machine-readable storage medium can be implemented in relation to any method or technology for storing information such as computer-readable instructions or machine-readable instructions, program modules, structured data or unstructured data.

[0079] A computer-readable storage medium can include, but is not limited to, random access memory ("RAM"), read only memory ("ROM"), electrically erasable programmable read only memory ("EEPROM"), flash memory or other memory technologies, compact disc read only memory ("CD-ROM"), digital versatile disc ("DVD"), Blu-ray disc ("BD") or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, solid state drive or other solid state storage devices, or other tangible media or non-transitory media that can be used to store desired information, or a combination thereof. In this regard, the terms "tangible" or "non-transitory" as used herein with respect to storage, memory, or computer-readable media should be understood to exclude only transient signals that propagate by themselves as modifiers, and do not waive rights to all standard storage, memory, or computer-readable media that are not transient signals that propagate by themselves.

[0080] A computer-readable storage medium can be accessed by one or more local or remote computing devices via, for example, access requests, queries, or other data acquisition protocols, for various operations related to the information stored by the medium.

[0081] A communication medium typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery or transport medium. The term "modulated data signal" or signal refers to a signal having one or more of its characteristic sets, or a signal that has been changed in such a way as to encode information within one or more signals. By way of example and not limitation, communication media includes wired media such as a wired network or direct wired connection, as well as wireless media such as acoustic waves, RF, infrared, and other wireless media.

[0082] Referring again to FIG. 10, an exemplary environment 1000 for implementing various embodiments of the aspects described herein includes a computer 1002, a computer 1002 including a processing unit 1004, a system memory 1006, and a system bus 1008. The system bus 1008 couples system components including, but not limited to, the system memory 1006 to the processing unit 1004. The processing unit 1004 can be any of a variety of commercially available processors. Dual processor and other multiprocessor architectures can also be utilized as the processing unit 1004.

[0083] System bus 1008 can be any of several types of bus structures that can be further interconnected to a memory bus, a peripheral bus, and a local bus (with or without a memory controller) that use any of various commercially available bus architectures. System memory 1006 includes ROM 1010 and RAM 1012. The basic input / output system (the "BIOS") can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (the "EPROM"), EEPROM, which includes basic routines that help the BIOS transfer information between elements within computer 1002 during startup and the like. RAM 1012 can also include high-speed RAM such as static RAM for caching data.

[0084] Computer 1002 further includes an internal hard disk drive (the "HDD") 1014 (e.g., EIDE, SATA), one or more external storage devices 1016 (e.g., a magnetic floppy disk drive (the "FDD") 1016, a memory stick or flash drive reader, a memory card reader, etc.), and an optical disk drive 1020 (e.g., capable of reading from or writing to a CD-ROM disk, a DVD, a BD, etc.). Although internal HDD 1014 is shown as being located within computer 1002, internal HDD 1014 can also be configured for external use in a suitable chassis (not shown). Additionally, although not shown in environment 1000, a solid state drive (the "SSD") can be used in addition to, or instead of, HDD 1014. HDD 1014, external storage device 1016, and optical disk drive 1020 can each be connected to system bus 1008 by an HDD interface 1024, an external storage interface 1026, and an optical drive interface 1028, respectively. Interface 1024 for an external drive implementation can include at least one or both of the universal serial bus (the "USB") and Institute of Electrical and Electronics Engineers (the "IEEE") 1394 interface technologies. Other external drive connection technologies are included within the scope of the embodiments described herein.

[0085] The drive and its associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. For computer 1002, the drive and storage media accommodate storage of any data in a suitable digital format. The foregoing description of computer-readable storage media refers to each type of storage device, but other types of storage media that are computer-readable, whether presently existing or developed in the future, may be used in exemplary operating environments, and further, any such storage media may contain computer-executable instructions for performing the methods described herein, as would be understood by one of ordinary skill in the art.

[0086] Some program modules, including operating systems 1030, one or more application programs 1032, other program modules 1034, and program data 1036, may be stored on the drive and in RAM 1012. All or part of an operating system, application, module, or data, or combinations thereof, may also be cached in RAM 1012. The systems and methods described herein may be implemented using various commercially available operating systems, or combinations of operating systems.

[0087] Computer 1002 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment for operating system 1030, and the emulated hardware may optionally differ from the hardware shown in FIG. 10. In such an embodiment, operating system 1030 may include one virtual machine ("VM") of a plurality of virtual machines hosted on computer 1002. Further, operating system 1030 may provide a runtime environment such as a Java (registered trademark) execution environment or.NET Framework for application 1032. The runtime environment is a consistent execution environment that enables application 1032 to be executed on any operating system that includes the runtime environment. Similarly, operating system 1030 can support containers, and application 1032 can be in the form of a container, which is a conditional lightweight, stand-alone, executable package that includes, for example, code, runtime, system tools, system libraries, and settings for the application.

[0088] Furthermore, computer 1002 can be enabled using a security module such as a trusted processing module ("TPM"). For example, using the TPM, a boot component hashes the next upcoming boot component in time and waits for the result to match a protected value before loading the next boot component. This process can occur at any layer in the code execution stack of computer 1002, for example, applied at the application execution level or the operating system ("OS") kernel level, thereby enabling security at any level of code execution.

[0089] The user can input commands and information into the computer 1002 through one or more wired / wireless input devices, such as a keyboard 1038, a touch screen 1040, and a pointing device such as a mouse 1042. Other input devices (not shown) can include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote controls, a joystick, a virtual reality controller or virtual reality headset or a combination thereof, a game pad, a stylus pen, a camera, a gesture sensor input device, a vision movement sensor input device, an image input device such as an emotion detection device or a face detection device, or a biometric input device such as a fingerprint scanner or an iris scanner. These and other input devices are often connected to the processing unit 1004 through an input device interface 1044 that can be connected to the system bus 1008, but can also be connected by other interfaces such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH interface, etc.

[0090] A monitor 1046 or other type of display device can also be connected to the system bus 1008 through an interface such as a video adapter 1048. In addition to the monitor 1046, the computer typically includes other peripheral output devices (not shown) such as speakers, printers, etc.

[0091] Computer 1002 can operate in a networked environment using logical connections via wired communication, wireless communication, or a combination thereof to one or more remote computers such as remote computer 1050. Remote computer 1050 can be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer device or other common network node, and typically only memory / storage device 1052 is shown for simplicity, but includes many or all of the elements described with respect to computer 1002. The logical connections shown include wired / wireless connections to a local area network ("LAN") 1054, or a larger network, such as a wide area network ("WAN") 1056, or a combination thereof. Such LAN networking environments and WAN networking environments are common in offices and enterprises, facilitate enterprise-scale computer networks such as intranets, and all of these can be connected to a global communication network, such as the Internet.

[0092] When used in a LAN networking environment, computer 1002 can be connected to local network 1054 through a wired, wireless, or combination communication network interface or adapter 1058. Adapter 1058 can facilitate wired or wireless communication to LAN 1054, and can also include a wireless access point ("AP") disposed therein for communicating with adapter 1058 in wireless mode.

[0093] When used in a WAN networking environment, computer 1002 may include a modem 1060 or may be connected to a communication server on WAN 1056 via other means for establishing communication on WAN 1056, such as via the Internet. Modem 1060, which may be internal or external and may be a wired or wireless device, may be connected to system bus 1008 via input device interface 1044. In a networked environment, program modules shown relative to computer 1002 or portions thereof may be stored in remote memory / storage device 1052. The network connections shown are exemplary, and it will be appreciated that other means of establishing a communication link between computers may be used.

[0094] When used in either a LAN networking environment or a WAN networking environment, computer 1002, as described above, may access a cloud storage system or other network-based storage system in addition to, or instead of, external storage device 1016. Generally, the connection between computer 1002 and the cloud storage system may be established on LAN 1054 or WAN 1056, for example, by respective adapter 1058 or modem 1060. When connecting computer 1002 to an associated cloud storage system, external storage interface 1026 may manage the storage provided by the cloud storage system to manage other types of external storage, using the assistance of adapter 1058 or modem 1060, or a combination thereof. For example, external storage interface 1026 may be configured to provide access to cloud storage sources as if those sources were physically connected to computer 1002.

[0095] Computer 1002 can be operable to communicate, for example, with a printer, scanner, desktop or portable computer or combination thereof, a portable data assistant, a communication satellite, any device or location associated with a wirelessly detectable tag (e.g., kiosk, newsstand, store shelf, etc.), and any wireless device or entity operably disposed in wireless communication, such as a telephone. This can include wireless fidelity (“Wi-Fi (registered trademark)”) and BLUETOOTH (registered trademark) wireless technologies. Thus, the communication may have a pre-specified structure similar to a conventional network, or may simply be an ad-hoc communication between at least two devices.

[0096] What has been described above includes merely examples of a system, computer program product, and computer-implemented method. Of course, it is not possible to describe every conceivable combination of components, products, or computer-implemented methods, or combinations thereof, for the purposes of describing the present disclosure, but one of ordinary skill in the art may recognize that many more combinations and permutations of the present disclosure are possible. Further, to the extent that the terms “including,” “having,” “comprising,” and the like are used in the detailed description, claims, accompanying documents, and drawings, such terms are intended to be inclusive in a manner similar to the way the term “comprising” is interpreted when used as a transitional phrase in a claim. The descriptions of the various embodiments have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, the practical application of the technology found in the marketplace, or improvements thereto, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

**Claim 1** A computer-implemented method for routing qubit data bits between a quantum controller and a conditional engine by a system operably coupled to a processor, the method comprising training a quantum controller high-speed path interface such that a mesochronous clock domain is characterized directly by an inter-register transfer pattern by adjusting a delay value. **Claim 2** The method of claim 1, further comprising selecting, by the system, a delay value that stabilizes the mesochronous clock domain by shifting a delay device of the quantum controller high-speed path interface. **Claim 3** The method of claim 1 or 2, wherein the training comprises centering the qubit data bit within a receiving clock domain from an active clock edge. **Claim 4** The method of claim 1 or 2, wherein the training maximizes a time margin of a receiving clock domain. **Claim 5** The method according to any one of claims 1 to 4, further comprising identifying boundaries of a plurality of stable regions of the mesochronous clock domain by the system tracking stability of the mesochronous clock domain at a plurality of delay values at which the quantum controller high-speed path interface can be implemented with respect to a target wire. **Claim 6** The training further comprises: selecting, by the system, a preferred delay value from the plurality of delay values associated with the largest stable region from the plurality of stable regions; and utilizing, by the system, the preferred delay value with the target wire to route the qubit data bit. **Claim 7** The method according to any one of claims 1 to 6, further comprising assessing, by the system, stability of the mesochronous clock domain at the delay value with respect to a target wire of the quantum controller high-speed path interface. **Claim 8** The assessing comprises ​ ​ ​ ​ ​ Based on the assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern by the system, determining whether the target wire is the reference wire of the quantum controller high-speed path interface; Based on the assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern by the system, determining whether the target wire is aligned with the reference wire; The computer-implemented method according to claim 7, comprising:

9. The step of assessing further includes: Based on the determination by the system as to whether the target wire is the reference wire or is aligned with the reference wire, determining whether the qubit data bit is within the stable region of the mesochronous clock domain; The computer-implemented method according to claim 8, comprising:

10. A computer program for routing qubit data bits between a quantum controller and a conditional engine, causing a processor to: A procedure for training the quantum controller high-speed path interface by adjusting a delay value such that the mesochronous clock domain of the quantum controller high-speed path interface is characterized by a direct register-to-register transfer pattern; A computer program for execution.

11. Causing the processor to: A procedure for selecting a delay value for stabilizing the mesochronous clock domain by shifting a delay device of the quantum controller high-speed path interface; The computer program according to claim 10, further causing execution.

12. Causing the processor to: A procedure for assessing the stability of the mesochronous clock domain at the delay value with respect to a target wire of the quantum controller high-speed path interface; The computer program according to claim 10 or 11, further causing execution.

13. Causing the processor to: Based on the assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern, a procedure for determining whether the target wire is the reference wire of the quantum controller high-speed path interface; A procedure for determining whether the target wire is aligned with the reference wire based on an assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern, and The computer program according to claim 12, further causing the execution.

14. To the processor, A procedure for determining whether the qubit data bit is within the stable region of the mesochronous clock domain based on a determination of whether the target wire is the reference wire or aligned with the reference wire, and A procedure for increasing the size of the stable region based on a determination that the qubit data bit is within the stable region The computer program according to claim 13, further causing the execution.

15. The delay value is a value from a plurality of delay values evaluated by the processor, and the evaluating procedure renders a plurality of stable regions associated with the plurality of delay values for the target wire. The computer program causes the processor to A procedure for selecting a preferred delay value from the plurality of delay values associated with the largest stable region among the plurality of stable regions, and A procedure for using the preferred delay value together with the target wire to route the qubit data bit The computer program according to claim 14, further causing the execution.

16. A quantum controller high-speed pass interface that routes the qubit data packet between a quantum controller and a conditional engine via a packet transfer protocol in which source information is inferred from a data position within the qubit data packet. A system comprising.

17. The quantum controller broadcasts qubit data to a transmission logic circuit of the quantum controller high-speed pass interface, and the transmission logic circuit is synchronized using a reception logic circuit operably connected to the conditional engine. The system according to claim 16.

18. The transmission logic circuit circulates through a plurality of routing schemes, and the plurality of routing schemes assign the qubit data packet to a transmission wire from a plurality of transmission wires. The system according to claim 17.

19. The system according to claim 18, wherein the packet transfer protocol continuously transfers qubit data between the transmission logic circuit and the reception logic circuit while circulating through the plurality of routing schemes. **Claim 20** The system according to any one of claims 16 to 19, wherein the qubit data packet consists of a pairing of the data position and qubit validity.

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