Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device

Abstract

A substrate current suppression circuit (11) is provided with a fixed voltage line (8) that supplies a fixed voltage to collectors of third and fourth transistors. The fixed voltage is a voltage (VDD2) higher than the base voltage of the third and fourth transistors when a first polarity is P-type, and is a voltage (VSS2) lower than the base voltage when the first polarity is N-type.

Description

Technical Field

[0001] The present disclosure relates to a substrate current suppression circuit, a reference voltage generation circuit, and a semiconductor device.

Background Art

[0002] Conventionally, as a circuit for generating a reference voltage, a bandgap reference circuit (BGR circuit) has been widely used.

[0003] Patent Documents 1 and 2 disclose a circuit that generates a reference voltage by utilizing the difference in the bandgap of two diodes of the same type or two bipolar transistors of the same type connected in diode configuration. According to this, fluctuations due to temperature characteristics and fluctuations in the power supply voltage are corrected, and the accuracy of the reference voltage is improved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when a reference voltage generation circuit is formed on a semiconductor substrate, there is a problem that unnecessary substrate current may be generated.

[0006] The present disclosure provides a substrate current suppression circuit, a reference voltage generation circuit, and a semiconductor device that suppress the generation of unnecessary substrate current.

Means for Solving the Problems

[0007] A substrate current suppression circuit according to one aspect of the present disclosure includes a semiconductor substrate of a first polarity having a first main surface and a second main surface located on the side opposite to the first main surface, first to fourth transistors formed on the first main surface side of the semiconductor substrate, and a fixed voltage line that supplies a fixed voltage to the collector of the third transistor and the collector of the fourth transistor. The collector of the first transistor and the collector of the second transistor are each connected to a substrate region of the first polarity on the second main surface side in the semiconductor substrate. The polarity of the third transistor is opposite to that of the first transistor, and the polarity of the fourth transistor is opposite to that of the second transistor. The fixed voltage is a voltage higher than the base voltages of the third transistor and the fourth transistor when the first polarity is P-type, and is a voltage lower than the base voltage when the first polarity is N-type.

[0008] Further, a reference voltage generation circuit according to one aspect of the present disclosure includes the substrate current suppression circuit and a bandgap reference circuit including the substrate current suppression circuit.

[0009] Further, a reference voltage generation circuit according to one aspect of the present disclosure includes the substrate current suppression circuit, a current source that generates a current according to a control signal, a first resistor that connects the current source and the base of the third transistor, a second resistor and a third resistor that connect the current source and the base of the fourth transistor and are connected in series with each other, a differential amplifier that detects a difference between the base voltage of the third transistor and the voltage at the connection point of the second resistor and the third resistor and feeds back the control signal indicating the difference to the current source, and an output terminal that outputs the voltage at the connection point of the current source and the first resistor as a reference voltage.

[0010] Further, a semiconductor device according to one aspect of the present disclosure includes the reference voltage generation circuit and an avalanche photodiode formed on the semiconductor substrate.

[0011] Note that these general or specific aspects may be implemented in a system or an integrated circuit, or may be implemented in any combination of a system and an integrated circuit.

Advantages of the Invention

[0012] According to the substrate current suppression circuit, reference voltage generation circuit, and semiconductor device of the present disclosure, generation of unnecessary substrate current can be suppressed.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7A

Figure 7B

Figure 7C

Figure 8A

Figure 8B

Figure 8C

DETAILED DESCRIPTION OF THE INVENTION

[0014] (Knowledge underlying the present disclosure) The inventors of the present invention have found that the following problems occur with respect to the reference voltage generation circuit described in the "Background Art" section. This will be described with reference to the drawings.

[0015] FIG. 7A is a diagram showing a reference voltage generation circuit 90 according to Comparative Example 1. Further, FIG. 7B is an explanatory diagram showing a partial cross-sectional example of the reference voltage generation circuit according to Comparative Example 1. The reference voltage generation circuit 90 is configured as a bandgap reference circuit.

[0016] In FIG. 7A, the reference voltage generation circuit 90 includes a PNP transistor 91, a PNP transistor 92, a current source 95, a differential amplifier 96, an output terminal 97, and resistors R91 to R93. This reference voltage generation circuit 90 shows a circuit example formed on a P-type semiconductor substrate. VDD in the figure indicates a power supply line, and VSS indicates a ground line. Vsub indicates a substrate voltage, that is, a voltage applied to the region Psub on the back side of the semiconductor substrate in FIG. 7B.

[0017] The operation of generating the reference voltage in the reference voltage generation circuit 90 is the same as that in prior art documents such as Patent Documents 1 and 2, and thus the description thereof is omitted here.

[0018] In FIG. 7B, a cross-section of a part of the reference voltage generation circuit 90 formed on the semiconductor substrate, that is, a circuit part including the PNP transistor 91, is schematically shown. The region Psub in the figure is a P-type region of the semiconductor substrate. The region N is an N-type contact region on the surface of the semiconductor substrate. The region NW is an N-type well region. The region NX is an N-type embedded region. The region P is a P-type contact region on the surface of the semiconductor substrate. The region PW is a P-type well region. The region PX is a P-type embedded region.

[0019] As shown in FIG. 7B, the emitter of the PNP transistor 91 corresponds to the contact region P to which the voltage V1 is applied. The base of the PNP transistor 91 corresponds to the embedded region NX, the well region NW, and the contact region N to which the voltage VSS is applied. The collector of the PNP transistor 91 corresponds to the P-type region Psub.

[0020] Also, although not shown explicitly in FIG. 7A but shown in FIG. 7B, a diode-connected PNP transistor 91a is formed. The emitter and the base of the PNP transistor 91a are common to the emitter and the base of the PNP transistor 91. The collector of the PNP transistor 91a corresponds to the contact region P to which the voltage VSS is applied. The base and the collector of the PNP transistor 91a are connected to each other, that is, diode-connected.

[0021] Here, the relationship between the PNP transistor 91 and the PNP transistor 91a will be described.

[0022] When the potential of the region Psub is, for example, equal to or higher than the potential of VSS, the PNP transistor 91a essentially functions as a diode that constitutes the reference voltage generation circuit 90 connected in diode. In this case, the PNP transistor 91 is a parasitic transistor and is an ignorable existence, or an existence that functions in the same way as the PNP transistor 91a.

[0023] On the other hand, when the potential of the region Psub is lower than the potential of VSS, as schematically shown in FIG. 7B, unnecessary substrate current can be generated from the emitter to the collector of the PNP transistor 91. In this case, since the unnecessary substrate current flows, no current flows through the PNP transistor 91a, and the PNP transistor 91a does not substantially function as a diode. There is a problem that the unnecessary substrate current flowing through the PNP transistor 91 can be a cause of malfunction of the reference voltage generation circuit 90.

[0024] Note that the PNP transistor 92 in Fig. 7A also has the same problem as the PNP transistor 91.

[0025] Next, an example in which this problem can occur more prominently will be described.

[0026] Fig. 7C is an explanatory diagram showing another partial cross-sectional example of the reference voltage generation circuit according to Comparative Example 1. Fig. 7C is different from Fig. 7B in that an avalanche photodiode APD and a power supply 99 are added to the semiconductor substrate.

[0027] A high reverse bias voltage of about 20 volts is applied to the avalanche photodiode APD by the power supply 99. That is, as shown in Fig. 7C, a large negative voltage is applied to the region Psub on the back side of the semiconductor substrate by the power supply 99. Due to this negative voltage, there is a problem that the unnecessary substrate current flowing through the PNP transistor 91 increases more than in Fig. 7B. This substrate current becomes a factor in the malfunction of the reference voltage generation circuit 90 and the malfunction of the avalanche photodiode.

[0028] Next, this problem will be described using Comparative Example 2.

[0029] Fig. 8A is a diagram showing the reference voltage generation circuit 90 according to Comparative Example 2. Fig. 8B is an explanatory diagram showing a partial cross-sectional example of the reference voltage generation circuit 90 according to Comparative Example 2.

[0030] In Fig. 8A, the reference voltage generation circuit 90 includes a PNP transistor 91, a PNP transistor 92, an NPN transistor 93, an NPN transistor 94, a current source 95, a differential amplifier 96, an output terminal 97, and resistors R91 to R93. This reference voltage generation circuit 90 shows an example of a circuit formed on a P-type semiconductor substrate. The symbols such as VDD, VSS, Vsub, and region N in the figure are the same as those in Fig. 7A.

[0031] As shown in FIG. 8B, the emitter of the PNP transistor 91 corresponds to the well region PW and the contact region P to which the voltage V1 is applied. The base of the PNP transistor 91 corresponds to the embedded region NX, the well region NW, and the contact region N to which the voltage V1 is applied. The collector of the PNP transistor 91 corresponds to the region Psub which serves as the substrate base of the P-type semiconductor region. This PNP transistor 91 can be said to be an unintentionally formed parasitic transistor rather than an essential transistor intentionally formed in the reference voltage generation circuit 90. When the potential of the region Psub is lower than the potential of VSS, as schematically shown in FIG. 8B, an unnecessary substrate current may be generated from the emitter to the collector of the PNP transistor 91.

[0032] The emitter of the NPN transistor 93 corresponds to the N-type region for contact to which the voltage VSS is applied. The base of the NPN transistor 93 corresponds to the contact region P to which the voltage V1 is applied. The collector of the NPN transistor 93 corresponds to the embedded region NX. In this way, the base and the collector of the NPN transistor 93 are connected to each other via the resistor R95, and the voltage V1 is applied. That is, the NPN transistor 93 is diode-connected.

[0033] Next, the relationship between the PNP transistor 91 and the NPN transistor 93 will be described.

[0034] The NPN transistor 93 functions as a diode. On the other hand, the PNP transistor 91 is a parasitic transistor.

[0035] When the potential of the region Psub is lower than the potential of VSS, as schematically shown in FIG. 8B, an unnecessary substrate current may be generated from the emitter to the collector of the PNP transistor 91. There is a problem that this unnecessary substrate current may cause a malfunction of the reference voltage generation circuit 90.

[0036] Note that the PNP transistor 92 also has the same problem as the PNP transistor 91.

[0037] Furthermore, an example in which this problem can occur more prominently will be described.

[0038] FIG. 8C is an explanatory diagram showing another partial cross-sectional example of the reference voltage generation circuit according to Comparative Example 2. The circuit configuration of FIG. 8C is different from that of FIG. 8B in that an avalanche photodiode APD and a power supply 99 are added to the semiconductor substrate. Also in the circuit configuration of FIG. 8C, similar to FIG. 7C, there is a problem that the unnecessary substrate current flowing through the PNP transistor 91 increases more than in the circuit configuration of FIG. 8B. This substrate current becomes a factor in the malfunction of the reference voltage generation circuit 90 and the malfunction of the avalanche photodiode.

[0039] Therefore, the present disclosure provides a substrate current suppression circuit, a reference voltage generation circuit, a semiconductor device reference voltage generation circuit, etc. that suppress the generation of unnecessary substrate current.

[0040] In order to solve such a problem, a substrate current suppression circuit according to an aspect of the present disclosure includes a semiconductor substrate of a first polarity having a first main surface and a second main surface, first to fourth transistors formed on the first main surface side of the semiconductor substrate, and a fixed voltage line that supplies a fixed voltage to the collector of the third transistor and the collector of the fourth transistor. The collector of the first transistor and the collector of the second transistor are each connected to a first-polarity substrate region on the second main surface side in the semiconductor substrate. The collector of the third transistor is connected to the base of the first transistor, the emitter of the third transistor is connected to the base of the first transistor, the polarity of the third transistor is opposite to that of the first transistor, the collector of the fourth transistor is connected to the base of the second transistor, the emitter of the fourth transistor is connected to the base of the second transistor, the polarity of the fourth transistor is opposite to that of the second transistor, the fixed voltage is a voltage higher than the base voltages of the third transistor and the fourth transistor when the first polarity is P-type, and is a voltage lower than the base voltage when the first polarity is N-type.

[0041] Note that the statement that the polarity of the third transistor is opposite to that of the first transistor has the following meaning. The polarity of the base of the third transistor is opposite to that of the base of the first transistor. That is, one of the third transistor and the first transistor is an NPN-type transistor, and the other is a PNP-type transistor.

[0042] Also, a reference voltage generation circuit according to an aspect of the present disclosure includes the substrate current suppression circuit and a bandgap reference circuit including the substrate current suppression circuit.

[0043] Also, a semiconductor device according to an aspect of the present disclosure includes a reference voltage generation circuit and an avalanche photodiode formed on the semiconductor substrate.

[0044] According to the above current suppression circuit, reference voltage generation circuit, and semiconductor device, generation of unnecessary substrate current can be suppressed.

[0045] Note that these general or specific aspects may be implemented by a system, an integrated circuit, or any combination of a system and an integrated circuit.

[0046] Hereinafter, embodiments will be specifically described with reference to the drawings.

[0047] Note that all of the embodiments described below show general or specific examples. Numerical values, shapes, materials, components, arrangement positions of components, connection forms, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0048] (Embodiment 1) FIG. 1 is a diagram showing a configuration example of a reference voltage generation circuit 10 including a substrate current suppression circuit 11 according to Embodiment 1. Further, FIG. 2 is an explanatory diagram showing a partial cross-sectional example of the substrate current suppression circuit according to Embodiment 1. The reference voltage generation circuit 10 is configured as a bandgap reference circuit.

[0049] In FIG. 1, the reference voltage generation circuit 10 includes a substrate current suppression circuit 11, a current source 5, a differential amplifier 6, an output terminal 7, a resistor R1, a resistor R2, and a resistor R3. As shown in FIG. 2, this reference voltage generation circuit 10 shows a circuit example formed on a semiconductor substrate 30 of the first polarity. The semiconductor substrate 30 in FIG. 2 shows the case where the first polarity is P-type. Also, VDD in FIG. 1 indicates a power supply line, and VSS indicates a ground line. Vsub indicates a substrate voltage, that is, the voltage applied to the region Psub on the back side of the semiconductor substrate in FIG. 2.

[0050] First, the substrate current suppression circuit 11 will be described.

[0051] As shown in FIG. 1, the substrate current suppression circuit 11 includes a first transistor 1, a second transistor 2, a third transistor 3, a fourth transistor 4, a fixed voltage line 8, and a fixed voltage source 9a.

[0052] Each of the first transistor 1 to the fourth transistor 4 is formed on the first main surface side of the semiconductor substrate 30. The first main surface of the semiconductor substrate 30 is the substrate surface on the side where the first transistor 1 and the like are formed. Also, the second main surface is the substrate surface of the semiconductor substrate 30 on the side opposite to the first main surface.

[0053] Each of the first transistor 1 and the second transistor 2 is a PNP transistor.

[0054] The collector of the first transistor 1 is connected to the substrate region 31. In other words, the collector of the first transistor 1 and the substrate region 31 are not separate entities, and the collector of the first transistor 1 is all or part of the substrate region 31.

[0055] The collector of the second transistor 2 is connected to the substrate region 31. In other words, the collector of the second transistor 2 and the substrate region 31 are not separate entities, and the collector of the second transistor 2 is all or part of the substrate region 31.

[0056] The third transistor 3 has a polarity opposite to that of the first transistor 1 and is of the NPN type. That is, while the first transistor 1 is of the PNP type, the third transistor 3 is of the NPN type. The collector of the third transistor 3 is connected to the base of the first transistor 1.

[0057] The base of the third transistor 3 is connected to the emitter of the first transistor 1.

[0058] The collector of the third transistor is connected to a fixed voltage line 8 that supplies a fixed voltage.

[0059] The fourth transistor 4 has a polarity opposite to that of the second transistor 2 and is of the NPN type. That is, while the second transistor 2 is of the PNP type, the fourth transistor 3 is of the NPN type. The collector of the fourth transistor 4 is connected to the base of the second transistor 2.

[0060] The base of the fourth transistor 4 is connected to the emitter of the second transistor.

[0061] The collector of the fourth transistor 4 is connected to a fixed voltage line 8 that supplies a fixed voltage.

[0062] The fixed voltage source 9a supplies a fixed voltage to the collectors of the third transistor 3 and the fourth transistor 4 via the fixed voltage line 8. Here, the fixed voltage is a voltage VDD2 higher than the base voltages of the third transistor 3 and the fourth transistor 4 when the first polarity is of the P type, that is, in the case of FIG. 2. If the first polarity is of the N type, it is a voltage VSS2 lower than the above base voltage. This fixed voltage completely turns off the first transistor 1 and the second transistor 2. That is, unnecessary substrate current is suppressed.

[0063] Next, an example of the cross-sectional structure shown in FIG. 2 will be described. FIG. 2 schematically shows a cross-section of a part of the substrate current suppression circuit 11 formed on the semiconductor substrate 30, that is, a circuit part including the first transistor 1 and the third transistor 3. The region Psub in the figure is the substrate region 31 of the first polarity, that is, the P-type substrate region. The region N is an N-type contact region on the surface side of the semiconductor substrate 30, that is, the first main surface side. The region NW is an N-type well region. The region NX is an N-type buried region. The region P is a P-type contact region on the surface side of the semiconductor substrate 30, that is, the first main surface side. The region PW is a P-type well region. The region PX is a P-type buried region.

[0064] As shown in FIG. 2, the emitter of the first transistor 1 corresponds to the well region PW and the contact region P to which the voltage V1 is applied. In other words, the emitter of the first transistor 1 is all or part of the contact region P to which the voltage V1 is applied and the well region PW adjacent immediately below the region P.

[0065] The base of the first transistor 1 corresponds to the buried region NX, the well region NW, and the contact region N to which the voltage VDD2 is applied. In other words, the base of the first transistor 1 is all or part of the buried region NX, the well region NW, and the contact region N to which the voltage VDD2 is applied.

[0066] The collector of the first transistor 1 corresponds to the substrate region 31 on the second main surface side of the semiconductor substrate 30. In other words, the collector of the first transistor 1 is not separate from the substrate region 31, and the collector of the first transistor 1 is all or part of the substrate region 31.

[0067] This first transistor 1 is an unintentionally formed parasitic transistor rather than an intentionally formed transistor. Even when the potential of the region Psub is a negative voltage lower than the potential of VSS, as schematically shown in FIG. 2, the first transistor 1 can suppress the generation of unnecessary substrate current from the emitter to the collector. This is because when the voltage VDD2 is applied to the base of the first transistor 1, the first transistor 1 is completely turned off. The voltage VDD2 is a voltage higher than the voltage V1.

[0068] Also, the emitter of the third transistor 3 corresponds to the N-type region for contact to which the voltage VSS is applied. In other words, the emitter of the third transistor 3 is all or part of the N-type region for contact to which the voltage VSS is applied.

[0069] The base of the third transistor 3 corresponds to the region P for contact to which the voltage V1 is applied and the well region PW directly below it. In other words, the base of the third transistor 3 is all or part of the region P for contact to which the voltage V1 is applied and the well region PW directly below it.

[0070] The collector of the third transistor 3 corresponds to the embedded region NX, the well region NW, and the region N for contact to which the voltage VDD2 is applied. In other words, the collector of the third transistor 3 is all or part of the embedded region NX, the well region NW, and the region N for contact to which the voltage VDD2 is applied. Also, the collector of the third transistor 3 is connected to the base of the first transistor 1. In other words, the region in the semiconductor substrate 30 corresponding to the collector of the third transistor 3 is also the region corresponding to the base of the first transistor 1.

[0071] Note that the second transistor 2 and the fourth transistor 4 in FIG. 1 may have the same configuration as the first transistor 1 and the third transistor 3 in FIG. 2. The second transistor 2 can also suppress the generation of unnecessary substrate current in the same manner as the first transistor 1.

[0072] Also, the pair of the first transistor 1 and the third transistor 3, and the pair of the second transistor 2 and the fourth transistor 4 may constitute a part of a circuit pair formed by a current mirror circuit. Each of the second transistor 2 and the fourth transistor 4 may be composed of K parallel transistors. The mirror ratio may be 1 to (1 / K). Here, K may be 1 or an integer greater than or equal to 1.

[0073] Next, the reference voltage generation circuit 10 will be described.

[0074] The reference voltage generation circuit 10 in FIG. 1 includes a substrate current suppression circuit 11, a current source 5, a differential amplifier 6, an output terminal 7, a resistor R1, a resistor R2, and a resistor R3.

[0075] The current source 5 is a current source that generates a current according to an output signal from the differential amplifier 6. The current source 5 in FIG. 1 is composed of a PMOS transistor. The source of the PMOS transistor is connected to the power supply VDD. The drain of the PMOS transistor is connected to a reference voltage output line. The reference voltage output line is a wiring connected to the output terminal 7 that outputs a reference voltage, one end of the resistor R1, and one end of the resistor R2. The gate of the PMOS transistor inputs the output signal of the differential amplifier 6. Note that the current source 5 may be composed of an NMOS transistor.

[0076] The differential amplifier 6 negatively feeds back an output signal indicating the difference between the voltage V1 and the voltage V2 to the gate of the PMOS transistor. The negative feedback of the output signal from the differential amplifier 6 to the current source 5 makes the difference between the voltage V1 and the voltage V2 zero. Note that the voltage V1 and the voltage V2 are set to vary in the opposite direction with respect to fluctuations in the power supply voltage VDD and temperature fluctuations. In addition, the above negative feedback keeps the reference voltage of the reference voltage output line constant.

[0077] The output terminal 7 is a terminal that outputs the voltage of the reference voltage output line as a reference voltage.

[0078] The resistor R1 defines the current value flowing from the current source 5 to the combination of the first transistor 1 and the third transistor 3. Also, it defines the voltage V1.

[0079] The resistors R2 and R3 define the current value flowing from the current source 5 to the combination of the second transistor 2 and the fourth transistor 4. Also, the resistors R2 and R3 are set so that the voltage V2, which is their voltage division value, is the same as the voltage V1.

[0080] The combination of the resistor R1, the first transistor 1, and the third transistor 3 and the combination of the resistor R2, the resistors R3, the second transistor 2, and the fourth transistor 4 form a current mirror circuit. Also, the temperature characteristics of the combination of the first transistor 1 and the third transistor 3 are configured to have a positive temperature coefficient. In contrast, the temperature characteristics of the combination of the second transistor 2 and the fourth transistor 4 are configured to have a negative temperature coefficient. Thereby, fluctuations depending on the temperature characteristics of the reference voltage are suppressed.

[0081] Note that the substrate current suppression circuit 11 may be a part of other circuits other than the reference voltage generation circuit 10. The other circuit may be, for example, a temperature sensor. The temperature sensor can use the output signal of the differential amplifier 6 in FIG. 1 as a signal indicating the temperature by giving a positive temperature coefficient to the temperature characteristics of the combination of the first transistor 1 and the third transistor 3 and a negative temperature coefficient to the temperature characteristics of the combination of the second transistor 2 and the fourth transistor 4.

[0082] As described above, the substrate current suppression circuit 11 according to Embodiment 1 includes a semiconductor substrate 30 of a first polarity having a first main surface and a second main surface located on the side opposite to the first main surface, first to fourth transistors 1 to 4 formed on the first main surface side of the semiconductor substrate 30, and a fixed voltage line 8 that supplies a fixed voltage to the collectors of the third transistor 3 and the fourth transistor 4. The collectors of the first transistor 1 and the second transistor 2 are each connected to a substrate region 31 of the first polarity on the second main surface side in the semiconductor substrate 30. The polarity of the third transistor 3 is opposite to that of the first transistor 1, and the polarity of the fourth transistor 4 is opposite to that of the second transistor 2. The fixed voltage is a voltage VDD2 higher than the base voltages of the third transistor 3 and the fourth transistor 4 when the first polarity is P-type, and a voltage VSS2 lower than the base voltage when the first polarity is N-type.

[0083] According to this, each of the first transistor 1 and the second transistor 2 can suppress the generation of unnecessary substrate current.

[0084] For example, the collector of the third transistor 3 may be connected to the base of the first transistor 1, and the base of the third transistor 3 may be connected to the emitter of the first transistor 1.

[0085] For example, the collector of the fourth transistor 4 may be connected to the base of the second transistor 2, and the base of the fourth transistor 4 may be connected to the emitter of the second transistor 2.

[0086] For example, the first polarity may be P-type, each of the first and second transistors may be PNP-type, and each of the third and fourth transistors may be NPN-type.

[0087] For example, the pair of the first transistor and the third transistor and the pair of the second transistor and the fourth transistor may be circuit pairs that constitute a part of a current mirror circuit.

[0088] According to this, the substrate current suppression circuit 11 can suppress the generation of unnecessary substrate current in the current mirror circuit.

[0089] Further, the reference voltage generation circuit 10 according to Embodiment 1 includes a substrate current suppression circuit 11 and a bandgap reference circuit including the substrate current suppression circuit 11.

[0090] According to this, the generation of unnecessary substrate current in the bandgap reference circuit can be suppressed.

[0091] Further, the reference voltage generation circuit 10 according to Embodiment 1 includes a substrate current suppression circuit 11, a current source 5 that generates a current according to a control signal, a resistor R1 (first resistor) that connects the current source 5 and the base of the third transistor, a resistor R2 (second resistor) and a resistor R3 (third resistor) that are connected in series and connect the current source 5 and the base of the fourth transistor, a differential amplifier 6 that detects the difference between the base voltage of the third transistor 3 and the voltage at the connection point of the resistors R2 and R3 and feeds back a control signal indicating the difference to the current source 5, and an output terminal 7 that outputs the voltage at the connection point of the current source 5 and the resistor R1 as a reference voltage.

[0092] According to this, the generation of unnecessary substrate current in the reference voltage generation circuit 10 can be suppressed.

[0093] For example, the semiconductor substrate 30 includes a substrate terminal for applying a substrate voltage to the second main surface, and the substrate voltage may be a negative voltage when the first polarity is P-type, or a positive voltage when the first polarity is N-type.

[0094] (Embodiment 2) In Embodiment 2, a substrate current suppression circuit, a reference voltage generation circuit, and a semiconductor device using a semiconductor substrate of opposite polarity and transistors of opposite polarity will be described with respect to Embodiment 1.

[0095] FIG. 3 is a diagram showing a configuration example of a reference voltage generation circuit 10 including a substrate current suppression circuit 11 according to Embodiment 2. FIG. 4 is an explanatory diagram showing a cross-sectional example of the substrate current suppression circuit 11 according to Embodiment 2.

[0096] Compared with FIG. 1, FIG. 3 is mainly different in that the polarity of the semiconductor substrate and the polarity of the transistors are reversed, and a fixed voltage source 9b is provided instead of the fixed voltage source 9a. Hereinafter, the description will focus on the differences.

[0097] In FIGS. 3 and 4, the semiconductor substrate 30 is an N-type instead of a P-type. Each of the first transistor 1 and the second transistor 2 is an NPN transistor. Each of the third transistor 3 and the fourth transistor 4 is a PNP transistor. Therefore, the polarity of the voltage applied to the semiconductor substrate 30 and these transistors is also reversed.

[0098] The fixed voltage source 9b supplies a fixed voltage to the collectors of the third transistor 3 and the fourth transistor 4 via the fixed voltage line 8. Here, when the first polarity is N-type as shown in FIG. 4, the fixed voltage is a voltage VSS2 lower than the base voltages of the third transistor 3 and the fourth transistor 4.

[0099] As described above, the substrate current suppression circuit 11 according to Embodiment 2 includes a semiconductor substrate 30 of a first polarity having a first main surface and a second main surface, first to fourth transistors 1 to 4 formed on the first main surface side of the semiconductor substrate 30, and a fixed voltage line 8 that supplies a fixed voltage to the collectors of the third transistor 3 and the fourth transistor 4. The collectors of the first transistor 1 and the second transistor 2 are each connected to a substrate region 31 of the first polarity on the second main surface side in the semiconductor substrate 30. The polarity of the third transistor is opposite to that of the first transistor 1, and the polarity of the fourth transistor 4 is opposite to that of the second transistor 2. The fixed voltage is a voltage VDD2 higher than the base voltages of the third transistor 3 and the fourth transistor 4 when the first polarity is P-type, and is a voltage VSS2 lower than the base voltage when the first polarity is N-type.

[0100] According to this, each of the first transistor 1 and the second transistor 2 can suppress the generation of unnecessary substrate current.

[0101] For example, the collector of the third transistor 3 may be connected to the base of the first transistor 1, and the base of the third transistor 3 may be connected to the emitter of the first transistor 1.

[0102] For example, the collector of the fourth transistor 4 may be connected to the base of the second transistor 2, and the base of the fourth transistor 4 may be connected to the emitter of the second transistor 2.

[0103] For example, the first polarity may be N-type, each of the first and second transistors may be NPN-type, and each of the third and fourth transistors may be PNP-type.

[0104] (Embodiment 3) In Embodiment 3, a configuration example of a semiconductor device including the reference voltage generation circuit 10 of Embodiment 1 will be described.

[0105] FIG. 5 is a diagram showing a configuration example of a semiconductor device according to Embodiment 3. FIG. 6 is an explanatory diagram showing a cross-sectional example of the semiconductor device according to Embodiment 3.

[0106] The semiconductor device 20 in FIG. 5 includes a reference voltage generation circuit 10 and an APD 12. Note that a power supply 21 is also shown in FIG. 5.

[0107] The reference voltage generation circuit 10 may be the same as that in FIG. 1 described in Embodiment 1.

[0108] The APD 12 is an avalanche photodiode, and has a Geiger multiplication mode in which charges are generated by the incidence of photons and the charges generated by the avalanche effect are multiplied. In the Geiger multiplication mode, a predetermined reverse bias voltage (for example, about 20 V) is required. The APD 12 also has a linear operation mode in which charges proportional to the incident photons are generated. In the Geiger multiplication mode, a reverse bias voltage different from that in the linear operation mode is required.

[0109] The power supply 21 applies a substrate voltage Vsub to the substrate terminal or the substrate electrode on the back surface, that is, the second main surface of the semiconductor substrate 30 in order to supply a reverse bias voltage to the APD 12.

[0110] As described above, the semiconductor device according to Embodiment 3 includes the reference voltage generation circuit 10 and the avalanche photodiode APD formed on the semiconductor substrate 30.

[0111] According to this, generation of unnecessary substrate current can be suppressed.

[0112] Note that the reference voltage generation circuit 10 in FIG. 5 may be the reference voltage generation circuit 10 of Embodiment 2. In this case, the polarities of the APD 12 and the power supply 21 may be reversed.

[0113] Note that in each of the above embodiments, each component may be configured by dedicated hardware.

[0114] The substrate current suppression circuit, reference voltage generation circuit, and semiconductor device according to one or more aspects have been described based on the embodiments. However, the present disclosure is not limited to these embodiments. As long as it does not depart from the spirit of the present disclosure, various modifications conceived by those skilled in the art applied to these embodiments, or forms constructed by combining components in different embodiments, may also be included within the scope of one or more aspects.

Industrial Applicability

[0115] The present disclosure can be applied to a substrate current suppression circuit, a reference voltage generation circuit, and a semiconductor device, and for example, can be applied to an imaging device.

Description of Reference Numerals

[0116] 1 First transistor 2 Second transistor 3 Third transistor 4 Fourth transistor 5 Current source 6 Differential amplifier 7 Output terminal 8 Fixed voltage line 9a, 9b Fixed voltage source 10 Reference voltage generation circuit 11 Substrate current suppression circuit 12 APD 20 Semiconductor device 21 Power supply 30 Semiconductor substrate 31 Substrate region R1, R2, R3 Resistor

Claims

1. A semiconductor substrate of a first polarity having a first main surface and a second main surface located on the side opposite to the first main surface; First to fourth transistors formed on the first main surface side of the semiconductor substrate; A fixed voltage line for supplying a fixed voltage to the collector of the third transistor and the collector of the fourth transistor; and Each of the collector of the first transistor and the collector of the second transistor is connected to a substrate region of the first polarity on the second main surface side in the semiconductor substrate; The polarity of the third transistor is opposite to the polarity of the first transistor; The polarity of the fourth transistor is opposite to the polarity of the second transistor; The fixed voltage is a voltage higher than the base voltages of the third transistor and the fourth transistor when the first polarity is P-type, and is a voltage lower than the base voltage when the first polarity is N-type A substrate current suppression circuit.

2. The collector of the third transistor is connected to the base of the first transistor; The base of the third transistor is connected to the emitter of the first transistor The substrate current suppression circuit according to claim 1.

3. The collector of the fourth transistor is connected to the base of the second transistor; The base of the fourth transistor is connected to the emitter of the second transistor The substrate current suppression circuit according to claim 1 or 2.

4. The first polarity is P-type; Each of the first and second transistors is PNP-type; Each of the third and fourth transistors is NPN-type The substrate current suppression circuit according to any one of claims 1 to 3.

5. The pair of the first transistor and the third transistor and the pair of the second transistor and the fourth transistor are circuit pairs constituting a part of a current mirror circuit The substrate current suppression circuit according to any one of claims 1 to 4.

6. The substrate current suppression circuit according to any one of claims 1 to 5; A bandgap reference circuit including the substrate current suppression circuit; and A reference voltage generation circuit.

7. The substrate current suppression circuit according to any one of claims 1 to 5; A current source that generates a current according to a control signal; A first resistor connecting the current source and the base of the third transistor; Connect the current source to the base of the fourth transistor, and the second resistor and the third resistor connected in series with each other, A differential amplifier that detects the difference between the base voltage of the third transistor and the voltage at the connection point of the second resistor and the third resistor, and feeds back the control signal indicating the difference to the current source, An output terminal that outputs the voltage at the connection point between the current source and the first resistor as a reference voltage, A reference voltage generation circuit.

8. The semiconductor substrate includes a substrate terminal for applying a substrate voltage to the second main surface, The substrate voltage is a negative voltage when the first polarity is P-type, and a positive voltage when the first polarity is N-type. The reference voltage generation circuit according to claim 6 or 7.

9. The reference voltage generation circuit according to any one of claims 6 to 8, An avalanche photodiode formed on the semiconductor substrate, A semiconductor device.

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