Exposure head and image forming apparatus

Abstract

To form a driving circuit in a semiconductor process of a low withstand voltage while securing a forward voltage of light-emitting elements and reduce the size of chips, in such a configuration that the light-emitting elements and a driving circuit are formed in one chip.SOLUTION: An exposure head 106 includes a printed board 202, a plurality of light-emitting elements 602 for emitting light, and an analog part 801 for driving the light-emitting elements 602, and has a plurality of light-emitting element array chips 400-1 to 400-20 that are arranged on the printed board 202 and have a strip shape, and a rod lens array 203 for condensing the light from the light-emitting elements 602 on a photoreceptor drum 102. The analog part 801 operates between a first potential and a second potential, and the light-emitting elements 602 operate between a third potential and a fourth potential. A potential difference between the third potential and the fourth potential is equal to or larger than a potential difference between the first potential and the second potential.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to an exposure head for exposing a photosensitive drum and an image forming apparatus including the same.

Background Art

[0002] Conventionally, as an electrophotographic printer, a printer that exposes a photosensitive drum by an exposure head using an LED or an organic EL or the like to form a latent image is generally known. Such an exposure head is composed of a light emitting element array arranged in the longitudinal direction of the photosensitive drum and a rod lens array that forms an image of the light of the light emitting element array on the photosensitive drum. The LED or the organic EL as the light emitting element is a light emitting element array in which the irradiation direction of the light from the light emitting surface is parallel to the optical axis of the rod lens array.

[0003] Here, in the exposure head, the length of the light emitting element array is determined according to the width of the image forming area on the photosensitive drum, and the interval between the light emitting elements is determined according to the image resolution of the printer. For example, in a printer with 1200 dpi, since the interval between pixels is 21.16 μm (omitting three decimal places), the interval between the light emitting elements is also 21.16 μm. A printer using such an exposure head has fewer parts to be used compared with a laser scanning type printer that deflects and scans a laser beam with a polygon motor, and thus it is easy to reduce the size and cost of the apparatus.

[0004] In recent years, a technique for reducing the size of the apparatus by mounting a light emitting element and a drive circuit on the same chip is also known. For example, an exposure head is known in which a drive integrated circuit and electrodes are formed on a Si substrate, and an organic EL film is deposited thereon to form a single chip of a light emitting element and a drive circuit. Further, Patent Document 1 discloses an exposure head provided with a TFT circuit and an organic EL on a transparent glass substrate.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in an exposure head having a configuration in which a conventional light-emitting element and a drive circuit are formed on one chip, in order to secure the forward voltage of the light-emitting element and obtain a predetermined light emission amount, it is necessary to form an integrated circuit using a semiconductor process with a relatively high breakdown voltage. When forming a drive circuit using such a high-breakdown-voltage semiconductor process, there is a problem that the size of the transistor becomes large, and as a result, the chip size becomes enlarged.

[0007] An object of the present invention is to provide an exposure head capable of forming a drive circuit using a low-breakdown-voltage semiconductor process while securing the forward voltage of a light-emitting element and reducing the chip size in a configuration in which the light-emitting element and the drive circuit are formed on one chip.

Means for Solving the Problems

[0008] The exposure head according to the present invention is Photosensitive drum an exposure head for exposing a substrate, a light-emitting element that emits light, a plurality of and a lens array that condenses the light from the light-emitting element onto the photosensitive a drive circuit for driving the light-emitting elements, and a plurality of strip-shaped semiconductor chips arranged on the substrate, as described above. drum It is characterized by the above. having, the drive circuit operates between a first potential and a second potential, the light-emitting element operates between a third potential and a fourth potential, a potential difference between the third potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential, the second potential is a ground potential, the first potential is a positive potential with respect to the ground potential, and the fourth potential is a negative potential with respect to the ground potential,

Effects of the Invention

[0009] According to the present invention, in a configuration in which a light-emitting element and a drive circuit are formed on one chip, it is possible to form a drive circuit using a low-breakdown-voltage semiconductor process while securing the forward voltage of the light-emitting element, and it is possible to reduce the chip size.

Brief Description of the Drawings

[0010]

Figure 1

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Figure 21

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0012] (Embodiment 1) <Configuration of the Image Forming Apparatus> The configuration of an image forming apparatus 1 according to Embodiment 1 of the present invention will be described in detail with reference to FIG. 1.

[0013] The image forming apparatus 1 includes a scanner unit 100, an image forming unit 103, a fixing unit 104, a paper feeding / conveying unit 105, and a registration roller 110.

[0014] The scanner unit 100 irradiates illumination on a document placed on a document table, optically reads the image of the document, converts the read image into an electrical signal, and creates image data. The scanner unit 100 outputs the created image data to a printer control unit (not shown).

[0015] The image forming unit 103 operates under the control of the printer control unit, forms an image on the sheet conveyed from the registration roller 110, and conveys the sheet on which the image has been formed to the fixing unit 104. The image forming unit 103 has four image forming units that perform a series of electrophotographic processes of charging, exposure, development, and transfer. The image forming unit 103 forms a full-color image on the sheet by four image forming units arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K). Each of the four image forming units sequentially executes the image forming operations of magenta, yellow, and black after a predetermined time has elapsed since the start of cyan image formation.

[0016] Specifically, the image forming unit 103 includes a photosensitive drum 102, an exposure head 106, a charger 107, a developer 108, a transfer belt 111, and an optical sensor 113.

[0017] The photosensitive drum 102 as an image carrier is attached to the image forming apparatus 1 by a mounting member (not shown) and is rotationally driven.

[0018] The exposure head 106 is attached to the image forming apparatus 1 by a mounting member (not shown). The exposure head 106 is composed of four exposure heads 106a, 106b, 106c, and 106d corresponding to the four image forming units. The exposure head 106 forms a latent image (electrostatic latent image) on the photosensitive drum 102 by condensing and exposing the light emitted according to the image data onto the photosensitive drum 102. The details of the configuration of the exposure head 106 will be described later.

[0019] The charger 107 charges the photosensitive drum 102.

[0020] The developer 108 forms a toner image (developer image) on the photosensitive drum 102 by supplying and developing toner to the latent image formed on the photosensitive drum 102.

[0021] The transfer belt 111 conveys the sheet conveyed from the registration roller 110 to the fixing unit 104. The toner image developed by the developing unit 108 is transferred onto the sheet conveyed by the transfer belt 111.

[0022] The optical sensor 113 is provided at a position facing the transfer belt 111, and detects the position of the test chart printed on the transfer belt 111 in order to derive the color misregistration amount between the image forming units. The optical sensor 113 outputs the detection result of the position of the test chart to an image controller unit (not shown). The image controller unit performs control to derive the color misregistration amount between the image forming units of the image forming unit 103 and correct the image positions of each color based on the detection result of the position of the test chart input from the optical sensor 113. A full-color toner image without color misregistration is transferred onto the sheet by this control.

[0023] The fixing unit 104 is composed of a combination of rollers and incorporates a heat source such as a halogen heater (not shown). The fixing unit 104 melts and fixes the toner on the sheet onto which the toner image has been transferred by the image forming unit 103 to the sheet by heat and pressure, and discharges the sheet onto which the toner has been fixed to the outside of the image forming apparatus 1 by the paper discharge roller 112.

[0024] The paper feeding / conveying unit 105 includes an in-body paper feeding unit 109a, an in-body paper feeding unit 109b, an external paper feeding unit 109c, and a manual paper feeding unit 109d, and feeds a sheet from a pre-instructed paper feeding unit and conveys it to the registration roller 110.

[0025] The registration roller 110 conveys the sheet conveyed from the paper feeding / conveying unit 105 to the transfer belt 111 at the timing of transferring the toner image formed in the image forming unit 103 onto the sheet.

[0026] The printer control unit controls the operations of the scanner unit 100, the image forming unit 103, the fixing unit 104, and the paper feeding / conveying unit 105. The printer control unit communicates with the MFP control unit that controls the entire MFP (the entire image forming apparatus 1), and in response to the instructions of the MFP control unit, controls the operations while managing the states of the scanner unit 100, the image forming unit 103, the fixing unit 104, and the paper feeding / conveying unit 105.

[0027] <Configuration of the exposure head> The configuration of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIGS. 2 and 3.

[0028] FIG. 2(a) shows the arrangement state of the exposure head 106 with respect to the photosensitive drum 102, and FIG. 2(b) shows the state where the light emitted from the light emitting element group 201 is condensed on the photosensitive drum 102 by the rod lens array 203.

[0029] FIG. 3(a) shows the surface of the printed circuit board 202 opposite to the surface on which the light emitting element group 201 is mounted (hereinafter referred to as the "non-light emitting element mounting surface"), and FIG. 3(b) shows the surface on which the light emitting element group 201 is mounted (hereinafter referred to as the "light emitting element mounting surface"). Further, FIG. 3(c) shows the state of the boundary portion between the chips of the light emitting element array chips 400-m (m is an integer of 1 or more and 19 or less) to 400-m+1.

[0030] The exposure head 106 includes a light emitting element group 201, a printed circuit board 202, a rod lens array 203, and a housing 204.

[0031] The light emitting element group 201 is mounted on the light emitting element mounting surface of the printed circuit board 202, and has a configuration in which 20 strip-shaped light emitting element array chips 400-1 to 400-20 are arranged in two rows in a staggered manner. The light emitting element array chips 400-1 to 400-20 in each row are arranged along the longitudinal direction of the printed circuit board 202.

[0032] In the light-emitting element array chips 400-1 to 400-20 as semiconductor chips, the light-emitting elements 602 are arranged at a predetermined pitch along the longitudinal direction (main scanning direction) and the lateral direction (sub-scanning direction) of the light-emitting element array chips 400-1 to 400-20. In each of the light-emitting element array chips 400-1 to 400-20, 748 light-emitting elements 602 are arranged at a predetermined image resolution pitch in the X direction, which is the longitudinal direction. Here, the image resolution pitch is exemplified by 1200 dpi (approximately 21.16 μm). Also, the distance from end to end of the 748 light-emitting elements 602 in each of the light-emitting element array chips 400-1 to 400-20 is exemplified by approximately 15.8 mm here.

[0033] The light-emitting element group 201 is formed by arranging 20 light-emitting element array chips 400-1 to 400-20 in the longitudinal direction, so that the number of light-emitting elements that can be exposed is 14,960 elements, enabling image formation corresponding to an image width of approximately 316 mm.

[0034] In this exemplary case, the image resolution pitch between the light-emitting element 602-n and the light-emitting element 602-1 located at the boundary of the light-emitting element array chips 400-1 to 400-20 shown in FIG. 3(c) is also 1200 dpi (approximately 21.16 μm). Also, the distance S in the lateral direction between the light-emitting element 602-n and the light-emitting element 602-1 is approximately 127 μm (6 pixels at 1200 dpi, 4 pixels at 800 dpi). Also, the distance L in the longitudinal direction between the light-emitting element 602-n and the light-emitting element 602-1 is approximately 21.16 μm (1 pixel at 1200 dpi). Note that the distances S and L between the light-emitting element 602-n and the light-emitting element 602-1 are not limited to the above-described values.

[0035] As shown in FIG. 3(a), on the printed circuit board 202 as a substrate, a connector 305 and a driver IC (not shown) for driving the light-emitting element group 201 are provided on the non-light-emitting element mounting surface. As shown in FIG. 3(b), the light-emitting element group 201 is mounted on the light-emitting element mounting surface as the surface of the printed circuit board 202.

[0036] The connector 305 is connected to a driver IC (not shown) and a power supply provided on the non-light-emitting element mounting surface of the printed circuit board 202 via signal lines (not shown), and is also connected to the light-emitting element group 201.

[0037] The rod lens array 203 is arranged such that the distance between the rod lens array 203 and the light-emitting element group 201 is a predetermined distance, and the distance between the rod lens array 203 and the photosensitive drum 102 is a predetermined distance, and the light emitted from the light-emitting element group 201 is imaged on the photosensitive drum 102.

[0038] The housing 204 has the rod lens array 203 and the printed circuit board 202 attached thereto.

[0039] The exposure head 106 having the above configuration is assembled as a single unit in a factory, and focusing adjustment and light amount adjustment for adjusting the spot at the focusing position to a predetermined size are performed. Here, in the focusing adjustment, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light-emitting element group 201 becomes a desired distance. In the light amount adjustment, each light-emitting element 602 of the light-emitting element group 201 is caused to emit light sequentially one by one, and the drive current of each light-emitting element 602 is adjusted so that the light condensed on the photosensitive drum 102 via the rod lens array 203 becomes a predetermined light amount.

[0040] <Configuration of the light-emitting element array chip> The configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIG. 4.

[0041] The light-emitting element array chip 400 is a chip configured by providing light-emitting elements 602 on an Si substrate, and includes a light-emitting substrate 402, a light-emitting portion 404, a circuit portion 406, and wire bonding pads (WB pads) 408.

[0042] The light-emitting substrate 402 is a Si substrate, on which a light-emitting portion 404 and wire bonding pads 408 are provided. A circuit portion 406 for controlling the light-emitting portion 404 is built in the light-emitting substrate 402. Here, since the Si substrate has a well-developed process technology for forming integrated circuits and has already been used as a substrate for various integrated circuits, it has the advantages that a high-speed and high-function circuit can be formed at high density, and large-diameter wafers are available in the market, so it can be obtained at low cost.

[0043] The light-emitting portion 404 includes a light-emitting element 602. Details of the configuration of the light-emitting portion 404 will be described later.

[0044] The circuit portion 406 has a circuit configuration including an analog drive circuit, a digital control circuit, or both an analog drive circuit and a digital drive circuit, and controls the light-emitting portion 404.

[0045] The wire bonding pads 408 perform power supply to the circuit portion 406 or input / output of signals between the light-emitting element array chip 400 and the outside.

[0046] <Configuration of the light-emitting portion> The configuration of the light-emitting portion 404 of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIG. 5.

[0047] The light-emitting portion 404 is a portion where the light-emitting substrate 402 and the upper electrode 508 face each other, and the light-emitting layer 506 of the opposing portion. A plurality of lower electrodes 504, a light-emitting layer 506, and an upper electrode 508 are laminated in this order on the light-emitting substrate 402.

[0048] The lower electrode 504 is an independent electrode and is formed on the light-emitting substrate 402. The lower electrode 504 has a width W in the X direction, and a plurality of lower electrodes 504 are formed with a predetermined interval d provided between adjacent lower electrodes 504 in the X direction. The lower electrode 504 is formed using Si integrated circuit processing technology with a processing rule of about 0.2 μm in high precision along with the formation of the circuit portion 406, and is connected to a driving portion (not shown) of the circuit portion 406. Thereby, the lower electrodes 504 can be arranged with high density and high precision. Also, since the light-emitting locations of the light-emitting elements 602 are substantially the same as the lower electrodes 504, it becomes possible to arrange the light-emitting elements 602 with high density.

[0049] The lower electrode 504 is preferably formed of a metal having a high reflectance with respect to the light-emitting wavelength of the light-emitting layer 506, and is formed of silver (Ag), aluminum (Al), or an alloy of silver and aluminum, etc.

[0050] The light-emitting layer 506 is formed on the lower electrode 504 and is, for example, an organic EL film or an inorganic EL film, etc. When the light-emitting layer 506 is an organic EL film, it is a laminated structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer as required.

[0051] When the light-emitting layer 506 is formed of a material vulnerable to moisture such as an organic EL layer or an inorganic EL layer, etc., it is preferably sealed to prevent the intrusion of moisture into the light-emitting portion 404. The light-emitting layer 506 prevents the intrusion of moisture into the light-emitting portion 404 by, for example, a single film of a thin film such as silicon oxide, silicon nitride, or aluminum oxide, or a sealing film formed by laminating thin films such as silicon oxide, silicon nitride, and aluminum oxide. As a method for forming the sealing film, a method excellent in the covering performance of structures such as steps is preferable, and for example, an atomic layer deposition method (ALD method) etc. can be used.

[0052] Note that the light-emitting layer 506 may be formed continuously or may be divided into sizes substantially equivalent to those of the lower electrode 504. Also, the materials, configurations, and formation methods of the above-described encapsulation film are merely examples and are not limited to the examples described above. Appropriate ones may be selected as appropriate.

[0053] The upper electrode 508 is a common electrode and is formed on the light-emitting layer 506. The upper electrode 508 is preferably transparent to the emission wavelength of the light-emitting layer 506, and a transparent electrode such as indium tin oxide (ITO) can be used.

[0054] The light-emitting unit 404 having the above configuration energizes the light-emitting layer 506 through the selected lower electrode 504 and the upper electrode 508 among the plurality of lower electrodes 504, thereby causing the light-emitting layer 506 at the location corresponding to the selected lower electrode 504 to emit light. Thereby, the light-emitting unit 404 emits the emitted light through the upper electrode 508 on the side opposite to the light-emitting substrate 402 of the light-emitting layer 506.

[0055] By using a transparent electrode such as indium tin oxide for the upper electrode 508, the aperture ratio can be made substantially 100%, and the light emission in the light-emitting layer 506 can be used as the emitted light as it is. Also, by forming the lower electrode 504 using high-precision Si integrated circuit processing technology, the lower electrodes 504 can be arranged at high density. Therefore, substantially the entire area of the light-emitting unit 404 can be made to emit light, and the utilization efficiency of the light-emitting unit 404 can be increased. Here, the area of the light-emitting unit 404 is the total area of the plurality of lower electrodes 504 and the total area of the plurality of intervals d.

[0056] <Arrangement of Light-Emitting Elements of Light-Emitting Unit> The arrangement of the light-emitting elements 602 of the light-emitting unit 404 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIGS. 6 to 8.

[0057] In FIG. 6, FIG. 6(a) is an example in which a plurality of light-emitting elements 602 are arranged in a row, and FIG. 6(b) is a schematic cross-sectional view of the light-emitting element row 604. FIG. 7 is an example in which a plurality of rows of the light-emitting element rows 604 are arranged in the Y direction in the drawing to form the light-emitting unit 404.

[0058] In FIGS. 6(a) and 6(b), W1 is the width of the light-emitting element 602 in the X direction, and d1 is the interval between adjacent light-emitting elements 602 in the X direction. Further, in FIG. 7, W2 is the width of the light-emitting element 602 in the Y direction, and d2 is the interval between adjacent light-emitting elements 602 in the Y direction.

[0059] Further, in FIG. 6(b), for example, the light-emitting element 602-3 is the portion surrounded by the dashed-dotted line.

[0060] The light-emitting element row 604 is configured by arranging a plurality of light-emitting elements 602 at a predetermined interval (pitch) along the X direction. The predetermined interval is, for example, 21.16 μm when the image resolution in the Y direction is 1200 dpi. Further, W1 is exemplified as 19.8 μm here, and d1 is exemplified as 0.68 μm here.

[0061] Here, when the light-emitting layer 506 is sufficiently thin, the light-emitting portion of the light-emitting element 602 is substantially the same as the lower electrode 504, and W1 may be regarded as W in FIG. 5 and d1 may be regarded as d in FIG. 5.

[0062] The light-emitting element row 604 is not limited to the case where the light-emitting elements 602 are arranged in a single row in the X direction as shown in FIG. 6(a), and the light-emitting elements 602 may also be arranged in the Y direction to form a plurality of rows as shown in FIG. 7. FIG. 7 exemplifies the case where 748 light-emitting elements 602 (602-1 to 4_1 to 748) are arranged in the X direction and 4 rows (604-1 to 4) are arranged in the Y direction different from the X direction on the matrix. W2 is exemplified as 19.8 μm, the same as W1 here. Further, d2 is exemplified as 0.68 μm, the same as d1 here, when arranged at a pitch of 21.16 μm (1200 dpi) in the Y direction.

[0063] The rod lens array 203 condenses the light emitted from the light emitting element group 201 onto the photosensitive drum 102. The number of light emitting element rows 604 in the Y direction is exemplified by 4 rows here. The pitch of the light emitting elements 602 in the X direction is exemplified by 21.16 μm shown in FIG. 8 here. The pitch of the light emitting elements 602 in the Y direction is exemplified by 21.16 μm shown in FIG. 8 here. The diameter of the rod lens array 203 is exemplified by 290 μm shown in FIG. 8 here. In this exemplary case, one rod lens array 203 is configured to condense the emitted light of a plurality of light emitting elements 602.

[0064] <Circuit configuration of the exposure head> The circuit configuration of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIG. 9.

[0065] In the description using FIG. 9, for the sake of simplicity, the circuit configuration of a single monochromatic exposure head 106 will be described. However, in reality, each of the four exposure heads 106 of four colors has the same circuit configuration. Further, these four exposure heads 106 perform parallel processing simultaneously.

[0066] The exposure head 106 has an image controller unit 700 that transmits signals or data for controlling the printed circuit board 202 to the printed circuit board 202 and performs processing on image data and processing on exposure timing. The signals and data transmitted from the image controller unit 700 to the printed circuit board 202 are a clock signal, image data, a signal indicating the start of capturing image data (hereinafter referred to as a "line synchronization signal"), and a communication signal.

[0067] Specifically, the image controller unit 700 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a -5V generation circuit 711, and a switch (SW) 714.

[0068] Here, the image controller unit 700 and the printed circuit board 202 are connected by a clock signal line 705, a line synchronization signal line 706, an image data signal line 707, a communication signal line 708, a +5V power supply line 712, and a -5V power supply line 713.

[0069] The clock signal line 705 connects the chip data conversion unit 702 to each of the light emitting element array chips 400-1 to 400-20.

[0070] The line synchronization signal line 706 connects the chip data conversion unit 702 to only the light emitting element array chip 400-1.

[0071] The image data signal line 707 connects the chip data conversion unit 702 to each of the light emitting element array chips 400-1 to 400-20. Here, the number of the image data signal lines 707 is exemplified by four, which is the same as the number of columns of the light emitting element columns 604.

[0072] The communication signal line 708 connects the CPU 703 to each of the light emitting element array chips 400-1 to 400-20.

[0073] The +5V power supply line 712 connects the +5V generation circuit 710 to each of the light emitting element array chips 400-1 to 400-20.

[0074] The -5V power supply line 713 connects the switch (SW) 714 to each of the light emitting element array chips 400-1 to 400-20.

[0075] The image data generation unit 701 performs dithering processing on the image data input from the scanner unit 100 or received and input from outside the image forming apparatus 1 at the image resolution instructed by the CPU 703 to generate image data for print output. The image data generation unit 701 generates image data of 1 line × 4 columns (the number of light emitting element columns), for example, by performing dithering processing at an image resolution of 1200 dpi in each of the main scanning direction and the sub-scanning direction. The image data generation unit 701 outputs the generated image data to the chip data conversion unit 702.

[0076] The chip data conversion unit 702 divides the image data input from the image data generation unit 701 for each of the light emitting element array chips 400-1 to 400-20 in synchronization with the line synchronization signal input from the synchronization signal generation unit 704. The chip data conversion unit 702 outputs the divided image data to each of the light emitting element array chips 400-1 to 400-20 via the image data signal line 707. At the same time, the chip data conversion unit 702 outputs the line synchronization signal to the light emitting element array chip 400-1 via the line synchronization signal line 706, and outputs the clock signal to the light emitting element array chips 400-1 to 400-20 via the clock signal line 705.

[0077] The CPU 703 sets the period in which the surface of the photosensitive drum 102 moves in the rotation direction by a predetermined pixel size at a predetermined rotation speed of the photosensitive drum 102 as one line period, and instructs the synchronization signal generation unit 704 of the time interval of the signal period.

[0078] The CPU 703 sets the cycle in which the surface of the photosensitive drum 102 moves in the rotational direction by a pixel size of 1200 dpi (approx. 21.16 μm) at a predetermined rotational speed of the photosensitive drum 102, for example, as one line cycle. Then, when the CPU 703 performs exposure at a speed of 200 mm / sec in the conveyance direction, for example, it sets one line cycle to 105.8 μsec (omitting two decimal places) and instructs the synchronization signal generation unit 704 of the time interval of the signal cycle. At this time, the CPU 703 calculates the speed in the conveyance direction using the set value (fixed value) of the printing speed set in a speed control unit (not shown) that controls the speed of the photosensitive drum 102.

[0079] The CPU 703 instructs the image data generation unit 701 regarding the image resolution. The CPU 703 outputs a power control signal to the switch 714 to turn on the switch 714. The CPU 703 transmits and receives communication signals via the communication signal line 708 to and from each of the light emitting element array chips 400-1 to 400-20. The CPU 703 sets set values in the communication signals based on head information and the like (described later) stored in the head information storage unit 709, and outputs the communication signals with the set values to the light emitting element array chips 400-1 to 400-20 via the communication signal line 708.

[0080] The synchronization signal generation unit 704 generates a line synchronization signal based on the time interval of the signal cycle instructed by the CPU 703, and outputs the generated line synchronization signal to the chip data conversion unit 702.

[0081] The +5V generation circuit 710 converts the +12V power supply voltage applied from the +12V power supply to a +5V voltage and supplies it to each of the light emitting element array chips 400-1 to 400-20 via the +5V power supply line 712. As the +5V generation circuit 710, a general switching regulator circuit can be applied.

[0082] The -5V generation circuit 711 converts the +12V power supply voltage applied from the +12V power supply to a -5V voltage and supplies it to the switch 714. As the -5V generation circuit 711, a general switching regulator circuit can be applied.

[0083] The switch 714 as a switching element switches whether to supply a voltage of -5V to the light-emitting element array chip 400 by turning ON or OFF according to the presence or absence of an input of a power control signal from the CPU 703. When a power control signal is input from the CPU 703, the switch 714 turns ON and supplies a voltage of -5V to each of the light-emitting element array chips 400-1 to 400-20 via the -5V power supply line 713. The -5V power supply line 713 becomes a floating state when the switch 714 turns OFF and does not supply a voltage of -5V to the light-emitting element array chips 400-1 to 400-20.

[0084] The printed circuit board 202 includes the light-emitting element array chips 400-1 to 400-20 and the head information storage unit 709.

[0085] The light-emitting element array chip 400-1 and the light-emitting element array chip 400-2 are connected by the signal line 708-1. The light-emitting element array chip 400-2 and the light-emitting element array chip 400-3 are connected by the signal line 708-2. Similarly, the light-emitting element array chips 400-3, ··· are connected in a daisy chain by the signal lines 708-3, ···.

[0086] Each of the light-emitting element array chips 400-1 to 400-20 generates a line synchronization signal for the next chip based on the input line synchronization signal and outputs it to the next light-emitting element array chips 400-1 to 400-20 via the signal lines 708-1, ···. Each of the light-emitting element array chips 400-1 to 400-20 causes the light-emitting element 602 to emit light based on the input clock signal, line synchronization signal, set values set for the image data and the communication signal.

[0087] The head information storage unit 709 is connected to the CPU 703 via the communication signal line 708. The head information storage unit 709 is a storage device that stores head information such as the light emission amount and mounting position information of the light-emitting element array chips 400-1 to 400-20.

[0088] <Circuit Configuration of Light-Emitting Element Array Chip> The circuit configurations of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIGS. 10 to 13.

[0089] Since the circuit configurations of the light-emitting element array chips 400-1 to 400-20 are the same, the circuit configuration of the light-emitting element array chip 400-1 will be described, and the description of the circuit configurations of the light-emitting element array chips 400-2 to 400-20 will be omitted. Also, since the clock signal is input to all blocks of the digital unit 800, the clock signal line 705 is connected to all blocks of the digital unit 800, but its description is omitted in FIG. 10.

[0090] The light-emitting element array chip 400-1 includes a light-emitting unit 404 and a circuit unit 406. The circuit unit 406 includes a digital unit 800 and an analog unit 801.

[0091] The digital unit 800 receives a clock signal, an image data signal, and a line synchronization signal from the chip data conversion unit 702, and a communication signal from the CPU 703. The digital unit 800 generates a drive signal (pulse signal) for causing the light-emitting element 602 to emit light based on the set value set in the communication signal, the image data signal, and the line synchronization signal in synchronization with the clock signal, and outputs the generated drive signal to the analog unit 801. The digital unit 800 generates a line synchronization signal for the next chip based on the line synchronization signal, and outputs the generated line synchronization signal for the next chip to the light-emitting element array chip 400-2, which is the next chip, via the signal line 708-1.

[0092] Specifically, the digital unit 800 includes a communication IF unit 802, a register unit 803, a line synchronization signal generation unit 804, a capture signal generation unit 805, and data holding units 806-001 to 748.

[0093] The communication IF unit 802 is connected to the CPU 703 via the communication signal line 708.

[0094] The register unit 803 has set values in the communication signals input from the CPU 703 via the communication IF unit 802 written into it. The register unit 803 has the set values written by the CPU 703 read out, and outputs the read set values to the analog unit 801 as drive current information and outputs them to the capture signal generation unit 805 as delay time information. Here, the drive current information is information on the current set value of the drive current flowing through the light emitting unit 404, and is a digital value. Also, the delay time information is information on the delay time for delaying the output of the data latch signal, and is a digital value.

[0095] The line synchronization signal generation unit 804 delays the line synchronization signal input from the line synchronization signal line 706 by a predetermined time, generates a line synchronization signal for the next chip, and outputs it to the light emitting element array chip 400-2 via the signal line 708-1.

[0096] The capture signal generation unit 805 outputs the data latch signal we001 to the data holding unit 806-001 at a timing delayed by the delay time of the delay time information input from the register unit 803 based on the line synchronization signal input from the line synchronization signal line 706.

[0097] Each of the data holding units 806-001 to 748 has the clock signal and the data latch signal wen (n = 1 to 748) input thereto, and the image data 1 to 4 for four columns are input at the timing when the data latch signal wen is input.

[0098] As shown in FIG. 11, the data holding units 806-001 to 748 include four flip-flop circuits 807 and four gate circuits 808 that latch the input image data 1 to 4, generate drive signals 1 to 4, and output them to the analog unit 801. The data holding units 806-001 to 748 include one flip-flop circuit 809 that delays the input data latch signal wen by one clock and outputs the delayed data latch signal we(n + 1) to the next data holding units 806-001 to 748.

[0099] Based on the drive current information input from the register unit 803 and the drive signals input from the data holding units 806-001 to 748, the analog unit 801 controls the driving of the light emitting unit 404.

[0100] Specifically, as shown in FIG. 12, the analog unit 801 includes a drive circuit 900 including a current setting DAC 901, a current control MOSFET 902, and a switching MOSFET 903.

[0101] The drive circuits 900 are connected one-to-one to each light emitting element 602 and provided in the same number as the number of light emitting elements 602. In the present embodiment, 748 × 4 columns = 2992 drive circuits 900 are provided for one light emitting element array chip 400-1 to 400-20. Since all the drive circuits 900 have the same configuration, only the configuration of one drive circuit 900 will be described for simplicity of explanation.

[0102] The current setting DAC 901 converts the digital value of the drive current to be passed through the light emitting unit 404 indicated by the drive current information input from the register unit 803 of the digital unit 800 into an analog voltage and outputs it to the gate terminal G of the current control MOSFET 902.

[0103] The MOSFET 902 for current control is a Pch MOSFET. The source terminal S is connected to the power supply voltage VDD, the gate terminal G is connected to the output terminal of the DAC 901, and the drain terminal D is connected to the source terminal S of the switching MOSFET 903. The MOSFET 902 for current control is configured such that the higher the analog voltage input from the current setting DAC 901, the greater the drive current of the light emitting element 602 flowing from the source terminal S to the drain terminal D.

[0104] The switching MOSFET 903 is a Pch MOSFET. For the switching MOSFET 903, the source terminal S is connected to the drain terminal D of the MOSFET 902 for current control, the gate terminal G is connected to the output terminal of the data holding unit 806, and the drain terminal D is connected to the anode terminal A of the light emitting element 602 of the light emitting unit 404. Binary drive signals 1 to 4 of Hi level or Low level are input to the gate terminal G of the switching MOSFET 903 from the data holding unit 806-001 to 748.

[0105] The switching MOSFET 903 turns ON when a Hi level drive signal is input to the gate terminal G, and turns OFF when a Low level drive signal is input to the gate terminal G. When a Hi level drive signal is input to the gate terminal G of the switching MOSFET 903 and it turns ON, a current that is the drive current of the light emitting element 602 controlled by the MOSFET 902 for current control flows from the source terminal S to the drain terminal D.

[0106] Next, the power supply configuration for each of the digital unit 800, the analog unit 801, and the light emitting element 602 will be described in detail with reference to FIG. 13.

[0107] In FIG. 13, for the sake of simplicity of explanation, the description of the blocks inside the digital unit 800 is omitted, and only one drive circuit 900 and one light emitting element 602 inside the analog unit 801 are described respectively.

[0108] The digital section 800 is supplied with a voltage of +5V from the +5V power supply line 712 as the power supply voltage. The digital section 800 is connected to GND (0V) as the reference potential. From this, each block of the digital section 800 operates with voltages of +5V and 0V. Also, a voltage in the range of 0V to 5V is applied to the gate terminal of the switching MOSFET 903.

[0109] The current setting DAC 901 in the analog section 801 is supplied with a voltage of +5V from the +5V power supply line 712 as the power supply voltage. The current setting DAC 901 is connected to GND (0V) as the reference potential. As a result, a voltage in the range of 0V to 5V is applied to the gate terminal of the current control MOSFET 902. Also, the source terminal of the current control MOSFET 902 is supplied with a voltage of +5V from the +5V power supply line 712 as the power supply voltage.

[0110] The light emitting element 602 is, for example, an organic EL. The anode terminal A is connected to the drain terminal of the switching MOSFET 903, and the cathode terminal K is connected to the -5V power supply line 713. The light emitting element 602 is supplied with a voltage of -5V from the -5V power supply line 713 to the cathode terminal K. Generally, a forward voltage of about 6V is generated in the light emitting element 602 by a driving current of several μA. In this case, the potential of the anode terminal A of the light emitting element 602 becomes about +1V obtained by adding +6V to -5V.

[0111] Since the voltages between the drain and source of the current control MOSFET 902 and the switching MOSFET 903 are each about 1.5V, when adding the forward voltage of 6V of the light emitting element 602 and the drain-source voltage of 1.5V × 2 = 3V, it becomes about 9V. Therefore, the light emitting element array chips 400-1 to 400-20 require a voltage of about 9V or more to cause the light emitting element 602 to emit light. Since the light emitting element array chips 400-1 to 400-20 can drive the light emitting element 602 in a 10V range of +5V and -5V, the light emitting element 602 can be caused to emit light.

[0112] Conventionally, in a configuration where an EL film is deposited or the like on a circuit section and laminated, in order to ensure a forward voltage of 6V for the light-emitting element, it was necessary to form a light-emitting element array chip using a semiconductor process of 9V or higher in consideration of the voltage between the drain and source of the MOSFET. On the other hand, in the present embodiment, +5V and -5V are supplied as power supply voltages to drive the light-emitting element 602 in a 10V range, and the digital section 800 and the analog section 801 are configured with a semiconductor process of +5V from GND. Thereby, in the present embodiment, the sizes of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip sizes of the light-emitting element array chips 400-1 to 400-20 can be reduced.

[0113] <Operation of the exposure head> The operation of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIGS. 14 and 15.

[0114] The exposure head 106 starts operating at the timing when the main power supply of the image forming apparatus 1 is turned on.

[0115] First, the CPU 703 determines whether a print JOB has been requested by the user (S1).

[0116] When the CPU 703 has not been requested a print JOB by the user (S1: No), the operation of step S1 is repeated.

[0117] On the other hand, when the CPU 703 has been requested a print JOB by the user (S1: Yes), the CPU 703 writes a set value to the register section 803 of the light-emitting element array chips 400-1 to 400-20 to perform register setting (S2).

[0118] Next, the CPU 703 outputs a power control signal to the switch 714 to supply a voltage of -5V to the cathode electrode of the light-emitting element 602 of the light-emitting element array chips 400-1 to 400-20 (-5V ON) (S3).

[0119] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 400-1 to 400-20 at a predetermined timing to expose the photosensitive drum 102 (S4).

[0120] Next, the CPU 703 determines whether the printing JOB has ended (S5).

[0121] When the printing JOB has not ended (S5: No), the CPU 703 repeats the operation of step S5.

[0122] On the other hand, when the printing JOB has ended (S5: Yes), the CPU 703 stops transmitting the power control signal to the switch 714, floats the potential of the cathode electrode of the light-emitting element 602, and ends the operation.

[0123] Subsequently, the operation of the exposure head 106 will be described in more detail with reference to FIG. 15.

[0124] From FIG. 15, at time t = t0, the power of the image forming apparatus 1 is turned on, and a power supply voltage of +12V is supplied to the +5V generation circuit 710 and the -5V generation circuit 711. As a result, the voltage of the +5V power supply line 712 becomes +5V after the elapse of time t = t1. At this time, since the switch 714 is OFF, the -5V power supply line 713 is in a floating state (0V in FIG. 15).

[0125] At time t = t1, by receiving a JOB request from the user, the CPU 703 outputs a power control signal to the switch 714, whereby the potential of the -5V power supply line 713 becomes -5V, and the light-emitting element 602 becomes drivable.

[0126] At time t = t2, when the JOB ends, the CPU 703 stops outputting the power control signal to the switch 714, turns off the switch 714, and makes the -5V power supply line 713 in a floating state (0V in FIG. 15).

[0127] <Operation of the light-emitting element array chip> The operation of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to Embodiment 1 of the present invention will be described in detail with reference to FIG. 16.

[0128] Four columns of image data (D1[1] to D1[4]) are simultaneously input to the data holding unit 806-001. The data holding unit 806-001 latches the image data (D1[1] to D1[4]) at the timing when the data latch signal we001 is input from the capture signal generation unit 805, and generates drive signals (P001[1] to P001[4]).

[0129] In addition, the data holding unit 806-001 outputs a data latch signal we002 obtained by delaying the input data latch signal we001 by one clock to the next data holding unit 806-002.

[0130] Four columns of image data (D2[1] to D2[4]) are simultaneously input to the data holding unit 806-002 in the same manner as the data holding unit 806-001. The data holding unit 806-002 latches the image data (D2[1] to D2[4]) at the timing when the data latch signal we002 is input from the data holding unit 806-001, and generates drive signals (P002[1] to P002[4]).

[0131] In addition, the data holding unit 806-002 outputs a data latch signal we003 obtained by delaying the input data latch signal we002 by one clock to the next data holding unit 806-003.

[0132] In this way, the data holding units 806-001 to 748 sequentially latch the image data while sequentially outputting the data latch signals.

[0133] The data holding units 806-001 to 748 latch the image data and output the latched signal as a drive signal to the analog unit 801. Since the data holding units 806-001 to 748 latch the image data for four columns with one data latch signal, they output the drive signals for four columns (for four pixels) simultaneously.

[0134] In this way, in the configuration where the light-emitting element 602 and the analog unit 801 are formed on the same chip, a voltage (-5V) lower than the voltages (+5V and the reference potential (GND)) supplied to the analog unit 801 is supplied to the cathode electrode of the light-emitting element 602. As a result, since the analog unit 801 can be formed using a semiconductor process with a relatively low breakdown voltage, the size of the analog unit 801 can be reduced, and the chip size can be reduced.

[0135] Also, during non-exposure, the potential of the cathode electrode connected to the -5V power supply line 713 of the light-emitting element 602 is set to a floating state. Thereby, even in the OFF state during non-exposure, the leakage current from the current control MOSFET 902 and the switching MOSFET 903 to the light-emitting element 602 can be suppressed, and the power consumption can be suppressed.

[0136] In the present embodiment, the analog unit 801 operates between the first potential +5V and the second potential 0V, and the light-emitting element 602 operates between the third potential +1V and the fourth potential -5V. Also, the potential difference between the third potential +1V and the fourth potential -5V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. Thereby, in the configuration where the light-emitting element 602 and the analog unit 801 are formed on one chip, the analog unit 801 can be formed using a low breakdown voltage semiconductor process while ensuring the forward voltage of the light-emitting element 602, and the chip size can be reduced.

[0137] In addition, in the present embodiment, the third potential of +1V is lower than the first potential of +5V, and the fourth potential of -5V is lower than the second potential of 0V. The potential difference between the second potential of 0V and the fourth potential of -5V is equal to or greater than the potential difference between the first potential of +5V and the second potential of 0V. The second potential of 0V is the ground potential, the first potential of +5V is a positive potential with respect to the ground potential, and the fourth potential of -5V is a negative potential with respect to the ground potential.

[0138] In addition, in the present embodiment, when the switch 714 is switched so that the potential of the cathode terminal K of the light-emitting element 602 does not supply current to the light-emitting element 602, the potential becomes a fifth potential of 0V that is at least higher than the fourth potential of -5V. The fifth potential of 0V is equal to the second potential of 0V.

[0139] Furthermore, in the present embodiment, the fourth potential of -5V is lower than the first potential of +5V. The second potential of 0V is the ground potential. The third potential of +1V is higher than the second potential of 0V.

[0140] Note that in the present embodiment, not limited to the voltages of +5V and -5V, any voltage other than +5V and -5V can be supplied as long as it can drive the light-emitting element 602. For example, not limited to the case of securing a voltage range of 10V between +5V and -5V, a voltage range of 10V between +4V and -6V may be secured.

[0141] In addition, in the present embodiment, 20 light-emitting element array chips 400-1 to 400-20 are provided on the printed circuit board 202. However, the present invention is not limited to this, and any number of light-emitting element array chips can be provided on the printed circuit board 202 as needed.

[0142] (Embodiment 2) The configuration of the image forming apparatus according to Embodiment 2 of the present invention is the same as that of the image forming apparatus 1 shown in FIG. 1, and thus the description thereof is omitted. In addition, the configuration of the exposure head according to the present embodiment is the same as that of FIGS. 3 to 8 except for the circuit configuration of the exposure head, and thus the description of the configuration other than the circuit configuration of the exposure head is omitted.

[0143] In the above-described Embodiment 1, the cathode electrodes of the plurality of light-emitting elements 602 are common, but in this embodiment, the anode electrodes of the plurality of light-emitting elements 602 are common.

[0144] <Circuit Configuration of Exposure Head> The circuit configuration of the exposure head according to Embodiment 2 of the present invention will be described in detail with reference to FIG. 17.

[0145] In FIG. 17, the same components as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted.

[0146] The exposure head according to this embodiment has an image controller unit 1301 that transmits signals or data for controlling the printed circuit board 1302 to the printed circuit board 1302 and performs processing on image data and processing on exposure timing. The signals and data transmitted from the image controller unit 1301 to the printed circuit board 1302 are a clock signal, image data, a line synchronization signal, and a communication signal.

[0147] Specifically, the image controller unit 1301 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a switch 714, and a +10V generation circuit 1303.

[0148] Here, the image controller unit 1301 and the printed circuit board 1302 are connected by a clock signal line 705, a line synchronization signal line 706, an image data signal line 707, a communication signal line 708, a +5V power supply line 712, and a +10V power supply line 1304.

[0149] The +10V power supply line 1304 connects the switch 714 and each of the light-emitting element array chips 1400-1 to 1400-20.

[0150] The +10V generation circuit 1303 converts the +12V power supply voltage applied from an external +12V power supply into a +10V voltage and supplies it to the switch 714. As the -5V generation circuit 711, a general switching regulator circuit is applicable.

[0151] The switch 714 switches whether to supply a +10V voltage to the light-emitting element array chip 1400 by turning ON or OFF according to the presence or absence of an input of a power supply control signal from the CPU 703. The switch 714 turns ON when a power supply control signal is input from the CPU 703, and supplies a +10V voltage to each of the light-emitting element array chips 1400-1 to 1400-20 via the +10V power supply line 1304. The +10V power supply line 1304 becomes a floating state when the switch 714 turns OFF and does not supply a +10V voltage to the light-emitting element array chips 1400-1 to 1400-20.

[0152] The printed circuit board 1302 includes a head information storage unit 709 and the light-emitting element array chips 1400-1 to 1400-20. Note that the arrangement and array of the light-emitting element array chips 1400-1 to 1400-20 on the printed circuit board 1302 are the same as the arrangement and array of the light-emitting element array chips 400-1 to 400-20 on the printed circuit board 302.

[0153] The light-emitting element array chip 1400-1 and the light-emitting element array chip 1400-2 are connected by a signal line 708-1. The light-emitting element array chip 1400-2 and the light-emitting element array chip 1400-3 are connected by a signal line 708-2. Similarly, the light-emitting element array chips 1400-3, ··· are connected in a daisy chain by signal lines 708-3, ···.

[0154] Each of the light-emitting element array chips 1400-1 to 1400-20 generates a line synchronization signal for the next chip and outputs it to the next light-emitting element array chips 1400-2 to 1400-20 via signal lines 708-1, ···. Each of the light-emitting element array chips 1400-1 to 1400-20 causes the light-emitting element 602 to emit light based on the input clock signal, line synchronization signal, set values set for the image data and communication signal.

[0155] The head information storage unit 709 is connected to the CPU 703 via the communication signal line 708. The head information storage unit 709 is a storage device that stores head information such as the light emission amount and mounting position information of the light-emitting element array chips 1400-1 to 1400-20.

[0156] Note that since the light-emitting portions of the light-emitting element array chips 1400-1 to 1400-20 have the same configuration as the light-emitting portion 404 shown in FIG. 5, the description thereof is omitted.

[0157] <Circuit configuration of the light-emitting element array chip> The circuit configuration of the light-emitting element array chips 1400-1 to 1400-20 of the exposure head according to Embodiment 2 of the present invention will be described in detail with reference to FIG. 18.

[0158] Note that since the circuit configurations of the light-emitting element array chips 1400-1 to 1400-20 are the same, the circuit configuration of the light-emitting element array chip 1400-1 will be described, and the description of the circuit configurations of the light-emitting element array chips 1400-2 to 1400-20 will be omitted. Also, parts having the same configuration as those in FIG. 12 in FIG. 18 are denoted by the same reference numerals, and the description thereof is omitted.

[0159] The light-emitting element array chip 1400-1 includes a light-emitting portion 404 and a circuit portion 406. The circuit portion 406 includes a digital portion 800 and an analog portion 801.

[0160] In this embodiment, 2992 drive circuits 900 are provided for one light-emitting element array chip 1400-1 to 1400-20, which is 748 pieces × 4 columns. Since all the drive circuits 900 have the same configuration, for the sake of simplifying the explanation, only the configuration of one drive circuit 900 will be described.

[0161] The MOSFET 902 for current control is a Pch MOSFET. The source terminal of the MOSFET 902 for current control is connected to the cathode of the light-emitting element 602, the gate terminal is connected to the output terminal of the DAC 901 for current setting, and the drain terminal is connected to the source terminal of the MOSFET 903 for switching. The MOSFET 902 for current control is configured such that the higher the analog voltage input from the DAC 901 for current setting, the greater the current flowing from the source terminal to the drain terminal.

[0162] The MOSFET 903 for switching is a Pch MOSFET. The source terminal of the MOSFET 903 for switching is connected to the drain terminal of the MOSFET 902 for current control, the gate terminal is connected to the output terminal of the data holding unit 806, and the drain terminal is connected to GND. Binary drive signals 1 to 4 of Hi level or Low level are input from the data holding units 806-001 to 748 to the gate terminal of the MOSFET 903 for switching.

[0163] The MOSFET 903 for switching turns ON when a Hi-level drive signal is input to the gate terminal, and turns OFF when a Low-level drive signal is input to the gate terminal. When a Hi-level drive signal is input to the gate terminal of the MOSFET 903 for switching and it turns ON, a current, which is the drive current of the light-emitting element 602 controlled by the MOSFET 902 for current control, flows from the source terminal to the drain terminal.

[0164] Next, the power supply configuration for each of the digital unit 800, the analog unit 801, and the light-emitting element 602 will be described in detail with reference to FIG. 19.

[0165] For the parts having the same configuration as those in FIG. 11 in FIG. 19, the same reference numerals are assigned and their descriptions are omitted. Further, in FIG. 19, for simplicity of explanation, the description of the blocks inside the digital section 800 is omitted, and only one drive circuit 900 and one light emitting element 602 inside the analog section 801 are described respectively.

[0166] The anode terminal A of the light emitting element 602 is supplied with a voltage of +10V from the +10V power supply line 1304, and the cathode terminal is connected to the source terminal of the current control MOSFET 902. The light emitting element 602 is, for example, an organic EL, and generally a forward voltage of about 6V is generated with a drive current of several μA. That is, the potential of the cathode terminal K of the light emitting element 602 becomes about +4V obtained by subtracting 6V from +10V.

[0167] Since the voltage between the drain and source of the current control MOSFET 902 and the switching MOSFET 903 is about 1.5V respectively, when adding the voltage between the drain and source of 1.5V×2 = 3V to the forward voltage of 6V of the light emitting element 602, it becomes about 9V. Therefore, the light emitting element array chips 1400-1 to 1400-20 require a voltage of about 9V or more to cause the light emitting element 602 to emit light. Since the light emitting element array chips 1400-1 to 1400-20 can drive the light emitting element 602 in a 10V range between GND (0V) and +10V, the light emitting element 602 can be caused to emit light.

[0168] Conventionally, in a configuration where an EL film is deposited or the like on a circuit section, in order to ensure a forward voltage of 6V for the light-emitting element, it was necessary to form a light-emitting element array chip using a semiconductor process of 9V or higher in consideration of the voltage between the drain and source of the MOSFET. On the other hand, in the present embodiment, GND and +10V are supplied as power supply voltages to drive the light-emitting element 602 in the 10V range, and the digital section 800 and the analog section 801 are configured using a semiconductor process from GND to +5V. As a result, in the present embodiment, the sizes of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip sizes of the light-emitting element array chips 1400-1 to 1400-20 can be reduced.

[0169] <Operation of the exposure head> The operation of the exposure head 106 according to Embodiment 2 of the present invention will be described in detail with reference to FIGS. 20 and 21.

[0170] The exposure head 106 starts operating at the timing when the main power supply of the image forming apparatus 1 is turned on.

[0171] First, the CPU 703 determines whether a print JOB has been requested by the user (S11).

[0172] When the CPU 703 has not been requested a print JOB by the user (S11: No), the operation of step S11 is repeated.

[0173] On the other hand, when the CPU 703 has been requested a print JOB by the user (S11: Yes), the CPU 703 writes set values to the register section 803 of the light-emitting element array chips 1400-1 to 1400-20 to perform register setting (S12).

[0174] Next, the CPU 703 outputs a power control signal to the switch 714 to supply a voltage of +10V to the anode electrode of the light-emitting element 602 of the light-emitting element array chips 1400-1 to 1400-20 (+10V ON) (S13).

[0175] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 1400-1 to 1400-20 at a predetermined timing to expose the photosensitive drum 102 (S14).

[0176] Next, the CPU 703 determines whether the printing JOB has ended (S15).

[0177] If the printing JOB has not ended (S15: No), the CPU 703 repeats the operation of step S15.

[0178] On the other hand, when the printing JOB has ended (S15: Yes), the CPU 703 stops sending the power control signal to the switch 714, floating the potential of the anode electrode of the light-emitting element 602, and ends the operation.

[0179] Subsequently, the operation of the exposure head 106 will be described in more detail with reference to FIG. 21.

[0180] From FIG. 21, at time t = t10, the power of the image forming apparatus 1 is turned on, and a power supply voltage of +12V is supplied to the +5V generation circuit 710 and the +10V generation circuit 1303. As a result, the voltage of the +5V power supply line 712 becomes +5V after the elapse of time t = t10. At this time, since the switch 714 is OFF, the potential of the +10V power supply line 1304 is in a floating state (0V in FIG. 21).

[0181] At time t = t11, by receiving a JOB request from the user, the CPU 703 outputs a power control signal to the switch 714, whereby the potential of the +10V power supply line 1304 becomes +10V, and the light-emitting element 602 becomes drivable.

[0182] At time t = t12, when the JOB ends, the CPU 703 stops outputting the power control signal to the switch 714, turns off the switch 714, and makes the potential of the +10V power supply line 1304 float (0V in FIG. 21).

[0183] Thus, in the configuration where the light-emitting element 602 and the analog unit 801 are formed on the same chip, a voltage (+10V) higher than the voltages (+5V and the reference potential (GND)) supplied to the analog unit 801 is supplied to the anode electrode of the light-emitting element 602. Thereby, since the analog unit 801 can be formed by a semiconductor process with a relatively low breakdown voltage, the size of the analog unit 801 can be reduced, and the chip size can be reduced.

[0184] Also, when not exposed, the potential of the anode electrode connected to the +10V power supply line 1304 of the light-emitting element 602 is set to a floating state. Thereby, even in the OFF state when not exposed, the leakage current from the current control MOSFET 902 and the switching MOSFET 903 that generate leakage current can be suppressed, and the power consumption can be suppressed.

[0185] In the present embodiment, the analog unit 801 operates between the first potential +5V and the second potential 0V, and the light-emitting element 602 operates between the third potential +10V and the fourth potential +4V. Also, the potential difference between the third potential +10V and the fourth potential +4V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. Thereby, in the configuration where the light-emitting element 602 and the analog unit 801 are formed on one chip, the analog unit 801 can be formed by a semiconductor process with a low breakdown voltage while ensuring the forward voltage of the light-emitting element 602, and the chip size can be reduced.

[0186] Also, in the present embodiment, the third potential +10V is at a higher potential than the first potential +5V, and the fourth potential +4V is at a higher potential than the second potential 0V. The potential difference between the first potential +5V and the third potential +10V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V.

[0187] Also, in this embodiment, when the switch 714 is switched so as not to supply current to the light-emitting element 602, a fifth potential of 0V, which is at least lower than the first potential of +5V, is obtained. The fifth potential of 0V is equal to the second potential of 0V.

[0188] Furthermore, in this embodiment, the fourth potential of +4V is lower than the first potential of +5V. The second potential of 0V is the ground potential. The third potential of +10V is higher than the second potential of 0V.

[0189] Note that in this embodiment, not limited to +5V and +10V, voltages other than 5V and 10V may be used as long as they can drive the light-emitting element 602.

[0190] Also, in this embodiment, 20 light-emitting element array chips 1400-1 to 1400-20 are provided on the printed circuit board 1302. However, the present invention is not limited to this, and any number of light-emitting element array chips can be provided on the printed circuit board 1302 as required.

[0191] It goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0192] 1 Image forming apparatus 102 Photosensitive drum 103 Image forming unit 104 Fixing unit 105 Conveying unit 106 Exposure head 107 Charger 108 Developing device 110 Registration roller 111 Transfer belt 112 Paper discharge roller 113 Optical sensor 201 Light-emitting element group 202 Printed circuit board 203 Rod lens array 204 Housing 305 Connector Light-emitting element array chips 400-1 to 400-20 Light-emitting substrate 402 Light-emitting section 404 Circuit section 406 Pad for wire bonding 408 Lower electrode 504 Light-emitting layer 506 Upper electrode 508 Light-emitting element 602 Light-emitting element row 604

Claims

Claim 1: An exposure head for exposing a photosensitive drum, comprising: a substrate; a plurality of light-emitting elements that emit light, and a drive circuit that drives the light-emitting elements, the plurality of strip-shaped semiconductor chips arranged on the substrate; a lens array that condenses the light from the light-emitting elements onto the photosensitive drum; and having: the drive circuit operates between a first potential and a second potential; the light-emitting elements operate between a third potential and a fourth potential; a potential difference between the third potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential; the second potential is a ground potential; the first potential is a positive potential with respect to the ground potential; the fourth potential is a negative potential with respect to the ground potential. An exposure head characterized by the above.

2. The light-emitting elements include an anode terminal connected to the third potential and a cathode terminal connected to the fourth potential; the third potential is lower than the first potential; the fourth potential is lower than the second potential. The exposure head according to claim 1, characterized by the above.

3. A potential difference between the second potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential. The exposure head according to claim 1 or claim 2, characterized by the above.

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