Imaging device

Abstract

To provide a noise detection circuit configured to detect noise entered into a cable.SOLUTION: A reference clock counter 22 counts reference clocks for every line. A reference line counter 23 counts the number of lines in each frame. A detection clock counter 24 counts reference clocks, resets the count value every time a horizontal synchronization pulse is input, and resets the count value when noise is input through a first bidirectional pin 213. The detection line counter 25 counts the number of lines, resets the count value every time a vertical synchronization pulse is input, and resets the count value when noise is input through a second bidirectional pin 212. An anomaly detection unit 26 generates an anomaly detection flag when there is a difference between the count values counted by the reference clock counter 22 and the detection clock counter 24, or when there is a difference between the count values counted by the reference line counter 23 and the detection line counter 25.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention , pick relates to an imaging device.

Background Art

[0002] A video camera (imaging device) is provided with a viewfinder for checking the video during shooting. The video display driving unit mounted on the video camera supplies the video data generated by shooting a subject to the viewfinder and drives the viewfinder to display the video on the viewfinder.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The video display driving unit and the viewfinder are often connected by a wiring material (cable) typified by a flexible flat cable. When noise such as static electricity jumps into the flexible flat cable, the video displayed on the viewfinder may remain distorted, or the video may freeze and the video during shooting may become unviewable. This problem may occur not only when the video display unit connected to the video display driving unit via the flexible flat cable is a viewfinder, but also when the video display unit is a liquid crystal panel.

[0005] One or more embodiments can detect noise that jumps into the cable connecting the video display driving unit and the video display unit Imaging device and provide an imaging device capable of eliminating abnormalities such as the video remaining distorted or freezing even when noise jumps into the cable.

Means for Solving the Problem

[0006] According to a first aspect of one or more embodiments, a video display unit and a video display driving unit that supplies video data to the video display unit to drive the video display unit are connected by a cable. According to the first aspect, the video display driving unit and the cable are connected by a first bidirectional pin that outputs a horizontal synchronization signal of the video data to the cable and inputs noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving unit, and a second bidirectional pin that outputs a vertical synchronization signal of the video data to the cable and inputs noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit.

[0007] According to the first aspect, a reference clock counter, a reference line counter, a detection clock counter, a detection line counter, and an abnormality detection unit are An imaging device including a noise detection circuit provided.

[0008] The reference clock counter counts a reference clock supplied from the video display driving unit to the video display unit via the cable, and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, thereby counting the reference clock for each line in each frame of the video data. The reference line counter counts the number of lines of the video data, and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, thereby counting the number of lines in each frame of the video data.

[0009] The detection clock counter counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the first bidirectional pin. The detection line counter counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the second bidirectional pin.

[0010] When the count value by the reference clock counter and the count value by the detection clock counter are different, the abnormality detection unit determines that noise is superimposed on the horizontal synchronization signal and an abnormality has occurred in the horizontal synchronization signal. When the count value by the reference line counter and the count value by the detection line counter are different, the abnormality detection unit determines that noise is superimposed on the vertical synchronization signal and an abnormality has occurred in the vertical synchronization signal. When it is determined that an abnormality has occurred in at least one of the horizontal synchronization signal and the vertical synchronization signal, the abnormality detection unit generates an abnormality detection flag.

[0011] According to a second aspect of one or more embodiments, a video display unit and a video display driving unit that supplies video data to the video display unit and drives the video display unit are connected by a cable. According to the second aspect, the video display driving unit and the cable are connected by a bidirectional pin that outputs the horizontal synchronization signal of the video data to the cable and inputs the noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving unit.

[0012] According to the second aspect, a reference clock counter, a detection clock counter, and an abnormality detection unit are An imaging device including a noise detection circuit provided.

[0013] The reference clock counter counts the reference clock supplied from the video display driving unit to the video display unit via the cable, and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, thereby counting the reference clock for each line in each frame of the video data. The detection clock counter counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the bidirectional pin. When the count value by the reference clock counter and the count value by the detection clock counter are different, the abnormality detection unit determines that noise is superimposed on the horizontal synchronization signal and an abnormality has occurred in the horizontal synchronization signal, and generates an abnormality detection flag when it is determined that an abnormality has occurred in the horizontal synchronization signal.

[0014] According to a third aspect of one or more embodiments, a video display unit and a video display driving unit that supplies video data to the video display unit and drives the video display unit are connected by a cable. According to the third aspect, the video display driving unit and the cable are connected by a bidirectional pin that outputs the vertical synchronization signal of the video data to the cable and inputs the noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit.

[0015] According to the third aspect, a reference line counter, a detection line counter, and an abnormality detection unit are An imaging device including a noise detection circuit provided.

[0016] The reference line counter counts the number of lines of the video data, and counts the number of lines of each frame of the video data by resetting the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input. The detection line counter counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the bidirectional pin. When the count value by the reference line counter and the count value by the detection line counter are different, the abnormality detection unit determines that noise is superimposed on the vertical synchronization signal and an abnormality has occurred in the vertical synchronization signal, and generates an abnormality detection flag when it is determined that an abnormality has occurred in the vertical synchronization signal.

[0017] According to a fourth aspect of one or more embodiments, there is provided an imaging device including a video display unit, a video display driving unit that supplies video data, a horizontal synchronization signal of the video data, a vertical synchronization signal of the video data, and a reference clock to the video display unit to drive the video display unit, and a cable that connects the video display driving unit and the video display unit and transmits the video data, the horizontal synchronization signal, the vertical synchronization signal, and the reference clock from the video display driving unit to the video display unit.

[0018] According to a fourth aspect, the video display driving unit and the cable are connected by a first bidirectional pin that outputs the horizontal synchronization signal to the cable and inputs noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving unit, and a second bidirectional pin that outputs the vertical synchronization signal to the cable and inputs noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit.

[0019] According to a fourth aspect, there is provided an imaging device further including a reference clock counter, a reference line counter, a detection clock counter, a detection line counter, an abnormality detection unit, and a restart control unit.

[0020] The reference clock counter counts the reference clock, and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, thereby counting the reference clock for each line in each frame of the video data. The reference line counter counts the number of lines of the video data, and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, thereby counting the number of lines in each frame of the video data.

[0021] The detection clock counter counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the first bidirectional pin. The detection line counter counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the second bidirectional pin.

[0022] When the count value by the reference clock counter and the count value by the detection clock counter are different, the abnormality detection unit determines that noise is superimposed on the horizontal synchronization signal and an abnormality has occurred in the horizontal synchronization signal. When the count value by the reference line counter and the count value by the detection line counter are different, the abnormality detection unit determines that noise is superimposed on the vertical synchronization signal and an abnormality has occurred in the vertical synchronization signal. When it is determined that an abnormality has occurred in at least one of the horizontal synchronization signal and the vertical synchronization signal, the abnormality detection unit generates an abnormality detection flag. When the abnormality detection unit generates the abnormality detection flag, the restart control unit controls the video display unit to restart the video display unit.

Advantages of the Invention

[0023] One or more embodiments An imaging device according to According to one or more embodiments, it is possible to detect noise that jumps into the cable connecting the video display driving unit and the video display unit. One or more embodimentsAccording to According to the imaging device, even if noise enters the cable connecting the video display driving unit and the video display unit, abnormalities such as the video remaining distorted or freezing can be eliminated.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Embodiments for Carrying Out the Invention

[0025] Hereinafter, one or more embodiments According to The imaging device will be described with reference to the accompanying drawings. As shown in FIG. 1, one or more embodiments According to The imaging device (hereinafter referred to as a video camera) includes a video signal processing unit 1, a video display driving unit 2, and a viewfinder 5 as a video display unit. The video camera may include a liquid crystal panel as another video display unit.

[0026] In FIG. 1, the video signal processing unit 1 processes a video signal generated by imaging a subject by an imaging device (not shown), and supplies video data Vdata, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync of the video data Vdata to the video display driving unit 2. As an example, the video data Vdata consists of a luminance signal (Y signal) and two color difference signals (Cb and Cr signals). For example, the Y signal is 8-bit digital data, and the Cb and Cr signals are 8-bit digital data time-division multiplexed with each other.

[0027] The video display driving unit 2 is composed of an integrated circuit of hardware. The video display driving unit 2 may be composed of an FPGA (Field Programmable Gate Array) whose circuit configuration can be changed, or may be composed of a CPLD (Complex Programmable Logic Device) with fewer gates than the FPGA. That is, the video display driving unit 2 may be composed of an integrated circuit whose circuit configuration cannot be changed, or may be composed of an integrated circuit which is a programmable logic device including an FPGA or a CPLD.

[0028] The video display driving unit 2 is connected to the viewfinder 5 by a flexible flat cable (hereinafter referred to as FFC) 4. When the video camera includes a liquid crystal panel, the video display driving unit 2 is connected to the liquid crystal panel by the FFC 4. The video display driving unit 2 drives the viewfinder 5 or the liquid crystal panel. The video display driving unit 2 and the viewfinder 5 may be connected by a cable other than the FFC 4. The video display driving unit 2 and the viewfinder 5 may be connected by a flexible printed circuit (FPC). Noise may enter the cable connecting the video display driving unit 2 and the viewfinder 5 due to static electricity or the like.

[0029] The number of lines per frame and the number of pixels per line of the viewfinder 5 often differ from the number of lines and the number of pixels of the video data Vdata output from the video signal processing unit 1. In one or more embodiments, the case where the number of lines per frame and the number of pixels per line of the viewfinder 5 are less than the number of lines and the number of pixels of the video data Vdata output from the video signal processing unit 1 will be described. Therefore, the format conversion unit 21 reduces the number of lines and the number of pixels of the video data Vdata to convert the video format. The format conversion unit 21 supplies the video data Vdata with the converted video format to the driver 201, and supplies the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the drivers 202 and 203, respectively.

[0030] The driver 201 supplies the video data Vdata to the viewfinder 5 via the output pin 211 and the FFC4. The drivers 202 and 203 supply the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the viewfinder 5 via the bidirectional pins 212 and 213 and the FFC4, respectively. The bidirectional pin 213 is the first bidirectional pin, and the bidirectional pin 212 is the second bidirectional pin.

[0031] The bidirectional pins 212 and 213 are pins having the functions of both an output pin for outputting the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync from the video display driving unit 2 to the FFC4 and an input pin for inputting a signal superimposed on the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync for transmitting the FFC4 to the video display driving unit 2. Usually, in order for the video display driving unit 2 to supply the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the viewfinder 5 via the FFC4, the video display driving unit 2 is provided with output pins. In one or more embodiments, instead of the usually provided output pins, the bidirectional pins 212 and 213 are provided.

[0032] One end of a pull-up resistor 208 is connected between a driver 202 and a bidirectional pin 212. One end of a pull-up resistor 207 is connected between a driver 203 and a bidirectional pin 213. The other ends of the pull-up resistors 207 and 208 are connected to a power supply (not shown).

[0033] A clock CLK0 generated by an external clock generator is input to a PLL (Phase Locked Loop) circuit 27. The PLL circuit 27 generates and outputs a clock CLK, which is a reference clock for the operation of a video display driving unit 2 and a viewfinder 5, based on the clock CLK0. A driver 204 supplies the clock CLK to the viewfinder 5 via an output pin 214 and an FFC4. The clock CLK is supplied to a format conversion unit 21 and each circuit block described later.

[0034] The video display driving unit 2 includes a reference clock counter 22, a reference line counter 23, a detection clock counter 24, a detection line counter 25, and an abnormality detection unit 26. The reference clock counter 22, the reference line counter 23, the detection clock counter 24, the detection line counter 25, and the abnormality detection unit 26 constitute a noise detection circuit. The noise detection circuit detects pulse-shaped noise superimposed on a vertical synchronization signal Vsync or a horizontal synchronization signal Hsync transmitted through the FFC4, which is generated when noise such as static electricity jumps into the FFC4.

[0035] The clock CLK and the horizontal synchronization signal Hsync supplied to the driver 204 and 203 are respectively input to the reference clock counter 22. The clock CLK, the count value of the reference clock counter 22, and the vertical synchronization signal Vsync are input to the reference line counter 23. The clock CLK and the vertical synchronization signal Vsync supplied to the reference line counter 23 are respectively the clock CLK and the vertical synchronization signal Vsync supplied to the driver 204 and 202.

[0036] The reference clock counter 22 counts the input clock CLK and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal Hsync is input. That is, the reference clock counter 22 counts the clock CLK for each line in each frame of the video data Vdata. The reference line counter 23 increments the count value when the count value of the reference clock counter 22 reaches the maximum value and resets the count value each time the vertical synchronization signal Vsync is input. That is, the reference line counter 23 counts the number of lines in each frame of the video data Vdata.

[0037] The detection clock counter 24 receives the clock CLK and the horizontal synchronization signal Hsync. When noise jumps into the FFC4 and pulse-shaped noise is superimposed on the horizontal synchronization signal Hsync that transmits the FFC4, the pulse-shaped noise is input to the video display driving unit 2 via the bidirectional pin 213. When the pulse-shaped noise is input to the video display driving unit 2 via the bidirectional pin 213, the noise is input to the detection clock counter 24.

[0038] The detection line counter 25 receives the clock CLK, the count value of the detection clock counter 24, and the vertical synchronization signal Vsync. When noise jumps into the FFC4 and pulse-shaped noise is superimposed on the vertical synchronization signal Vsync that transmits the FFC4, the pulse-shaped noise is input to the video display driving unit 2 via the bidirectional pin 212. When the pulse-shaped noise is input to the video display driving unit 2 via the bidirectional pin 212, the noise is input to the detection line counter 25.

[0039] The detection clock counter 24 counts the input clock CLK in the same way as the reference clock counter 22, and resets the count value every time the horizontal synchronization signal Hsync is input. However, the detection clock counter 24 resets the count value when pulsed noise is input. Although the detection clock counter 24 counts the clock CLK for each line, if pulsed noise is input in the middle of a line, the count value is reset and the clock CLK is counted again.

[0040] The detection line counter 25 increments the count value when the count value of the detection clock counter 24 reaches the maximum value, in the same way as the reference line counter 23, and resets the count value every time the vertical synchronization signal Vsync is input. However, the detection line counter 25 resets the count value when pulsed noise is input. Although the detection line counter 25 counts the number of lines in each frame, if pulsed noise is input within a frame, the count value is reset and the number of lines is counted again.

[0041] The abnormality detection unit 26 compares the count value of the reference clock counter 22 with the count value of the detection clock counter 24. The abnormality detection unit 26 detects an abnormality in the horizontal synchronization signal Hsync based on whether the count values of both are the same. Specifically, if the count values of both are the same, the abnormality detection unit 26 determines that no abnormality has occurred in the horizontal synchronization signal Hsync, and if the count values of both are different, the abnormality detection unit 26 determines that an abnormality has occurred in the horizontal synchronization signal Hsync. An abnormality in the horizontal synchronization signal Hsync means that noise is superimposed on the horizontal synchronization signal Hsync that transmits FFC4.

[0042] The abnormality detection unit 26 compares the count value of the reference line counter 23 with the count value of the detection line counter 25. The abnormality detection unit 26 detects an abnormality in the vertical synchronization signal Vsync based on whether the count values of both are the same value. Specifically, if the count values of both are the same value, the abnormality detection unit 26 determines that no abnormality has occurred in the vertical synchronization signal Vsync, and if the count values of both are different values, the abnormality detection unit 26 determines that an abnormality has occurred in the vertical synchronization signal Vsync. The abnormality in the vertical synchronization signal Vsync means that noise is superimposed on the vertical synchronization signal Vsync that transmits the FFC4.

[0043] When the abnormality detection unit 26 detects an abnormality in at least one of the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync, the abnormality detection unit 26 generates an abnormality detection flag and supplies it to the processor 3. The processor 3 may be a central processing unit (CPU) of a microcomputer. As will be described later, the processor 3 instructs the abnormality detection unit 26 to start or stop abnormality detection, or instructs the abnormality detection unit 26 to clear the abnormality detection flag.

[0044] As described above, in one or more embodiments An imaging device according to according to the present invention, it is possible to detect noise that jumps into the FFC4 connecting the video display driving unit 2 and the viewfinder 5.

[0045] When the abnormality detection flag is input from the abnormality detection unit 26, the processor 3 supplies a restart command to the viewfinder 5 and controls the viewfinder 5 to restart. When the abnormality detection unit 26 generates the abnormality detection flag, the processor 3 functions as a restart control unit that controls the viewfinder 5 to restart the viewfinder 5. In one or more embodiments, the restart control unit is provided outside the video display driving unit 2, but the restart control unit may be provided inside the video display driving unit 2. That is, the restart control unit may be configured as a part of an integrated circuit.

[0046] When the viewfinder 5 is restarted, abnormalities such as the video displayed on the viewfinder 5 remaining distorted or freezing are resolved, and the viewfinder 5 can display a normal video again. Therefore, one or more embodiments According to According to the video camera, even if noise enters the FFC4, abnormalities such as the video remaining distorted or freezing can be resolved.

[0047] Using the flowchart shown in FIG. 2, a schematic operation by the video display driving unit 2 or the processor 3 will be described. In FIG. 2, when the power of the video camera is turned on and the video camera is started and the process is started, the video display driving unit 2 activates the viewfinder 5 in step S1. The video display driving unit 2 (abnormality detection unit 26) starts detecting an abnormality in the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync in step S2 according to an instruction from the processor 3 to start abnormality detection.

[0048] The video display driving unit 2 (abnormality detection unit 26) determines in step S3 whether an abnormality has occurred. If no abnormality has occurred (NO), the video display driving unit 2 determines in step S8 whether the power of the video camera has been turned off. If the power of the video camera has been turned off (YES), the video display driving unit 2 ends the process. If the power of the video camera has not been turned off (NO), the video display driving unit 2 returns the process to step S3.

[0049] If an abnormality occurs in step S3 (YES), the video display driving unit 2 (abnormality detection unit 26) generates an abnormality detection flag in step S4. The video display driving unit 2 (abnormality detection unit 26) stops abnormality detection in step S5 according to an instruction from the processor 3 to stop abnormality detection, and further clears the abnormality detection flag in step S6.

[0050] The reason for stopping the abnormality detection in step S5 is that if an abnormality is detected again during the restart of the viewfinder 5, it may cause an unexpected abnormal operation, and such a risk is avoided. In step S7, the processor 3 restarts the viewfinder 5, and the video display driving unit 2 returns the process to step S2.

[0051] The operation of the video display driving unit 2 will be described in detail using the timing charts shown in FIGS. 3A, 3B, 4A, and 4B. FIG. 3A shows the operation of the video display driving unit 2 when no noise is superimposed on the horizontal synchronization signal Hsync. As shown in FIG. 3A, the horizontal synchronization pulse Hpls included in the horizontal synchronization signal Hsync has a negative polarity. The reference clock counter 22 resets the count value to 0 at the falling edge of the horizontal synchronization pulse Hpls. The reference clock counter 22 counts the clock CLK during the period of one line (1H), and sequentially increments the count value from 0 to the maximum value Hmax.

[0052] The reference line counter 23 increments the count value when the count value of the reference clock counter 22 reaches the maximum value Hmax. Therefore, the count value of the reference line counter 23 increases as n - 1, n, n + 1,... every 1H.

[0053] The detection clock counter 24 resets the count value to 0 at the falling edge of the horizontal synchronization pulse Hpls. The detection clock counter 24 counts the clock CLK during the period of 1H, and sequentially increments the count value from 0 to the maximum value Hmax. The detection line counter 25 increments the count value when the count value of the detection clock counter 24 reaches the maximum value Hmax. Therefore, the count value of the detection line counter 25 increases as n - 1, n, n + 1,... every 1H.

[0054] Although not shown in FIG. 3A, as described in step S2 of FIG. 2, the abnormality detection unit 26 starts abnormality detection in accordance with an instruction from the processor 3 to start abnormality detection. In FIG. 3A, the abnormality detection unit 26 detects that the count value of the reference clock counter 22 and the count value of the detection clock counter 24 are always the same value. Therefore, the abnormality detection unit 26 does not detect an abnormality in the horizontal synchronization signal Hsync, and sets the abnormality detection value of the horizontal synchronization signal Hsync to low (L). The abnormality detection value L indicates a state in which no abnormality in the horizontal synchronization signal Hsync is detected.

[0055] Since the abnormality detection unit 26 does not detect an abnormality in the horizontal synchronization signal Hsync, it does not generate an abnormality detection flag. That is, the abnormality detection unit 26 continuously outputs L indicating that it has not generated an abnormality detection flag.

[0056] FIG. 3B shows the operation of the video display driving unit 2 when noise is superimposed on the horizontal synchronization signal Hsync. As shown in FIG. 3B, when noise Ns is superimposed on the horizontal synchronization signal Hsync, the count value of the detection clock counter 24 is reset to 0. Here, the noise Ns is an example of a plurality of consecutive pulse-shaped noises. On the other hand, since the reference clock counter 22 is not reset, when the count value of the detection clock counter 24 is reset to 0, the count value of the reference clock counter 22 is a predetermined value x that is not 0.

[0057] The abnormality detection unit 26 detects that the count value x of the reference clock counter 22 and the count value 0 of the detection clock counter 24 are different. Therefore, the abnormality detection unit 26 detects an abnormality in the horizontal synchronization signal Hsync, and sets the abnormality detection value of the horizontal synchronization signal Hsync to high (H). The abnormality detection value H indicates a state in which an abnormality in the horizontal synchronization signal Hsync is detected. Until the count values of the reference clock counter 22 and the detection clock counter 24 are reset at the falling edge of the next horizontal synchronization pulse Hpls, the count values of both are different, so the abnormality detection unit 26 outputs the abnormality detection value H until the falling edge of the next horizontal synchronization pulse Hpls.

[0058] When the abnormality detection unit 26 sets the abnormality detection value of the horizontal synchronization signal Hsync as H, it also outputs H as an abnormality detection flag. The abnormality detection flag H indicates a state in which an abnormality has been detected. Although not shown in FIG. 3B, the abnormality detection unit 26 stops the abnormality detection in accordance with an instruction from the processor 3 to stop the abnormality detection. After the abnormality detection unit 26 stops the abnormality detection, the processor 3 instructs to clear the abnormality detection flag, and the abnormality detection unit 26 sets the abnormality detection flag as L. The abnormality detection flag becomes L at a predetermined timing after the abnormality detection value of the horizontal synchronization signal Hsync becomes L at the falling edge of the next horizontal synchronization pulse Hpls. Subsequently, the processor 3 restarts the viewfinder 5.

[0059] FIG. 4A shows the operation of the video display driving unit 2 when no noise is superimposed on the vertical synchronization signal Vsync. As shown in FIG. 4A, the vertical synchronization pulse Vpls included in the vertical synchronization signal Vsync has a negative polarity. The reference line counter 23 and the detection line counter 25 reset the count value to 0 at the falling edge of the vertical synchronization pulse Vpls. The reference line counter 23 and the detection line counter 25 count the number of lines during the period of 1 frame (1V), and increment the count value in order from the count value 0 to the maximum value Vmax.

[0060] Assume that the abnormality detection unit 26 starts the abnormality detection at time t1 in accordance with an instruction from the processor 3 to start the abnormality detection. In the start / stop of the abnormality detection shown in FIG. 4A, L indicates a state in which the abnormality detection is stopped, and H indicates a state in which the abnormality detection has been started and an abnormality has been detected.

[0061] In FIG. 4A, the abnormality detection unit 26 detects that the count value of the reference line counter 23 and the count value of the detection line counter 25 are always the same value. Therefore, the abnormality detection unit 26 does not detect an abnormality in the vertical synchronization signal Vsync, and sets the abnormality detection value of the vertical synchronization signal Vsync to L. The abnormality detection unit 26 detects an abnormality in the horizontal synchronization signal Hsync in each 1H period within the 1V period in FIG. 4A, as described with reference to FIGS. 3A and 3B. Here, it is assumed that no abnormality is detected in either the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync. Therefore, the abnormality detection unit 26 outputs L as the abnormality detection flag.

[0062] FIG. 4B shows the operation of the video display driving unit 2 when noise is superimposed on the vertical synchronization signal Vsync. As shown in FIG. 4B, when noise Ns is superimposed on the vertical synchronization signal Vsync, the count value of the detection line counter 25 is reset to 0. On the other hand, since the reference line counter 23 is not reset, when the count value of the detection line counter 25 is reset to 0, the count value of the reference line counter 23 is a predetermined value y that is not 0.

[0063] The abnormality detection unit 26 detects that the count value y of the reference line counter 23 and the count value 0 of the detection line counter 25 are different. Therefore, the abnormality detection unit 26 detects an abnormality in the vertical synchronization signal Vsync, and sets the abnormality detection value of the vertical synchronization signal Vsync to H. Until the count values of the reference line counter 23 and the detection line counter 25 are reset at the falling edge of the next vertical synchronization pulse Vpls, the count values of both are different. Therefore, the abnormality detection unit 26 outputs H as the abnormality detection value until the falling edge of the next vertical synchronization pulse Vpls.

[0064] The abnormality detection unit 26 outputs H as an abnormality detection flag in accordance with setting the abnormality detection value of the vertical synchronization signal Vsync to H. The abnormality detection flag H indicates a state in which an abnormality has been detected. The abnormality detection unit 26 stops abnormality detection at time t2 in accordance with an instruction from the processor 3 to stop abnormality detection. The processor 3 instructs to clear the abnormality detection flag at time t3, and the abnormality detection unit 26 sets the abnormality detection flag to L. Subsequently, the processor 3 restarts the viewfinder 5.

[0065] As described above, since the abnormality detection unit 26 detects an abnormality of the horizontal synchronization signal Hsync every 1H and detects an abnormality of the vertical synchronization signal Vsync during each 1V period, when detecting an abnormality of at least one of the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync, an abnormality detection flag is generated. Preferably, the abnormality detection unit 26 detects the presence or absence of abnormalities in both the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync, and generates an abnormality detection flag when detecting an abnormality in at least one of them.

[0066] For simplification of the configuration, the abnormality detection unit 26 may detect only the presence or absence of an abnormality of the horizontal synchronization signal Hsync, and generate an abnormality detection flag when detecting an abnormality of the horizontal synchronization signal Hsync. In this case, the reference line counter 23 and the detection line counter 25 can be omitted. Further, the abnormality detection unit 26 may detect only the presence or absence of an abnormality of the vertical synchronization signal Vsync, and generate an abnormality detection flag when detecting an abnormality of the vertical synchronization signal Vsync. In this case, the reference clock counter 22 and the detection clock counter 24 can be omitted. When the reference clock counter 22 and the detection clock counter 24 are omitted, the reference line counter 23 and the detection line counter 25 may count the horizontal synchronization pulses Hpls.

[0067] As described above, one or more embodiments According to According to the video camera, even if noise jumps into the FFC 4 connecting the video display driving unit 2 and the viewfinder 5, abnormalities such as the video remaining disturbed or freezing can be eliminated. Therefore, one or more embodimentsAccording to The video camera does not need to be additionally provided with electrostatic countermeasure components or the like. The video camera of the present embodiment does not need to be covered with a case or coated with tape so that the cable is not exposed in the movable part of the viewfinder 5.

[0068] The present invention is not limited to one or more of the embodiments described above, and various modifications can be made without departing from the gist of the present invention.

Explanation of reference numerals

[0069] 1 Video signal processing unit 2 Video display driving unit 3 Processor (restart control unit) 4 Flexible flat cable 5 Viewfinder 21 Format conversion unit 22 Reference clock counter 23 Reference line counter 24 Detection clock counter 25 Detection line counter 26 Abnormality detection unit 201~204 Driver 207,208 Pull-up resistor 211,214 Output pin 212,213 Bidirectional pin

Claims

1. A video display unit, a video display driving unit that supplies video data, a horizontal synchronization signal of the video data, a vertical synchronization signal of the video data, and a reference clock to the video display unit to drive the video display unit, a cable that connects the video display driving unit and the video display unit and transmits the video data, the horizontal synchronization signal, the vertical synchronization signal, and the reference clock from the video display driving unit to the video display unit, comprising: the video display driving unit and the cable are connected by a bidirectional pin that outputs the horizontal synchronization signal of the video data to the cable and inputs noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving unit, a reference clock counter that counts the reference clock supplied from the video display driving unit to the video display unit via the cable and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, thereby counting the reference clock for each line in each frame of the video data, a detection clock counter that counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the bidirectional pin, an abnormality detection unit that determines that noise is superimposed on the horizontal synchronization signal and an abnormality has occurred in the horizontal synchronization signal when the count value by the reference clock counter and the count value by the detection clock counter are different, and generates an abnormality detection flag when it is determined that an abnormality has occurred in the horizontal synchronization signal, An imaging device further comprising a noise detection circuit including the above.

2. A video display unit, a video display driving unit that supplies video data, a horizontal synchronization signal of the video data, a vertical synchronization signal of the video data, and a reference clock to the video display unit to drive the video display unit, a cable that connects the video display driving unit and the video display unit and transmits the video data, the horizontal synchronization signal, the vertical synchronization signal, and the reference clock from the video display driving unit to the video display unit, comprising: the video display driving unit and the cable are connected by a bidirectional pin that outputs the vertical synchronization signal of the video data to the cable and inputs noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit, A reference line counter that counts the number of lines of the video data and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, thereby counting the number of lines of each frame of the video data. A detection line counter that counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the bidirectional pin. An abnormality detection unit that determines that noise is superimposed on the vertical synchronization signal and an abnormality has occurred in the vertical synchronization signal when the count value by the reference line counter and the count value by the detection line counter are different, and generates an abnormality detection flag when it is determined that an abnormality has occurred in the vertical synchronization signal. An imaging device further comprising a noise detection circuit including the above. The imaging device according to claim 1 or 2, further comprising a restart control unit that controls the video display unit to restart when the abnormality detection unit generates the abnormality detection flag.

4. A video display unit, A video display driving unit that supplies video data, a horizontal synchronization signal of the video data, a vertical synchronization signal of the video data, and a reference clock to the video display unit to drive the video display unit. A cable that connects the video display driving unit and the video display unit and transmits the video data, the horizontal synchronization signal, the vertical synchronization signal, and the reference clock from the video display driving unit to the video display unit. Comprising The video display driving unit and the cable are connected by a first bidirectional pin that outputs the horizontal synchronization signal to the cable and inputs noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving unit, and a second bidirectional pin that outputs the vertical synchronization signal to the cable and inputs noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit. A reference clock counter that counts the reference clock and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, thereby counting the reference clock for each line in each frame of the video data. A reference line counter that counts the number of lines of the video data and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, thereby counting the number of lines of each frame of the video data. A detection clock counter that counts the reference clock, resets the count value each time a horizontal synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the first bidirectional pin. A detection line counter that counts the number of lines of the video data, resets the count value each time a vertical synchronization pulse is input, and resets the count value when noise is input from the cable to the video display driving unit via the second bidirectional pin. When the count value by the reference clock counter and the count value by the detection clock counter are different, it is determined that noise is superimposed on the horizontal synchronization signal and an abnormality has occurred in the horizontal synchronization signal. When the count value by the reference line counter and the count value by the detection line counter are different, it is determined that noise is superimposed on the vertical synchronization signal and an abnormality has occurred in the vertical synchronization signal. An abnormality detection unit that generates an abnormality detection flag when it is determined that an abnormality has occurred in at least one of the horizontal synchronization signal and the vertical synchronization signal. A restart control unit that controls the video display unit to restart the video display unit when the abnormality detection unit generates the abnormality detection flag. An imaging device further comprising the above.

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