Dynamic reset latency

Abstract

A method for resetting multiple functional components in a computing device includes determining a number of cycles required to reset the functional components based on a predetermined voltage, and controlling a reset synchronizer to operate for the determined number of cycles, the reset synchronizer controlling a reset network connected to the functional components, wherein the determined number of cycles at a first voltage is different from the determined number of cycles at a second voltage.

Description

Background Art

[0001] Background In a digital logic system, a reset signal clears the values stored by the system's functional components. Performing a reset brings the system to a known state and can be done in response to an error or other event. For example, a reset can be executed in response to an error condition when continued processing activity is not desired or when other error recovery mechanisms have failed. For example, a digital logic system can execute a reset when a command times out and the error recovery scheme also fails.

[0002] When designing a system or implementing a reset response, metrics such as latency, which is the response time of the reset, and entry / exit power, which is the power used during a reset, can be important. Often, latency and entry / exit power are in a trade-off relationship. A reset at a high voltage has a large latency, while a reset at a low voltage has a small latency. Usually, a digital logic system is designed such that all resets take a constant latency regardless of power usage.

Summary of the Invention

[0003] Summary This specification describes methods and systems for dynamically changing the reset latency of a digital logic system. For example, the reset latency can vary depending on the voltage required to reset the system. The desired reset latency can be determined using the target voltage for resetting the digital logic system. By changing the reset latency according to the voltage, the overall latency of the system can be reduced.

[0004] Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages.

[0005] The methods and systems described shorten the latency of resets in digital logic systems. Typically, systems are designed such that all resets have a constant latency regardless of power usage. The methods and systems described enable dynamic reset latency according to power usage, reducing the overall latency of the system. Also, the methods and systems described can use natural scaling, making the latency predictable for further scaling. The methods and systems described advantageously can conserve power. For example, when high latency is not required, power can be conserved in the clock network by reducing toggle cycles, and power can be conserved in the reset network by using natural scaling. The methods and systems described advantageously enable a user to control the latency of the system, for example, by programming reset settings. Also, the security of the device can be enhanced by changing the reset latency, as, for example, a hacker may not know the exact latency of the reset.

[0006] Details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the specification, the drawings, and the claims.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

[0008] Like reference numerals and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION FIG. 1 is a diagram of an example of system 100. System 100 can include a plurality of components 102, 104, 106, 108. Each of components 102, 104, 106, 108 can be any suitable functional component, such as, by way of example, a memory, such as a static random access memory (SRAM), a processing device, or a power controller. This system includes a reset network 110 that shows how a reset signal propagates throughout components 102, 104, 106, 108. This system also includes a clock network 112 through which a clock signal propagates to components 102, 104, 106, 108. Both the reset network 110 and the clock network 112 include delay components, and it takes time for signals to reach components 106, 108 that are far from the signal source. The delay components of the network can cause problems in resetting the components. In some implementations, the reset network can be controlled to operate in an inverted clock phase. The inverted clock phase helps to synchronize the arrival of the signal to the components so that components 102, 104, 106, 108 are reset simultaneously.

[0010] Figure 2 shows a plot demonstrating the advantages of dynamic reset latency. For example, the first plot 200 shows the number of clock cycles required for reset with respect to the target voltage of the reset. In many cases, latency and entry / exit power are in a trade-off relationship. Reset at a high voltage has a large latency, while reset at a low voltage has a small latency. Usually, digital logic systems are designed such that all resets take a constant latency regardless of power consumption. As shown in plot 200, at a lower desired voltage, the latency can be shortened. For example, a reset at 1 volt requires 8 clock cycles, while a reset at a lower voltage requires fewer clock cycles. As the desired voltage decreases, the number of required clock cycles also decreases. The number of clock cycles required for reset can be determined from the target voltage of the reset. For example, the number of clock cycles can be obtained by dividing the average reset latency by the functional clock cycle time. The number of required clock cycles can also be determined by statistically dividing a value close to the average value, such as the median and / or the value obtained by adding sigma to the average value, by the functional clock cycle time. In some implementations, the number of required clock cycles is equal to the upper limit of the reset latency divided by the operating frequency.

[0011] The second plot 202 shows the cost opportunity when using a fixed latency for all resets. For example, at a high voltage such as 1 volt, since the high voltage reset requires more clock cycles, the cost opportunity is low. However, at a low voltage such as 0.54 volts, since the low voltage reset requires fewer clock cycles, the cost opportunity is higher. Since the reset uses more clock cycles than necessary, the cost opportunity increases.

[0012] Figure 3 shows a reset synchronizer 300 connected to system 302. For example, the system can be similar to system 100 of FIG. 1. The reset synchronizer can control the reset network and the clock network of the system. For example, the reset synchronizer can be made to operate for a determined number of cycles. The determined number of cycles determines the reset latency. As shown, the reset synchronizer 300 controls the clock gate 302. The clock gate 302 can control the clock network of the system. In some implementations, the reset synchronizer 300 can be controlled to operate with an inverted clock phase. Inverting the clock phase can help synchronize the reset signal to reach many components of the system simultaneously. In some implementations, the reset synchronizer can be controlled by software. For example, a user can control the reset synchronizer to operate for a desired number of cycles. In other implementations, the reset synchronizer is limited by the design of the system. For example, a desired number of clock cycles can be predetermined for each voltage, and the run synchronizer can be programmed to operate accordingly.

[0013] Figure 4 shows an example of a reset synchronizer 400. For example, the reset synchronizer 400 is connected to a system and, similar to the reset synchronizer 300 in FIG. 3, can control the reset network and the clock network of the system. The reset synchronizer 400 includes a programmable counter 402. In some implementations, the programmable counter can be configured via a software process, for example, via a signal generator 410. In some implementations, the programmable counter can be programmed to operate for a desired number of cycles by applying pre-configured settings stored in the signal generator 410, for example, for various scenarios. For example, different voltage and latency cycles can be useful for designers aiming to improve latency in a specific voltage range. In some implementations, it may be desirable to reduce the number of cycles required at a low voltage. In some implementations, the signal generator can dynamically select the value to apply to the programmable counter, for example, by calculating an optimal value as described above. In other implementations, the counter 402 is limited by the system design. For example, the desired number of clock cycles for each voltage can be determined in advance, and the counter 402 can be programmed to operate accordingly. The reset synchronizer also includes a dynamic voltage frequency scaling (DVFS) decoder 404. The DVFS decoder can process by changing the frequency of the received signal. For example, the DVFS decoder adjusts the number of cycles to release or disable the reset based on the combination of voltage and frequency. The reset synchronizer 400 also includes a reset pipeline slice 406. The reset pipeline slice 406 can ensure that the reset signal is inverted. Operating the reset signal with an inverted phase can help synchronize the reset signal to reach multiple components of the system simultaneously. This is particularly advantageous, for example, for a large number of components when the reset network is large. The reset synchronizer 400 includes a clock inenable 408 and can send a signal to a clock gate. For example, the reset synchronizer 400 can control the clock gate, similar to the reset synchronizer 300 in FIG. 3.

[0014] The reset synchronizer may have many or few components. For example, FIG. 5 shows an example of a reset synchronizer 500 with few components. The reset synchronizer 500 includes a programmable counter 502 that can be similar to the programmable 402 of FIG. 4, and a clock enabler 506 that can be similar to the clock enabler 408 of FIG. 4. The reset synchronizer 500 can be connected to the system and can control the system's reset network and clock network, similar to the reset synchronizer 300 of FIG. 3.

[0015] FIG. 6 shows a set of plots 600 showing reset and clock signals that can be sent to the system. For example, the reset and clock signals can propagate through the reset network and clock network as described above. The clock phase 602 indicates how many clock cycles elapse during the reset process. As shown, a reset signal 604 is received. For example, the reset signal can be received by a reset synchronizer. The inverted reset signal 606 is inverted with respect to the clock phase 602. The inverted reset signal 606 can be transmitted in response to the reception of the reset signal 604. For example, the inverted reset signal 606 can be transmitted by a reset synchronizer. The signal 608 represents the reset signal asserted on the reset network. As shown, the signal 608 operates with an inverted phase similar to the inverted reset signal 606. When the signal 608 reaches the components of the system, the reset is de-asserted. The de-assertion of the reset is indicated by a signal 610 that is the de-assertion cycle. The signal 612 indicates the reset latency. The latency can be any natural number.

[0016] A second plot 614 is illustrated and includes signals 616, 618, 620, 622, 624, 626. Signals 616, 618, 620, 622, 624, 626 can each be similar to signals 602, 604, 606, 608, 610, 612. The second plot 614 shows a reset that is executed with different latencies, assert cycles, and de-assert cycles. The clock phase 616 indicates how many clock cycles elapse during the reset process. As illustrated, a reset signal 618 is received. For example, the reset signal can be received by a reset synchronizer. The inverted reset signal 620 is inverted with respect to the clock phase 616. The inverted reset signal 620 can be transmitted in response to the reception of the reset signal 618. For example, the inverted reset signal 620 can be transmitted by a reset synchronizer. Signal 622 represents a reset signal that is asserted on the reset network. As illustrated, signal 622 operates in an inverted phase similar to the inverted reset signal 620. When signal 622 reaches the components of the system, the reset is de-asserted. The de-assertion of the reset is indicated by signal 624, which is the de-assertion cycle. Signal 626 indicates the latency of the reset. In the plot of the figure, the latency is 3 clock cycles.

[0017] Embodiments and functional operations of the subject matter described in this specification can be implemented in digital electronic circuitry within a computer hardware including the structures disclosed herein and their structural equivalents, or in one or more combinations thereof. Processes and logic flows can also be executed by a special-purpose logic circuit, such as an FPGA or an ASIC, or by a combination of a special-purpose logic circuit and one or more programmed computers.

[0018] In addition to the above-described embodiments, the following embodiments are also innovative. Embodiment 1 is a method for resetting a plurality of functional components within a computing device, the method comprising Determining the number of cycles required to reset a functional component based on a predetermined voltage; Controlling a reset synchronizer to operate for the determined number of cycles, including.

[0019] The reset synchronizer controls a reset network connected to the functional component.

[0020] The determined number of cycles at the first voltage is different from the determined number of cycles at the second voltage.

[0021] Embodiment 2 is the method of Embodiment 1, wherein the number of cycles is derived from a measurable delay component in the reset network.

[0022] Embodiment 3 is the method of Embodiment 2, wherein the number of cycles is the ratio of the delay components.

[0023] Embodiment 4 is the method of any one of Embodiments 1 to 3, further including controlling a reset clock gate to operate for the determined number of cycles. The reset clock gate controls a clock network connected to the functional component.

[0024] Embodiment 5 is the method of Embodiment 4, wherein the reset synchronizer controls the reset clock gate.

[0025] Embodiment 6 is the method of any one of Embodiments 1 to 5, wherein controlling the reset synchronizer includes updating the reset synchronizer via software.

[0026] Embodiment 7 is the method of Embodiment 6, wherein the reset synchronizer controls a reset pipeline stage connected to the reset network.

[0027] Embodiment 8 is any one of Embodiments 1 to 7, and controlling the reset synchronizer includes instructing the reset synchronizer to start in a half cycle of the hold margin.

[0028] Embodiment 9 is the method of Embodiment 8, wherein the reset synchronizer operates with an inverted clock phase.

[0029] Embodiment 10 is a computing device, a plurality of functional components, determining the number of cycles required to reset the functional components based on a predetermined voltage, and a processor configured to control the reset synchronizer to operate for the determined number of cycles.

[0030] The reset synchronizer controls a reset network connected to the functional components.

[0031] The determined number of cycles at the first voltage is different from the determined number of cycles at the second voltage.

[0032] Embodiment 11 is the system of Embodiment 10, wherein the number of cycles is derived from a delay component measurable from the reset network.

[0033] Embodiment 12 is the system of Embodiment 11, wherein the number of cycles is a ratio of delay components.

[0034] Embodiment 13 is the system of any one of Embodiments 10 to 12, wherein the processor is further configured to control a reset clock gate to operate for the determined number of cycles. The reset clock gate controls a clock network connected to the functional components.

[0035] Embodiment 14 is the system of Embodiment 13, wherein the reset synchronizer is configured to control a reset clock gate.

[0036] Embodiment 15 is the system of any one of Embodiments 10 to 14, wherein controlling the reset synchronizer includes updating the reset synchronizer via software.

[0037] Embodiment 16 is the system of Embodiment 15, wherein the reset synchronizer is configured to control a reset pipeline stage connected to a reset network.

[0038] Embodiment 17 is the system of any one of Embodiments 10 to 16, wherein controlling the reset synchronizer includes instructing the reset synchronizer to start at half a cycle of a hold margin.

[0039] Embodiment 18 is the system of Embodiment 17, wherein the reset synchronizer is configured to operate with an inverted clock phase.

[0040] Although many specific details of specific embodiments are described herein, these should not be construed as limitations on the scope of any invention or the scope that can be claimed, but rather should be construed as descriptions of features that may be specific to specific embodiments of a particular invention. The specific features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable partial combination. Furthermore, features are described above as acting in a particular combination and may even initially be claimed as such, but one or more features from the claimed combination may in some cases be excluded from the combination, and the claimed combination may be directed to a partial combination or a variation of a partial combination.

[0041] Similarly, the operations are depicted in the drawings in a particular order, but this should not be construed as requiring that such operations be performed in the particular order shown, or in a sequential order, or that all of the operations shown be performed, in order to obtain a desirable result. Depending on the situation, multitasking or parallel processing may be advantageous. Further, the separation of the various system modules and components in the embodiments described above should not be understood as being necessary in all embodiments, and it should be understood that the program components and systems described may generally be integrated together in a single software product or packaged into multiple software products.

[0042] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the acts recited in the claims may be performed in a different order and still obtain a desirable result. As one example, the steps depicted in the accompanying figures do not necessarily require the particular order or sequential order shown in order to obtain a desirable result. In some cases, multitasking or parallel processing may be advantageous.

Claims

1. A method for resetting a plurality of functional components within a computing device, the method comprising: determining, based on a predetermined voltage, the number of cycles required to reset the functional component; controlling a reset synchronizer to operate for the determined number of cycles, wherein the reset synchronizer controls a reset network connected to the functional component, wherein the determined number of cycles at a first voltage is different from the determined number of cycles at a second voltage.

2. The method according to claim 1, wherein the number of cycles is derived from a measurable delay component in the reset network.

3. The method according to claim 2, wherein the number of cycles is a ratio of the delay components.

4. The method according to any one of claims 1 to 3, further comprising controlling a reset clock gate to operate for the determined number of cycles, wherein the reset clock gate controls a clock network connected to the functional component.

5. The method according to claim 4, wherein the reset synchronizer controls the reset clock gate.

6. The method according to any one of claims 1 to 3, wherein controlling the reset synchronizer includes updating the reset synchronizer via software.

7. The method according to claim 6, wherein the reset synchronizer controls a reset pipeline stage connected to the reset network.

8. The method according to any one of claims 1 to 3, wherein controlling the reset synchronizer includes instructing the reset synchronizer to start at a half cycle of a hold margin.

9. The method according to claim 8, wherein the reset synchronizer operates with an inverted clock phase.

10. A plurality of functional components, and a processor configured to determine, based on a predetermined voltage, the number of cycles required to reset the functional component, and to control a reset synchronizer to operate for the determined number of cycles. ​ The reset synchronizer controls a reset network connected to the functional component, A system in which the determined number of cycles at a first voltage is different from the determined number of cycles at a second voltage. **Claim 11** The system according to claim 10, wherein the number of cycles is derived from a delay component measurable from the reset network. **Claim 12** The system according to claim 11, wherein the number of cycles is a ratio of the delay components. **Claim 13** The processor is further configured to control a reset clock gate to operate for only the determined number of cycles, The system according to any one of claims 10 to 12, wherein the reset clock gate controls a clock network connected to the functional component. **Claim 14** The system according to claim 13, wherein the reset synchronizer is configured to control the reset clock gate. **Claim 15** The system according to any one of claims 10 to 12, wherein controlling the reset synchronizer includes updating the reset synchronizer via software. **Claim 16** The system according to claim 15, wherein the reset synchronizer is configured to control a reset pipeline stage connected to the reset network. **Claim 17** The system according to any one of claims 10 to 12, wherein controlling the reset synchronizer includes instructing the reset synchronizer to start at half a cycle of a hold margin. **Claim 18** The system according to claim 17, wherein the reset synchronizer is configured to operate with an inverted clock phase. **Claim 19** The method according to any one of claims 1 to 3, wherein the required number of cycles is determined such that the lower the voltage, the fewer the determined number of cycles. **Claim 20** The system according to any one of claims 10 to 12, wherein the processor determines the required number of cycles such that the lower the voltage, the fewer the determined number of cycles.

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