Low-Resistance Composite Silicon-Based Electrodes

Abstract

A silicon-based electrode forms an interface between a pair of layers: 1. a thin semi-dielectric layer of a lithium (Li) compound, such as lithium fluoride (LiF), disposed on and attached to the electrode surface of the silicon-based electrode; and 2. a molten, ion-concentrated conductive layer of a lithium-containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to create devices such as energy storage devices like batteries. The low resistance of the interface can reduce energy loss and heat generation in the device.

Description

Technical Field

[0001] The present invention relates to an interface with a silicon-based layer having reduced interfacial resistance / impedance. More specifically, the present invention relates to a composite lithium including a conductive layer and a structural reinforcement layer that interface with a silicon-based layer to reduce interfacial resistance and charge transfer resistance in an energy storage device.

Background Art

[0002] Integrating an energy storage device such as a battery into a microprocessor or a memory chip is an important requirement for IoT (Internet of Things) devices. In addition to IoT applications, new applications integrating on-board next-generation energy storage devices include mobile devices, communication devices, remote power, environmental, biological, and social autonomous functional machines such as drones, vehicles, robots, and sensors, smart dust, or biosensory / drug delivery devices, or combinations thereof.

[0003] Furthermore, it is necessary to scale while integrating electrochemically active materials and electrochemical processes into conventional applications such as electric vehicles, mobile computing and communication devices, and grid storage.

[0004] As the miniaturization of human-controlled devices and autonomous devices progresses, the requirement for the total energy consumption from the energy source supplying power to the electronic device decreases. However, although the power consumption of these integrated devices is expected to be less than 1 watt, the volume of the device also decreases due to miniaturization, so the energy density and power density per unit volume will continue to increase in the miniaturized device.

[0005] To increase the energy density and power density per unit volume, due to the very high theoretical specific capacity of lithium (Li) metal (~3860 mAh / g), lithium electrode materials are incorporated into the entire cell structure of semi-solid or all-solid energy storage devices. In many applications, since lithium-based energy storage devices are incorporated into, interface with, or both, complementary metal-oxide-semiconductor (CMOS) circuits, one or more lithium-based components will interface with a silicon (Si) layer. Also, it is assumed that high-energy / high-power density storage devices manufactured on a miniaturized scale and mass-producible can be directly applied to scalable applications such as mobile electronics, electric vehicles, and renewable grid storage.

[0006] In particular, in high-energy density and high-power density storage devices, a low-resistance interface between the silicon-based layer and the lithium-based component is required. Such a low-resistance interface is necessary for reducing power loss, improving efficiency, or preventing degradation of the silicon active electrode-containing device due to volume expansion, overheating, or Li dendrite formation in the device, or a combination thereof.

Summary of the Invention

[0007] According to one embodiment of the present invention, a composite electrode including a silicon-based electrode (layer pair) combining two layers is disclosed. The layer pair includes 1. a thin semi-dielectric lithium conductive layer composed of a lithium (Li) compound, such as lithium fluoride, LiF, disposed on and adhering to the electrode surface of the silicon-based electrode, and 2. a molten lithium ion-concentrated conductive layer (lithium salt layer) of a lithium-containing salt disposed on the semi-dielectric layer. The lithium salt layer has high conductivity with respect to lithium ions (Li + ).

[0008] One or more device layers may be disposed on the layer pair. Non-limiting examples of device layers include one or more cathode electrodes, one or more polymer solid electrolyte (SPE) layers or liquid electrolyte layers, one or more anode layers, or one or more other internal battery component layers, or combinations thereof.

[0009] The layer pair forms an interface with surprisingly low impedance / resistance between the device layer and the silicon-based electrode because it has the effect of reducing the charge transfer resistance across the silicon interface and the electrolyte / layer pair interface. This layer pair is used in devices having a silicon-based electrode, including microresistors, next-generation ion-based analog memory devices, energy storage devices such as lithium-ion batteries, and the like.

[0010] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings, which are briefly described herein. The figures illustrate various devices, structures, and process steps related to embodiments of the present invention.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Embodiments of the present invention are not limited to the exemplary methods, apparatuses, structures, systems, and devices disclosed herein. Instead, it will be understood that the present disclosure is more broadly applicable to other alternative and broader methods, apparatuses, structures, systems, and devices that will be apparent to those skilled in the art given the present disclosure.

[0013] Furthermore, it should be understood that the various layers, structures, or regions, or combinations thereof shown in the accompanying drawings are not drawn to scale, and that one or more layers, structures, or regions, or combinations thereof of a generally used type may not be explicitly shown in a given drawing. This does not mean that layers, structures, or regions, or combinations thereof that are not explicitly shown are omitted from the actual device.

[0014] Furthermore, when not necessarily focusing on elements with omitted descriptions, certain elements may be omitted from the figures for clarification or simplification or both. Furthermore, the same or similar reference numerals used throughout the drawings are used to indicate the same or similar features, elements, or structures, and thus, detailed descriptions of the same or similar features, elements, or structures will not be repeated for each of the drawings.

[0015] The semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention can include, but are not limited to, semiconductors, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., cells and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, neural networks, etc. Systems and hardware incorporating the present invention into semiconductor devices and structures are contemplated as embodiments of the present invention.

[0016] As used herein, "height" refers to the vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional or elevation view measured from the bottom surface to the top surface of the element, or measured with respect to the surface on which the element is disposed, or both.

[0017] Conversely, "depth" refers to the vertical dimension of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional or elevation view measured from the top surface to the bottom surface of the element. Terms such as "thick", "thickness", "thin", or derivatives thereof may be used in place of "height".

[0018] As used herein, "lateral", "lateral side", "side", and "lateral surface" refer to the sides of an element (e.g., a layer, an opening, etc.), such as the left or right side in a drawing.

[0019] As used herein, "width" or "length" refers to the size of an element in a drawing measured from one side of the element (e.g., a layer, a groove, a hole, an opening, etc.) to the opposite surface. Terms such as "thick", "thickness", "thin", or derivatives thereof may be used in place of "width" or "length".

[0020] As used herein, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods as oriented in the depicted drawings. For example, as used herein, "vertical" refers to a direction perpendicular to the upper surface of a substrate in an elevation view, and "horizontal" refers to a direction parallel to the upper surface of a substrate in an elevation view.

[0021] As used herein, unless otherwise specified, terms such as "on", "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element is present over a second element and intervening elements may be present between the first and second elements. As used herein, unless otherwise specified, the terms "on", "overlying", "atop", "on top", "positioned on", or "positioned atop", "disposed on", or the term "directly" when used in connection with the terms "in contact" or "direct contact" mean that the first and second elements are connected without intervening elements therebetween, such as an intermediate conductive layer, insulating layer, or semiconductor layer.

[0022] It is understood that these terms may be affected by the orientation of the device being described. For example, if the device is rotated upside down, the meaning of these descriptions may change, but the description remains valid as it describes the relative relationships between the features of the invention.

[0023] Reference is now made to the figures.

[0024] FIG. 1 is a cross-sectional view showing an embodiment of a symmetric cell 100 including two layer pairs (150 / 150U) symmetrically disposed between two silicon-based electrodes 105 / 105U and around a separator layer 115. This symmetric cell 100 is used for electrochemical impedance spectroscopy (EIS) analysis described hereinafter.

[0025] Each of the layer pairs 150 / 150U consists of a semi - dielectric layer 111 / 111U and a molten ion - conductive layer 112 / 112U. Each of the molten ion - conductive layers 112 / 112U has an interface 140 / 140U with the respective semi - dielectric layer 111 / 111U. Each of the semi - dielectric layers 111 / 111U has a semi - dielectric layer thickness 121, and each of the molten ion - conductive layers 112 / 112U has a molten ion - conductive layer thickness 122.

[0026] Each silicon - based electrode 105 / 105U combines with the respective layer pair 150 / 150U to form a composite electrode 105 / 150.

[0027] The separator layer 115 electrically insulates the layer pair 150 and the silicon - based electrode 110 on one side of the separator layer 115 from the layer pair 150U and the silicon - based electrode 110U on the other side of the separator layer 115. That is, the separator layer 115 substantially prevents electrons from flowing between the layer pairs 150 / 150U and the silicon - based electrodes 110 / 110U on the opposite sides of the separator layer 115. Thereby, an electrical short - circuit of the cell 100 is prevented. However, the separator layer 115 allows the passage of ions, for example, lithium ions (Li+). Therefore, the separator layer 115 allows the flow of ion current while preventing most of the electron current.

[0028] A polymer solid electrolyte (SPE) layer 114 is included. In this embodiment 100, the separator layer 115 divides the polymer solid electrolyte (SPE) layer 114 into an upper SPE layer 114B above the separator layer 115 and a lower SPE layer 114A below the separator layer 115. The SPE layers 114A / 114B are also saturated through the separator layer 115.

[0029] In some embodiments, the electrolyte layer 114 (e.g., 114A / 114B) is a garnet / polymer electrolyte composite (e.g., Li 6.5 La3Zr 1.5 Ta 0.5 O 12It consists of a (PEO composite) and functions as both the solid polymer electrolyte 114 and the separator 115. In other embodiments, when the electrolyte is harder than Li metal (e.g., sputtered LiPON), the electrolyte functions as both the separator and the electrolyte, so a separator is not necessary.

[0030] In this Figure 1, the reference number "U" indicates that it is located relatively above (or on the opposite side of) the separator layer 115 with respect to the layer without the reference number "U", and is symmetric about the separator layer 115. In the following discussion, when explaining layers that are common and symmetric without loss of generality, the "U" in the general numerical notation can be omitted for clarification.

[0031] The layer pair 150 has a pair of upper surfaces 151 (the side surfaces of the separator 115) and a pair of bottom surfaces 152 (the side surfaces of the electrode 152 / 152U). The layer pair 150 is directly disposed on the silicon-based electrode 110 such that the pair of bottom surfaces 152 is in physical and electrical direct contact with the electrode facing surface 131 (the semi-dielectric layer 111 side) of the silicon-based electrode 110. The electrode interfaces 131 / 152 (131U / 152U respectively) are where the pair of bottom surfaces 152 (the side surfaces of the electrode 152 / 152U) and the electrode facing surfaces 131 / 131U are in direct contact respectively.

[0032] In some embodiments, the silicon-based electrodes 110 / 110U are respectively disposed on the electrode contacts 105 / 105U. The silicon-based electrode 110 has a silicon-based electrode surface 132 / 132U that is in electrical contact with the electrode contacts 105 / 105U, and the electrode facing surfaces 131 / 131U are in electrical contact with the semi-dielectric layer 111 pair of bottom surfaces 152 (or the semi-dielectric layer bottom surface 152, i.e., the electrode contact 105 side) at the electrode interfaces 131 / 152 (131U / 151U respectively). In some embodiments, the silicon-based electrode 110 is a disk with a diameter of about 15.5 millimeters (mm) and the area of the electrode facing surface 131 is about 1.88 cm 2 which is a disk.

[0033] Any electrode contact 105 / 105U is made of a conductive material, such as a metal like copper (Cu), titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al), gold (Au), tungsten (W), or titanium nitride (TiN). The electrode contact 105 / 105U may include a single layer of a conductive metal, such as a conductive metal nitride, or a material stack including at least two different conductive metals or conductive metal nitrides or both. In one example, the electrode contact 105 can include a stack (not shown) of titanium (Ti), platinum (Pt), and titanium (Ti) from bottom to top. The electrode contact 105 can be formed using deposition techniques well known to those skilled in the art.

[0034] If any, the electrode contact 105 may be mechanically or chemically attached, adhered, or bonded to the silicon electrode surface 132 of the silicon-based electrode 110.

[0035] The silicon-based electrode 110 / 110U may include silicon and / or any other material having semiconductor material or semiconductor characteristics. In one embodiment, the silicon-based electrode 110 / 110U is a bulk semiconductor substrate. "Bulk" means that the base substrate is entirely composed of at least one semiconductor material, such as crystalline silicon. In one example, the silicon-based electrode 110 / 110U may be composed of silicon, which may be entirely single crystal. In some embodiments, the bulk semiconductor may include a multilayer semiconductor material stack including at least two different semiconductor materials, one of which is silicon. In one example, the multilayer semiconductor material stack may include a stack of Si and a silicon germanium alloy in any order. In another embodiment, the multilayer semiconductor material may include a stack of Si and one or more silicon-based alloys such as silicon germanium or carbon-doped silicon-based alloys in any order.

[0036] According to the present application, the silicon electrode 110 is composed of a material containing silicon, that is, the silicon electrode 110 is silicon-based. The term "silicon-based" is used throughout the present application to indicate a material that contains at least silicon and has properties as a semiconductor material. Examples of silicon-based materials that can be employed as the silicon-based electrode 110 include silicon (Si), silicon-germanium alloy, or carbon-doped silicon-based alloy. Typically, the silicon-based electrode 110 is composed of only silicon (Si).

[0037] The silicon-based material provided in the silicon-based electrode 110 may be an amorphous semiconductor material or a crystalline semiconductor material. The silicon-based electrode 110 may be entirely non-porous, entirely porous, or may include some regions that are non-porous and other regions that are porous. The silicon-containing material may be undoped, doped, or may include some regions that are doped and other regions that are undoped. The dopant may be a p-type dopant or an n-type dopant.

[0038] "p-type" refers to the addition of impurities to an intrinsic semiconductor that creates a deficiency of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, that is, impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of the p-type dopant in the silicon-containing material providing the silicon-based electrode 110 can range from 1E16 atoms / cm 3 ~3E20 atoms / cm 3 up to.

[0039] "n-type" refers to the addition of impurities that give free electrons to an intrinsic semiconductor. In a silicon-containing semiconductor material, examples of n-type dopants, that is, impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The concentration of the n-type dopant in the silicon-containing material of the silicon-based electrode 110 / 110U is 1E16 atoms / cm3 ~1E21 atoms / cm 3 can be up to.

[0040] Exemplary examples of silicon-containing materials that can be used as the silicon-based electrode 110 / 110U include non-porous silicon, partially porous crystalline silicon, single-crystalline non-porous silicon, crystalline silicon, low-resistance doped crystalline silicon, boron-doped crystalline silicon, or boron-doped crystalline porous silicon. In one embodiment, as the silicon-based electrode 110, boron-doped crystalline silicon having a boron dopant concentration of 1×10 19 atoms / cm 3 ~3×10 20 atoms / cm 3 is used.

[0041] The term "low-resistance doped crystalline silicon" refers to a silicon-based electrode 110 that is a unit structure (i.e., a monolithic structure) and includes a non-porous region and a porous region, as defined in U.S. Serial No. 16 / 026,461, filed July 3, 2018, entitled "Battery Structure with Anode Structure Containing a Porous Region and Method of Operation", the entire content and disclosure of which are hereby incorporated by reference.

[0042] The low-resistance doped crystalline silicon that can be used as the silicon-based electrode 110 / 110U can be manufactured by immersing a substrate including at least an upper region of a p-type silicon material washed using a standard organic cleaning process in a solution of concentrated HF (49%) and using an anodization process in which platinum is the anode and the substrate is the cathode to pass a current. The anodization process is carried out with a constant current source operating at a current density of 0.05 mA / cm 2 ~150 mA / cm 2 where mA is milliamperes. In some examples, the current density is 1 mA / cm 2 , 2 mA / cm 2 , 5 mA / cm 2 , 50 mA / cm2 or 100 mA / cm 2 is. In a preferred embodiment, the current density is 1 mA / cm 2 ~10 mA / cm 2 is. The current density can be applied for 1 second to 5 hours. In some examples, the current density may be applied for 5 seconds, 30 seconds, 20 minutes, 1 hour, or 3 hours. In one embodiment, the current density is from 10 seconds to 4800 seconds, specifically 10 19 atoms / cm 3 It may be applied for doping levels in the range of. Anodization is typically carried out at a nominal room temperature of (20 °C) to (30 °C), or at a temperature slightly above room temperature. After anodization, the structure is typically washed with deionized water and then dried.

[0043] The semi-dielectric layer 111 (111U) is a thin layer 121 that adheres well to the silicon-based electrodes 110 (110U respectively) at the electrode facing surface 131, the electrode interface 131 / 151 (131U / 151 respectively). The thickness 121 of the semi-dielectric layer 111 involves a trade-off. Since the semi-dielectric layer 111 is an electrical insulator, usually by using a dielectric material in contact with the electrode facing surface 131, the resistance / impedance between the electrode interface 131 / 152 (131U / 152U), and between the silicon-based electrode 110 and the molten ion conductive layer 112 will be increased. However, by keeping the semi-dielectric layer 111 very thin at 121, the resistance at this electrode interface 131 / 152 is reduced. Nevertheless, the thickness 121 of the semi-dielectric layer 111 needs to be large enough to enable strong adhesion to the silicon-based electrode 110 and maintain uniform contact across the entire electrode facing surface 131. In some embodiments, the thickness 121 of the semi-dielectric layer 111 is between 15 nanometers (nm) and 30 (nm). In other embodiments, the thickness 121 is between 15 nm and 23 nm, and in other embodiments, the thickness 121 is between 18 nm and 23 nm.

[0044] In some embodiments, the semi-dielectric layer 111 is made of a dielectric containing lithium. In some embodiments, the semi-dielectric layer 111 is made of lithium fluoride (LiF). The lithium fluoride semi-dielectric layer 111 forms an amorphous lithium fluoride layer 111 directly disposed on the electrode facing surface 131 of the silicon-based electrode 110 and can be deposited on the silicon-based electrode 110 by evaporating it onto the electrode facing surface 131 that forms the electrode interface 131 / 152.

[0045] The semi-dielectric layer 111 can be made of other materials including, but not limited to, titanium dioxide, niobium oxide, rubidium oxide, tungsten oxide, aluminum oxide, zinc oxide, zirconium oxide, and any of the aforementioned lithium compounds.

[0046] Evaporation includes providing a material of lithium fluoride. Next, the source material is evaporated in a vacuum. The vacuum enables the vapor particles of lithium fluoride, LiF, to move to the silicon-based electrode 110 where the vapor particles condense and return to the solid state. Evaporation includes an evaporation apparatus including at least a vacuum pump and an energy source for evaporating the source material to be deposited, such as LiF. The evaporation process includes, but is not limited to, electron beam evaporation, thermal evaporation using a Ni, Ta, Mo, or W boat, or radio frequency (RF) sputtering. The pressure during deposition is usually controlled between 10E-8 and 10E-4 Torr, and the temperature is controlled between 875°C and 1180°C. The thickness 121 of the semi-dielectric layer 111 can be controlled by pre-measuring the mass of the evaporated material or through a crystal microbalance rate monitor.

[0047] In some embodiments, a crystalline boron-doped (at the defined concentration) silicon disk 110 with a diameter of 5 / 8 inch was etched with hydrofluoric acid at a concentration of 4% to 10% for 25 seconds to 60 seconds to remove the native oxide layer. These silicon disks were then immediately attached to the steel plate 105 and vacuum-encapsulated as target objects in an evaporation system within a nitrogen environment glove box. A layer of lithium fluoride, LiF, was thermally evaporated using a pre-measured amount of LiF between 3.5 and 6.5 milligrams (mg) and deposited on a conductive powder sample holder attached to the user-controlled power supply of the evaporation system. The LiF powder was resistively heated in a tungsten boat and completely evaporated by applying a current of 20 amperes to 50 amperes to heat the boat to 1100 °C or higher under a vacuum of less than 2 × 10 -5 torr.

[0048] Thereafter, the molten ion conductive layer 112 was deposited on the semi-dielectric layer 111 to complete the formation of the layer pair 150. The deposition of the molten ion conductive layer 112 forms an interface 140 between the semi-dielectric layer 111 and the molten ion conductive layer 112. The upper interface 151 is the surface of the molten ion conductive layer 112 facing the interface 140.

[0049] The molten ion conductive layer 112 is made of a material having high conductivity for ions (particularly high conductivity for lithium ions (Li+)). In some embodiments, the molten ion conductive layer 112 is made of a lithium-containing salt. In some embodiments, the molten ion conductive layer 112 is made of one or more of the following lithium-containing salts: lithium hexafluorophosphate, lithium perchlorate, lithium trifluoromethanesulfonate, lithium fluoride, LiBF4, LiBF6, lithium chloride, lithium phosphate compounds, lithium bromide compounds, lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), lithium difluoro(oxalato)borate (LiDFOB), or lithium bis(oxalato)borate (LiBOB).

[0050] In some embodiments, the molten ion conductive layer 112 consists of bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0051] The molten ion conductive layer 112 can be formed by depositing a layer of a lithium-containing salt as defined above on the semi-dielectric layer 111. The deposition of the lithium-containing salt layer may include any conventional deposition technique, such as drop coating followed by using a doctor blade to provide a homogeneous and uniform layer of the lithium-containing salt on the surface of the semi-dielectric layer 111. Next, the lithium-containing salt layer is heated to a temperature that provides a molten lithium-containing salt. In some embodiments of the present application, the heating can be carried out at a temperature exceeding 350 degrees Celsius (°C) to provide molten lithium ions. The heating can be carried out, for example, in an inert atmosphere such as helium (He), neon (Ne), argon (Ar), nitrogen (N2), or a combination thereof. As an example, the heating is carried out at 415 °C in a nitrogen glove box. The molten salt increased the adhesion (wetting) of high-concentration mobile lithium on the semi-dielectric layer 111 that provides a uniform layer thickness 122. Next, the molten lithium-containing salt is cooled to form a molten ion conductive layer 112 consisting of the molten lithium-containing salt. The cooling is carried out from the heating temperature to the nominal room temperature and can be in the range of 15 °C to 25 °C or lower. When cooled, the molten ion conductive layer 112 is a solid continuous layer formed on the semi-dielectric layer 111 at the interface 140.

[0052] In some embodiments, the molten ion conductive layer 112 can have a thickness 122 between 1 nm and 500 nm. In other embodiments, the molten ion conductive layer 112 can have a thickness 122 between 1 nm and 50 nm. Other thicknesses are envisioned.

[0053] If on the opposite side of the separator layer 115, the order of layer deposition may be reversed.

[0054] FIG. 2 is a cross-sectional view of an alternative embodiment 200 of a single layer pair 150 disposed on a silicon-based electrode 110 having one or more device layers 175 disposed on layer pair 150.

[0055] A polymer solid electrolyte (SPE) layer 114 is included. In this alternative embodiment 200, the separator layer 115 divides the polymer solid electrolyte (SPE) layer 114 into an upper SPE layer 114B above the separator layer 115 and a lower SPE layer 114A below the separator layer 115.

[0056] In some embodiments, the electrolyte layer 114 comprises a garnet / polymer electrolyte composite (e.g., Li 6.5 La3Zr 1.5 Ta 0.5 O 12 / PEO composite) and functions as both the solid polymer electrolyte 114 and the separator 115. In other embodiments, when the electrolyte is harder than Li metal (e.g., sputtered LiPON), the electrolyte functions as both the separator and the electrolyte, so a separator is not required.

[0057] In FIG. 2, the layers 175 (e.g., 114 (114A and 114B), 115, 116, 118, 120) formed on the opposing surface 151 are referred to as device layers, typically 175. The device layer 175 can take a plurality of forms and can be in a plurality of combinations depending on the structure of the device / embodiment 100. As will be described later, the combination of the silicon-based electrode 110, the layer pair 150, and one or more device layers 175 will reduce the resistance / impedance throughout the structure due to the reduction of resistance / impedance at the electrode interface 131 / 152 between the pair layer 150 and the silicon-based electrode 110.

[0058] In one embodiment of the battery, the electrolyte layer 114 is disposed on the opposing surface 151 as the device layer 175. The electrolyte layer 114 can be any known electrolyte used in prior art batteries. In one embodiment, the electrolyte layer 114 consists of a solid electrolyte or a polymer solid electrolyte (SPE).

[0059] Non-limiting embodiments of the solid polymer electrolyte layer (SPE) 114 include any solid polymer material capable of conducting Li ions. In one embodiment, the solid polymer electrolyte layer 114 consists of a mixture of a polymeric structural host material, a Li-conductive / plasticizing material, and a lithium-containing salt.

[0060] In such embodiments, the mixture includes 35 wt% to 50 wt% of the polymeric structural host material, 15 wt% to 25 wt% of the conductive / plasticizing material, and 30 wt% to 45 wt% of the lithium-containing salt. In some embodiments, the polymeric host material and the conductive / plasticizing material are dissolved in anhydrous acetonitrile having a solid:solvent ratio between 1:2 and 1:10, and one preferred ratio is 1:3. This mixture can be made using techniques well known to those skilled in the art.

[0061] Exemplifications of the polymeric structural host material include at least one of poly(ethylene oxide) (PEO), poly(propylene oxide) (PPO), poly(dimethylsiloxane), poly(vinyl chloride), or polycaprolactone.

[0062] Exemplifications of the Li-conductive / plasticizing material include at least one of succinonitrile (SN), poly(ethylene glycol) (PEG), an aprotic organic solvent, or dimethyl sulfoxide (DMSO), or a combination thereof.

[0063] Exemplary lithium-containing salts that can be used in the formation of the solid polymer electrolyte layer include, but are not limited to, lithium hexafluorophosphate, lithium perchlorate, lithium trifluoromethanesulfonate, lithium fluoride, LiBF4, lithium chloride, lithium phosphate compounds, lithium bromide compounds, lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), lithium difluoro(oxalato)borate (LiDFOB) or lithium bis(oxalato)borate (LiBOB).

[0064] The lithium-containing salt present in the polymer solid electrolyte (SPE) layer 114 may be the same as or different from the lithium-containing salt used when providing the molten ion conductive layer 112. Typically, the lithium-containing salt used in the polymer solid electrolyte layer 114 is the same as the lithium-containing salt used in the molten ion conductive layer 112. In one embodiment, the lithium-containing salts used in the polymer solid electrolyte layer 114 and the molten ion conductive layer 112 are both composed of lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0065] In an exemplary embodiment, the silicon-based electrode 110 is made of boron-doped crystalline silicon, the semi-dielectric layer 111 is made of LiF, the molten ion conductive layer 112 is made of bis(trifluoromethanesulfonyl)imide (LiTFSI), and the polymer solid electrolyte layer 114 is made of a mixture of polycaprolactone, succinonitrile (SN), and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0066] The polymer solid electrolyte layer 114 can be formed using deposition processes such as drop casting, spin coating, doctor blading, etc.

[0067] In some embodiments, an optional interface layer 116 can be formed on the polymer solid electrolyte layer 114. The optional interface layer 116 can have a thickness of 1 nm to 50 nm. In some embodiments, the interface layer 116 is omitted. When present, the interface layer 116 forms an interface 116 between the polymer solid electrolyte layer 114 and the counter electrode 118.

[0068] In some embodiments, the interface layer 116 is a solid electrolyte interface phase (SEI) layer that develops at the cathode / electrolyte interface during the electrochemical cycle. The interface layer 116 is conductive to Li ions but not conductive to electrons.

[0069] In some embodiments (typically used when the counter electrode 118 is made of the same or a similar silicon-containing material as the material making up the silicon-based electrode 110), the interfacial layer 116 consists of a lithium-containing salt. The lithium-containing salt used to form the interfacial layer 116 can be one or more of the lithium-containing salts used in the molten ion conductive layer 112 described above. In one embodiment, the interfacial layer 116 and the molten ion conductive layer 112 consist of the same lithium-containing salt. In an alternative embodiment, the lithium-containing salt forming the molten ion conductive layer 112 and the interfacial layer 116 are different materials. In one embodiment, both the molten ion conductive layer 112 and the interfacial layer 116 consist of lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0070] In some embodiments (typically used when the counter electrode 118 is made of the same or a similar silicon-containing material as the material making up the silicon-based electrode 110), the interfacial layer 116 consists of a lithium-containing salt mixed within a polymer. In one embodiment, the interfacial layer consists of polyaniline mixed with a LiTFSI lithium salt.

[0071] In some embodiments (typically used when the counter electrode 118 consists of a cathode material or an electrode material), the interfacial layer 116 consists of an interfacial additive material such as, for example, a carbon (C)-based material, gold (Au), or a dielectric oxide material such as aluminum oxide. The material forming the interfacial layer 116 can be a mixture with any combination of not only electrically insulating components but also Li-ion conductive components such as, but not limited to, LiNbO3, LiZrO2, Li4SiO4, or Li3PO4.

[0072] Depending on the material of the selected interfacial layer 116, the interfacial layer 116 can be formed using a deposition process including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), evaporation, electroplating, drop casting, spin coating, or atomic layer deposition (ALD).

[0073] In an embodiment where the silicon-based electrode 110 has an electrode polarity, the counter electrode 118 has a counter electrode polarity opposite to the electrode polarity. In some embodiments of the present application, the silicon-based electrode 110 may be an anode electrode, and the counter electrode 118 may be a cathode electrode. In other embodiments of the present application, the silicon-based electrode 110 may be a cathode electrode, while the counter electrode 118 may be an anode electrode.

[0074] The counter electrode 118 can be formed on the polymer solid electrolyte (SPE) layer 114 or, optionally, on the interface layer 116. The counter electrode 118 can function as an anode electrode or a cathode electrode, but typically, the counter electrode 1 18 is a lithium-hosting electrode, for example, a cathode.

[0075] In an embodiment where the silicon-based electrode 110 is an anode electrode, the counter electrode 118 is a cathode electrode. In such an embodiment, the cathode electrode (i.e., the counter electrode 118) may also be made of a silicon-based material. When the counter electrode 118 is made of a silicon-based material, the material of the counter electrode 118 may be compositionally the same as or different from the material used to make the silicon-based electrode 110, and one of the materials of the silicon-based electrode 110 described above can be used.

[0076] In some embodiments, when the counter electrode 118 functions as the cathode electrode 118, the material for making the cathode electrode 118 is a lithium-containing cathode material. The lithium-containing cathode material may include, for example, a lithium-containing material such as a lithium-based mixed oxide. Examples of lithium-based mixed oxides that can be employed as the lithium-containing cathode material include lithium cobalt oxide (LiCoO2), lithium nickel oxide (LiNiO2), lithium manganate (LiMn2O4), lithium manganese oxyfluoride (Li2MnO2F), lithium vanadium pentoxide (LiV2O5), nickel manganese cobalt lithium (NMC), nickel cobalt aluminum oxide (NCA), any combination of sulfur-based materials and structural support elements such as lithium and iron, or lithium iron phosphate (LiFePO4), among others, but are not limited thereto.

[0077] In some embodiments, when, for example, a polymer or a liquid electrolyte 114 is used, the layer of the lithium-containing cathode (counter electrode 118) material may be formed using a deposition process such as slurry casting, lamination and calendaring, or electroplating. In one embodiment, the layer of the lithium-containing cathode material is formed by sputtering when using a non-liquid-based electrolyte using any conventional precursor raw material or combination of precursor raw materials. In one example, when forming a lithium cobalt mixed oxide, a lithium precursor raw material and a cobalt precursor raw material are employed.

[0078] Sputtering can be carried out in a mixture of an inert gas and oxygen. In such embodiments, the oxygen content of the inert gas / oxygen mixture can be from 0.1 atomic percent to 70 atomic percent, and the remainder of the mixture contains an inert gas. Examples of inert gases that can be used include argon, helium, neon, nitrogen, or any combination thereof in combination with oxygen.

[0079] In some embodiments, the layer of the lithium-containing cathode 118 material may be formed by slurry casting that can include a mixture of electrochemically active [cathode material, electronically conductive material (e.g., carbon-based material)] and inert (binder material) components. The thickness of such a layer can range from 5 micrometers to 500 micrometers. These slurries can also have electrolyte components in the mixture along with lithium-based salts.

[0080] In an embodiment where the silicon-based electrode 110 is the cathode electrode, the counter electrode 118 is the anode electrode. In such an embodiment, the anode electrode (i.e., the counter electrode 118) may be a second silicon-based electrode. This second silicon-based electrode 118 may be compositionally the same as or different from the silicon-based electrode 110.

[0081] In some embodiments, the anode electrode (i.e., the counter electrode 118) includes a lithium ion source material or a lithium intercalation active material. Examples of materials that can be used as the anode electrode 118 include lithium metal, such as Li x lithium-based alloys such as Si, prelithiated carbon-based materials, prelithiated silicon-based materials, or lithium-based mixed oxides such as lithium titanate (Li2TiO3), but are not limited thereto. The anode electrode can be formed using deposition techniques well known to those skilled in the art. In some embodiments, the anode electrode can be formed by sputtering.

[0082] The current collector 120 or the contact 120 of the counter electrode 118 may be formed on the counter electrode 118. The current collector 120 / counter electrode contact 120 is made of one or more conductive materials that are the same as or similar to the material making the electrode contact 105. In some embodiments, the counter electrode contact 120 can be formed using techniques well known to those skilled in the art.

[0083] In the embodiment shown in FIG. 2, the polymer solid electrolyte layer has a lower region 1 14A and an upper region 1 14B, and a separator (or dielectric region) 115 exists between the lower region 114A and the upper region 114B. The separator (or dielectric region) 115 may consist of at least one of polyacrylonitrile (PAN), a polyethylene oxide (PEO)-based copolymer matrix or structural film, a quaternized polysulfone film, electrospun polyvinylidene fluoride, or a methyl methacrylate (MMA) / polyethylene (PE) composite.

[0084] The separator layer 115 electrically insulates the silicon-based electrode 110 from the counter electrode 118. That is, the separator layer 115 substantially prevents electrons from flowing between the silicon-based electrode 110 and the counter electrode 118. However, the separator layer 115 allows the passage of ions, such as lithium ions (Li+). Thus, the separator layer 115 allows an ion current to flow while substantially preventing any electron current. In some embodiments where a liquid electrolyte 116 is employed, the separator material may consist of a liquid-permeable membrane, such as Nafion.

[0085] In some embodiments, the cell 200 can be used as a microresistor. For example, when lithium is intercalated into the electrode, the resistance of the cell changes. By controlling the amount of lithium transferred to the electrode 110 and keeping that amount constant, the cell 200 has a specific resistance or resistance state. By creating or changing the resistance state of the cell, the device can be used as a resistance-based computing device in which memory is stored as the resistance state held within the cell. In some embodiments, the variable resistance state cell has a cathode 118, an electrolyte 114, and a host anode (e.g., silicon, carbon) 110.

[0086] Figure 3 is a micrograph 300 showing a thin semi - dielectric layer 111 composed of a lithium (Li) compound, such as lithium fluoride, LiF, disposed and adhered on the electrode facing surface 131 of the silicon - based electrode 110. The thickness 121 of the semi - dielectric layer 111 is 23.29 nm. In this micrograph 300, the molten ion - conductive layer 112 is not shown and the layer pair 150 is not formed.

[0087] In micrograph 300, it can be confirmed that the adhesion between the semi - dielectric layer 111 and the silicon - based electrode 110 is excellent.

[0088] As described above, the semi - dielectric layer 111 was fabricated by evaporating 5.7 mg of LiF powder in an evaporation system at 30 amperes to 33 amperes and condensing LiF on the surface 152 of the electrode facing surface 131.

[0089] Figure 4 is a micrograph 400 showing the layer pair 150 disposed on a silicon - based electrode 110 having one or more device layers 175 disposed thereon. The micrograph represents the structure 400 after the disassembly of the symmetric cell, that is, the structure 100 after the EIS test. The upper half (designated as "U’s") of the symmetric cell 100 was separated during the cutting of the symmetric cell 100, whereby only half of the symmetric cell 100 is shown.

[0090] The semi - dielectric layer 111 is made by evaporating and condensing LiF powder as described in Figure 3. Further, the molten ion - conductive layer 112 is fabricated by depositing LiTFSI salt and heating until a molten ion - conductive layer 112 with a good adhesion of the molten phase on the semi - dielectric layer 111 is formed to form the layer pair 150. The layer pair 150 is formed on the silicon - based electrode 110 as described above. The thickness 121 of the semi - dielectric layer 111 is 26.04 nm and the thickness 122 of the molten ion - conductive layer 112 is 39.75 nm. The electrode interface 131 / 152 is shown.

[0091] The interphase layer 425, which is the device layer 175, is formed by the movement of materials, ions, and electrons throughout the structure 400 when the cell is completed and includes a characteristic voltage difference between the two electrodes of the device structure 400. Further, the small applied potential amplitude used in the EIS measurement can promote the mobilization of Li ions in the system and thus can also promote the formation of the interphase layer 425. Typically, the interphase layer 425 is generated by the reaction of the electrolyte material 114 with the electrode surface 110 / 110U, and the interphase layer 425 is formed. The solid electrolyte interphase (SEI) layer 425 electrically insulates the electrode while promoting the charge mobility of ions. In this example, the interphase layer 425 has a thickness of 42.49 nm.

[0092] Figure 5 is an RC model 500 of a symmetric cell energy storage device, such as silicon / layer pair / SPE-PAN / layer pair / silicon, used for fitting an electrochemistry impedance spectroscopy (EIS) generated spectrum.

[0093] Generally, in EIS analysis, as shown in FIG. 6, R is measured / estimated as the real part of the impedance at the high or highest frequency (the leftmost data point) of the Nyquist plot. s R s is a pure resistance component called the ohmic resistance or series resistance between electrodes such as the anode and cathode of the battery and is often associated with either the contact resistance of the cell or the electrolyte resistance within the cell due to the electrical conductivity of the electrolyte or both.

[0094] Generally, the resistance components in model 500 refer to elements such as resistance in the electrochemical model configuration of the cell, and the capacitor element refers to the impedance component of the cell that has a voltage / current phase change (towards -90 degrees) with respect to the current flowing through the resistance element in the component AC current response at a predetermined frequency. For example, an EIS element (e.g., the "C" element) with advanced capacitance characteristics often corresponds to one or more surfaces in the cell 100 / 200 that are often related to layers, e.g., non-intimate contact (separation layer). The constant phase element (CPE) is an element in the cell impedance that can maintain a constant phase of the AC current response over a predetermined frequency range (often related to a transition layer grown or established in-situ). These elements are often utilized in an optimal RC model when the interphase layer is formed in-situ, or the interfacial addition layer is attached in-situ or ex-situ, or both.

[0095] This model includes a series or ohmic-related resistance R s and is connected in series with a parallel combination of resistance R1 and capacitor element C1, and its associated impedance, and in series with a parallel combination of resistance R2 and constant phase element CPE2. Also, the "Warburg" impedance element Ws1 is connected in series.

[0096] The combined elements R1 and C1 in the RC model 500 show the influence of the real and imaginary components of the impedance detected as current with a predetermined applied voltage (e.g., 50 mV) over a frequency range from high (1 MHz) to medium (~100 Hz), and it is assumed to represent the electrode interface 131 / 152, i.e., the electrode facing surface 131 that is in electrical contact with the semi-dielectric layer 111 against the bottom surface 152 (or the bottom surface 152 of the semi-dielectric layer). Therefore, the R1 / C1 time constant present in the RC model represents the charge transfer resistance across the layer pair / silicon interface. The impedance of the combination of resistance R2 and the capacitance CPE2, which is a constant phase element, is considered to represent the interface of the interfacial phase 425 and SPE114. The R2 / CPE2 time constant seems to represent a higher impedance magnitude due to the in-situ interface formation.

[0097] The Warburg impedance, Ws1, models the 100 / 200 impedance effect due to the diffusion of ions, such as lithium ions, through the electrodes and electrolyte cell components. Generally, in the EIS analysis of cells with high-performance ion diffusion, the Warburg impedance component of the cell over the mid-frequency (~100 Hz) to low-frequency (200 mHz) range with respect to the electrodes 110 / 118, or the mass transport (electrolyte migration) related to the electrolyte, or both, is observed as a nearly 45-degree "straight line, diagonal" section of the Nyquist plot.

[0098] The series resistance Rs represents the pure resistance component of the impedance related to the contact resistance of the cell, or the electrolyte resistance within the cell due to the electrical conductivity of the electrolyte, or both. Therefore, since the value of the resistance Rs affects the ease of movement of charge particles within the cell, it has an important influence on the power loss and heat generated in the battery / cell 100 / 200. The present invention including the thin semi-dielectric layer 111 contained in the layer pair 150 can significantly reduce the resistance value and the resistance value per area (resistivity) of the resistance Rs by about 5 to 10 times compared to currently known structures. Therefore, by using the thin semi-dielectric layer 111 within the layer pair 150, the power loss and the heat generated in the battery / cell 100 / 200 can be reduced.

[0099] FIG. 6 is a Nyquist plot 600 with fitting plots 625, 615 from the RC model 500 used in the EIS analysis described in FIG. 5.

[0100] The battery structure used for the Nyquist plot 600 is a symmetric cell that includes a silicon-based electrode 110 having a layer pair 150 and a polymer solid electrolyte (SPE) having a polyacrylonitrile (PAN) separator, and has a cell sandwiched together with a complementary silicon-based electrode 110 having a layer pair 150. The semi-dielectric layer 111 of the layer pair 150 was a LiF layer with a thickness 121 of 23 nm. The molten ion conductive layer 112 was one with the LiTFSI salt at about its melting temperature or at a temperature exceeding the melting temperature. The SPE layer 114 was a mixture of polycaprolactone (PCI), succinonitrile (SN), and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), and included a saturated polyacrylonitrile (PAN) separator.

[0101] The Nyquist plot 600 is a plot of a series of points, and each point, typically 605, is measured at a predetermined frequency of the excitation voltage across a cell, such as 100. At each frequency, the associated point on the Nyquist plot 600 represents the real component, Z’, of the total impedance of the cell (100, 200) measured in ohms on the X-axis 624, with respect to the imaginary component Z” of the total impedance measured in ohms on the Y-axis 626 of the Nyquist plot 600. Typically, the imaginary component Z” is a negative value (indicating capacitance), as shown. The points 605 measured at low frequencies are on the right side of the Nyquist plot 600, and the points that were scanned / plotted first towards the left have higher frequencies, i.e., the highest frequency is typically closest to the 0 / 0 vertex. Each point 605 is the impedance measured at one independent frequency.

[0102] Curve 610 is a linear curve that fits the exact impedance measured at each point 605. Curve 615 is the "best fit" curve of the points 605 on curve 610 generated from the RC model in FIG. 5. Region 625 on curve 615 is approximately linear and has a slope near 45 degrees. This indicates that the transport / diffusion of ions, such as lithium ions, Li+, through cells 100 / 200 is efficient over a wide range of frequencies, thereby warranting the use of the Warburg impedance element shown in FIG. 5.

[0103] In this exemplary embodiment, when the entire cell was biased to 0 volts, the frequency of the applied voltage varied from 1 megahertz to 200 millihertz with an excitation potential amplitude of 50 millivolts.

[0104] FIG. 6A is a graph of the enlarged portion 650 of FIG. 6, showing the points 605 and the RC model line fit 615 at high to medium frequencies of the large Nyquist plot 600. Again, at each frequency, the relevant point on the Nyquist plot 650 represents the real component, Z', of the total impedance of the cell (100, 200) measured in ohms on the X-axis 664, with respect to the imaginary component, Z", of the total impedance measured in ohms on the Y-axis 665 of the Nyquist plot 650.

[0105] In this plot, the value 675 of R1 represents the interfacial resistance of the silicon-based electrode 110 and the layer pair and is determined to be 17 ohms. This value is extracted from the diameter of the small semi-circle in the high-frequency region, as indicated by the black arrow pointing from R1. The value 685 of R2 is determined to be 1114 ohms. It is proposed that the value of R2, which is the bulk cell resistance representing the mass transport and diffusion resistance through the electrolyte and the electrodes, can be further decreased by reducing the SPE electrolyte and potentially the thickness 121 of the layer pair. Rs is estimated as the real resistance (the value on the X-axis) from the first highest-frequency data point.

[0106] Prior art symmetric cells / batteries of the same dimensions that do not include the layer pair 150 between the silicon-based electrode 110 and the SPE 114 have an R1 value in the range of around 150 ohms and an R2 value in the range of around 4527 ohms. Thus, by including the layer pair 1500, the value of R1 is improved by nearly 10 times and the value of R2 is improved by about 4 times.

[0107] TIFF0007705204000001.tif66167

[0108] FIG. 7 is a block diagram showing the layer pair 110 disposed on a silicon-based electrode used in a three-dimensionally patterned full lithium battery cell 700.

[0109] FIG. 7 is a block diagram of a novel energy storage device 700 having an active anode material (LiTFSI-PANI & graphite slurry) laminated on the active silicon regions 760A / 110 in the silicon-based electrode substrate 110 / 760. The active anode material 777 is present at the base of the groove 750 and on the groove sidewalls 754 that are partially formed in-situ in the structure 700 during the initial current cycle and before the formation of the lithium metal anode layer 740.

[0110] In this embodiment, as an example, in the structure 700, the anode 777 is completely contained within the 3D grooves 750 of the substrate 110 / 760. In this non-limiting example, the cathode contacts 785 / 118, the separator 735 / 115, and the electrolyte (732A / 732B) are disposed outside the groove 750 on the field 756. The field 756 is the surface of the substrate 760 / 110 outside the groove 750. Further, the active anode material 777, the polymer 770, and, during cycling or in-situ, the lithium metal anode layer 740 are laminated on the groove sidewalls 754 and the groove bottom 771. The structure 700 is shown after being cycled and, for example, after being exposed to currents of various amplitudes through the battery 700 to form the structures and components within the battery 700.

[0111] The battery structure 700 is partially encapsulated in the groove 750 of the substrate 760 / 110. The liner / insulator 754 covers the sidewalls 751 of the groove 750 and can overlap on the field 756. The liner 754 is made of a dielectric, an electrical insulating material such as silicon dioxide (SiO2) or silicon nitride (Si3N4), or a combination of multiple insulating layers, and is deposited by known methods.

[0112] The liner 754 does not cover the active surface 760A / 110 of the groove bottom 771, which is the surface of the groove bottom region 770 between the liner 754 layers on the sidewalls 751 of the groove 750. The electrically active surface 760A / 110 of the groove bottom 771 undergoes alteration at these surfaces by galvanic cycling and is the portion where the groove 750 first interfaces with the substrate 760 / 110 before first forming the lithiated substrate region 760A and the lithium metal layer 740 on the groove bottom 771.

[0113] In some embodiments, the pair layer 150 is deposited partially or entirely on the active surface 725 and on the insulating layer 754 on the sidewalls 751. In still other embodiments, the pair layer 150 is deposited entirely on the insulating layer 754 and on the field 756 of the substrate 760 / 110. The different laminations of the pair layer 150 are performed by known mask deposition techniques.

[0114] In some embodiments, the adhesive region 770 is a layer that covers the groove bottom 771 and the sidewalls 751 of the groove 750.

[0115] In some embodiments, the anode composition (e.g., graphite mixture and lithium / electronic conductive adhesive) 777 also covers the sidewalls 751 of the groove 750.

[0116] In some embodiments, the battery structure 700 includes electrolyte layers 732A / 114A and 732B / 114B having a separator layer 735 / 115. In some embodiments, the electrolyte layers 732A / 732B are, for example, a polymer solid electrolyte (SPE) as described above. However, any electrolyte material will function in the structure 700.

[0117] The cathode 755 / 118 is electrically connected to a cathode contact 785 / 120 that is made of a conductive material, such as a metal like aluminum (Al), or the other conductive materials described above, or both. In some embodiments, the cathode contact 785 / 120 is connected to another upper outer contact 705, such as a coin cell conductive spacer or casing, or both.

[0118] In some embodiments, a bottom outer contact 710, such as a coin cell casing, is attached to the substrate 760 / 110.

[0119] FIG. 8 is a flowchart of a method 800 of manufacturing or processing a lithium battery using layer pairs 150 such that the battery has 40 ohm cm 2 (corresponding to a charge transfer time constant of 2.25E-6 seconds) Electrode interface resistivity R1 less than and 2×10 3 ohm cm 2 (corresponding to a charge transfer time constant of 1.26E-2 seconds) Bulk cell resistivity R2 less than FIG. 8 is a flowchart of a method 800 of manufacturing or processing a lithium battery using layer pairs 150 such that the battery has 40 ohm cm and 2×10 ohm cm.

[0120] Process 800 begins, as described above, with step 810 of forming a thin semiconducting layer 111 on the silicon-based electrode 110. The thin semiconducting layer 111 has a thickness 121 of a thin semiconducting layer of 15 nanometers (nm) and 30 nm.

[0121] In step 820, as described above, a molten ion-conductive layer 112 is deposited on the thin semiconducting layer 111 to form layer pair 150.

[0122] In step 830, one or more device layers are stacked on layer pair 150 to form device 100 / 200 / 700.

[0123] The descriptions of various embodiments of the present invention are presented for illustrative purposes and are not intended to be exhaustive or to limit the invention to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. For example, the semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention can include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, and the like. Systems and hardware incorporating semiconductor devices are contemplated as embodiments of the present invention.

[0124] The terms used herein are selected to explain the principles of the embodiments, the practical application to or technical improvement of the technology found in the market, or to enable those skilled in the art to understand the embodiments described herein. Devices, components, elements, features, apparatuses, systems, structures, technologies, and methods described in different terms that perform substantially the same function, work in substantially the same way, have substantially the same use, or execute similar steps, or combinations thereof, are contemplated as embodiments of the present invention.

Claims

1. A composite electrode, comprising: a silicon-based electrode; a dielectric layer disposed directly on the silicon-based electrode, the dielectric layer having a dielectric layer thickness between 15 nanometers (nm) and 30 (nm); a conductive layer disposed on the dielectric layer, the conductive layer and the dielectric layer forming a layer pair, the conductive layer being composed of a lithium-containing salt having high conductivity for lithium ions, and the layer pair being at the bottom of a groove of the silicon-based electrode; a composite electrode comprising the above; an anode disposed on the composite electrode and in the groove; an electrolyte layer disposed on the anode; a cathode disposed on the electrolyte layer; a separator layer for preventing the flow of current between the anode and the cathode; wherein: The composite electrode has a resistivity of less than 40 ohm cm ２ and the dielectric layer is made of lithium fluoride (LiF); the lithium-containing salt is one or more of the materials of lithium hexafluorophosphate, lithium perchlorate, lithium trifluoromethanesulfonate, LiBF4, LiBF6, lithium chloride, lithium phosphate compounds, lithium bromide compounds, lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), lithium difluoro(oxalato)borate (LiDFOB), and lithium bis(oxalato)borate (LiBOB); an energy storage device.

2. The energy storage device according to claim 1, wherein the charge transfer time constant is less than 2.25E-6 seconds.

3. The energy storage device according to claim 1, wherein the dielectric layer thickness is between 18 nm and 23 nm.

4. The energy storage device according to claim 1, wherein the conductive layer has a conductive layer thickness between 1 nm and 50 nm.

5. The energy storage device according to claim 1, wherein the silicon-based electrode is composed of one or more of the materials of bulk silicon, crystalline silicon, amorphous silicon, doped silicon, boron-doped silicon, porous silicon, non-porous silicon, silicon-germanium alloy, and carbon-doped silicon-based alloy.

6. The energy storage device according to claim 1, further comprising an electrode contact composed of one or more of conductive materials, metals, metal nitrides, tungsten (W), copper (Cu), titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al), gold (Au), and titanium nitride (TiN).

7. The energy storage device according to claim 1, wherein the layer pair is disposed directly on the silicon-based electrode such that the opposing bottom surface of the layer pair is in direct physical and electrical contact with the electrode opposing surface of the silicon-based electrode, and the electrode interface is where the opposing bottom surface and the electrode opposing surface are in contact.

8. The energy storage device according to claim 1, wherein the electrolyte layer is one of a polymer solid electrolyte (SPE), a solid electrolyte, a hybrid polymer / solid electrolyte, and a liquid electrolyte.

9. The energy storage device according to claim 1, which is composed of a composite and has a charge transfer time constant of less than 2.25E-6 seconds.

10. The silicon-based electrode is made of boron-doped crystalline silicon, the dielectric layer is made of LiF, the conductive layer is made of bis(trifluoromethanesulfonyl)imide (LiTFSI), and the electrolyte layer is a polymer solid electrolyte (SPE) further mixed with polycaprolactone, succinonitrile (SN), and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI). The energy storage device according to claim 1.

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