Data Encoding Method, Electronic Device, and Storage Medium

Abstract

This application discloses a data encoding method, an electronic device, and a storage medium, which includes the steps of: writing information bits into at least two buffer blocks, in which check bits corresponding to the information bits are stored, and two adjacent bits of data of the check bits are stored in different buffer blocks (S110); and performing LDPC encoding based on the information bits in the buffer blocks and the check bits (S120).

Description

Technical Field

[0001] This application is filed based on a Chinese patent application with an application number of 202110686521.7 and an application date of June 21, 2021, claims the priority of the Chinese patent application, and incorporates all the contents of the Chinese patent application by reference into this application.

[0002] This application relates to the technical field of communications, and in particular, but not limited to, data encoding methods, electronic devices, and storage media.

Background Art

[0003] A satellite communication system is composed of a satellite, a master station system, an end station system, and an application (APP) system. The master station system and the end station system located on the earth use the satellite as a relay station to realize signal transfer. Here, the transmission link from the master station system to the satellite and then to the end station system is called the forward link. In order to improve the signal transmission quality of the satellite communication system and enhance the anti-interference ability of the channel, in the Digital Video Broadcasting - Satellite 2 (DVB - S2) protocol, the encoding method of the forward link is defined as the Low Density Parity Check Code (LDPC) encoding method. After dividing the information bits into multiple data blocks, sequential update iterative calculations and exclusive OR operations are performed on the check bits based on the set check bits.

[0004] DVB-LDPC symbolization is usually performed by a Field Programmable Gate Array (FPGA). A common implementation idea is to place 1 bit of check bits in each column of a Random Access Memory (RAM), and use the check bits arranged in series in the columns to realize the parallel calculation of update iterations. Although this improves the efficiency of update iterations, in the exclusive OR operation, data must be acquired in a serial manner. However, in an FPGA, it is impossible to acquire data at only one address in the same buffer at a time. Therefore, the exclusive OR operation can only be executed 1 bit at a time, resulting in low coding efficiency and affecting the interaction speed of the satellite communication system.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The following is an overview of the subject matter described in detail in the text. This overview is not intended to limit the scope of protection of the claims.

[0006] Embodiments of the present application provide a data encoding method, an electronic device, and a storage medium that can improve the interaction speed of a satellite communication system by improving the efficiency of exclusive OR operations.

Means for Solving the Problems

[0007] In a first aspect, embodiments of the present application provide a data encoding method. The data encoding method includes the steps of writing information bits into at least two buffer blocks, where check bits corresponding to the information bits are stored in the buffer blocks, and the adjacent 2-bit data of the check bits are stored in different buffer blocks, and performing LDPC encoding based on the information bits and the check bits in the buffer blocks.

[0008] In a second aspect, embodiments of the present application further provide an electronic device. The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the data encoding method described in the first aspect is implemented.

[0009] Other features and advantages of the embodiments of the present application will be described in the following specification, and will become partially apparent from the specification, or will be understood by implementing the embodiments of the present application. The objectives and other advantages of the present application can be achieved and obtained by the configurations specifically pointed out in the specification, claims, and drawings.

[0010] The accompanying drawings provide a further understanding of the technical solution of the present application, constitute a part of the specification, and are used together with the embodiments of the present application to interpret the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0012] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below by combining the accompanying drawings and embodiments. The specific embodiments described here are only used for interpreting the present application and are not used for limiting the present application.

[0013] Note that although the schematic diagram of the device shows the functional module division and the flowchart shows the logical order, in some cases, it may be different from the module division in the device, or the steps illustrated or described may be executed in a different order from the order in the flowchart. Terms such as "first", "second", etc. in the specification, claims or the above drawings are for distinguishing similar objects and are not necessarily for describing a specific order or sequence.

[0014] Embodiments of the present application provide a data encoding method, an electronic device, and a storage medium. The data encoding method includes the steps of writing information bits into at least two buffer blocks, where check bits corresponding to the information bits are stored in the buffer blocks, and two adjacent bits of data of the check bits are stored in different buffer blocks, and performing LDPC encoding based on the information bits and the check bits in the buffer blocks. According to the solution provided by the embodiments of the present application, since the check bits are stored in different buffer blocks, after the update iterative calculation of the check bits is completed, the FPGA can read the check bits from multiple buffer blocks in a parallel manner, realizing an improvement in the reading speed of the check bits, and effectively improving the encoding efficiency and the interaction speed of the satellite communication system.

[0015] Hereinafter, in connection with the accompanying drawings, the embodiments of the present application will be further described.

[0016] As shown in FIG. 1, FIG. 1 is a data encoding method provided by an embodiment of the present application, and the method includes the following steps, but is not limited thereto.

[0017] In step S110, write the information bits into at least two buffer blocks, where check bits corresponding to the information bits are stored in the buffer blocks, and two adjacent bits of data of the check bits are stored in different buffer blocks.

[0018] Note that the information bits may be from one transport block. After obtaining the transport block, first, the available buffer space may be determined. Only when there is sufficient space to store the transport block, the subsequent steps are executed. Thereby, the failure of encoding due to insufficient space can be avoided.

[0019] Note that since the FPGA can read only one address at a time from one buffer, in order to realize parallel reading of check bits, at least two buffer blocks are used to store the check bits, and the check bits are written one by one into the buffer blocks in the order of arrangement. This enables the FPGA to read check bits from multiple buffers, realizing parallel reading of check bits and improving the efficiency of LDPC encoding.

[0020] In step S120, LDPC encoding is performed based on the information bits and check bits in the buffer block.

[0021] Note that since the check bits are distributed in different buffer blocks, they can be read in parallel when performing exclusive OR operations, effectively improving the data acquisition efficiency of exclusive OR operations compared to the method of reading serially one by one. Therefore, the interaction speed of the satellite communication system is improved.

[0022] Also, in one embodiment, at least two buffer blocks belong to the same RAM.

[0023] Note that in order to implement having at least two buffer blocks in the FPGA, a concatenated RAM structure may be used. For example, as shown in the schematic diagram of the RAM structure in FIG. 2, the RAM is formed by sequentially concatenating N buffer blocks such that buffer block 1 and buffer block 2 are concatenated, buffer block 2 and buffer block 3 are concatenated, and so on.

[0024] In the case of an FPGA, the size of the RAM is usually fixed, such as the commonly seen 18k and 36k. Taking 18K as an example, the RAM usually has 1024 rows, and each row can store 18-bit data. To increase the resource utilization rate, set the bit width of the buffer block to 18 bits, and connect 20 buffer blocks together, then it can be used to store 360-bit data. Further specify an inspection bit buffer for each buffer block. Of course, it is also possible to arrange the buffer blocks with a bit width less than 18 bits. Those skilled in the art have the motivation to adjust the specific numerical value of the bit width according to the actual situation, and will not be further limited here.

[0025] Also, referring to FIG. 3, in one embodiment, before the execution of step S110 in the embodiment shown in FIG. 1, the following steps are further included, but are not limited thereto.

[0026] In step S310, obtain a preset target array configuration.

[0027] In step S320, determine the inspection bit buffers in at least two buffer blocks so that the array configuration composed of all the inspection bit buffers matches the target array configuration.

[0028] Note that the arrangement structure of the check bit buffer may be determined according to actual needs. For example, when adopting the RAM structure shown in FIG. 9, considering that it is necessary to write the check bits and information bits in order, a spiral structure may be adopted as the target arrangement structure. That is, the check bit buffer is offset row by row. When adopting 18 bits as the bit width, the first 18 bits at the beginning of the first row of the first buffer block are the check bit buffer 1, and the 19th to 36th bits of the second row of the second buffer block are the check bit buffer 2, and so on, to realize a spiral structure offset row by row. Thereby, it becomes possible to make full use of the buffer resources. Of course, those skilled in the art have the motivation to adjust the arrangement according to the actual memory situation, and it is only necessary to ensure that each check bit buffer is arranged in a different buffer block.

[0029] Note that for the check bit buffer obtained as described above, the offset between the check bits stored therein is determined by the target arrangement structure. For example, if the size of the RAM space for LDPC encoding is 360 bits, the range of values that the offset can take may be any numerical value from 1 to 359. Referring to FIG. 9, when adopting the spiral structure shown in FIG. 9, the offset between two adjacent check bits is the same as the bit width, which is 18 bits. Since the specific offset amount may be adjusted according to the bit width and arrangement method of the check bit buffer, specific numerical values are not further limited here.

[0030] Note that there is no strict correspondence between the offset and the bit width of the buffer block. As long as each bit of the check bit can be directly stored in the corresponding buffer block, the offset may be set to a value different from the bit width.

[0031] Also, referring to FIG. 4, in one embodiment, after the execution of step S320 in the embodiment shown in FIG. 3 is completed, the following steps are further included, but are not limited thereto.

[0032] In step S410, perform a zero reset operation in the check bit buffer.

[0033] Note that after determining the check bit buffer, by performing a zero reset operation on the check bit buffer, initial check bits with all initial values of each bit being zero can be obtained.

[0034] Note that the position where the zero reset operation is performed is the position corresponding to the transport block, that is, the position for storing check bits. Since the check bit buffer has a certain bit width, if there is a space not involved in the current LDPC encoding, it is not necessary to perform a zero reset operation on the above space, but in this embodiment, no further limitation is imposed on this.

[0035] Also, referring to FIG. 5, in one embodiment, step S110 in the embodiment shown in FIG. 1 includes, but is not limited to, the following steps.

[0036] In step S510, obtain a data block based on information bits.

[0037] In step S520, determine the initial check bits updated by the data block, and determine the target buffer address information corresponding to the initial check bits.

[0038] In step S530, based on the target buffer address information, write the data block into the check bit buffer. Here, the data of the data block in the check bit buffer has the same encoding processing order as the data of the initial check bits.

[0039] Regarding satellite communication, in the relevant protocol, the size of the information bits is defined, for example, as 64,800 bits. Therefore, in order to make full use of the memory resources of the RAM, the scale of the data block may be determined in advance. For example, the information bits may be divided into several 360-bit data blocks according to a predetermined scale. Of course, the scale of the data block may be adjusted according to the actual buffer resources and the need to reduce computing complexity, but in this embodiment, further explanation about this will be omitted.

[0040] Note that the method for obtaining the initial check bits can refer to the method described in the embodiment of FIG. 4, and for the sake of brevity, the description will be omitted here.

[0041] Once the initial check bits are determined, the buffer addresses of the check bits for each bit should also be determined. Therefore, after the initial check bits are determined, the corresponding buffer addresses may be stored, for example, in a Read-Only Memory (ROM). Also, since the correspondence between the information bits and the check bits should be determined before encoding, before writing the data block, determine the initial check bits that need to be updated by the data block, read the target buffer address information corresponding to the initial check bits from the ROM, and after writing the data block to the buffer block, based on the target buffer address information, adjust the positions of each data in the data block to match the spiral structure of the check bits. Thereby, the data block data and the initial check bits with the same encoding processing order are stored in each check bit buffer.

[0042] After dividing the data block, the data of each bit may be stored in one check bit buffer. For example, as shown in FIG. 9, there are 20 buffer blocks, the bit width of each buffer block is 18 bits, and the check bit buffer is distributed in the buffer block in a spiral configuration. After obtaining the data block, 1-bit data block data is stored in the check bit buffer 1, and 1-bit data block data is stored in the check bit buffer 2. Furthermore, while the data block has 360 bits, the bit width of the check bit buffer is 18, and since one data block data occupies only 1 bit, the 21st data block data is stored in the 2nd bit of the check bit buffer 1, and the 22nd data block data is stored in the 2nd bit of the check bit buffer 2. This is repeated until all 360-bit data block data is stored in the check bit buffer. The arrangement method of the check bits may be similar to the data block data, and the description is omitted here.

[0043] Note that by storing data in a spiral configuration as shown in FIG. 9, the data in the check bit buffer can be read in parallel. For example, when the processor can achieve a parallelism of 18 bits, in the first time, the 1st to 18th bits of the check bits are obtained from the check bit buffers 1 to 18, and in the second time, the 19th to 36th bits of the check bits are obtained from the check bit buffers 19 to 20 and the check bit buffers 1 to 16. This is repeated for acquisition. Thereby, parallel reading of the check bits is realized, the efficiency of data reading is improved, and the efficiency of LDPC encoding is improved.

[0044] Also, referring to FIG. 6, in one embodiment, step S120 in the embodiment shown in FIG. 1 includes the following steps, but is not limited thereto.

[0045] In step S610, update iterative calculations are performed based on the initial check bits and the data block in the check bit buffer to obtain target information bits and target check bits. The target information bits and the target check bits are stored in the check bit buffer.

[0046] In step S620, the target information bits and the target check bits are acquired from the check bit buffer, exclusive OR calculations are performed on the target check bits, and an LDPC encoding result is obtained.

[0047] In addition, when all of the initial check bits and the data of the data block are stored in the check bit buffer, based on the acquired target buffer address information, the FPGA may read the initial check bits from the buffer and perform update iterative calculations with the reconfigured data block. The specific update iterative calculation method is not an improvement according to this embodiment, and those skilled in the art are familiar with how to execute it after data acquisition, so the description is omitted here.

[0048] When the update iterative calculation is completed, the data in the check bit buffer are the target information bits and the target check bits. Since the target check bits are stored in different buffer blocks due to the array configuration of the check bit buffer, the efficiency of LDPC encoding can be improved by reading the target check bits in a parallel manner.

[0049] In addition, as the reading method for the target information bits, general serial reading may be adopted, and no further explanation is provided for this in this embodiment.

[0050] Note that the exclusive OR calculation of the target check bits is performed for two adjacent bits. For example, in the configuration shown in FIG. 9, it can be inferred that the result of the exclusive OR of check bit 1 is itself, and the exclusive OR calculation of check bit 2 is performed with check bit 1. After parallel acquisition of the target check bits is realized using the technical solution of the present embodiment, those skilled in the art are familiar with the method of completing the exclusive OR calculation and obtaining the LDPC encoding result from the target check bits after the exclusive OR calculation and the target information bits, so the description is omitted here.

[0051] Also, referring to FIG. 7, in one embodiment, the number of data blocks is at least two, and step S610 in the embodiment shown in FIG. 6 includes, but is not limited to, the following steps.

[0052] In step S710, a data block and initial check bits are acquired from the check bit buffer.

[0053] In step S720, update iterative calculations are performed on each data block and the corresponding initial check bits to obtain intermediate check bits, and the intermediate check bits and the data blocks are written into the corresponding check bit buffer.

[0054] In step S730, when all the intermediate check bits are obtained, it is determined that the data in the check bit buffer is the target information bits and the target check bits.

[0055] In addition, through the update iteration calculation executed in step S720, the first update for the initial inspection bits is realized. After obtaining the intermediate inspection bits, since the information bits are divided into a plurality of data blocks, it is necessary to ensure that the calculation of this step is executed for any of the data blocks. Therefore, after obtaining the intermediate inspection bits, write them into the corresponding inspection bit buffer, write the next data block into the inspection bits in the same method described in the above embodiments, and further execute the update iteration calculation described in step S720. When all data blocks are completed, it can be determined that the calculation of the inspection bits is completed, and it can be determined that the obtained inspection bits are the target inspection bits.

[0056] Also, referring to FIG. 8, in one embodiment, step S620 in the embodiment shown in FIG. 6 includes, but is not limited to, the following steps.

[0057] In step S810, obtain a preset parallelism.

[0058] In step S820, obtain the target information bits in a serial manner according to the parallelism.

[0059] In step S830, obtain the target inspection bits from the inspection bit buffer in a parallel manner according to the parallelism and the target array configuration.

[0060] Note that the parallelism may be adjusted according to the actual processing capacity, and the specific numerical value of the parallelism is not further limited in this embodiment. For example, when performing data reading with a parallelism of 18 bits, for the first time, read the data of the first bit from the first buffer address of the first 18 buffer blocks, for the second time, read the data of the first bit from the first buffer address of buffer blocks 19 - 20, and read the data of the second bit from the address of the second bit of buffer blocks 1 - 16. Since none of the above operations includes reading a plurality of addresses from one buffer, it is possible to be realized by an FPGA, and the efficiency of data reading is effectively improved.

[0061] Note that obtaining target information bits in a serial manner based on the set parallelism is a technique well known to those skilled in the art, and thus the description thereof will be omitted here.

[0062] Note that referring to the arrangement method of the spiral structure shown in FIG. 9, the data block data and the check code of each bit are in different rows and columns, and two adjacent bits are in different buffer blocks. For different buffer blocks, since data can be read simultaneously in an FPGA, when the target array configuration is determined, it is possible to know the address of the check bit buffer. Therefore, with the array configuration of the check bit buffer and the check bits in this embodiment, parallel reading of the check bits becomes possible.

[0063] To better explain the technical solution of the embodiment of the present application, one example is given below for illustration.

[0064] In this illustration, as shown in FIG. 9, the RAM configuration consists of 20 buffer blocks with a bit width of 18 bits. To reduce complexity, the offset value is set to 18 bits, and a spiral configuration is adopted as the array configuration of the check bit buffer.

[0065] Referring to FIG. 10, the data encoding method of this illustration includes the following steps, but is not limited thereto.

[0066] In step S1010, a zero reset operation is performed on the positions of the current information bits and check bits in the buffer RAM.

[0067] In step S1020, the information bits are divided into data blocks every 360 bits and divided into at least one 360-bit data block.

[0068] In step S1030, write the first 360-bit data block into the check bit buffer, perform an offset of the position according to the spiral configuration so that it matches the data in the 360-bit data block, take out the check bits and the 360-bit data block after offset from the check bit buffer, perform an exclusive OR operation, and write the intermediate result obtained by the update iteration operation into the check bit buffer.

[0069] In step S1040, repeat step S1030 until the update iteration operation for all 360-bit data blocks is completed.

[0070] In step S1050, when the update calculation for all 360-bit data blocks is completed, read the information bits serially with a parallelism of 18 bits and read the check bits with a parallelism of 18 bits according to the spiral configuration method.

[0071] In step 1060, perform an exclusive OR operation on the check bits with a parallelism of 18 bits to complete the LDPC encoding.

[0072] Furthermore, referring to FIG. 11, one embodiment of the present application further provides an electronic device. The electronic device 1100 includes a memory 1110, a processor 1120, and a computer program stored in the memory 1110 and executable on the processor 1120.

[0073] The processor 1120 and the memory 1110 may be connected by a bus or other means.

[0074] The non - transient software programs and instructions necessary to implement the data encoding method of the above - described embodiments are stored in the memory 1110 and, when executed by the processor 1120, execute the data encoding methods in the above - described embodiments, for example, the method steps S110 to S120 in FIG. 1, the method steps S310 to S320 in FIG. 3, the method step S410 in FIG. 4, the method steps S510 to S530 in FIG. 5, the method steps S610 to S620 in FIG. 6, the method steps S710 to S730 in FIG. 7, and the method steps S810 to S830 in FIG. 8, as described above.

[0075] The device embodiments described above are merely exemplary. The units described as separate components may or may not be physically separated, that is, they may be located in one place or dispersed among a plurality of network units. To achieve the objectives of the embodiments of this aspect, some or all of these modules can be selected according to actual needs.

[0076] In addition, an embodiment of the present application further provides a computer - readable storage medium. The computer - readable storage medium stores computer - executable instructions, and when the computer - executable instructions are executed by a processor or a controller, such as the processor in the above - described electronic device embodiments, the data encoding methods in the above - described embodiments, for example, the method steps S100 to S120 in FIG. 1, the method steps S310 to S320 in FIG. 3, the method step S410 in FIG. 4, the method steps S510 to S530 in FIG. 5, the method steps S610 to S620 in FIG. 6, the method steps S710 to S730 in FIG. 7, and the method steps S810 to S830 in FIG. 8, can be executed by the above - mentioned processor.

[0077] An embodiment of the present application includes the steps of writing information bits into at least two buffer blocks, where check bits corresponding to the information bits are stored in the buffer blocks, and data of two adjacent bits of the check bits are stored in different buffer blocks, and performing LDPC encoding based on the information bits and the check bits in the buffer blocks. According to the solution provided by the embodiment of the present application, since the check bits are stored in different buffer blocks, after the update iteration calculation of the check bits is completed, the FPGA can read the check bits from multiple buffer blocks in parallel, realizing an improvement in the reading speed of the check bits, and effectively improving the encoding efficiency and the interaction speed of the satellite communication system.

[0078] All or some of the steps of the method disclosed above, and the system, may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical assemblies may be implemented as software executed by a processor such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). The term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. Further, it is well known to those skilled in the art that a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information transmission medium.

[0079] In the above, the embodiments of the present application have been specifically described, but the present application is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions without departing from the spirit of the present application, and these various equivalent modifications or substitutions are included within the scope defined by the claims of the present application.

Claims

1. A data encoding method, comprising: writing information bits into at least two buffer blocks, wherein check bits corresponding to the information bits are stored in the buffer blocks, the check bits include data of a plurality of bits, and data of two adjacent bits in the check bits are stored in different buffer blocks; performing low-density parity-check (LDPC) encoding based on the information bits and the check bits in the buffer blocks; wherein the step of writing information bits into at least two buffer blocks includes: obtaining a data block based on the information bits; determining initial check bits updated by the data block and determining target buffer address information corresponding to the initial check bits; writing the data block into a check bit buffer based on the target buffer address information; and data of the data block in the check bit buffer has the same encoding processing order as data of the initial check bits. A method.

2. The at least two buffer blocks belong to the same random access memory (RAM). The method according to claim 1.

3. Before the step of writing information bits into at least two buffer blocks, the method further includes: obtaining a preset target array configuration; determining check bit buffers in at least two of the buffer blocks such that an array configuration formed by all the check bit buffers matches the target array configuration. The method according to claim 1, comprising the above.

4. After the step of determining check bit buffers in at least two of the buffer blocks, the method further includes: performing a zero reset operation on the check bit buffers. The method according to claim 3, comprising the above.

5. The step of performing LDPC encoding based on the information bits and the check bits in the buffer blocks includes: A step of performing an update iterative calculation based on the initial check bits and the data block in the check bit buffer to obtain target information bits and target check bits, wherein the target information bits and the target check bits are stored in the check bit buffer; A step of acquiring the target information bits and the target check bits from the check bit buffer, performing an exclusive OR calculation on the target check bits, and obtaining an LDPC encoding result; The method according to claim 1, comprising the above steps.

6. The number of the data blocks is at least two; The step of performing an update iterative calculation based on the initial check bits and the data block in the check bit buffer: A step of acquiring the data block and the initial check bits from the check bit buffer; Performing an update iterative calculation on each of the data blocks and the corresponding initial check bits to obtain intermediate check bits, and writing the intermediate check bits and the data block into the corresponding check bit buffer; When all the intermediate check bits are obtained, determining that the data in the check bit buffer is the target information bits and the target check bits; The method according to claim 5, comprising the above steps.

7. The step of acquiring the target information bits and the target check bits from the check bit buffer: A step of acquiring a preset parallelism; According to the parallelism, acquiring the target information bits in a serial manner, and according to the parallelism and a preset target array configuration, acquiring the target check bits from the check bit buffer in a parallel manner; The method according to claim 5, comprising the above steps.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method according to any one of claims 1 to 7 is realized. Electronic device.

9. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to realize the method according to any one of claims 1 to 7 when executed by a processor. Computer-readable storage medium.

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