MEMS device constructed using metal layers in the BEOL process of a solid-state semiconductor process

Abstract

A MEMS device formed using back-end of line (BEOL) materials in a CMOS process, where vHF post-processing and post-backing are applied to form the MEMS device, and the MEMS device has a total dimension of 50 μm to 150 μm. The MEMS device can be implemented as an inertial sensor, among other applications.

Description

Technical Field

[0001] This application generally relates to MEMS devices, and more specifically to techniques for manufacturing MEMS devices.

Background Art

[0002] An integrated circuit is a semiconductor device having a substrate of semiconductor material on which a series of layers are deposited using photolithography techniques. The layers are doped and polarized so that electrical elements (e.g., resistors, capacitors, or impedances) or electronic elements (e.g., diodes or transistors) are created. Then, other layers are deposited, which form the structure of the interconnecting layers necessary for electrical connections.

[0003] Microelectromechanical or microelectromechanical systems (MEMS) are small electromechanical devices manufactured using layer deposition techniques based on photolithography technology. MEMS can provide cavities or hollow spaces inside them, which can be filled with liquids or gases. Conventional integrated circuits are completely solid devices, i.e., they do not have any kind of cavities. A cavity can be defined as a cavity larger than an atomic or subatomic scale cavity. MEMS can have movable elements inside them. The movable elements can be coupled to the rest of the MEMS structure by one of their ends or can be completely loose (i.e., not physically attached around it) inside a housing that is at least partially closed (to prevent the loose part from "escaping" from the MEMS). A chip can include a MEMS device and an integrated circuit (IC), where the IC can control the MEMS.

[0004] The main problem with today's MEMS devices is the need for a custom manufacturing process. This does not occur in solid-state electronics, which has converged towards a manufacturing standard called complementary metal-oxide-semiconductor (CMOS), mainly classified from the node perspective and having many variants. This is the minimum feature size that the process can solve at the front end of the line (FEOL).

[0005] In reality, most MEMS ICs seen in the market today are composed of packages having two dice inside. One of these dice is from a CMOS wafer, and the other is from a MEMS wafer manufactured in a custom process. The dice inside the package are generally wire-bonded and packaged using a plastic package. In some combo ICs that require several MEMS devices, the package may require more than two dice inside. One is a CMOS with control electronics, and several MEMS dice are constructed in different manufacturing processes respectively.

[0006] This requirement for a unique development manufacturing process for each MEMS manufacturer and various MEMS devices has several problems, such as cost, size, time to market, performance, and mass production capacity. 90% of the semiconductor industry consists of solid-state ICs, which do not involve MEMS, and most of them are constructed by CMOS processing. Therefore, most semiconductor companies use the so-called fabless model and outsource all production to large-scale CMOS foundries, which are companies that concentrate their business only on the manufacturing of CMOS wafers.

[0007] This creates an economy of scale generally more than 100 times that of the largest MEMS foundry. Therefore, the cost of MEMS processing becomes much higher than that of CMOS wafers. However, the cost of MEMS wafers can be lower than that of CMOS wafers, especially when we consider lower nodes, because of the increased complexity at each stage of the CMOS process compared to the MEMS process. However, for the same level of complexity, CMOS has a much lower cost than any MEMS process. If MEMS could be constructed using the same CMOS process, the cost of the entire IC would be significantly reduced. This is because initially two dice are not required, and only one die in the package is sufficient. Therefore, we remove the MEMS die and simplify the packaging.

[0008] There is an interest in reducing the size of integrated circuits (ICs), especially for applications such as smartphones and even for wearables where space is highly constrained, particularly earphones. The best packaging technology currently used to minimize the overall size of an IC is wafer-level chip-scale packaging (WLCSP). This essentially involves the deposition of a sealing layer on the wafer to protect the wafer, bumping of pads, and dicing of the wafer by a previous selective backgrinding. There may be additional steps in processes such as RDL (redistribution layer), but they are not essential or necessary for all implementations. However, if more than one die needs to be packaged, WLCSP cannot be used. If MEMS can be built within the same CMOS die, we can apply WLCSP to package it, thereby significantly reducing the overall package die. If possible, various MEMS devices can be implemented in the same CMOS process. This allows manufacturers to build a combo chip packaged by WLCSP. This will result in further reduction compared to the multi-die plastic packages currently in use.

[0009] When a new type of MEMS device is developed, a new manufacturing process for building that new MEMS device needs to be developed. This is a complex project because the volume that this process has to handle is very large as the MEMS market is generally for consumers, and a high yield is expected from it to minimize costs. This usually takes several years and is also costly. If MEMS can be built using the same CMOS process that already exists and is ready for low-cost mass production, only the device needs to be developed, so the time to market will be minimized. There is no need to spend time (and cost) developing a custom manufacturing process.

[0010] Due to the different economies of scale present in the CMOS vs. MEMS processes, the equipment used in the CMOS process is state-of-the-art, while in the MEMS process, they are typically legacy equipment, reducing the cost of setting up the MEMS process. This means that the minimum feature size, also known as the critical dimension, is usually smaller for the CMOS process than for the MEMS process. Therefore, if MEMS can be built using the CMOS manufacturing process, they will be able to manufacture MEMS devices with small feature sizes. This helps to improve the performance of the device, as it is possible to build softer springs / membranes and smaller gaps.

[0011] In addition to this, if MEMS can be built using the CMOS process, they will minimize the parasitic capacitance that appears when connecting the MEMS to the electronic interface (usually sensing / driving) circuits in the CMOS die. This is typically done via wire bonding inside a plastic package, which adds a capacitance on the order of usually 1 pF to 10 pF. With MEMS built within the same CMOS process, this parasitic capacitance resulting from the connection of the MEMS to the electronic device will generally be reduced to between 1 fF and 10 fF. This is a reduction of x100 to x1000. Since the parasitic capacitance masks the capacitance of the MEMS device and degrades the performance of the MEMS device, reducing it can improve the performance of the MEMS IC. Improving performance means increasing the sensitivity of the sensor, reducing its power consumption, or a combination of the two.

[0012] Furthermore, as already mentioned, mainstream CMOS foundries have a mass production capacity that is more than 100 times larger than that of the major MEMS foundries. Therefore, if we can build MEMS devices using CMOS processing, we will benefit from this mass production capacity. This makes it possible for us to target new markets such as the IoT (Internet of Things), which would otherwise be impossible. Today, MEMS providers are having difficulty contributing to the existing MEMS market because their mass production capacity is limited. The IoT is expected to expand the volume of the current MEMS market by more than 100 times. This can only be achieved today if MEMS devices are built using mainstream CMOS foundries.

[0013] Some companies build MEMS together with CMOS using monolithic solutions. This leaves a single die with both CMOS and MEMS at the end of the manufacturing process. The two options for building this are either to bond the MEMS and CMOS wafers after manufacturing them separately, or to build the MEMS wafer on top of the completed CMOS wafer instead of starting from a blanket silicon wafer. In both cases, a custom MEMS manufacturing process is required. These monolithic solutions reduce the size of the IC, which makes it possible to use WLCSP with them without the need for wire bonding. Also, they increase the performance slightly, which is due to the lower parasitic interconnect capacitance between the MEMS and CMOS, which generally drops to between 100 fF and 1 pF.

[0014] However, previous approaches still have issues with cost, time-to-market, and mass production capabilities because they continue to require a full custom MEMS process. Also, while dimensions are shrinking and performance is increasing, it would still be quite good if we could build MEMS using a CMOS process. From a dimensional perspective, basically, since we stack two dies on top of each other, the profile is always larger. However, in CMOS, it is one die, and this can be backgrinded. In terms of performance, this reduces parasitic capacitance by a factor of 10 compared to the conventional two-die package solution, but by building MEMS devices using a CMOS process, we would achieve a 100-fold reduction.

[0015] Also ultimately, these monolithic solutions only work if we have a single MEMS device or sensor. If a combi-chip with different types of sensors is required, this can no longer be applied. However, by building all these MEMS devices using a CMOS process, we continue to have a single die solution that can be backgrinded. Therefore, when we transition to a combi-chip, building MEMS using a CMOS process significantly increases the cost and dimensional advantages.

[0016] The reduction in cost and dimensions is partly due to the elimination of many bonding pads that are no longer necessary when we transition to a combi-chip. Considering the known advantages if we could build MEMS devices using a CMOS manufacturing process, several solutions have been proposed. The first solution proposes changes to the CMOS process that add several steps to build the MEMS device. Depending on whether these are executed at the beginning, in the middle, or at the end of the CMOS process, the solution is called pre-processing, mid-processing, or post-processing.

[0017] A change in the CMOS process was required. This is because when MEMS devices need to perform mechanical movements, they require some free space inside the IC to perform this movement. Also, these free spaces are not something that CMOS can create. Another reason for the change was to add layers of different materials or layers with different mechanical properties that were not seen in the CMOS process.

[0018] Considering the very high cost of implementing modern CMOS processes in mainstream foundries and the cost of maintaining them stably, pre - processing and mid - processing changes were abandoned in order to continue very high - volume production while maintaining a very high yield. The only remaining option is CMOS post - processing for implementing MEMS.

[0019] CMOS post - processing means that after the manufacture of CMOS wafers, they go through some additional manufacturing steps where MEMS are implemented. However, unlike the aforementioned monolithic approach, it consists of wafer bonding or the construction of MEMS on top of the CMOS wafer, in which case we simply create the free space necessary to enable the mechanical movement of the MEMS. Also, the MEMS are then constructed using the materials present inside the CMOS wafer.

[0020] One possibility would be to implement MEMS using polysilicon, but this requires deep etching to reach it, either etching from the top of the wafer, thus first through all of the back - end - of - line (BEOL), or from the back, through the silicon substrate, which requires a complex process that is not cost - effective.

[0021] The only solution remaining in that case is to implement MEMS using the materials present in the CMOS BEOL. Since the BEOL is at the top of the CMOS die, post-processing is minimized, and thus the cost can be minimized as well.

[0022] In contrast, for example, combinations of plasma and / or wet etching with HF and other chemicals have been proposed as different solutions. These processes are difficult to result in high yield mass production, especially when accompanied by wet etching.

[0023] The previously proposed simple post-processing approach lies in using a single vapor HF (vHF) maskless post-processing step. vHF etches away the silicon oxide present between the metal layers of the BEOL, leaving all the metals behind. This was proposed by Baolab. Due to its simplicity, it is the lowest-cost CMOS post-processing approach. Furthermore, it can be implemented in the same CMOS foundry or in packaging or in an assembly house.

[0024] In this approach, MEMS devices are constructed using metal layers, generally Al or AlCu and W, although other layers such as Cu may also be present. With proper design, it is possible to confine the oxide inside the metal casing. Other materials can be used, but they must be present in the CMOS BEOL. Most of the previous approaches use a laminate package, such as a special package like LGA, to protect the MEMS. This increases the cost and dimensions, thus minimizing or eliminating the dimensional and cost advantages that we would otherwise obtain when constructing MEMS using the CMOS process.

[0025] Baolab proposed using the top metal layer to protect the MEMS while having small holes that would allow vHF to enter the MEMS cavity. Subsequently, a second set of post - processing steps in Al sputtering and patterning is applied to properly seal the MEMS device. This generally adds 10% to the cost of the CMOS process. This simplifies the package requirements and eliminates the need to use a laminate or other special package. Instead, standard packaging technologies such as QFN can be used. This reduces the cost and size of the final IC.

[0026] In addition to the top metal layer, a bottom metal layer was used to complete the metal cavity in which the MEMS device is placed. This was done to limit the etching of vHF to the bottom, considering that most CMOS processes have doped silicon oxide under M1, which is the bottom - most metal layer. The doped silicon oxide reacts very aggressively with vHF, rapidly increasing the etching rate and leaving very troublesome residues that are difficult to remove. This makes the design transplantable to most CMOS processes; otherwise, it could only be applied to special processes that do not have doped silicon oxide under the bottom - most metal layer of the BEOL.

[0027] The Baolab solution surrounds the MEMS device with metal walls that define the MEMS cavity within the ASIC die, like other solutions that use materials in the BEOL to implement MEMS devices. In this way, the electronics are placed around it. The implementation of these metal walls is made of a stack of metal layers (usually made of aluminum) and vias (usually tungsten). However, when we move to CMOS nodes below the 0.18μm process, the materials may be different, mainly copper. In principle, this is not a straight vertical wall, because the DRC rules require that the metal layer extends beyond the edge of the via. However, we can make some exceptions to this, for example, when we are interested in growing the lateral area exposed to the wall, as in the case of in-plane capacitive sensors. This becomes a DRV that the foundry has to accept in that case.

[0028] By using the Baolab solution, the vertical metal walls in principle connect the top and bottom metal surfaces, thus electrically shorting all MEMS cavities. Usually, we are not interested in this, or at least it does not occur everywhere in all cavities. To solve this problem, Baolab uses a vertical interleaved anchor structure. These structures shuttle vHF up and down through the silicon oxide layer until it is exhausted, leaving unetched silicon oxide. In this way, we can obtain mechanically consistent walls without electrically shorting the top and bottom metal plates.

[0029] One reason this is particularly effective is that the silicon oxide layers deposited between the metal layers of the BEOL in a CMOS process typically exist on two different sub-layers with different oxide densities. Therefore, one of these layers is etched away more slowly by vHF than the other. Etching silicon oxide vertically in this way is more difficult (i.e., it takes more time) than etching horizontally. This is because in that case, the etching propagates faster along one of the silicon oxide sub-layers. With these anchor structures, we force the vHF to etch all sub-layers with low etching rates without propagating quickly through the high-speed sub-layer. These interleaved anchors can also be used to add columns or pillars at various positions of the MEMS to provide higher consistency to the upper metal surface. This is particularly important from the perspective of generally supporting subsequent sealing with Al sputtering. This way, the upper metal surface is not bent, which would ultimately render the MEMS device broken or unusable.

[0030] The main problem with these anchor walls is that while they provide mechanical robustness while electrically isolating the upper and lower metal surfaces, the capacitance between them is very large. This is because large surfaces are placed close to each other inside the interleaved anchor structure, one connected to the upper plate and the other to the lower plate, and to make matters worse, this important part is filled with silicon oxide.

[0031] Another problem related to the previous one is that there is a significant trade-off between this parasitic capacitance between the top and bottom metal plates and production yield and reliability. To minimize this parasitic capacitance, we can minimize the length of the anchor structure, reduce the number and / or their height of the fingers, and / or increase the etching time. In this way, when we minimize this parasitic capacitance, the silicon oxide remaining inside after vHF etching has a small anchor structure with a minimum amount. However, this is a very weak structure and is prone to mechanical failure due to mechanical shock, vibration, or simply when sealing or packaging the device. Also, it results in low yield. Slight over-etching completely removes the silicon oxide inside the anchor structure, causing the collapse of the top and bottom parts and making the device completely unusable. In manufacturing, we need to avoid this requirement for critical vHF etching because it always leads to low yield. The reason is that the etching rate and silicon oxide etched inside the MEMS cavity depend not only on both the applied vHF machine and recipe but also on the CMOS process. Although we can have strict control over the vHF machine and its recipe, generally, we cannot control the CMOS process with a tolerance on the order of 30%.

[0032] In addition to potentially requiring all metal layers to implement the MEMS device, it requires a special packaging process, a specific CMOS process without doped silicon oxide under the bottommost metal plate, and also a large parasitic capacitance. The two main problems for all solutions using the CMOS BEOL materials for implementing MEMS are yield and reliability. These problems become even more important when using the Baolab approach on the top and bottom metal surfaces. However, if we do not use them, the process becomes more complex and expensive, thus losing cost advantages, the time to mass production and market entry, and even performance advantages.

[0033] One of the major problems seen when using the BEOL metal of the CMOS process to implement MEMS devices is the vertical stress gradient. This is minimized in a custom MEMS manufacturing process. However, in CMOS, since these metal lines are not intended to implement a mechanical structure but are merely electrical connections surrounded by silicon oxide in a solid-state IC, residual stress is not of much concern and generally has a large value. In addition to the large residual stress, we generally find a large vertical stress gradient. This generally results in upward metal bending or curling, which depends on the layer and can be downward especially in the upper layer. This bending is a major concern when we use the upper and bottom metal surfaces. Therefore, the vertical gap spacing available above and below the device is minimal, which makes it easy to contact them. When the MEMS device contacts the upper or bottom metal surface, it becomes unusable. This leads to very poor yield and reliability.

[0034] One possibility to reduce this problem would be to increase this vertical gap spacing and reduce the number of metal layers used in the MEMS device itself. However, this reduces the out-of-plane performance because the gap becomes larger, and thus the relative capacitance variation of a certain point sensor for the same displacement is reduced. Also, in the case of inertial sensors, we are forced to have a smaller proof mass and cannot use all the available metal layers, resulting in further performance degradation. Also, reducing the number of metal layers used to construct the movable part of the device, such as the proof mass in the case of inertial sensors, further increases its curvature as described later. Therefore, it is necessary to minimize the curvature height of the MEMS device. This is defined as the maximum vertical displacement of any metal layer along all MEMS devices or their specific elements, and thus the maximum vertical displacement in the out-of-plane direction.

[0035] One known solution to this problem is to stack two or more metal layers. In this way, we increase the radius of curvature of the resulting metal structure, thereby reducing the total curvature height. However, while this is an excellent solution for designing certain parts of MEMS devices such as the proof mass of inertial sensors, we would like to make it as large as possible to improve the sensitivity of the sensor. On the other hand, in other components such as springs, this leads to very high stiffness, thereby significantly reducing the sensitivity. In fact, stiffness is inversely proportional to the cube of the length to thickness, so increasing the thickness quickly results in a very stiff spring. This means that the sensor is very insensitive and the drive voltage for the actuator is high. Furthermore, the multi-layer stack is limited by the number of metal layers in the process, and if it is necessary to modify or use a CMOS process with more metal layers in BEOL, this rapidly increases its cost.

[0036] In summary, there is a need to find a suitable design for implementing MEMS devices by reusing BEOL materials existing in standard CMOS processes and etching away a portion of the silicon oxide within the MEMS cavity using vHF. This can then be packaged by WLCSP, and these devices have very high yields, reliability, and performance.

[0037] Another problem with using a vHF etching post-processing step after CMOS is that the SiN passivation layer deposited and patterned on top of the CMOS wafer is partially etched away by vHF. This means that, in practice, the SiN passivation layer will be largely or completely etched away unless a very short vHF etching step is performed. This leaves troublesome residues on the wafer and exposes all wafers with ASIC regions where the silicon oxide should not be etched away.

[0038] A known solution to prevent this is to increase the silicon content of the passivation, which is generally measured by the refractive index or RI of the layer. This is not technically complex to implement, but requires fine-tuning of the process, and it is very difficult for large-scale mainstream foundries to accept it. Ultimately, this requirement means that we can no longer use a complete standard CMOS process, and thus we lose some of the advantages of low cost, short time to market, and high-volume production capabilities. SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0039] This application addresses defects associated with the manufacture of MEMS devices in various implementations. MEANS FOR SOLVING THE PROBLEM

[0040] In various aspects, systems, devices, and methods result from or use vHF etching to etch away a portion of the silicon oxide in the BEOL of a CMOS process, thereby liberating the materials present in the BEOL that make up the MEM device. The innovative approach uses a bottom metal surface and a top metal surface having an array of small holes that allow vHF to enter inside the MEMS cavity. An important innovative concept is to limit the overall MEMS size on the layout to 50 μm to 150 μm, preferably less than 100 μm. For a given radius of curvature of a MEMS device or element, the total radius of curvature depends on the horizontal dimension. Thus, when the device is small enough, the curvature height is limited despite a large vertical stress gradient.

[0041] The second innovative concept is the spring design. To endow such a small device with excellent performance, small and soft springs are required while maintaining a small curvature height. These seem to be conflicting requirements. Short springs mean that they are very stiff, and thus the sensitivity (performance) of the MEMS sensor decreases. To have soft springs, we need to minimize their thickness. This means minimizing or not using metal stacks at all. However, this increases the vertical stress gradient, which rapidly increases the total curvature height.

[0042] A preferred innovative solution to the spring design problem is to use a set of at least three springs, rather than a single one, evenly distributed around the device and rotating around the central axis of the device. As a result, due to symmetry, the MEMS device cannot tilt after being released by vHF etching.

[0043] In the case of inertial sensors, the MEMS device may include a central proof mass made of several metal stacks, and thus is very flat compared to the surrounding springs. This proof mass can be made larger than the springs in order to have sufficient sensitivity. When one or more springs holding it are curved, if the proof mass is tilted, the proof mass itself is relatively flat, but as a result, the curvature height increases. However, when there are at least three springs evenly arranged around it, the proof mass experiences a small vertical displacement due to the curvature of the springs, but it remains flat and thus does not contribute to its large total vertical height.

[0044] In a particular implementation, the central mass is circular in shape, the surrounding springs have a helical shape, and it is made of a single metal layer or a stack-up of only two metal layers. When using a stack-up of two metal layers, we connect them with a via layer in between. In a preferred implementation, this via layer has the same linear or helical shape as the upper and lower metal layers, but in principle, it is slightly narrower in the lateral direction to satisfy the DRC rules in at least one horizontal direction at each point. Throughout this application, when we say we use a stack-up of a particular set of metal layers, it is understood that we use a via layer between them to maintain their connection. The use of circular and rounded shapes for the proof mass, springs, and generally all or as many parts of the MEMS device as possible avoids high mechanical stress, which would otherwise accumulate at the straight angles of the device geometry. These rounded shapes promote the stress balance of the springs and, when we use an array of at least three equally distributed springs around it, result in the necessary horizontal tilt of the central mass.

[0045] One aspect includes a MEMS device formed using materials of the BEOL of a CMOS process, where vHF post-processing and post-bonding are applied to form the MEMS device. The total dimensions of the MEMS device are between 50 μm and 150 μm. The total dimensions of the MEMS device can be less than 100 μm. In some implementations, the total dimensions of the MEMS device are 50 μm or less. The MEMS device can include a set of at least three springs that are evenly distributed around the MEMS device and rotated around the central axis of the MEMS device or its movable part. The shape of the device can be circular and the springs can have a helical shape. The springs can consist of a single metal layer or a stack-up of at least two metal layers. The MEMS device can include an inertial sensor.

[0046] A MEMS device may include a proof mass. The proof mass may be formed or made by a stack-up of four metal layers and springs. Here, the spring is either connected to the upper metal layer of the proof mass forming the stack-up or connected to two upper metal layers of the stack-up. The spring may be connected to an external ring such that a part of it remains embedded in silicon oxide on its outer edge after vHF etching.

[0047] In some implementations, the MEMS device has an upper metal surface and a bottom metal surface that is smaller than the upper metal surface. The outer ring width of the bottom metal surface can be equal to or less than 10% - 50% of the width of the outer ring of the upper metal surface. The outer ring width of the bottom metal surface can be about 30% of the outer ring width of the upper metal surface. The MEMS device may include at least one pad. The at least one pad includes an upper metal layer arranged such that vertically aligned passivation openings extend laterally more than 15 μm to 25 μm in all directions. The at least one pad can have vertically aligned passivation openings that extend laterally more than 20 μm in all directions. The MEMS device can be formed within a MEMS cavity that does not include a metal fill structure. In some implementations, the MEMS device is configured to have more capacitance so that, for example, a more conventional sensing circuit can be used to measure the MEMS capacitance. The MEMS device can be constructed by an array of MEMS devices connected electrically in parallel. Each of these MEMS devices has its own passivation opening and they are completely separated except for the lines / tracks that form the electrical connections.

[0048] In another aspect, the MEMS device includes a set of at least three springs that are evenly distributed around the MEMS device and are rotatable about the central axis of the MEMS device. The device shape can be circular and the springs can be helical. The springs can be made by a single metal layer or a stack-up of at least two metal layers. The MEMS device can include an inertial sensor. The MEMS device can include a proof mass. The proof mass is made by a stack-up of four metal layers and springs. The springs are connected to the upper metal layer of the proof mass forming the stack-up or are connected to two upper metal layers of the stack-up.

[0049] In a further aspect, the MEMS device includes a spring in which the ratio of the maximum displacement to the spring length is at least 1%. The MEMS device can include a proof mass. The proof mass is made by a stack-up of four metal layers and springs. The springs are connected to the upper metal layer of the proof mass forming the stack-up or are connected to two upper metal layers of the stack-up. The springs can be connected to an external ring such that a part of them remains embedded in silicon oxide on its outer edge after vHF etching. The MEMS device can include an upper and a bottom metal surface, and the outer ring width of the bottom metal surface is equal to or less than 10% - 50% of the width of the outer ring of the upper metal surface.

[0050] Yet another aspect is a method for manufacturing a MEMS device using BEOL materials of a CMOS process, including applying vHF post-processing and post-backing to form the MEMS device. Here, the total dimensions of the MEMS device are 50μm - 150μm. The total dimensions of the MEMS device can be less than 100μm. This method can further include forming a set of at least three springs that are evenly distributed around the MEMS device and are rotatable about the central axis of the MEMS device.

[0051] This method may include forming a device shape that is circular and forming a spring in a helical shape. This method may include forming the spring by a single metal layer or a stack-up of at least two metal layers. This method may form a MEMS device including an inertial sensor.

[0052] This method may include forming a proof mass. Here, the proof mass is made by a stack-up of four metal layers and a spring. The spring is connected to the upper metal layer of the proof mass forming the stack-up or is connected to two upper metal layers of the stack-up. This method may include connecting the spring to an external ring such that a part of it remains embedded in silicon oxide on its outer edge after vHF etching.

[0053] This method may include forming a MEMS device having an upper metal surface and a bottom metal surface smaller than the upper metal surface. This method may include forming a width of the outer ring of the bottom metal surface that is equal to or less than 10% - 50% of the width of the outer ring of the upper metal surface. This method may include forming the width of the outer ring of the bottom metal surface to be about 30% of the width of the outer ring of the upper metal surface. This method may include forming a MEMS device within a MEMS cavity that does not include a metal filling structure.

[0054] In a further aspect, a method for manufacturing a MEMS device includes forming a set of at least three springs that are evenly distributed around the MEMS device or its movable part and are rotated around the central axis of the MEMS device or its movable part. The method may include forming the shape of the MEMS device that is circular and forming the springs to have a spiral shape. The method may include forming the springs by a single metal layer or a stack-up of at least two metal layers. The method may include forming the MEMS device to include an inertial sensor. The method may include forming a proof mass, where the proof mass is made of a stack of four metal layers and springs, and the springs are connected to the upper metal layer of the proof mass forming the stack-up or are connected to two upper metal layers of the stack-up.

[0055] In yet another aspect, a method for manufacturing a MEMS device includes forming a spring in which the ratio of the maximum displacement to the spring length is at least 1%. The method may include forming a proof mass having a stack-up of four metal layers and springs, where the springs are connected to the upper metal layer of the proof mass forming the stack-up or are connected to two upper metal layers of the stack-up. The method may include connecting the spring to an outer ring such that a part of it remains embedded in silicon oxide on its outer edge after vHF etching. The method may include forming the width of the outer ring of the bottom metal surface to be equal to or less than 10% - 50% of the width of the outer ring of the upper metal surface.

[0056] In a further aspect, a smartphone, a wearable, an earphone, or a monolithic Internet of Things (IoT) device includes a MEMS device according to the foregoing aspects.

[0057] All concepts of the invention described throughout this section and the entire application are, in principle, applicable to CMOS, but may also be applicable to the BEOL of any other solid-state semiconductor process such as BiCMOS, GaAs, SiGe, GaN, SOI, etc.

[0058] Any two or more of the features described in this specification, including this summary section, may be combined to form embodiments not specifically described in this specification.

[0059] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description, drawings, and claims.

Brief Description of the Drawings

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Modes for Carrying Out the Invention

[0061] Like reference numerals in different figures indicate like elements.

[0062] This application addresses defects associated with the fabrication and / or structure of MEMS devices in various aspects.

[0063] In various aspects, systems, devices, and methods etch away some of the silicon oxide in the BEOL (backend of line) of a CMOS process, either resulting from or using vHF etching, thereby liberating the materials present in the BEOL that constitute the MEMS device. The approach of the present invention uses a bottom metal surface and an upper metal surface having an array of small holes to allow vHF to enter inside the MEMS cavity. The key innovative concept is to limit the overall MEMS size on the layout to 50 μm to 150 μm, preferably less than 100 μm. For a certain radius of curvature of a MEMS device or element, the total height of the curvature depends on the horizontal size. Thus, when the device is small enough, the height of the curvature is limited despite a large vertical stress gradient.

[0064] The second innovative concept is the spring design. For such small devices to have excellent performance, small and soft springs are required while maintaining a small height of curvature. These may seem like conflicting requirements. Short springs mean that the springs become very stiff, thus reducing the sensitivity (performance) of the MEMS sensor. To have soft springs, it is necessary to minimize their thickness, which means minimizing or not using the metal stack at all. However, this increases the vertical stress gradient, thereby rapidly increasing the total height of the curvature.

[0065] A preferred and innovative solution to the spring design problem is to use a set of at least three springs, not just one, that are evenly distributed around the device and rotate around the central axis of the device. As a result, due to symmetry, the MEMS device cannot tilt after being released by vHF etching.

[0066] In the case of inertial sensors, the MEMS device includes a central proof mass made of several metal stacks and is thus very flat compared to the surrounding springs. This proof mass may also be larger than the springs in order to have sufficient sensitivity. If one or more of the springs holding this bend, when the proof mass is tilted, although the proof mass itself is relatively flat, it will have a large curvature height. However, if the springs are evenly arranged around it and there are at least three springs, the proof mass undergoes a small vertical displacement due to the curvature of the springs, but since it flattens, it does not contribute to the total vertical height of its large size.

[0067] Figure 1 shows the center and / or proof mass 100 of a MEMS device, which has three springs 102, 104, and 106 made and / or connected around its circumference and evenly arranged. The proof mass 100 also includes an array of etching holes 108. In some implementations, the central mass 100 is circular, the springs 102, 104, and 106 around it are helical, and are made from only one metal layer or only two stacks, or more than two layers. By using circular and rounded shapes for the proof mass 100, the springs 102, 104, and 106, and generally all or as many as possible of the components of the MEMS device, high mechanical stresses that would otherwise accumulate at the sharp corners of the device form are avoided. Next, these rounded shapes facilitate the balance of stress on the springs 102, 104, and 106, which leads to a horizontal tilt. When we use an array of at least three springs 102, 104, and 106 evenly distributed around the central mass 100, we require a horizontal tilt for the central mass 100.

[0068] The number of springs can be increased, so we can use four or more, which will further assist in achieving a horizontal tilt of the central proof mass 100. However, in certain implementations, there are only three springs, because otherwise the overall stiffness of the MEMS device would increase proportionally to the number of springs, thereby reducing its sensitivity.

[0069] In this application, we use the term "inertial sensor" to refer to various devices that sense acceleration. This can include, at a minimum, accelerometers, motion detectors, and bone conduction sensors. The physical principles of these operations are the same, but their differences lie in the frequencies they detect. Therefore, their bandwidths, whether they need to detect direct current (DC), and furthermore, their resolution and / or sensitivity requirements.

[0070] In another implementation, linear pairs of springs disposed on both sides of the proof mass 100 may be used such that each pair of springs is on the same straight line. This solution works because the residual stress in the wire is known to be tensile in most CMOS processes, although the upper metal layer may be excluded. In this way, the height of the curvature is minimized. However, this solution results in a relatively high stiffness, which also depends strongly on the temperature of the device. Therefore, this is a solution that can be applied to some MEMS devices, especially when a particularly high mechanical resonance frequency is required and the temperature dependence of the spring stiffness is not critical.

[0071] If the central part of the MEMS device attached to the proof mass (such as in the case of an inertial sensor) or the spring is thicker than the spring and thus made from a larger stack-up of metal layers, a preferred implementation is that the spring is made using the upper metal layer when we connect the central part of the MEMS or the proof mass to the upper metal surface. This minimizes the parasitic capacitance to the lower metal plate of the spring and the support outer ring.

[0072] Figure 2 is an exploded view of the metal and via layers of a MEMS device 200, not showing SiO2, passivation, and the substrate. Figure 2 depicts an out-of-plane inertial sensor. This is constructed using a 6-metal BEOL CMOS process. The metal layers are numbered from M1 (bottom) to M6 (top). There are five via layers numbered from V1 (between M1 and M2) to V5 (between M5 and M6), and V1 is not used in this particular design. The proof mass has a circular structure and has three spiral springs evenly arranged around it, and the diameter of the proof mass and the springs is 50 μm. The proof mass consists of a stack-up of metal layers M2 to M5, and the springs stack metal layers M4 and M5. The proof mass has concentric rings and is stopped by etching holes that cross it vertically and consists of via layers V2 to V4.

[0073] The upper metal surface has the same diameter and an outer ring with a width of 20 μm around it, which corresponds to a circle with a diameter of 90 μm. There is an array of 0.8-μm holes with a spacing of approximately 5 μm between the centers of two holes in both the X and Y directions. The springs have a surrounding ring with a width of 20 μm around them, which is built in the same layers M4 and M5. There is an array of concentric vias that connect these rings to the upper metal surface on these rings. That is, they are implemented in layers V4 and V5.

[0074] There is a circular bottom metal surface made in M1, which also has a diameter of 50 μm and an outer ring with a width of 6 μm. Therefore, it is smaller than the outer ring of the upper layer for supporting the upper metal surface and the springs. Combining the inner circle and the outer ring corresponds to a circle with a diameter of 62 μm. The difference between the inner circle and the outer ring results from the fact that after vHF etching, the outer ring is partially etched and the edges remain buried (and exposed) in silicon oxide. The upper passivation is opened by a 50-μm circular shape on top of the MEMS device.

[0075] The MEMS device 200 includes an M6 layer 202, a V5 layer 204, an M5 layer 206, a V4 layer 208, an M4 layer 210, a V3 layer 212, an M3 layer 214, a V2 layer 216, an M2 layer 218, and an M1 layer 220. The M6 layer 202 includes an upper plate 222, and the upper plate 222 has an array of etching holes and a connection portion to the ASIC. The V5 layer 204 includes an array of concentric via rings 224 that extend on the outer metal. The M5 layer 206 includes a proof mass upper lid 226 having an array of etching holes. The layer 206 also includes a part of a spiral spring 228 and an outer metal ring 230. The V4 layer 208 includes an array of concentric via rings 232 that extend on the outer metal, a part of the spiral spring 228 that extends in the V4 layer 208, and an array of concentric via rings 236 that extend on the proof mass and surround the positions of the etching holes with a square ring and stop at the positions of the etching holes. The M4 layer 210 includes a proof mass plane 238 with an array of etching holes, a part of the spiral spring 228, and a part of the outer metal ring 230. The V3 layer 212 includes an array of concentric via rings 244 that extend on the proof mass and surround the positions of the etching holes with a square ring and stop at the positions of the etching holes. The M3 layer 214 includes a proof mass metal surface 246 having an array of etching holes. The V2 layer 216 includes an array of concentric via rings 248 that extend on the proof mass, stop at the positions of the etching holes, and surround them with a square ring. The M2 layer 218 includes a proof mass metal bottom lid 250 including an array of etching holes. The M1 layer 220 includes a bottom metal surface 252 including a connection portion to the ASIC.

[0076] A preferred implementation for an accelerometer using a 6-metal layer process where the M1 layer 220 is the bottom layer and the M6 layer 202 is the top layer is as follows. The M1 layer 220 is used to implement the bottom surface, and the M6 layer 202 is used to implement the top metal surface, which is shorted to the proof mass and the spring. The proof mass is implemented using a stack-up from the M2 layer 218 to the M5 layer 206. Also, the spring 228 is implemented using either only the M5 layer 206 or a stack-up of the M4 layer 210 and the M5 layer 206.

[0077] When we set the total diameter of the proof mass and the spring, there are optimal conditions for the length or maximum angle by which the spring rotates. Longer springs (longer total angles) mean that they become softer, but the proof mass becomes smaller. Shorter springs allow for a larger proof mass, but the spring becomes stiffer. Thus, there are always optimal conditions, which depend on specific design and process characteristics. However, in general, it is difficult to construct a highly reliable device with a high yield and a spring having an angle exceeding 360°. That is, it is preferable that the individual springs do not complete a rotation around the circular proof mass.

[0078] Another parameter that affects the design yield, performance, and reliability is the spacing around the spring. That is, it is the horizontal spacing or gap that exists at each point of the spring without any other spring, proof mass, anchor, or part of the device (except at the edges of the spring. These start and eventually fuse with the outer ring or anchor / wall and the proof mass or other MEMS components). This should clearly be at least equal to the minimum spacing set by the design rule check (DRC) of the process. However, in practice, we set it to a higher value between x2 and x10 of this minimum spacing set by the DRC of the process. The preferred value is x5. For example, in a 180nm process with a minimum gap DRC of 300nm between metals, we preferably set this horizontal spacing for the spring to 1.5μm. The trade-off here is that at very large spacings, we reduce the sensitivity and / or performance. This is because we reduce the proof mass area and thus the mass for the same spring length (thus achieving a given softness / rigidity for the spring). However, narrowing this horizontal spacing between the springs results in poor yield and reliability.

[0079] Another important aspect of the springs, which is particularly important when they are soft, such as when using a set of three or more helical springs evenly distributed around a central proof mass, is to make the springs sufficiently short compared to the displacement (both perpendicular, thus out-of-plane, and horizontal, thus in-plane). Since we have a small proof mass and require very soft springs to achieve sufficient sensitivity, this is prone to sticking problems in principle, which leads to poor reliability of the MEMS device.

[0080] Figure 3 is an enlarged view 300 of the M4 layer 210 of the MEMS device of Figure 2. The M4 layer 210 includes a 50 μm circular metal surface 302 inside the proof mass, helical springs 306, an external 20 μm wide ring 304 partially embedded in silicon oxide in the outer part after vHF etching to support the springs and thus the proof mass, and an array 308 of etching holes penetrating the proof mass.

[0081] Figure 4 is an enlarged view 400 of the M5 layer 206 of the MEMS device of Figure 2. The M5 layer 400 includes a proof mass top cover 402 having an array of etching holes, helical springs 404, and an outer metal ring 406.

[0082] Figure 5 is an enlarged view 500 of the V4 layer 208 of the MEMS device of Figure 2. The V4 layer 500 includes a concentric via ring array 502 that extends over the proof mass, stops at the position of each etching hole 504, and surrounds each hole 504 with a square-shaped ring. The layer 500 also includes a concentric via ring array 508 that extends over the outer metal.

[0083] Figure 6 is a non-decomposed 3D view 600 of a metal layer such as the M6 layer 202 including the etching holes of the MEMS device of Figure 2 (thus not showing the remaining silicon oxide, passivation, and substrate). The layer 202 includes an array 602 of etching holes, an outer ring 604, and a connection 606 to the ASIC (upper electrode and proof mass). The M1 layer 220 includes a lower electrode connection 608 to the ASIC.

[0084] FIG. 7 shows a side view 700 of metal layers M1 - M6 and via layers V2 - V5 (since V1 is empty) of the MEMS device of FIG. 2. The side view 700 includes a connection portion 702 to the ASIC (upper electrode and proof mass), an upper metal surface 704, an outer ring 706, a proof mass 708, a bottom metal surface 710, and a lower electrode connection portion 712 to the ASIC.

[0085] FIG. 8 is a schematic cross - sectional view 800 of the MEMS device of FIGS. 2, 6, and 7. The view 800 shows a passivation layer 802, a passivation opening 804, a spring 806, an array of etching holes 808, an outer metal ring 810, an M6 layer 812, a V5 layer 814, an M5 layer 816, a V4 layer 818, an M4 layer 820, a SiO2 deposition portion 822, an M1 layer 824, a V3 layer 826, an M3 layer 828, a V2 layer 830, an M2 layer 832, a bottom metal surface 834, a proof mass 836, an array of concentric via rings 838 inside the proof mass 836, and an array of concentric via rings 840 along the outer metal ring 810.

[0086] The MEMS devices are designed to operate in a linear region. This is because they are of large dimensions and have large springs that make them soft enough despite their thickness, and also because the maximum displacement they can have, which covers all the gaps they have on the sides, above, below, in front, or there, is very small. In this way, the MEMS springs follow Hooke's law and have a constant stiffness, which generates a mechanical restoring force proportional to the displacement.

[0087] In one example, if the displacement is large compared to the length of the spring, the mechanical restoring force begins to be proportional to the displacement, but after a certain initial displacement it is no longer linear and grows faster. Thus, the spring is soft for small displacements around the equilibrium point, where the sensor operates with very good sensitivity. However, when the proof mass experiences a larger displacement, for example, when it is subject to an impact or strong vibration and contacts the surrounding walls, roof, or floor, the mechanical restoring force will increase significantly in each stage at this point. In this way, the MEMS device returns to the equilibrium position and is disengaged from the stiction force by this increased mechanical restoring force at the moment of contact.

[0088] In a more detailed view of this phenomenon, all springs are non-linear. However, while other MEMS devices experience only small displacements, the devices described herein can experience large displacements such that they enter the non-linear region of the mechanical restoring force with respect to displacement before contacting the surrounding walls, roof, or floor.

[0089] We can count the length of the spring in two ways. One is the straight-line distance from one end to the other. The second measurement is the total distance along the full length of the spring following its meandering and curvature. We consider the longest of these measurements as the "length" of the spring. In the implementation described here, the shortest ratio of the minimum displacement at which the spring can come into contact with the surrounding walls, roof, or floor to the length of any spring is at least 1%, but in some designs it can be 5%, or even 10%. This principle will function at lower ratios as well, but the robustness may not be sufficient. However, depending on the specific process and overall implementation, ratios as low as 0.5%, or even 0.1% can yield satisfactory results. Such short ratios are a factor of the MEMS devices described herein that are not seen in other MEMS designs, which enables the implementation of soft springs and short gaps, while realizing high-performance devices that can be packaged with all packaging technologies including WLCSP with high yield and reliability.

[0090] Another innovative concept involves the design of vertical walls, more precisely, the definition of the MEMS area, or the limitation of the lateral etching of silicon oxide, and the mechanical anchors or supports of the MEMS. As previously mentioned, other designs use vertical metal walls or anchors.

[0091] In the first case, using vertical metal walls, we cannot seal the device from the top and / or bottom using the upper and / or bottom metal layers. This means that we require a special CMOS process without doped silicon beneath the bottom metal layer of the BEOL, and / or a special and more expensive packaging technology such as a laminate substrate to properly protect the MEMS cavity from the top, and usually also a more expensive post - processing etching sequence. This can be avoided, in whole or in part, if the MEMS device allows the top and bottom metal surfaces to be electrically short - circuited to the surrounding walls. This is usually not possible.

[0092] The second option of using anchors electrically isolates the upper and lower metal layers, but this generates a large parasitic capacitance between them, which degrades the device performance. Furthermore, any attempt to improve the performance of reducing this parasitic capacitance by reducing the anchor structure or increasing the vHF etching time degrades the device yield and reliability.

[0093] The devices of the present invention have no vertical metal walls or capacitive anchors connecting the upper and lower metal surfaces. Instead, there are two different solutions used by these devices. One solution is to extend components of the MEMS device, such as a spring, disposed between the upper and lower metal surfaces or electrodes, which can also be other electrodes, so that they are horizontally spaced by a sufficient distance where vHF cannot reach and are embedded in silicon oxide. In fact, we have found that long distances are not necessary. For example, in the 180nm CMOS node, 20μm of metal around the MEMS device is sufficient. Thus, there is metal disposed around the released MEMS device, which holds it, and this is because its outer edge has silicon oxide around and / or adjacent to it so that it is not etched. Preferably, this surrounding metal has a circular outer edge, although other shapes will be implemented.

[0094] In the aforementioned solution, we have at least three electrically disconnected components, where the upper metal surface, the lower metal surface, and the components of the MEMS device between them are electrically separated, and more components can be electrically disconnected. Alternative implementations can be applied, where instead of having three or more electrically disconnected components, there are only two components. In this example, a part of the MEMS device may be attached between the upper and lower metal surfaces using a vertical metal wall on one of them but not on the other. In some implementations, the MEMS device is connected to the uppermost one. This is because the upper metal layer is usually not as flat and more curved than the lower metal layer. This is because the lower metal layer is not separated from the underlying silicon oxide. To enhance the mechanical consistency of these external rings, we can use an array of vias to connect them. To make them more robust, instead of the usual square-shaped via array, an array of concentric via rings, such as those used inside the proof mass, can be used. However, in this case, there are no holes passing through the external rings as would occur in the proof mass, so the rings do not need to be segmented and they can be continuous.

[0095] Another implementation aspect that can be applied to these last two options is that we can reduce the dimensions of the bottom metal surface compared to the increasing dimensions of the top metal surface, since we do not use vertical metal walls to short - circuit the top and bottom metal surfaces, nor do we couple them with capacitive anchors. The reason for this is that the lateral over - etching is greater for the top metal than for the bottom metal layer. This is because vHF has to etch first and reach there first in order to etch the bottom metal layer. The lateral over - etching is the distance from the outermost edge of the passivation opening window on the MEMS device that we need to release, to the outermost position where there is silicon oxide that is etched after the vHF post - processing step. That is, instead of using metal vertical walls that short - circuit from top to bottom and not using capacitive anchors either, we surround the MEMS device with a metal region that extends into the surrounding silicon oxide. A part of this metal region has the surrounding silicon oxide that is etched during the vHF step, but beyond a certain point it is no longer etched.

[0096] This approach reduces the parasitic capacitance between the top and bottom metal surfaces, which is also the parasitic capacitance between the top or bottom metal surface and the movable part of the MEMS device when we use the second approach, i.e., when we shorten a part between the top and bottom metal surfaces using one of these vertical surfaces or connections. This reduction in parasitic capacitance improves the sensitivity or performance of the device.

[0097] The size for reducing the width of the outer ring in the lower metal plate compared to the upper metal plate depends on the CMOS process and the overall design. However, in some implementations, it is from 10% to 50%, with 30% being a preferred value. In some implementations, the width for the outer ring of the upper metal plate is 20 μm, which means that the outer ring width in the bottom metal plate can have a preferred dimension of 6 μm. If the central disk (proof mass and spring) has a diameter of 50 μm, the total dimension of the upper plate is 90 μm, and the diameter for the entire bottom plate can be 62 μm.

[0098] We fix a part between the upper and bottom metal surfaces by the metal region, and around this part, there extends a metal region that will be embedded in unetched silicon oxide. Then, we can also create them with dimensions smaller than the upper metal surface but larger than the bottom metal surface. In this case, due to their over-etching, there is somewhat between the upper and bottom metal surfaces. In some implementations, the outer ring width for this intermediate plate or multiple plates is 30% - 70% of the ring width for the upper metal surface. In one implementation, the value will be 50%. However, ultimately, it depends on the specific CMOS process and the overall design. If the upper metal surface has a circular shape, it can include an internal disk adjacent to the outer ring surrounding it. The internal disk can have an array of holes there that allow vHF to enter inside the MEMS cavity, while the outer ring is solid (with possible exceptions as described below for constructing trenches to electrically insulate most of this outer ring).

[0099] The expansion of the internal disk is, in principle, the expansion of the MEMS that we want to release by vHF. However, another innovative concept is to reduce the expansion of the inner disk and not place release holes around the outer part of the MEMS that needs to be released for this purpose. Since vHF can travel relatively long distances, all MEMS are released, and we can minimize the over-etching of the external rings in all metal layers, thereby reducing the dimensions of those external rings. This reduces the parasitic capacitance between the upper and lower metal plates and thus enhances the performance of the MEMS. When using this reduced expansion for the release holes, the passivation opening can also be reduced, as we only need to open it over the area where we have an array of holes.

[0100] The reduction of the internal disk that we can implement depends on the CMOS process. In one implementation, it is 2μm to 20μm on each side, and the preferred value is 6μm. That is, the disk diameter is reduced between 4μm and 40μm, and the preferred diameter reduction is 12μm. By implementing this reduction of the internal disk, the external rings can be reduced to the same value in all metal layers having such external rings. For clarity, the internal disk and the external rings are discussed, but in reality, the layout of the upper metal layer is a single disk. Next, an array of etching holes is placed in the center and covers the area defined by the dimensions of the internal disk. Thus, the surrounding solid area without etching holes can be called the external ring. Also for clarity, when we say that we reduce the internal disk, this does not affect the dimensions for the proof mass, spring, or other parts of the MEMS device that need to be released. The internal disk here only defines the area on the MEMS device or on the part that needs to be released and has an array of etching holes.

[0101] The above description is also valid when there are several electrically isolated components between the top and bottom metal layers. In such cases, each has its own metal extension embedded in silicon oxide, which are electrically isolated from each other, but there is always some electrical parasitic capacitance between them.

[0102] A preferred approach is to have this external metal region for supporting MEMS components between the top and bottom metal surfaces, surrounding all MEMS released internally, to provide better mechanical consistency, but this is not strictly necessary. This can be particularly beneficial in the above cases where there are two or more electrically isolated MEMS components between the top and bottom metal layers. An example of this is for in-plane inertial sensors, which have several side electrodes arranged to sense accelerations in different directions.

[0103] Another variant for reducing the parasitic electrical capacitance between the top metal surface (or, for example, the middle part of the MEMS device if it is electrically shorted to it using a vertical metal connection to it) and the bottom metal surface is to add very short trenches around all top metal surfaces that need to be released at a certain distance from the MEMS that needs to be released. In some implementations, this trench is placed at half of the over-etching distance. In one configuration, this is about 10 μm because the total length of this metal region around the MEMS is about 20 μm. However, the distance can be made shorter, down to 5 μm or even zero. Preferably, it is placed at a distance of 5 μm to 15 μm. Also, the extension of the top metal plate can be at a distance of about 20 μm. However, depending on the specific CMOS process characteristics, the overall MEMS design, and the required vHF characteristics and recipe, it can be from 5 μm to 30 μm.

[0104] The width of the trench should be minimized as permitted by the process. This width can be 0.8 μm, but in some implementations, it can range from 0.5 μm to 2 μm depending on the process and, in particular, the thickness of the upper metal layer. A metal ring can be implemented over this trench to maintain passivation. In this trench, the outer ring is split into two parts, one inside the other, which are electrically isolated and also mechanically cut. There is some parasitic capacitance between them, and since they are ultimately connected to silicon oxide, they do not move relative to each other.

[0105] Therefore, it may be questioned why we need to maintain the outer part of this split outer ring. The reason is that there is over-etching during the vHF post-processing step, so the silicon oxide placed between the passivation and this upper metal layer is removed by etching, making the passivation very brittle. For this reason, it is preferable to maintain the outermost metal ring in case the passivation breaks, so that it can be supported. However, depending on the process characteristics and the overall design, it may be possible to simply remove this outer part of the outer ring and, instead of constructing a trench for the outer ring, simply reduce its diameter. This would further reduce the parasitic capacitance.

[0106] A preferred implementation has short vertical metal walls that surround the MEMS device and are connected to the upper metal surface. This vertical metal wall may or may not be connected to the movable part of the MEMS, such as a spring anchor, etc., disposed between the upper and bottom metal surfaces. The purpose of this short (i.e., not reaching down to the bottom metal surface) wall is to prevent vHF from etching horizontally under the upper metal surface towards its outer edge, forcing the vHF to first descend the vertical wall and then return upwards so that it can etch under the upper metal surface towards the outer edge. Depending on the implementation, this short vertical metal wall can also provide mechanical integrity and / or electrical connections to other components of the MEMS device (such as the anchor of a spring, etc.).

[0107] Another implementation that achieves mechanically connecting two parts of a MEMS without electrically short - circuiting them without using capacitive anchors is to use a MIM layer in the MEMS process. This layer is typically not etched away by vHF or is etched at least slowly, which depends on a particular CMOS process. This provides a more compact solution than capacitive anchors. However, the capacitance tends to be larger and the mechanical robustness may not be sufficient. However, in some implementations, depending on the MEMS device, process, and overall design, it may still be beneficial. In some implementations, it may also be beneficial to use horizontal capacitive anchors instead of vertical capacitive anchors. In some configurations, a hybrid design can be implemented while implementing feed - throughs through connections to MEMS metal walls or surfaces using the same design principle as any type or combination of types of capacitive anchors.

[0108] The array of holes in the upper metal surface 222 is made as small as possible. They may be smaller than what is allowed by the DRC of the process, but are sufficient to ensure opening through all of the upper metal thickness. This minimum dimension depends on the particular CMOS process, especially the upper metal thickness. In some implementations, the dimension is 0.8 μm in width. Below this, usually they are difficult to fully open, which will result in a low production yield. As will be described later, when we apply the sealing layer, larger values may not be properly met. So there is a trade-off, and when patterning the upper metal layer during the CMOS process, we can't have holes that are too small to open nor holes that are too large to be properly sealed during later packaging. Therefore, in some implementations, the hole dimension is from 0.5 μm to 1.5 μm, and the preferred value is 0.8 μm. However, depending on the CMOS process, upper metal thickness, sealing material, thickness, and the process being used, the etched hole dimension can vary. In some implementations, when the holes are very small, they are depicted as square-shaped holes. This is because in fact, as we push forward with the process solution, any other shape doesn't make any difference, and also during the manufacture of the device, they are all somewhat rounded anyway.

[0109] The separation between the upper metal surfaces, e.g., the holes on the upper plate 222, may be similar to the vertical length of the vertical distance from the upper to the bottom metal layers M1 to M6. In some configurations, the etching holes are horizontally spaced on the upper metal layer 222 up to a distance of at least twice this vertical distance between M1 and M6. In some implementations, considering that vHF etches slowly in the vertical direction compared to the horizontal direction due to multiple oxide sub-layers with different densities and etching rates, the distance can be larger. The goal is that the holes can be placed close enough since we want to etch all the capacitances inside the MEMS cavity properly, but at the same time, to prevent as much as possible the formation of a weak upper metal surface with a very large number of holes and little metal remaining, which, as will be described later in the specification, might not be able to withstand the sealing on its top when the device is packaged.

[0110] We have experimentally found that a sufficient value is to space the etching holes at a distance of 50% to 200% of the height of the metal stack. This height is counted from the lowest point of the bottom metal layer M1 to the uppermost point of the upper metal layer, e.g., M6. A preferred value is to separate the holes at a distance equal to this height (e.g., 100%). The distance between the holes is measured in both the horizontal (X) and vertical (Y) directions from the center of one hole to the center of another hole.

[0111] An identical array of holes is implemented that penetrates all MEMS devices within the cavity to allow the vHF to drop to the lowest level of silicon oxide so that all silicon oxide that needs to be removed is properly etched in all cavities. This can be shifted laterally with respect to the holes in the upper metal surface, but the preferred implementation is to simply position them in the same location. These holes can be surrounded by via walls to prevent the vHF from passing through the interior of these holes and etching the silicon oxide that we want to remain unetched when passing through structures with silicon oxide trapped inside, such as proof masses. Considering the small size of these holes, which can preferably be made square-shaped, these via barriers can be implemented as square rings.

[0112] The fourth innovative concept is the use of a sealing layer present in the WLCSP process, also called repassivation, which generally consists of polyimide (PI), although benzocyclobutene (BCB) etc. can also be used to seal the MEMS cavity. This avoids the need for a specific aluminum sputtering and patterning process, reducing the complexity and cost of post-processing, which is further reduced only for vHF etching and post-backing. In addition to this, the use of PI or BCB has been found to provide a better seal and cover the array of holes in the upper metal layer better. In contrast, aluminum sputtering requires a very thick deposition, and yet, due to the orthogonality of the deposition, some holes may not be properly sealed. This does not occur with PI, which seals all holes very well. In examples including other types of packages that are not WLCSP, the process can apply PI or BCB or other coatings and patterning (even aluminum sputtering, which may not be ideal but can be done with a sufficient thickness and appropriate set of parameters), and then continue with the packaging process.

[0113] Another important inventive concept involves not using metal fill structures within the MEMS cavity. To compensate for metal residual stress, the CMOS design needs to have a certain metal density across all regions of the ASIC. To achieve this, once the ASIC design is complete, an automated process called "metal fill" is executed, which fills all empty regions with random small metal shapes to achieve the required target metal density. This metal fill should not be performed within the MEMS cavity. Otherwise, after applying vHF, all these small metal fill structures will be released, and they may adhere to the MEMS device due to stiction, preventing it from operating properly or not operating at all.

[0114] All the descriptions given in this application can be applied to different CMOS nodes, different metal stacks, and even different solid-state semiconductor processes. Also, when we describe the top metal layer and the bottom metal layer, these are usually the topmost and bottommost metal layers of the process layer stack. However, it may also be applicable to other metal layers. When constructing an inertial sensor in a 6-metal layer process, we usually need all the available metal layers to maximize the thickness, and thus the mass, of the sensor proof mass. However, if the process has more available metal layers, or if we are constructing another type of MEMS device, or even for an inertial sensor, if we can somehow achieve the required specifications, we may not need to use all the available metal layers in the metal stack. In this case, we preferably use what is placed on top and thus leave the metal layer placed at the bottom as used in the ASIC to make electrical connections to the ASIC. In this case, there is no dedicated area for mounting the MEMS. Instead, the MEMS is mounted on the ASIC.

[0115] In all cases, the active area (FEOL) under the MEMS can be used to implement the ASIC. However, if there are no available metal layers for connections, they are all used for implementing the MEMS, so it is difficult to implement useful parts of the ASIC under the MEMS. However, depending on the process and the specific ASIC design, it may be beneficial to implement large transistors or other circuits that require little wiring, and / or polysilicon lines can be used for this wiring if available. If not all metal layers of the process stack are used for implementing the MEMS, all descriptions in this application should be understood as follows. "Upper" and "lower" metal layers are the top and bottom of the metal layers used for implementing the MEMS device, not the top and bottom of the metal stack. Preferred embodiments include using circular and rounded shapes, but the disclosed invention can be applied to other types of shapes.

[0116] Yet another important invention concept includes sense electronics that interface with the MEMS when they are capacitive MEMS sensors such as, without limitation, accelerometers, bone conduction sensors, motion detectors, ultrasonic sensors, or any other capacitive sensors. In one implementation, the MEMS capacitance sensors herein uniquely include small capacitances. This is also due to the small dimension unique functions and minimum parasitic capacitances resulting from some of the conceptions described above, as well as due to the proximity of the ASIC attached to the MEMS edge, eliminating the need to wire the MEMS to another die where the ASIC is located, and also eliminating the need to even connect to the top of the wafer where the ASIC is located when using wafer bonding methods or building the MEMS on an ASIC CMOS wafer.

[0117] In some implementations, the capacitance of current MEMS sensors is on the order of 10 fF to 100 fF or about 50 fF. This is about one-hundredth of commercially available MEMS devices for household appliances. This enables the implementation of a completely different sensing method that cannot be achieved with other MEMS devices because it implies too much power consumption.

[0118] In some configurations, the sensing of MEMS capacitance is performed by constructing a ring oscillator, where at least one of the capacitances of the loop is a MEMS device as described herein. This ring oscillator powers a counter that is read and reset every sample period. The output of the counter is already digital, which outputs the capacitance value. This approach has many technical advantages. First, it simplifies the analog design, which is digital except for the only exception of the ring oscillator. This means that there are many analog blocks that we need and avoid in other methods, such as, among others, transconductance amplifiers, programmable gain amplifiers, A / D converters, analog filters, choppers, and capacitance mismatch compensation. This simplification has many technical advantages, including smaller ASIC area, very low manufacturing cost, shorter design time, very short time to market, reduced development cost, easy porting to other CMOS nodes and processes, and reduced power.

[0119] Lower power consumption results from avoiding a very large number of analog blocks that consume large amounts of power. However, in exchange for these blocks, the process involves continuously charging and discharging the MEMS sensor capacitance at a very high frequency. This high frequency can be between 10 MHz and 100 MHz, but depends on the MEMS design, the CMOS process, and the target specifications for the sensor. This would consume excessive power for a normal capacitance on the order of a few pF. However, for current MEMS sensors with capacitances on the order of less than one-hundredth, this shows more, but actually less, power consumption, and in addition to the other advantages described above for this sensing method, makes the unique sensor very power efficient.

[0120] A ring oscillator can vary its frequency according to many factors such as the supply voltage and its noise, temperature, and even process variations. To compensate for this, a second ring oscillator can be implemented, which uses another MEMS device constructed very close to the first ring oscillator. Thereby, it sees almost the same process, voltage, and temperature variations. This second MEMS device (or devices if multiple MEMS are included in the ring oscillator loop) is slightly different and has a stiffer spring. Preferably, this is made using a wider and / or thicker spring (i.e., using more metal stack-up). Thus, the capacitance reading value from the counter connected to this second sensor hardly moves for the magnitude (e.g., acceleration in the case of an accelerometer) measured by the sensor, but it varies in the same way as the first sensor for all other factors such as supply voltage, process, and temperature changes.

[0121] In one implementation, the two ring oscillators operate different counters until the second ring oscillator reaches a predetermined value. In this case, we read the first counter, which gives us the value of the sensed magnitude. We then reset the two counters and resume counting. This predetermined value can be programmable, so that we can define different sampling frequencies. When the sampling frequency is low, the ring oscillator and / or counter are disabled between samples, thus minimizing power consumption. In some implementations, a third digital counter with a very slow digital clock is included to operate the device each time a new sample needs to be acquired.

[0122] In some implementations, a metal wall is constructed and / or formed around the entire perimeter of the MEMS device to increase the proof mass without increasing its dimensions. In this way, silicon oxide is trapped inside the proof mass and is not etched away by vHF. This is further because the proof mass with many vias is made of tungsten, which has a higher density than silicon oxide and aluminum, the materials of the metal layer. To further increase the effective density and total mass of the proof mass, a via array larger and closer than what is allowed by the DRC of the process can be implemented. In the case of a circular proof mass, we can also use concentric via rings spaced at the same distance as the thickness of the ring, preferably making this distance and the width of the ring equal to the via dimensions and via spacing defined by the CMOS process DRC. The vias of the CMOS process generally need to be squares of fixed dimensions, but in practice, we can expand these vias in one dimension, but at least, we need to maintain the specified via dimensions in the other dimension. Otherwise, the wafer will not be properly fabricated. Since we need to make holes throughout the proof mass, these circular rings may need to be interrupted around the holes. Other shapes can be implemented for both the proof mass and the ring, or for the via filling structure inside them.

[0123] Another important inventive concept involves pad modification. This is because there are passivation openings not only on the MEMS device but also on each pad, i.e., aligned perpendicular to the pad. This is why there are passivation openings in the CMOS process. This means that when vHF is applied in post - processing, the oxide under the passivation (i.e., between the passivation and the upper metal layer) is etched away. If the upper metal layer in the pad is not large enough, the silicon etching will go beyond it and etch under the passivation without the lower metal. When this occurs, a lot of silicon oxide around the pad is etched away, and the upper passivation will ultimately have no oxide underneath at all. As a result, the passivation breaks, and a lot of silicon oxide is etched away, which may damage part of the ASIC electronic circuit. The implementation to solve this technical problem is to expand at least the upper metal layer more than the conventional pad design (and if we expand more or all of the other metal layers for better consistency). This expansion depends on the specific process applied and the details of the vHF etching. In some implementations, the metal has a lateral expansion of 15 μm to 25 μm beyond the passivation opening in all directions. In one implementation, this expansion is 20 μm. There is no need to use a rounded shape, so in various implementations, the pad maintains a square design for the passivation opening and thus for the metal that defines it. However, other shapes are also implemented.

[0124] Most of the innovative concepts disclosed in this specification can be applied to many different devices, including, but not limited to, inertial sensors, gyroscopes, pressure sensors, ultrasonic sensors, transducers such as CMUTs, loudspeakers, magnetometers and compasses, microphones, RF switches, adjustable capacitors, RF inductors, temperature sensors, and many others. To avoid the need for a CMOS foundry to increase the silicon content of passivation, we can use, for example, special recipes and / or equipment developed by Memsstar (Scotland). After the vHF etching step, we bake the wafer to sublime fluorine residues.

[0125] Due to the smaller size, cost, and higher performance of the MEMS devices disclosed herein, as well as their mass production capabilities and short time to market, the concepts of the present invention enable the construction of smaller, higher performance smartphones, wearables, and earphones, which have longer lifetimes and autonomy due to more functions and more space for larger batteries. These sensors are also enablers for many mono Internet of Things (IoT) applications, where there are requirements for very low power consumption (high performance), yet very low cost and small size sensors that are produced in very large quantities. Another application is RFID with embedded sensors.

[0126] Figure 9 is an exploded view of the metal layer and via layer of a MEMS device 900 including side electrodes. Figure 9 shows a variation of the implementation of Figure 2, which senses planar acceleration including side electrodes around the bottom of the proof mass without springs. That is, the proof mass is composed of four metal layers M2 to M5. The springs are made of metal layers M4 and M5 and have outer metal rings supporting them. Therefore, the proof mass does not use metal around it in layers M2 and M3. In this way, we use layers M2 and M3 to construct side electrodes for the proof mass. The shape of these side electrodes is essentially similar to the outer rings of the above metal layers (M4 and M5), but instead of the whole ring, there are two half rings. Each of these half rings is made of two available metal layers (M2 and M3) stacked together, which means there are many vias inside to connect them. These vias are formed as an array of concentric half rings.

[0127] The outer diameter of these side electrodes is shorter than the outer ring of the upper metal layer. In this design, it is made shorter than the bottom metal surface, but it would be an improvement to make the diameter of the bottom metal surface smaller than the outer diameter of these side electrodes.

[0128] Since we maintain the bottom metal surface, we can still sense out-of-plane acceleration as well. Therefore, the MEMS device has several electrodes, which can be fully sensed in 1, 2 or even 3 axes by the same device. This is possible when these are divided into quarter rings instead of dividing these side electrodes into half rings. Furthermore, differential capacitance can be implemented in the X and Y axes (i.e., in-plane acceleration). This design is for inertial sensors, but the same design principles (electrodes, spring support, etc.) can be used to implement other types of capacitive sensors and actuators.

[0129] The MEMS device 900 includes an M6 layer 902, a V5 layer 904, an M5 layer 906, a V4 layer 908, an M4 layer 910, a V3 layer 912, an M3 layer 914, a V2 layer 916, an M2 layer 918, and an M1 layer 920. The M6 layer 902 includes an upper plate 922 having an array of etching holes and connections to the ASIC. The V5 layer 904 includes an array of concentric via rings 924 extending on the outer metal. The M5 layer 906 includes a proof mass upper lid 926 having an array of etching holes. The layer 906 also includes a part of a spiral spring 928 and an outer metal ring 930. The V4 layer 908 includes an array of concentric via rings 932 extending on the outer metal, a part of the spiral spring 928 extending to the V4 layer 908, and an array of concentric via rings 936 extending on a proof mass that stops at the positions of the etching holes and surrounds them with a square ring. The M4 layer 910 includes a proof mass plane 938, a part of the spiral spring 928, and a part of the outer metal ring 930. The V3 layer 912 includes an array of concentric via rings 944 that extend on the proof mass, stop at the positions of the etching holes while surrounding those positions with a square ring. The M3 layer 914 includes a proof mass metal surface 946 having an array of etching holes and side electrodes 954 having connections to the ASIC. The V2 layer 916 includes an array of concentric via half-rings 948 that extend on the proof mass, stop at the positions of the etching holes, and surround them with a square ring. The V2 layer 916 also includes an array of concentric via half-rings 956 that extend on the side electrodes. The M2 layer 918 includes a proof mass metal bottom lid 950 having an array of etching holes. The M2 layer 918 also includes side electrodes 958. The M1 layer 920 includes a bottom metal surface 952 having connections to the ASIC.

[0130] The elements or steps of the different implementations described can be combined to form other implementations not specifically recited. Elements or steps can generally be excluded from the systems or processes described above without adversely affecting their operation or the operation of the system. Further, various distinct elements or steps can be combined with one or more individual elements or steps to perform the functions described herein.

[0131] Other implementations not specifically described in this specification are also within the scope of the following claims.

Claims

1. A MEMS device formed using materials of the BEOL of a CMOS process, wherein vHF post-treatment and post-backing are applied to form the MEMS device, the total dimensions of the MEMS device are from 50 μm to 150 μm, comprising pads, the pads including an upper metal layer arranged such that passivation openings vertically aligned extend laterally by more than 15 μm to 25 μm in all directions, a MEMS device.

2. The MEMS device according to claim 1, wherein the total dimensions of the MEMS device are less than 100 μm.

3. The MEMS device according to claim 1 or 2, further comprising a set of at least three springs evenly dispersed around the MEMS device and rotated around the central axis of the MEMS device.

4. The MEMS device according to any one of claims 1 to 3, wherein the shape of the MEMS device is circular and the springs have a spiral shape.

5. The MEMS device according to any one of claims 1 to 4, wherein the springs are made by either a single metal layer or a stack-up of at least two metal layers.

6. The MEMS device according to any one of claims 1 to 5, wherein the MEMS device is an inertial sensor.

7. Comprising a proof mass, the proof mass made from a stack-up of four metal layers and the springs, the springs being made by and connected to the upper metal layer of the proof mass forming the stack-up or connected to two upper metal layers of the stack-up, the MEMS device according to any one of claims 1 to 6.

8. The MEMS device according to any one of claims 1 to 7, wherein a part of the springs is connected to an outer ring such that it remains embedded in silicon oxide on its outer edge after vHF etching.

9. The MEMS device according to any one of claims 1 to 8, having an upper metal surface and a bottom metal surface smaller than the upper metal surface.

10. The MEMS device according to claim 9, wherein the width of the outer ring of the bottom metal surface is equal to or less than 10% to 50% of the width of the outer ring of the upper metal surface.

11. The MEMS device according to any one of claims 1 to 10, which is formed in a MEMS cavity that does not include a metal filling structure.

12. A MEMS device, comprising a set of at least three springs that are evenly distributed around the MEMS device and are rotated around the central axis of the MEMS device, and comprising a proof mass, the proof mass being made from a stack of four metal layers and the springs, the springs being connected to the upper metal layer of the proof mass that forms the stack, or being connected to two upper metal layers of the stack.

13. The MEMS device according to claim 12, wherein the shape of the MEMS device is circular and the springs have a spiral shape.

14. The MEMS device according to claim 12 or 13, wherein the springs are made by one of a single metal layer and a stack of at least two metal layers.

15. The MEMS device according to any one of claims 12 to 14, wherein the MEMS device is an inertial sensor.

16. A MEMS device comprising a spring, wherein the ratio of the maximum displacement to the length of the spring is at least 1%, and the proof mass is made by a stack of four metal layers and the spring, the spring being connected to the upper metal layer of the proof mass that forms the stack, or being connected to two upper metal layers of the stack.

17. A part of the spring is connected to an external ring such that it remains embedded in silicon oxide on its outer edge after vHF etching, and the width of the outer ring of the bottom metal surface is equal to or less than 10% to 50% of the width of the outer ring of the upper metal surface. The MEMS device according to claim 16.

18. A method for manufacturing a MEMS device using materials of the BEOL of a CMOS process, applying vHF post-treatment and post-backing to form the MEMS device, and forming pads, the pads including an upper metal layer arranged such that passivation openings aligned vertically extend laterally by more than 15 μm to 25 μm in all directions. A method including that the total dimension of the MEMS device is 50 μm to 150 μm.

19. The method according to claim 18, wherein the total dimension of the MEMS device is less than 100 μm.

20. The method according to claim 18 or 19, further including forming a set of at least three springs that are evenly distributed around the MEMS device and rotated around the central axis of the MEMS device.

21. The method according to any one of claims 18 to 20, including forming the device shape into a circle, and the spring having a spiral shape.

22. The method according to any one of claims 18 to 21, including forming the spring by one of a single metal layer and a stack-up of at least two metal layers.

23. The method according to any one of claims 18 to 22, wherein the MEMS device is an inertial sensor.

24. The method according to any one of claims 18 to 23, including forming a proof mass, the proof mass being made from a stack-up of four metal layers and the spring, and the spring being connected to the upper metal layer of the proof mass forming the stack-up or connected to two upper metal layers of the stack-up.

25. The method according to any one of claims 18 to 24, including connecting the spring to an external ring such that a part of the spring remains embedded in silicon oxide on its outer edge after vHF etching.

26. The method according to any one of claims 18 to 25, including forming the MEMS device having an upper metal surface and a bottom metal surface smaller than the upper metal surface.

27. The method according to claim 26, including forming the width of the outer ring of the bottom metal surface to be equal to or less than 10% to 50% of the width of the outer ring of the upper metal surface.

28. The method according to any one of claims 18 to 27, including forming the MEMS device in a MEMS cavity without a metal filling structure.

29. Including forming a set of at least three springs that are evenly distributed around the MEMS device and rotated around the central axis of the MEMS device. A method for manufacturing a MEMS device, including forming a proof mass, the proof mass being made from a stack of four metal layers and the spring, the spring being connected to the upper metal layer of the proof mass forming the stack, or being connected to two upper metal layers of the stack.

30. The method according to claim 29, including forming the shape of the MEMS device into a circle and forming the spring into a spiral shape.

31. The method according to claim 29 or 30, including forming the spring by one of a single metal layer and a stack of at least two metal layers.

32. The method according to any one of claims 29 to 31, wherein the MEMS device is an inertial sensor.

33. A method for manufacturing a MEMS device, including forming a spring in which the ratio of the maximum displacement to the length of the spring is at least 1%, connecting the spring to an outer ring such that a part of the spring remains embedded in silicon oxide on its outer edge after vHF etching, and forming the width of the outer ring of the bottom metal surface to be equal to or less than 10% to 50% of the width of the outer ring of the upper metal surface.

34. A method according to claim 33, including forming a proof mass, the proof mass being made from a stack of four metal layers and the spring, the spring being connected to the upper metal layer of the proof mass forming the stack, or being connected to two upper metal layers of the stack.

35. A smartphone, wearable, earphone, or single Internet of Things (IoT) device including the MEMS device according to any one of claims 1 to 17.

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