Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes a base substrate, a plurality of first connection wires, and a plurality of second connection wires. The base substrate includes a display region having a first display region and a second display region, the first display region including a plurality of first light-emitting elements and a plurality of second light-emitting elements, and the second display region including a plurality of first pixel circuits and a plurality of second pixel circuits. At least some of the first connection wires extend along a first direction, at least some of the second connection wires extend along the first direction, at least some of the first connection wires are located on a first side of a row in which first electrodes of the first light-emitting elements and the second light-emitting elements are located in a second direction, and at least some of the first connection wires are located on a second side of a row in which first electrodes of the first light-emitting elements and the second light-emitting elements are located in the second direction.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202010483701.0 filed on June 1, 2020, and the full text of the Chinese patent application is incorporated herein by reference and made a part of this application.

[0002] Embodiments of the present disclosure relate to a display substrate and a display device.

Background Art

[0003] Currently, displays used in electronic devices are developing in the direction of larger screens and full screens, enabling users to have a better visual experience. Taking electronic products such as mobile phones and tablet computers as examples, these electronic devices need to operate in combination with components such as cameras and optical sensors. Since these components generally occupy the display area of the display screen, it is difficult to achieve the design of a full-screen display screen. In order to ensure the light transmittance of the area where the camera is located on the display screen and the shooting effect of the camera, only the light-emitting elements of the pixel circuit are retained in the area where the camera is located.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a display substrate, the display substrate having a first side for display and a second side facing the first side, and including a base substrate, a plurality of first connection wirings, and a plurality of second connection wirings. The base substrate includes a display area including a first display area and a second display area at least locally surrounding the first display area, the first display area including a first sub-pixel array and allowing light from the first side of the display substrate to at least locally pass through to the second side of the display substrate, the first sub-pixel array including a plurality of light-emitting elements including a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged in an array, the second display area including a first pixel circuit array including a plurality of first pixel circuit units, the plurality of first pixel circuit units including a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of first connection wirings extending at least locally along a first direction and connecting the plurality of first pixel circuits and the plurality of first light-emitting elements in a one-to-one correspondence such that the first pixel circuits are configured to drive the first light-emitting elements by the first connection wirings, the plurality of second connection wirings extending at least locally along the first direction and connecting the plurality of second pixel circuits and the plurality of second light-emitting elements in a one-to-one correspondence such that the second pixel circuits are configured to drive the second light-emitting elements by the second connection wirings, each of the plurality of light-emitting elements including a first electrode, the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements being arranged in the same row along the first direction, in the first display area, at least a part of the plurality of first connection wirings being located on a first side of the row in the second direction where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located, at least a part of the plurality of first connection wirings being located on a second side of the row in the second direction where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located, the second direction intersecting the first direction, and the first side and the second side of the row in the second direction where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located being opposite to each other in the second direction.

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, in the first direction, the plurality of first light-emitting elements are located on a side closer to the second display region of the plurality of second light-emitting elements.

[0006] For example, in a display substrate according to at least one embodiment of the present disclosure, each of the plurality of first connection wirings includes a first main body portion and at least one first bent portion. The first main body portion extends along the first direction and is located on a first side of a row where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located. The first main body portion is connected to the first electrodes of the plurality of first light-emitting elements in a one-to-one correspondence. The at least one first bent portion is connected to the first pixel circuit and the first main body portion. The at least one first bent portion extends from the first pixel circuit to the first side of the first pixel circuit, so that the first main body portion is separated from the first electrodes of the plurality of first light-emitting elements in the first display region.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, at least a part of the at least one first bent portion extends along a third direction toward the first side of the first pixel circuit. The third direction intersects the first direction and the second direction.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, at least one first bent portion of the plurality of first connection wirings includes a first sub-bent portion. The first sub-bent portion is located on the first side of the first pixel circuit and extends along the third direction. The first sub-bent portion is connected to the first pixel circuit and the first main body portion. One of the first pixel circuits connected to the first sub-bent portion is adjacent to the second pixel circuit.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, at least one first bending portion of at least one of the plurality of first connection wirings extends from a second side of the first pixel circuit to a first side of the first pixel circuit, and includes a second sub-bending portion, a third sub-bending portion, a first sub-connection portion, and a second sub-connection portion. The first sub-connection portion and the second sub-bending portion are located on the second side of the first pixel circuit. The second sub-bending portion extends along the third direction. The first sub-connection portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion. The second sub-connection portion extends along the second direction and is located between two adjacent first pixel circuits. The second sub-connection portion is connected to the second sub-bending portion and the third sub-bending portion. The third sub-bending portion is located on the first side of the first pixel circuit. The third sub-bending portion extends along the third direction and is connected to a first main body portion of the first connection wiring. The second side and the first side of the first pixel circuit face each other in the second direction.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, at least one first bending portion of at least one of the plurality of first connection wirings includes a second sub-bending portion, a third sub-bending portion, a first sub-connection portion, and a second sub-connection portion. The first sub-connection portion and the second sub-bending portion are located on the second side of the first pixel circuit. The second sub-bending portion extends along the third direction. The first sub-connection portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion. The second sub-connection portion extends along the second direction and is located between an adjacent first pixel circuit and a second sub-pixel circuit. The second sub-connection portion is connected to the second sub-bending portion and the third sub-bending portion. The third sub-bending portion is located on the first side of the first pixel circuit. The third sub-bending portion extends along the third direction and is connected to a first main body portion of the first connection wiring. The second side and the first side of the first pixel circuit face each other in the second direction.

[0011] For example, in the display substrate according to at least one embodiment of the present disclosure, each of the plurality of second connection wirings includes a second main body portion, and the second main body portion extends along the first direction and is located on the second side of the row where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located. The second main body portion is connected to the first electrode of the second light-emitting element and the second pixel circuit. In the first display region, the orthographic projection of the main body portion of the second connection wiring on the base substrate overlaps with the orthographic projection of at least one of the plurality of second light-emitting elements and the first electrodes of the plurality of first light-emitting elements on the base substrate.

[0012] For example, in the display substrate according to at least one embodiment of the present disclosure, the first main body portions of the plurality of first connection wirings and the second main body portions of the plurality of second connection wirings are installed in parallel in the first direction.

[0013] For example, in the display substrate according to at least one embodiment of the present disclosure, the plurality of first connection wirings and the plurality of second connection wirings are transparent conductive wirings.

[0014] For example, the display substrate according to at least one embodiment of the present disclosure further includes a first insulating layer, a second insulating layer, a third insulating layer, a first transparent wiring layer, and a second transparent wiring layer. The first insulating layer is located on the side of the base substrate away from the plurality of first pixel circuits and the plurality of second pixel circuits. The second insulating layer is located on the side of the base substrate away from the first insulating layer. The third insulating layer is located on the side of the base substrate away from the second insulating layer. The first transparent wiring layer is located between the first insulating layer and the second insulating layer. The second transparent wiring layer is located on the side of the base substrate away from the second insulating layer. The first electrodes of the plurality of first light-emitting elements are located on the side of the base substrate away from the third insulating layer. The first transparent wiring layer includes one of two adjacent ones of the plurality of first connection wirings and one of two adjacent ones of the plurality of second connection wirings. The second transparent wiring layer includes the other one of two adjacent ones of the first connection wirings and the other one of two adjacent ones of the plurality of second connection wirings.

[0015] For example, the display substrate according to at least one embodiment of the present disclosure further includes a plurality of pixel circuit connection holes located in the second display region and including a plurality of first pixel circuit connection holes and a plurality of second pixel circuit connection holes. The first pixel circuit connection holes penetrate the first insulating layer, and the second pixel circuit connection holes penetrate the first insulating layer and the second insulating layer. The first connection wiring and the second connection wiring located in the first transparent wiring layer are respectively connected to the first pixel circuit and the second pixel circuit through the first pixel circuit connection holes, and the first connection wiring and the second connection wiring located in the second transparent wiring layer are respectively connected to the first pixel circuit and the second pixel circuit through the second pixel circuit connection holes.

[0016] For example, the display substrate according to at least one embodiment of the present disclosure is located on the first side of the row where the plurality of first light-emitting elements and the first electrodes of the plurality of second light-emitting elements are located in the first display region, and further includes a plurality of electrode connection holes including a plurality of first electrode connection holes and a plurality of second electrode connection holes. The first electrode connection holes penetrate the second insulating layer and the third insulating layer, and the second electrode connection holes penetrate the third insulating layer. The first connection wiring and the second connection wiring located in the first transparent wiring layer are respectively connected to the first electrodes of the first light-emitting element and the second light-emitting element through the first electrode connection holes, and the first connection wiring and the second connection wiring located in the second transparent wiring layer are respectively connected to the first electrodes of the first light-emitting element and the second light-emitting element through the second electrode connection holes.

[0017] For example, the display substrate according to at least one embodiment of the present disclosure further includes at least one first virtual wiring located in the first display region. The at least one first virtual wiring is located between the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements in adjacent rows and extends along the second direction. The at least one first virtual wiring is connected to an end of the second connection wiring connected to the electrode connection hole, and extends in a direction away from the first electrode of the second light-emitting element from the electrode connection hole. The orthographic projection of the at least one first virtual wiring on the base substrate does not overlap with the first connection wiring and the second connection wiring.

[0018] For example, the display substrate according to at least one embodiment of the present disclosure further includes a pixel defining layer that is located on a side of the first electrodes of the plurality of light-emitting elements away from the base substrate and includes a plurality of first pixel openings. The plurality of first pixel openings correspond one-to-one with the plurality of light-emitting elements to form a light-emitting region of the plurality of light-emitting elements. Each of the plurality of light-emitting elements further includes a first light-emitting layer and a second electrode located on a side of the pixel defining layer away from the base substrate. The first light-emitting layer is located within the first pixel opening and between the first electrode and the second electrode. At least some of the first electrodes of the plurality of light-emitting elements include a first electrode main body portion and a first electrode connection portion. The first electrode main body portion is located in the light-emitting region of the light-emitting element, and the first electrode connection portion connects the electrode connection hole and the first electrode main body portion.

[0019] For example, in the display substrate according to at least one embodiment of the present disclosure, the second display region further includes a second sub-pixel array including a plurality of first pixel units. The plurality of first pixel units and the plurality of first pixel circuit units are alternately arranged. Each of the plurality of first pixel units includes a third light-emitting element and a third pixel circuit. The third pixel circuit is electrically connected to the third light-emitting element to drive the third light-emitting element. The first sub-pixel array and the second sub-pixel array include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. Each pixel of the first sub-pixel array and the second sub-pixel array includes at least one of the first sub-pixels, at least one of the second sub-pixels, and at least one of the third sub-pixels.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the display area further includes a third display area that at least locally surrounds the second display area. The third display area includes a third sub-pixel array. The third sub-pixel array includes a plurality of second pixel units. Each of the plurality of second pixel units includes a fourth light-emitting element and a fourth pixel circuit. The fourth pixel circuit is electrically connected to the fourth light-emitting element to drive the fourth light-emitting element. The third sub-pixel array includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. One of two adjacent pixels in the third sub-pixel array includes at least one of the first sub-pixels and at least one of the second sub-pixels, and the other of the two adjacent pixels includes at least one of the first sub-pixels and at least one of the third sub-pixels. Each second sub-pixel and each third sub-pixel are shared by at least two adjacent pixels respectively.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, the first sub-pixel is a green sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0022] At least one embodiment of the present disclosure further provides a display device including any one of the display substrates as described above.

[0023] For example, a display device according to at least one embodiment of the present disclosure further includes a sensor that is installed on a second side of the display substrate and is configured to receive light from a first side of the display substrate.

[0024] For example, in a display device according to at least one embodiment of the present disclosure, a front projection of the sensor on the base substrate overlaps at least locally with the first display area.

Brief Description of the Drawings

[0025] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description do not limit the present disclosure, but are only related to some embodiments of the present disclosure.

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DETAILED DESCRIPTION OF THE INVENTION

[0026] In order to more clearly explain the object, technical solution and advantages of the present disclosure, hereinafter, with reference to the drawings of the embodiments of the present disclosure, the technical solution of the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, other embodiments obtained by those skilled in the art without creative labor shall all be included in the protection scope of the present disclosure.

[0027] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first", "second" and the like used in this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components. Similarly, words such as "one", "a" or "the" do not indicate a quantity limitation, but indicate that at least one exists. Words such as "comprising" or "included" mean that the elements or things appearing before this word include the elements or things listed after this word, and their equivalents. For the sake of easy explanation, in some drawings, "up", "down", "front" and "back" are indicated. In the embodiments of this disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0028] To achieve the maximization of the occupancy rate of the moving display product screen, technologies such as bezel screen, water droplet screen, and hole drilling in the screen appear before and after. Such technologies can be used to install components such as sensors (such as image sensors, infrared sensors, distance sensors) by locally excavating the display area. The display area of this part is designed as a light-transmitting display area, and a camera is arranged below it to reduce the screen occupancy rate caused by the camera occupying the frame. Thereby, while realizing the display function, the light-transmitting display area can provide convenience for installing components such as sensors, and in a situation where it basically does not affect the display function of the light-transmitting display area, these sensors can execute functions such as imaging, infrared sensing, and distance sensing by the light-transmitting display area, which helps to realize an electronic device with a full screen.

[0029] However, the above technology still requires some display areas to be excavated, and the overall effect is still to form a deformed display area, which has an adverse impact on the visual experience. In order to avoid sacrificing the display area, a technology has emerged in which the pixel resolution PPI (Pixels Per Inch) is reduced in a local area and the light transmittance is improved to place a camera. The camera is placed in the area with a low resolution PPI. In this area, since the resolution PPI is low and the light transmittance is high, light rays can pass through the low PPI area and reach the camera. However, although the light transmittance is improved, the vertical and horizontal cross-wired pixel driving circuits form a grid and still have an adverse impact on camera imaging.

[0030] For example, FIG. 1A is a plan schematic view of a display substrate, and FIG. 1B is a cross-sectional schematic view taken along line I-I' of FIG. 1A.

[0031] As shown in FIGS. 1A and 1B, the display area of the display substrate 01 includes a light-transmissive display area 1, a peripheral display area 2, and a main body display area 3. The peripheral display area 2 at least locally surrounds the light-transmissive display area 1, and the main body display area 3 at least locally surrounds the light-transmissive display area 1 and the peripheral display area 2. As shown in FIG. 1A, the light-transmissive display area 1, the peripheral display area 2, and the main body display area 3 form an overall rectangular or substantially rectangular display area to display a complete (rectangular) screen.

[0032] As shown in FIG. 1B, the display substrate 01 includes a display structure layer 510 and a detection layer 520 for realizing the display area. Accordingly, the display structure layer 510 also includes the light-transmissive display area 1 and the peripheral display area 2. The detection layer 520 is installed on the non-display side S02 (i.e., the side opposite to the user) of the display substrate 01. The detection layer 520 includes a sensor 521. The sensor 521 at least locally overlaps with the light-transmissive display area 1 in the normal direction F1 of the display surface of the display substrate, and is configured to receive and process the optical signal that has passed through the light-transmissive display area 1 from the display side S01 (i.e., the side facing the user) of the display substrate 01. For example, the sensor 521 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 521 can be realized in the form of a chip or the like.

[0033] For example, the main body display area 3 is the main display area (or what is called the normal display area), has a higher resolution (PPI, Pixel Per Inch) than the transmissive display area 1 and the peripheral display area 2, that is, a plurality of sub-pixels with a higher density for use in a display are arranged within the main body display area 3. In the main body display area 3, each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element.

[0034] For example, the transmissive display area 1 and the peripheral display area 2 also each include a plurality of sub-pixels and are used for performing a display operation. For example, the transmissive display area 1 and the peripheral display area 2 have the same resolution.

[0035] The transmissive display area 1 can enable the light incident from the display side S01 of the display substrate 01 to pass through the display substrate 01 and reach the non-display side S02 of the display substrate 01, and thus is used for the normal sensing operation of components such as the sensor 521 located on the non-display side S02 of the display substrate 01. However, since the pixel circuit of the sub-pixel includes structures such as a plurality of electrodes, wirings, and active layers, generally it does not transmit light. In order to improve the light transmissibility of the transmissive display area 1, the light-emitting element of the sub-pixel in the transmissive display area 1 and the pixel circuit for driving the light-emitting element are separated from each other in the physical position.

[0036] For example, FIG. 2A is a plan schematic view of the arrangement of wirings in the display area of the display substrate shown in FIG. 1A. FIG. 2B is another plan schematic view of the arrangement of wirings in the display area of the display substrate shown in FIG. 1A.

[0037] As shown in FIGS. 2A and 2B, the sub-pixels of the transmissive display region 1 include a light-emitting element 02 located in the transmissive display region 1 and a pixel circuit D01 located in the peripheral display region 2. The light-emitting element 2 of the sub-pixel in the transmissive display region 1 still realizes the display function of the transmissive display region 1 by being held at a predetermined position within the transmissive display region 1. However, the pixel circuit D1 connected to and driving the light-emitting element 2 is taken out from the transmissive display region 1 and installed within the peripheral display region 2. Therefore, these pixel circuits D01 occupy a part of the space in the peripheral display region 2, and the remaining space in the peripheral display region 2 is used to install the sub-pixels P0 of the peripheral display region 2 itself (for example, shown by the dashed blocks within the peripheral display region 2 in FIG. 2A), that is, the sub-pixels that realize the display function in the peripheral display region 2. The sub-pixel P0 includes a first sub-pixel P01, a second sub-pixel P02, and a third sub-pixel P03. For example, the first sub-pixel P01 is a red sub-pixel, the second sub-pixel P02 is a green sub-pixel, and the third sub-pixel P03 is a blue sub-pixel.

[0038] For example, the sub-pixels P0 in the peripheral display region 2 and the pixel circuits D01 of the sub-pixels in the transmissive display region 1 are arranged in an array in the peripheral display region 2. As described above, the sub-pixels P0 in the peripheral display region 2 and the sub-pixels in the transmissive display region 1 have the same resolution. For example, the resolution of the transmissive display region 1 and the peripheral display region 2 can be set lower than the resolution of the main body display region 3, that is, the density of the sub-pixels used for display arranged within the transmissive display region 1 and the peripheral display region 2 is smaller than the density of the sub-pixels in the main body display region 3.

[0039] For example, as shown in FIGS. 2A and 2B, the light-emitting element 02 of the sub-pixel in the light-transmissive display area 1 is electrically connected to the pixel circuit D01 in the peripheral display area 2 located in the same row by the connection wiring LSn, and the connection wiring LSn is arranged along the direction X0, that is, the row direction. That is, the connection wiring LSn connects the pixel circuit D01 located in the peripheral display area 2 in the same row and the light-emitting element 02 located in the light-transmissive display area 1. For example, since the connection wiring LSn is at least locally a transparent wiring, the light transmittance of the light-transmissive display area 1 is improved, and the manufacturing material of the connection wiring LSn may include a transparent conductive material such as ITO (Indium Tin Oxide). The connection wiring LSn can pass through the sub-pixel P0 in the peripheral display area 2 to electrically connect the light-emitting element 02 of the sub-pixel located in the light-transmissive display area 1 and the pixel circuit D01 for driving the light-emitting element 02 located in the peripheral display area 2.

[0040] Furthermore, as shown in FIG. 2A, the data line DSn for driving the pixel circuit D01 of each sub-pixel in the light-transmissive display area 1 can be wound and arranged at the boundary close to the light-transmissive display area 1 of the peripheral display area 2, so that the data line DSn is taken out from the light-transmissive display area 1 and electrically connected to the pixel circuit D01 located in the peripheral display area 2 to provide a data signal necessary for display. For example, the data line DSn is wired to surround the light-transmissive display area 1 between the upper side and the lower side of the light-transmissive display area 1. This means that the pixel circuits of the sub-pixels located in the same column in the display area (here including the main body display area 3, the peripheral display area 2 and / or the light-transmissive display area 1) may be electrically connected to the same data line, so that the sub-pixels located in the same column can be driven by the same data line, and there is no need to change or increase the data driving circuit. The gate line GSn for driving the pixel circuit D01 of each sub-pixel in the light-transmissive display area 1 can be wound and arranged at the boundary close to the light-transmissive display area 1 of the peripheral display area 2, and is wired to surround the light-transmissive display area 1 from between the left side and the right side of the light-transmissive display area 1, thereby being taken out from the light-transmissive display area 1 and electrically connected to the pixel circuit D01 located in the peripheral display area 2 to provide a gate scanning signal necessary for display.

[0041] For example, as shown in FIG. 2B, one end of the connection wiring LSn (the end located in the peripheral display area 2) is connected to the pixel circuit D01 via the pixel circuit through-hole H01, and the other end of the connection wiring LSn (the end located in the light-transmitting display area 1) is connected to the first electrode 0111 (for example, the anode of the light-emitting element 02) of the light-emitting element 02 via the electrode through-hole H02. The first electrode 0111 of the light-emitting element 02 is connected to the electrode through-hole H02 by the wiring 0112. The first electrode 0111 and the wiring 0112 may be integrally formed. That is, the first electrode 0111 of the light-emitting element 02 is connected to the connection wiring LSn via the electrode through-hole H02. Since the plurality of connection wirings LSn are located on the same side of the row where the light-emitting element 02 is located in the light-transmitting display area 1, the plurality of connection wirings LSn need to occupy a lot of wiring space, so the distance between the electrode through-hole H02 and the first electrode 0111 is far (that is, the space occupied by the light-emitting element 02 in the direction Y0 is larger), thereby making it difficult to improve the arrangement density of the light-emitting elements 02 in the light-transmitting display area 1 and making it difficult to improve the resolution in the light-transmitting display area 1.

[0042] For example, FIG. 1C is a simulation diagram when the display area of the display substrate is irradiated with a point light source. FIG. 1D is another simulation diagram when the display area of the display substrate is irradiated with a point light source. As shown in FIGS. 1C and 1D, in order to test the light-transmitting effects of the light-transmitting display area 1 and the peripheral display area 2, simulations of light source irradiation can be performed on the light-transmitting display area 1 and the peripheral display area 2 as a test. The light source may be a point light source. For example, a point light source is installed on one side (for example, the display side) of the light-transmitting display area 1 and the peripheral display area 2. When performing light source irradiation, a grid effect appears in the effect diagrams of the displays of the light-transmitting display area 1 and the peripheral display area 2 (shown in FIG. 1C or FIG. 1D), and the grid effect in FIG. 1C is clearer. The grid effects of the light-transmissive display area 1 and the peripheral display area 2 are mainly generated by the vertical and horizontal intersecting wirings (for example, the dense connection wirings LSn) passing through the light-transmissive display area 1 and the peripheral display area 2.

[0043] For example, FIG. 1E is a display schematic diagram of a display substrate, and FIG. 1F is an enlarged view of region A0 in FIG. 1E. As shown in FIGS. 1F and 1E, the light-transmitting display region 1 and the peripheral display region 2 exhibit a strong screen granularity. After the resolution of the light-transmitting display region 1 and the peripheral display region 2 decreases, the brightness is reduced, thereby resulting in a strong visual difference from the main body display region 3 and causing a decrease in the display effect.

[0044] At least one embodiment of the present disclosure provides a display substrate, the display substrate having a first side used for display and a second side opposite to the first side, and including a base substrate, a plurality of first connection wirings, and a plurality of second connection wirings. The base substrate includes a display area including a first display area and a second display area at least locally surrounding the first display area, the first display area including a first sub-pixel array, and the first display area enabling light from the first side of the display substrate to at least locally transmit to the second side of the display substrate. The first sub-pixel array includes a plurality of light-emitting elements including a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged in an array. The second display area includes a first pixel circuit array including a plurality of first pixel circuit units, and the plurality of first pixel circuit units include a plurality of pixel circuits and a plurality of second pixel circuits. The plurality of first connection wirings extend at least locally along a first direction and connect the plurality of first pixel circuits and the plurality of first light-emitting elements in a one-to-one correspondence, and the first pixel circuit is configured to drive the first light-emitting element by the first connection wiring. The plurality of second connection wirings extend at least locally along the first direction and connect the plurality of second pixel circuits and the plurality of second light-emitting elements in a one-to-one correspondence, and the second pixel circuit is configured to drive the second light-emitting element by the second connection wiring. Each of the plurality of light-emitting elements includes a first electrode, and the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are arranged in the same row along the first direction. In the first display area, at least a part of the plurality of first connection wirings is located on the first side of the row where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located in a second direction, and at least a part of the plurality of first connection wirings is located on the second side of the row where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located in the second direction. The second direction intersects the first direction, and the first side and the second side of the row where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located are opposite to each other in the second direction.

[0045] In the display substrate according to the above embodiment, by installing the first connection wiring and the second connection wiring along the first direction on the first side and the second side of the rows where the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located respectively, the wiring space occupied by the first connection wiring and the second connection wiring in the second direction can be reduced, and further, the arrangement density of the light-emitting elements in the first display area and / or the number arranged along the first direction can be increased, thereby helping to improve the resolution of the first display area and / or increase the size (e.g., the number of pixels) along the first direction, and further helping to reduce the lattice effect caused by the first connection wiring and the second connection wiring in the second display area.

[0046] Hereinafter, embodiments of the present disclosure and their exemplifications will be described in detail with reference to the drawings.

[0047] For example, FIG. 3A is a plan schematic view of a display substrate according to at least one embodiment of the present disclosure. FIG. 3B is a cross-sectional schematic view taken along line B-B' of FIG. 3A. As shown in FIG. 3A, the display substrate 1000 according to the embodiment of the present invention includes a base substrate 14. The base substrate 14 includes a display area and a peripheral area 40 surrounding the display area, and the display area includes a first display area 10 (e.g., a transmissive display area), a second display area 20, and a third display area 30 (e.g., a normal display area) arranged in parallel. The second display area 20 surrounds the first display area 10 (e.g., at least locally). In FIG. 3A, the first display area 10 is identified by a circular frame.

[0048] For example, the display substrate according to the embodiment of the present disclosure may be a display substrate such as an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate, and the embodiments of the present disclosure do not limit the specific type of the display substrate.

[0049] For example, as shown in FIG. 3B, the first display area 10 is a transmissive display area, that is, incident light from the display side S1 (for example, the first side) of the display substrate 1000 can pass through this area and reach the non-display side S2 (for example, the second side) of the display substrate 1000. By further installing a sensor 192 on the non-display side S2 of the display substrate 1000 to receive the transmitted light, corresponding functions (such as imaging, infrared sensing, distance sensing, etc.) can be realized. For example, the sensor 192 is installed on the non-display side S2 of the display substrate 1000, and the orthographic projection of the sensor 192 on the base substrate 14 at least partially overlaps with the first display area 10 and is configured to receive and process light from the display side S1 of the display substrate 1000. The light from the display side S1 of the display substrate 1000 may be collimated light along the normal direction (for example, direction Z0) of the display substrate 1000, or non-collimated light.

[0050] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 can be realized in the form of, for example, a chip. The sensor 192 is installed on the non-display side S2 (the side opposite to the user) of the display substrate. The sensor 192 at least partially overlaps in the normal direction of the display surface of the display substrate of the first display area 10.

[0051] For example, the sensor 192 may be an image sensor, and may be used to collect an image of the external environment facing the light collecting surface of the sensor 192, and may be, for example, a CMOS image sensor or a CCD image sensor. The sensor 192 may also be an infrared sensor, a distance sensor, etc. The sensor 192 is used to realize the camera of a mobile terminal such as a mobile phone or a notebook computer, and may further include optical elements such as, for example, a lens, a mirror, or an optical waveguide as needed to modulate the optical path. The embodiments of the present disclosure do not limit the type, function, and installation form of the sensor 192.

[0052] The sensor 192 is installed on the non-display side S2 of the display panel by means such as double-sided tape, and the orthographic projection of the base substrate 14 of the sensor 192 at least partially overlaps with the first display area 10 and is configured to receive light from the first side S1. Thereby, the first display area 10 realizes display and at the same time provides convenience for the installation of the sensor 192.

[0053] For example, FIG. 4 is a partially enlarged schematic diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 4, the first display area 10 includes a first sub-pixel array (constituted by white blocks in the first display area 10). The first sub-pixel array includes a plurality of light-emitting elements 11 (white frames in the first display area 10) arranged in an array.

[0054] The second display area 20 includes a first pixel circuit array (constituted by gray blocks in the second display area 20), and the first pixel circuit array includes a plurality of first pixel circuit units D (gray blocks in the second display area 20) arranged in an array. The second display area 20 further includes a second sub-pixel array (constituted by white blocks in the second display area 20). The second sub-pixel array includes a plurality of first pixel units P arranged in an array, and the plurality of first pixel units P and the plurality of first pixel circuit units D are alternately arranged.

[0055] The third display area 30 at least partially surrounds the second display area 20. The third display area 30 includes a third sub-pixel array, and the third sub-pixel array includes a plurality of second pixel units C (white blocks in the third display area 30) arranged in an array.

[0056] The plurality of first pixel circuit units D are used to drive the plurality of light-emitting elements 11 in the first display area 10 in a one-to-one correspondence. That is, the pixel circuit D for the first sub-pixel array in the first display area 10 is installed in the second display area 20, and the pixel circuits and light-emitting elements of each sub-pixel unit are separated from each other in terms of position. The incident light from the display side S1 can pass through the blank area between adjacent light-emitting elements 11, thereby ensuring the light transmissibility of the first display area 10. Each first pixel unit P includes a third light-emitting element and a third pixel circuit that are directly connected to each other, and the third light-emitting element and the third pixel circuit are located within the same pixel area and are not separated from each other in terms of position. Each second pixel unit C includes a fourth light-emitting element and a fourth pixel circuit that are directly connected to each other, and the fourth light-emitting element and the fourth pixel circuit are located within the same pixel area and are not separated from each other in terms of position.

[0057] For example, as shown in FIG. 4, the array of the first pixel units P in the second display area 20 and the array of the plurality of light-emitting elements 11 in the first display area 10 are aligned with each other and distributed in a plurality of rows and a plurality of columns (the arrangement method in FIG. 4), and by forming a new (complete) array including a plurality of rows and a plurality of columns, the first display area 10 and the second display area 20 have the same resolution.

[0058] For example, FIG. 5 is a plan schematic diagram of the arrangement of wirings in the display area of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 5, the plurality of light-emitting elements 11 in the first display area 10 include a first light-emitting element 114 and a second light-emitting element 115. Correspondingly, the plurality of first pixel circuit units D in the second display area 20 include a first pixel circuit D10 and a second pixel circuit D20, and are respectively used to receive drive signals and drive the first light-emitting element 114 and the second light-emitting element 115 to emit light. For example, the first pixel circuit D10, the second pixel circuit D20, the first light-emitting element 114, and the second light-emitting element 115 are located in one row (for example, one of the two rows in FIG. 5). In the first display area 10, the first light-emitting element 114 and the first pixel circuit D10 are connected corresponding to the first direction X1, and functionally constitute one sub-pixel in the first display area 10. The second light-emitting element 115 and the second pixel circuit D20 are connected corresponding to the first direction X1, and functionally constitute one sub-pixel in the first display area 10.

[0059] Note that in FIG. 5, two rows of the first display area 10 and the second display area 20 are taken as an example, and the arrangement methods of other rows are the same and not shown.

[0060] For example, as shown in FIG. 5, the display substrate 1000 further includes a plurality of first connection wirings 101 and a plurality of second connection wirings 102. The plurality of first connection wirings 101 extend along the first direction X1 as a whole, and the plurality of second connection wirings 102 also extend along the first direction X1 as a whole. The plurality of first connection wirings 101 and the plurality of first connection wirings 102 are installed in parallel in the first direction X1, and the orthographic projections of the plurality of first connection wirings 101 and the plurality of second connection wirings 102 on the base substrate do not intersect, thereby avoiding signal crosstalk between each other. The plurality of first connection wirings 101 and the plurality of second connection wirings 102 are located in the first display area 10 and the second display area 20, that is, they extend through the first display area 10 and the second display area 20.

[0061] For example, as shown in FIG. 5, a plurality of first connection wirings 101 electrically connect a plurality of first pixel circuits D10 and a plurality of first light-emitting elements 114 in a one-to-one correspondence, and the first pixel circuit D10 is configured to drive the first light-emitting element 114 to emit light by the first connection wiring 101. The first connection wiring 101 electrically connects the first pixel circuit D10 and the first light-emitting element 114 located in the same row. A plurality of second connection wirings 102 connect a plurality of second pixel circuits D20 and a plurality of second light-emitting elements 115 in a one-to-one correspondence, and the second pixel circuit D20 is configured to drive the second light-emitting element 115 to emit light by the second connection wiring 102. The second connection wiring 102 electrically connects the second pixel circuit D20 and the second light-emitting element 115 located in the same row.

[0062] For example, as shown in FIG. 5, each of the plurality of light-emitting elements 11 includes a first electrode 111 (for example, the anode of the light-emitting element 11). The first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are arranged in the same row (for example, one column of the two rows in FIG. 5) along the first direction. In the first display region 10, a plurality of first connection wirings 101 and a plurality of second connection wirings 102 electrically connect the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 in the same row, respectively.

[0063] The plurality of first connection wirings 101 are located at least locally on the first side HS1 of the row in which the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located in the second direction Y1, and the plurality of second connection wirings 102 are located at least locally on the second side HS2 of the row in which the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located in the second direction Y1. The first side HS1 and the second side HS2 of the row in which the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located face each other in the second direction Y1. That is, the first side HS1 and the second side HS2 indicate the upper side and the lower side of the row in which the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located, respectively.

[0064] As shown in the figure, a plurality of first connection wirings 101 extend from the first side HS1 to the second display area 20 and then to the first display area 10, and a plurality of first connection wirings 102 extend from the second side HS2 to the second display area 20 and then to the first display area 10. Thereby, the utilization rate of the wiring space in the second direction Y1 of the plurality of first connection wirings 101 and the plurality of first connection wirings 102 is increased, which helps to increase the arrangement density of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115. For example, within the same spatial range in the second direction Y1, the number of rows in which the light-emitting elements are arranged increases, and accordingly, the number of rows of the first pixel units P in the second display area 20 can be increased, thereby increasing the resolution of the first display area and the second display area, and reducing the difference between the display effects of the first display area and the second display area and the display effect of the third display area.

[0065] For example, in some embodiments, the second direction X1 intersects the first direction Y1. In FIG. 4, the second direction X1 is, for example, the horizontal direction (row direction), the first direction Y1 is, for example, the vertical direction (column direction), and the second direction X1 is perpendicular to the first direction Y1. It should be noted that the second direction X1 and the first direction Y1 do not have to intersect and be perpendicular to each other. The embodiment shown in FIG. 5 is only an example, and the embodiments of the present disclosure are not limited thereto.

[0066] For example, as shown in FIG. 5, in the second display area 20, the first pixel circuit D10 is located on the left side of the first display area 10 in the first direction X1 (that is, the side away from the first display area 10). For example, the first light-emitting element 114 is located on the left side of the first display area 10 in the first direction X1 (that is, the side close to the second display area 20). When a plurality of first connection wirings 101 electrically connect a plurality of first light-emitting elements 114 and a plurality of second light-emitting elements 115 in the same row from the first side HS1, and a plurality of second connection wirings 102 electrically connect them from the second side HS2, the wiring density between the plurality of first connection wirings 101 and the plurality of second connection wirings 102 can be improved and they do not overlap each other.

[0067] For example, as shown in FIG. 4, the light-emitting elements 11 in the first display region 10 can be divided into the light-emitting elements 11 on the left side and the light-emitting elements 11 on the right side from the center line Y11 of the first display region 10. The light-emitting elements 11 on the left side can be connected to a part of the first pixel circuit unit D in the second display region 20 located on the left side of the first display region 10 in the connection form shown in FIG. 5. The light-emitting elements 11 on the right side are connected to a part of the first pixel circuit unit D in the second display region 20 located on the right side of the first display region 10 in the connection form shown in FIG. 5. That is, the configuration of the light-emitting elements 11 on the right side and a part of the second display region 20 on the right side and the configuration of the light-emitting elements 11 on the left side and a part of the second display region 20 on the left side may be symmetric with respect to the center line Y11.

[0068] For example, as shown in FIG. 5, when the second connection wiring 102 is electrically connected to the second light-emitting element 115 in the same row from the second side HS2, in the first display region 10, the orthographic projection of the second connection wiring 102 on the base substrate 14 overlaps with the first electrodes 111 of the plurality of second light-emitting elements 115 through which it passes. When the first connection wiring 102 is electrically connected to the second light-emitting element 115 in the same row from the first side HS2, in the first display region 10, the orthographic projection of the first connection wiring 102 on the base substrate 14 does not overlap with the first electrodes 111 of the first light-emitting element 114 and the second light-emitting element 115. Therefore, by reducing the number of connection wirings overlapping with the light-emitting element 111, the light transmittance of the first display region is improved.

[0069] For example, the first connection wiring 101 and the second connection wiring 102 (for example, at least the part in the first display region 10) are transparent conductive wirings. Thereby, the first connection wiring 101 and the second connection wiring 102 have high light transmittance, and it can be ensured that the first display region 10 has high light transmittance.

[0070] For example, the materials of the first connection wiring 151 and the second connection wiring 152 may include transparent conductive materials such as transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and the material of the metal wiring layer may include metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti) or alloy materials thereof.

[0071] For example, as shown in FIG. 4, the density of the array arrangement of the plurality of second pixel units C is greater than the density of the array arrangement of the plurality of first pixel units P in the second display region 20 and greater than the density of the array arrangement of the plurality of light-emitting elements 11 in the first display region 10. Thus, the display resolution of the third display region 30 is higher than the display resolutions of the second display region 20 and the first display region 10.

[0072] For example, as shown in FIG. 4, the density of the array arrangement of the light-emitting elements 11 in the first display region 10 is the same as the density of the array arrangement of the first pixel units P in the second display region. The first pixel circuit arrays are alternately arranged in the gaps after the array arrangement of the first pixel units P in the second display region 20, and are electrically connected to the array of the light-emitting elements 11 in the first direction Y1 and the second direction X1 respectively, and are used to drive the light-emitting elements 11 to emit light.

[0073] For example, each of the plurality of first connection wirings includes a first main body portion and at least one first bent portion. As shown in FIG. 5, each of the plurality of first connection wirings 101 includes a first main body portion 1011 and a first bent portion 1012.

[0074] The first main body portion 1011 is located in the first display area 10 and the second display area 20 and extends along the first direction X1. In the first display area 10, the first main body portion 1011 is located on the first side HS1 of the row where the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located. In the second display area 20, the first main body portion 1011 is located on the first side HS1 of the row where the first pixel circuit D10 is located. Since the first pixel circuit D10 and the light-emitting element 11 are located in the same row, the row where the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located and the row where the first pixel circuit D10 is located refer to the same row, and the first side HS1 also refers to the same side, that is, the side away from the first electrode 111 of the light-emitting element 11. Also, the second side HS2 described in the embodiment also refers to the side close to the first electrode 111 of the light-emitting element 11. The first main body portion 1011 provides a light-emitting drive current by being connected to the first electrodes 111 of the plurality of first light-emitting elements 114 in a one-to-one correspondence.

[0075] The first bending portion 1012 is located in the second display area 20 and is connected to the first pixel circuit D10 and the first main body portion 1011. The first bending portion 1012 extends from the first pixel circuit D10 to the first side HS1 of the first pixel circuit D10. That is, when the plurality of first connection wirings 101 are drawn out from the first pixel circuit D10, they are first bent and wired, and then wired along the first direction X1.

[0076] For example, the first connection wiring 101 connecting the first pixel circuit D10 in the first column (the leftmost) shown in the figure is first drawn out from the second side HS2 of the first pixel circuit D10 and extends to the first side HS1 of the first pixel circuit D10. The first connection wiring 101 can include two chamfered portions, a wiring extending along the first direction X1, and a wiring extending along the second direction Y1.

[0077] For example, the first connection wiring 101 connected to the first pixel circuit D10 in the second column (the second from the left) shown in the figure is first drawn out from the first side HS1 of the first pixel circuit D10, first extends in a direction away from the first pixel circuit D10, and then is connected to the main body portion 1011. The first connection wiring 101 can include a chamfered portion. Due to the first bending portion 1012, the first main body portion 1011 can improve the utilization rate of the wiring space by being separated from the first electrodes 111 of the plurality of first light-emitting elements 114 in the first display region 10.

[0078] For example, the second side HS2 of the first pixel circuit D10 faces the first side HS1 in the second direction Y1.

[0079] For example, in other embodiments, when the connection wirings do not overlap each other, the first bending portion 1012 may adopt the form of a partial arc-shaped wiring. For example, the chamfered portion is an arc line.

[0080] For example, at least a part of at least one first bending portion extends along the third direction to the first side of the first pixel circuit. As shown in FIG. 5, at least a part of the first bending portion 1012 extends along the third direction G1 to the first side HS1 of the first pixel circuit D10. For example, the two chamfered portions of the first connection wiring 101 connected to the first pixel circuit D10 in the first column (the leftmost) shown in the figure extend along the third direction G1. One chamfered portion of the first connection wiring 101 connecting the first pixel circuit D10 in the second column (the second from the left) shown in the figure extends along the third direction G1. The third direction G1 intersects the first direction X1 and the second direction Y1, that is, the third direction G1 is different from the first direction X1 and the second direction Y1.

[0081] For example, as shown in FIG. 5, the first bending portion 1012 in the first row in the figure and the first bending portion 1012 in the second row do not cross each other when wiring. For example, the chamfered portion located on the second side HS2 of the first connection wiring 101 connecting the first pixel circuit D10 in the first row and first column (the leftmost) shown in the figure and one chamfered portion of the first connection wiring 101 connecting the first pixel circuit D10 in the second row and second column (the second from the left) shown in the figure are arranged in parallel with each other. Thereby, the interval between different connection wirings is increased to avoid signal crosstalk.

[0082] For example, at least one first bending portion of at least one of a plurality of first connection wirings includes a first sub-bending portion.

[0083] FIG. 6 is a plan schematic diagram of the arrangement of wirings in the display area of a display substrate according to at least another embodiment of the present disclosure. As shown in FIG. 6, the first bending portion 1012 of the first connection wiring 101 includes a first sub-bending portion 1013 (for example, a chamfered portion). The first sub-bending portion 1013 is located on the first side HS1 of the first pixel circuit D10 (for example, the first pixel circuit D10 located in the fifth column from the left in FIG. 6) and extends along the third direction G1. The first sub-bending portion 1013 is connected to the first pixel circuit D10 and the first main body portion 1011. The first pixel circuit D10 connected to the first sub-bending portion 1013 is adjacent to the second pixel circuit D20. That is, the first pixel circuit D10 connected to the first sub-bending portion 1013 is the first pixel circuit D10 closest to the second pixel circuit D20. The distance between the first connection wiring 101 including the first sub-bending portion 1013 and the connection wiring in the previous row is the closest. That is, in the second direction Y1, all other connection wirings are arranged below the first connection wiring 101 including the first sub-bending portion 1013. The above installation method can make the most of the wiring space of the display substrate when ensuring that the connection wirings do not cross each other.

[0084] For example, at least one first bending portion of at least one of a plurality of first connection wirings extends from the second side to the first side of the first pixel circuit and includes a second sub-bending portion, a third sub-bending portion, a first sub-connection portion, and a second sub-connection portion.

[0085] As shown in FIG. 6, the first bent portion 1012 of the first connection wiring 101 extends from the second side HS2 of the first pixel circuit D10 to the first side HS1 of the first pixel circuit D10. For example, the first connection wiring 101 is a connection wiring that connects the first pixel circuits D10 in the first four columns on the left side in FIG. 6. The first connection wiring 101 includes a second sub-bent portion 1014 (for example, a chamfered portion), a third sub-bent portion 1015 (for example, a chamfered portion), a first sub-connection portion 1016, and a second sub-connection portion 1017. The first sub-connection portion 1016 and the second sub-bent portion 1014 are located on the second side HS2 of the first pixel circuit DH10. The second sub-bent portion 1014 extends along the third direction G1, and the first sub-connection portion 1016 extends along the first direction X1 and is connected to the first pixel circuit DH10 and the second sub-bent portion 1014. The second sub-connection portion 1017 extends along the second direction Y1 and is located between the adjacent first pixel circuit D10 (connected to the first connection wiring 101 including the first sub-bent portion 1013) and the second sub-pixel circuit D20. The second sub-connection portion 1017 is connected to the second sub-bent portion 1014 and the third sub-bent portion 1015. The third sub-bent portion 1015 is located on the first side HS1 of the first pixel circuit D10. The third sub-bent portion 1015 extends along the third direction G1 and is connected to the first main body portion 1011 of the first connection wiring 101, so that the first main body portion 1011 of the first connection wiring 101 is located on the first side HS1 of the first light-emitting element 114 in the first display area.

[0086] For example, as shown in FIG. 6, the first connection wiring 101 that connects the first pixel circuits D10 in the first four columns on the left side in FIG. 6 is located on one side close to the first pixel circuit D10 of the first connection wiring 101 that connects the first pixel circuits D10 in the fifth column on the left side in FIG. 6, and is respectively connected to the first light-emitting elements 114 in the first to fourth columns from the left side in the first display area. The first connection wiring 101 that connects the first pixel circuits D10 in the fifth column on the left side of FIG. 6 is further connected to the first light-emitting element 114 in the fifth column of the first display area.

[0087] For example, in other embodiments, the first connection wirings 101 are all installed in the same wiring pattern as the first connection wiring 101 that connects the first pixel circuits D10 in the first four columns on the left side in FIG. 6. That is, the first connection wiring 101 including the first sub-bending portion 1013 (for example, the first pixel circuit D10 that connects the fifth column on the left side in FIG. 6) is not provided. In this modified embodiment, the second sub-connection portion 1017 of the first connection wiring 101 that connects the first pixel circuits D10 in the first four columns on the left side in FIG. 6 penetrates between the first pixel circuits D10 in the fourth and fifth columns on the left side in FIG. 6, and the first connection wiring 101 that connects the first pixel circuit D10 in the fifth column on the left side in FIG. 6 is further connected to the first light-emitting element 114 in the leftmost (first column) in the first display area. The first connection wiring 101 that connects the first pixel circuits D10 in the first four columns on the left side in FIG. 6 is located on the side away from the first pixel circuit D10 of the first connection wiring 101 that connects the first pixel circuit D10 in the fifth column on the left side in FIG. 6, and is respectively connected to the first light-emitting elements 114 in the second to fifth columns from the left side in the first display area.

[0088] For example, as shown in FIGS. 5 and 6, each of the plurality of second connection wirings 102 includes a second main body portion 1021. The second main body portion 1021 extends along the first direction X1 and is located on the second side HS2 of the row where the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located. The second main body portion 1021 is connected to the first electrode 111 of the second light-emitting element 115 and the second pixel circuit connection D20. The second main body portion 1021 is located on the side of the first main body portion 1011 of the first connection wiring 101 that is close to the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115. In the first display area 10, the orthographic projection of the second main body portion 1021 of the second connection wiring 102 on the base substrate overlaps with the orthographic projection of the first electrodes 111 of the plurality of second light-emitting elements 114 and the plurality of first light-emitting elements 115 on the base substrate, thereby increasing the utilization rate of the wiring space and improving the resolution of the first display area and the second display area.

[0089] For example, as shown in FIG. 6, the first main body portions 1011 of the plurality of first connection wirings 101 and the second main body portions 1021 of the plurality of second connection wirings 102 are arranged in parallel in the first direction X1, thereby increasing the utilization rate of the wiring space and improving the resolution of the first display region and the second display region.

[0090] For example, FIG. 9A is a schematic cross-sectional view taken along line B1-B2 of FIG. 6, and FIG. 9B is a schematic cross-sectional view taken along line B3-B4 of FIG. 6. The line B1-B2 in FIG. 6 penetrates the thick-colored first connection wiring 101 (or the thick-colored second connection wiring 102), and the line B3-B4 in FIG. 6 penetrates the light-colored first connection wiring 101 (or the light-colored second connection wiring 102). For example, the lines B1-B2 and B3-B4 in FIG. 6 may be two adjacent lines that penetrate the first connection wiring 101, or two adjacent lines that penetrate the second connection wiring 102. As shown in FIGS. 9A and 9B, the display substrate 1000 further includes a first insulating layer (i.e., the first planarization layer 144), a second insulating layer (i.e., the second planarization layer 145), a third insulating layer (i.e., the third planarization layer 146), a first transparent wiring layer 151, and a second transparent wiring layer 152.

[0091] For example, as shown in FIGS. 9A and 9B, the first planarization layer 144 is located on the side away from the base substrate 14 of the first pixel circuit D10 or the second pixel circuit D20 to provide a planarized surface. The second planarization layer 145 is located on the side away from the base substrate 14 of the first planarization layer 144 to provide a planarized surface. The third planarization layer 146 is located on the side away from the base substrate 14 of the second planarization layer 145 to provide a planarized surface. The first transparent wiring layer 151 is located between the first planarization layer 144 and the second planarization layer 145 (shown in FIG. 9A). The second transparent wiring layer 152 is located on the side away from the base substrate 14 of the second planarization layer 145 (shown in FIG. 9B). The first light-emitting element 114 or the second light-emitting element 115 is located on the side away from the base substrate 14 of the third planarization layer 146. The first electrode 111 of the first light-emitting element 114 or the second light-emitting element 115 is located on the side away from the base substrate 14 of the third planarization layer 146.

[0092] For example, the materials of the first transparent wiring layer 151 and the second transparent wiring layer 152 may include transparent conductive materials such as transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). The material of the metal wiring layer may include metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti), or alloy materials thereof.

[0093] For example, the materials of the first planarization layer 144, the second planarization layer 145, and the third planarization layer 146 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include organic insulating materials such as polyimide, polyphthalide, polyphthalide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure are not limited thereto.

[0094] For example, as shown in FIGS. 6 and 9A, the first transparent wiring layer 151 includes one of two adjacent ones of the plurality of first connection wirings 101 and one of two adjacent ones of the plurality of second connection wirings 102. That is, the first transparent wiring layer 151 includes the thick-colored first connection wiring 101 and the thick-colored second connection wiring 102 in FIG. 6.

[0095] For example, as shown in FIGS. 6 and 9B, the second transparent wiring layer 152 includes the other of two adjacent ones of the first connection wirings 101 and the other of two adjacent ones of the plurality of second connection wirings 102. That is, the second transparent wiring layer 152 includes the light-colored first connection wiring 101 and the second connection wiring 102 in FIG. 6. The thick-colored first connection wiring 101 in the first connection wiring 101 is installed at a distance from the light-colored first connection wiring 101 and is located in different film layers to reduce crosstalk between signals. The thick-colored second connection wiring 102 in the second connection wiring 102 is installed at a distance from the light-colored second connection wiring 102 and is located in different film layers to reduce crosstalk between signals.

[0096] As shown in FIGS. 5, 9A, and 9B, the display substrate 1000 further includes a plurality of pixel circuit connection holes DH1. The plurality of pixel circuit connection holes DH1 are located in the second display region 20 and include a plurality of first pixel circuit connection holes DH11 and a plurality of second pixel circuit connection holes DH12. As shown in FIG. 9A, the first pixel circuit connection hole DH11 penetrates the first planarization layer 144. The first connection wiring 101 or the second connection wiring 102 located in the first transparent wiring layer 151 is electrically connected to the first pixel circuit D10 or the second pixel circuit D20 through the first pixel circuit connection hole DH11, respectively. As shown in FIG. 9B, the second pixel circuit connection hole DH12 penetrates the first planarization layer 144 and the second planarization layer 145, and the first connection wiring 101 or the second connection wiring 102 located in the second transparent wiring layer 152 is electrically connected to the first pixel circuit D10 or the second pixel circuit D20 through the second pixel circuit connection hole DH12, respectively.

[0097] For example, FIG. 7 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. FIG. 7 shows an arrangement diagram of wirings in the first display region 10 and the second display region 20, and the arrangement of the wirings is symmetric with respect to the center line Y11. Region A1 in FIG. 7 is a part of the first display region 10.

[0098] FIG. 8A is an enlarged view of region A1 in FIG. 7 according to at least one embodiment of the present disclosure, FIG. 8B is an enlarged view of region A1 in FIG. 7 according to at least another embodiment of the present disclosure, and FIG. 8C is an enlarged view of region A1 in FIG. 7 according to at least another embodiment of the present disclosure.

[0099] For example, as shown in FIGS. 5 and 8A, the display substrate 1000 further includes a plurality of electrode connection holes PH1. The plurality of electrode connection holes PH1 are located in the first display region 10, on the first side HS1 of the row where the first electrodes 111 of the plurality of first light-emitting elements 114 and the plurality of second light-emitting elements 115 are located, and include a plurality of first electrode connection holes PH11 and a plurality of second electrode connection holes PH12.

[0100] For example, as shown in FIG. 9A, the first electrode connection hole PH11 penetrates through the second planarization layer 144 and the third planarization layer 145, and the first connection wiring 101 or the second connection wiring 102 located in the first transparent wiring layer 151 is electrically connected to the first electrode 111 of the first light-emitting element 114 or the second light-emitting element 115 via the first electrode connection hole PH11, respectively.

[0101] For example, as shown in FIG. 9B, the second electrode connection hole PH12 penetrates through the third planarization layer 145, and the first connection wiring 101 and the second connection wiring 102 located in the second transparent wiring layer 152 are electrically connected to the first electrode 111 of the first light-emitting element 114 or the second light-emitting element 115 via the second electrode connection hole PH12, respectively.

[0102] For example, as shown in FIG. 8C, the display substrate 1000 further includes a first virtual wiring DML1 located in the first display area 10. The first virtual wiring DML1 is located between the first electrodes 111 of a plurality of first light-emitting elements 114 and a plurality of second light-emitting elements 115 in adjacent rows and extends along the first direction Y1. That is, the first virtual wiring DML1 is located between two rows in FIG. 8C. The first virtual wiring DML1 is connected to an end connected to the electrode connection hole PH1 of the second connection wiring 102. That is, the first virtual wiring DML1 can be regarded as a portion where the second connection wiring 102 extends from the electrode connection hole PH1 to the first side HS1. The first virtual wiring DML1 extends in a direction away from the first electrode 111 of the second light-emitting element 115 from the electrode connection hole PH1. The orthographic projection of the first virtual wiring DML1 on the base substrate 14 does not overlap with the first connection wiring 101 and the second connection wiring 102. When the second connection wiring 102 and the first electrode 111 of the second light-emitting element 115 are connected via the electrode connection hole PH1, the second connection wiring 102 penetrates through the first electrode 111 of the second light-emitting element 115, so that there is no wiring on the side away from the first electrode 111 of the second light-emitting element 115 of the electrode connection hole PH1, and the corresponding first connection wiring in this area has no wiring on the side away from the first electrode 111 of the first light-emitting element 114. Therefore, in order to make the wiring uniform and the light transmission uniform, the first virtual wiring DML1 is installed.

[0103] For example, as shown in FIGS. 9A and 9B, the display substrate 1000 further includes a pixel defining layer 147. The pixel defining layer 147 is located on the side of the base substrate 14 away from the first electrode 111 of the plurality of light-emitting elements 11 (the first light-emitting element 114 or the second light-emitting element 115), and includes a plurality of first pixel openings 147A. The plurality of first pixel openings 147A form the light-emitting regions 116 of the plurality of light-emitting elements 11 (the first light-emitting element 114 or the second light-emitting element 115) by corresponding one-to-one with the plurality of light-emitting elements 11. Each of the plurality of light-emitting elements 11 further includes a first light-emitting layer 112 and a second electrode 113 (for example, a cathode). The second electrode 113 is located on the side of the pixel defining layer 147 away from the base substrate 14. The light-emitting layer 112 is located in the first pixel opening 147 and between the first electrode 111 and the second electrode 112. The portion directly sandwiched between the first electrode 111 and the second electrode 112 of the light-emitting layer 112 emits light after being energized, and the region occupied by this portion corresponds to the above-mentioned light-emitting region 116.

[0104] For example, the material of the pixel defining layer 147 may include an organic insulating material such as polyimide, polyphthalide, polyphthalide, acrylic resin, benzocyclobutene, or phenolic resin, or may include an inorganic insulating material such as silicon oxide or silicon nitride. The embodiments of the present disclosure do not limit this.

[0105] For example, the material of the first electrode 111 can include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. Also, the first electrode 111 can include a metal with a high reflectivity as a reflective layer, for example, silver (Ag).

[0106] For example, for an OLED, the first light-emitting layer 112 may include a small molecule organic material or a polymer molecule organic material, and may be a fluorescent light-emitting material or a phosphorescent light-emitting material, and may emit red light, green light, blue light, or white light. And, if necessary, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For a QLED, the light-emitting layer may include quantum dot materials such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, and the particle size of the quantum dots is 2 to 20 nm.

[0107] For example, the second electrode 113 may include various conductive materials. For example, the second electrode 113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).

[0108] For example, as shown in FIGS. 5, 8B, 9A, and 9B, at least a part of the first electrodes 111 of the plurality of light-emitting elements 11 (the first light-emitting element 114 or the second light-emitting element 115) includes a first electrode main body portion 1111 and a first electrode connection portion 1112. The first electrode main body portion 1111 is located in the light-emitting region 116 of the light-emitting element 11 (the first light-emitting element 114 or the second light-emitting element 115). The first electrode connection portion 1112 connects the electrode connection hole PH1 (the first electrode connection hole PH11 or the second electrode connection hole PH12) and the first electrode main body portion 1111. Also, for example, at least a part of the first electrodes 111 of the plurality of light-emitting elements 11 (the first light-emitting element 114 or the second light-emitting element 115) includes only the first electrode main body portion 1111, and the first electrode main body portion 1111 is directly electrically connected to the electrode connection hole PH1, thereby reducing the resistance between the transistor and the light-emitting region. Since the first connection wiring 101 and the second connection wiring 102 are located on both sides of the light-emitting element 11, the arrangement density of the first electrodes 111 of the light-emitting element 11 increases, and the length of the first electrode connection portion 1112 in the second direction Y2 decreases, thereby increasing the light transmittance of the first display region 10.

[0109] For example, as shown in FIG. 8B, the shape of the first electrode main body portion 1111 of the first electrode 111 of the light-emitting element 11 may be different. The shape of the first electrode 111 is substantially hexagonal and extends along the second direction Y1. For example, the length of the first electrode main body portion 1111 of the leftmost first electrode 111 in the second direction Y1 as shown in the figure is large, the lengths of the first electrode main body portions 1111 of the middle two first electrodes 111 in the second direction Y1 are smaller than that of the first electrode main body portion 1111 of the leftmost first electrode 111, and the width of the first electrode main body portion 1111 of the first electrode 111 in the first direction X1 is larger than that of the first electrode main body portion 1111 of the leftmost first electrode 111. The shape of the first electrode main body portion 1111 of the first electrode 111 of the light-emitting element 11 can be designed according to the actual display requirements, and the embodiments of the present disclosure are not limited thereto. For example, the shape of the first electrode connection portion 1112 of the first electrode 111 of the light-emitting element 11 may be different. Since the positions of the first connection wiring 101 or the second connection wiring 102 connected to the first electrode 111 of the light-emitting element 11 are different and the shape of the first electrode main body portion 1111 of the first electrode 111 is different, the extending direction or the length in the second direction Y1 of the first electrode connection portion 1112 is also different. For example, the first electrode connection portion 1112 of the leftmost first electrode 111 in the figure extends along the first direction X1, and the first electrode connection portion 1112 of the second first electrode 111 from the left extends along the second direction Y1. The first electrode 111 of the light-emitting element 11 can be regarded as not having the first electrode connection portion 1112 installed, for example, the first electrodes 111 of the two light-emitting elements 11 on the right side in the figure. Since the first connection wiring 101 or the second connection wiring 102 connected to the first electrode 111 of the light-emitting element 11 is located on both sides of the first electrode 111 of the light-emitting element 11 respectively, the length of the first electrode connection portion 1112 in the second direction Y1 is reduced (the first electrode connection portion 1112 may not be installed), thereby increasing the light transmittance of the first display area. For example, FIG. 10A is a plan schematic diagram of the display area of the display substrate according to at least one embodiment of the present disclosure. The area A2 in FIG. 10A is located at the boundary between the third display area 30 and the second display area 20. FIG. 10B is an enlarged view of the area A2 in FIG. 10A according to at least one embodiment of the present disclosure.As shown in FIG. 10B, the second sub-pixel array (the arrangement method of the first sub-pixel array and the second sub-pixel array is the same) includes a plurality of first sub-pixels P1, a plurality of second sub-pixels P2, and a plurality of third sub-pixels P3. Each pixel P11 of the second sub-pixel array includes one first sub-pixel P1, one second sub-pixel P2, and one third sub-pixel P3. For example, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged along the first direction X1. The pixel circuit through-hole DH1 is located between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. That is, each pixel of the second sub-pixel array includes three sub-pixels and is arranged along the row direction. For example, the first sub-pixel P1 is a green sub-pixel G, the second sub-pixel P2 is a red sub-pixel R, and the third sub-pixel P3 is a blue sub-pixel B. The arrangement method of the pixels in the first display area 10 and the second display area 20 can increase the pixel density, that is, improve the resolution of the first display area 10 and the second display area 20, and reduce the granularity of the display in the first display area 10 and the second display area 20.

[0110] For example, as shown in FIG. 10B, the third sub-pixel array of the third display area 30 includes a plurality of first sub-pixels P1', a plurality of second sub-pixels P2', and a plurality of third sub-pixels P3'. One of two adjacent pixels in the third sub-pixel array, for example, pixel P12', includes one first sub-pixel P1' and one second sub-pixel P2', and the other of the two adjacent pixels, for example, pixel P11', includes one first sub-pixel P1' and one third sub-pixel P3'. Each second sub-pixel P2' and each third sub-pixel P3' are shared by at least two adjacent pixels. Different from the first display area 10 and the second display area 20, as described above, the resolution of the third display area 30 is higher than that of the first display area 10 and the second display area 20.

[0111] Embodiments of the present disclosure do not limit the pixel circuit of the sub-pixel. For example, it may be a 2T1C (i.e., two transistors and one capacitor) type pixel circuit. The two transistors are a data writing transistor and a driving transistor respectively, and the one capacitor is a signal accumulation capacitor. The pixel circuit can generate a driving current for driving the light emitting element to emit light based on the received scanning signal and data signal, and the light emitting element generates light of different intensities based on the magnitude of the driving current. The pixel circuit may be, for example, other types of pixel circuits, and may have, for example, further compensation functions, reset functions, sensing functions, etc., and thus may include two or more thin film transistors.

[0112] For example, as shown in FIGS. 9A and 9B, the display substrate 1000 further includes a first gate insulating layer 141, a second gate insulating layer 142, and an interlayer insulating layer 143. The first pixel circuit D10 (or the second pixel circuit D20) includes a thin film transistor 12 and a storage capacitor 13. The thin film transistor 12 includes an active layer 121, a gate electrode 122, and source-drain electrodes (source 123 and drain 124). The storage capacitor 13 includes a first capacitor electrode plate 131 and a second capacitor electrode plate 132. The active layer 121 is disposed on the base substrate 14, the first gate insulating layer 141 is disposed on the side of the active layer 121 away from the base substrate 100, the gate 122 and the first capacitor electrode plate 131 are disposed on the same layer on the side of the first gate insulating layer 141 away from the base substrate 14, and the second gate insulating layer 142 is disposed on the side of the gate 122 and the first capacitor electrode plate away from the base substrate 14. The second capacitor electrode plate 132 is disposed on the side of the second gate insulating layer 142 away from the base substrate 14, and the interlayer insulating layer 143 is disposed on the side of the second capacitor electrode plate 132 away from the base substrate 14. The source 123 and the drain 124 are disposed on the side of the interlayer insulating layer 143 away from the base substrate 14 and are electrically connected to the active layer 121 through through holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143. The first transparent wiring layer 151 is electrically connected to one of the source-drain electrodes through the first pixel circuit connection hole DH11 in the first planarization layer 144 (electrically connected to the drain 124 shown in FIG. 9A). The second transparent wiring layer 152 is electrically connected to one of the source-drain electrodes through the second pixel circuit connection hole DH12 in the first planarization layer 144 and the second planarization layer 145 (electrically connected to the drain 124 shown in FIG. 9B).

[0113] In the embodiments of the present disclosure, "installed in the same layer" means that two functional layers or structural layers are in the same layer and formed of the same material in the hierarchical structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers may be formed of the same material layer and can form the required patterns and structures by the same patterning process. The primary patterning process includes, for example, processes such as photoresist formation, exposure, development, and etching.

[0114] In another example, as a modification of the example shown in FIGS. 9A and 9B, the first capacitor electrode plate 131 of the storage capacitor 13 is still installed in the same layer as the gate 122, and the second capacitor electrode plate 132 of the storage capacitor 13 is installed in the same layer as the source 123 and the drain 124. Thus, the first capacitor electrode plate 131 and the second capacitor electrode plate 132 use the stack of the second gate insulating layer 142 and the interlayer insulating layer 143 to form a storage capacitor as a dielectric material.

[0115] In yet another example, as a modification of the example shown in FIGS. 9A and 9B, the first capacitor electrode plate 131 of the storage capacitor 13 is not installed in the same layer as the gate 223 and is located between the second gate insulating layer 142 and the interlayer insulating layer 143. The second capacitor electrode plate 132 of the storage capacitor 13 is installed in the same layer as the source 123 and the drain 124. Thus, the first capacitor electrode plate 131 and the second capacitor electrode plate 132 use the interlayer insulating layer 143 as a dielectric material to form a capacitor.

[0116] For example, as shown in FIGS. 9A and 9B, the first display region 10 further includes a transparent support layer 191 located on the base substrate 14, and the light-emitting elements 11 (the first light-emitting element 114 and the second light-emitting element 115) are located on the side of the transparent support layer 191 away from the base substrate 14. Thereby, with respect to the base substrate 14, the light-emitting elements 11 in the first display region 10 can be positioned at substantially the same height as the third light-emitting element 21 (shown in FIG. 11) in the second display region 20 and the fourth light-emitting element 31 (shown in FIG. 12) in the third display region 30, thereby improving the display effect of the display substrate.

[0117] For example, the transparent support layer 191 is disposed in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the first planarization layer 144. For example, the transparent support layer 191 is disposed in the same layer as all of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the first planarization layer 144, so that the light-emitting elements 11 in the first display region 10, the third light-emitting element 21 (shown in FIG. 11) in the second display region 20, and the fourth light-emitting element 31 (shown in FIG. 12) in the third display region 30 are substantially at the same height and simplify the manufacturing process of the display substrate.

[0118] For example, one or more materials of the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143 can include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The materials of the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143 may be the same or different.

[0119] For example, the material of the active layer 121 can include polycrystalline silicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 122 can include a metal material or an alloy material, and is, for example, a single-layer or multi-layer structure of a metal formed of molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal stack (e.g., a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The materials of the source 123 and the drain 124 can include a metal material or an alloy material, and are, for example, a single-layer or multi-layer structure of a metal formed of molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal stack (e.g., a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0120] For example, an inert layer can be further provided between the first planarization layer and the source 123 and the drain 124. The inert layer may be provided to expose one of the source 123 and the drain 124 including a through-hole, for example, to expose the drain 124. The inert layer can protect the source 123 and the drain 124 from being corroded by water vapor. For example, the material of the inert layer can include an organic insulating material or an inorganic insulating material, and is, for example, a silicon nitride material, which has a high dielectric constant and a high hydrophobic function, and thus can well protect the first pixel circuit D10 or the second pixel circuit D20 from being corroded by water vapor.

[0121] For example, as shown in FIGS. 9A and 9B, the display substrate 1000 further includes a sealing layer 148. The sealing layer 148 is located on the side of the second electrode 113 away from the base substrate 148. The sealing layer 148 can seal the light-emitting element 11 (the first light-emitting element 114 or the second light-emitting element 115), thereby reducing or preventing the deterioration of the light-emitting element 11 caused by moisture and / or oxygen contained in the environment. The sealing layer 148 may have a single-layer structure or a composite-layer structure, and the composite-layer structure includes a structure in which an inorganic layer and an organic layer are laminated. The sealing layer 148 includes at least one sub-sealing layer. For example, the sealing layer 148 can include a first inorganic sealing layer, a first organic sealing layer, and a second inorganic sealing layer that are sequentially provided.

[0122] For example, the material of the sealing layer 148 can include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc. The material of the organic sealing layer may be a polymer material containing a desiccant or a polymer material capable of blocking water vapor. For example, a polymer resin can be used to planarize the surface of the display substrate, and can relieve the stress of the first inorganic sealing layer and the second inorganic sealing layer. Further, it can include a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that have intruded inside.

[0123] For example, FIG. 11 is a schematic cross-sectional view of a second display region in a display substrate according to at least one embodiment of the present disclosure. FIG. 12 is a schematic cross-sectional view of a third display region in a display substrate according to at least one embodiment of the present disclosure.

[0124] For example, as shown in FIG. 11, each of the plurality of first pixel units P in the second display region 20 of the display substrate 1000 includes a third light-emitting element 21 and a third pixel circuit. The third pixel circuit is electrically connected to the third light-emitting element 21 to drive the third light-emitting element 21. For example, the second pixel circuit includes structures such as a thin-film transistor 22 and a storage capacitor 23. The third light-emitting element 21 includes a third electrode 211, a fourth electrode 213, and a second light-emitting layer 212 between the third electrode 211 and the fourth electrode 213. The third electrode 211 is electrically connected to the third pixel circuit through a through hole. For example, the third electrode 211 is the anode of the third light-emitting element 21, and the fourth electrode 213 is the cathode of the third light-emitting element 21. The pixel defining layer 147 is disposed on the side of the third electrode 211 away from the base substrate 14 and includes a plurality of openings. The second light-emitting layer 212 is disposed in the plurality of openings of the pixel defining layer 147. The fourth electrode 213 is disposed on the side of the second light-emitting layer 212 and the pixel defining layer 147 away from the base substrate 14. The third electrode 211 is disposed in the same layer as the first electrode 111 and has the same material, and the fourth electrode 213 is disposed in the same layer as the second electrode 113 and has the same material. The second light-emitting layer 212 is disposed in the same layer as the first light-emitting layer 112 and has the same material.

[0125] For example, the thin film transistor 22 includes structures such as an active layer 221, a gate 222, source-drain electrodes (i.e., a source electrode 223 and a drain electrode 224), and a first relay electrode 215, and the storage capacitor 23 includes a first capacitor electrode plate 231 and a second capacitor electrode plate 232. The active layer 221 is disposed on the base substrate 14, the first gate insulating layer 141 is disposed on the side of the active layer 221 away from the base substrate 14, the gate 222 and the first capacitor electrode plate 231 are disposed in the same layer on the side of the first gate insulating layer 141 away from the base substrate 14, the second gate insulating layer 142 is disposed on the side of the gate 222 and the first capacitor electrode plate 231 away from the base substrate 14, the second capacitor electrode plate 232 is disposed on the side of the second gate insulating layer 142 away from the base substrate 14, the interlayer insulating layer 143 is disposed on the side of the second capacitor electrode plate 232 away from the base substrate 14, the source-drain electrodes are disposed on the side of the interlayer insulating layer 143 away from the base substrate 14 and are electrically connected to the active layer 221 through through-holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143. A first planarization layer 144 is disposed on the side of the source-drain electrodes away from the base substrate 14 to provide a first planarized surface, thereby planarizing the third pixel circuit.

[0126] For example, the active layer 221, the gate 222, and the source-drain electrodes (i.e., the source 223 and the drain 224) of the thin film transistor 22 are disposed in the same layer and made of the same material as the active layer 121, the gate 122, and the source-drain electrodes (the source 123 and the drain 124) of the thin film transistor 12, respectively. The first capacitor electrode plate 231 and the second capacitor electrode plate 232 of the storage capacitor 23 are disposed in the same layer and made of the same material as the first capacitor electrode plate 131 and the second capacitor electrode plate 132 of the storage capacitor 13, respectively.

[0127] For example, as shown in FIG. 11, the first planarization layer 144 has a first through hole 144A, and the first relay electrode 215 is installed on the side of the first planarization layer 144 away from the base substrate 14, and is electrically connected to the source 223 (or drain 224) of the source-drain electrode through the first through hole 144A. The second planarization layer 145 and the third planarization layer 146 have a second through hole 145A, and the fourth electrode 213 of the third light-emitting element 21 is electrically connected to the first relay electrode 215 through the second through hole 145A.

[0128] For example, in another embodiment, the first relay electrode 215 may be further installed on the side of the second planarization layer 145 away from the base substrate 14. In this case, the first through hole 144A penetrates the first planarization layer 144 and the second planarization layer 145, and the second through hole 145A penetrates the third planarization layer 146.

[0129] For example, as shown in FIG. 12, each of the plurality of second pixel units C in the third display area 30 of the display substrate 1000 includes a fourth light-emitting element 31 and a fourth pixel circuit, and the fourth pixel circuit is electrically connected to the fourth light-emitting element 31 to drive the fourth light-emitting element 31. For example, the fourth pixel circuit includes structures such as a thin-film transistor 32 and a storage capacitor 33. The fourth light-emitting element 31 includes a fifth electrode 311, a sixth electrode 313, and a third light-emitting layer 312 between the fifth electrode 311 and the sixth electrode 313. The fifth electrode 311 is electrically connected to the fourth pixel circuit through a through hole. For example, the fifth electrode 311 is the anode of the fourth light-emitting element 31, and the sixth electrode 313 is the cathode of the fourth light-emitting element 31. The pixel defining layer 147 is installed on the side of the fifth electrode 311 away from the base substrate 14 and includes a plurality of openings. The third light-emitting layer 312 is installed in the plurality of openings of the pixel defining layer 147. The sixth electrode 313 is installed on the side of the third light-emitting layer 312 and the pixel defining layer 147 away from the base substrate 14. The fifth electrode 311 is installed in the same layer as the first electrode 111 and has the same material, and the sixth electrode 213 is installed in the same layer as the second electrode 113 and has the same material. The third light-emitting layer 312 is installed in the same layer as the first light-emitting layer 112 and has the same material.

[0130] For example, the thin film transistor 32 includes structures such as an active layer 321, a gate 322, source / drain electrodes (i.e., a source electrode 323 and a drain electrode 324), and a first relay electrode 315, and the storage capacitor 33 includes a first capacitor plate 331 and a second capacitor plate 332. The active layer 321 is disposed on the base substrate 14, the first gate insulating layer 141 is disposed on the side of the active layer 321 away from the base substrate 14, the gate 322 and the first capacitor plate 331 are disposed in the same layer on the side of the first gate insulating layer 141 away from the base substrate 14, the second gate insulating layer 142 is disposed on the side of the gate 322 and the first capacitor plate 331 away from the base substrate 14, and the second capacitor plate 332 is disposed on the side of the second gate insulating layer 142 away from the base substrate 14. An interlayer insulating layer 143 is disposed on the side of the second capacitor plate 332 away from the base substrate 14, and the source / drain electrodes are disposed on the side of the interlayer insulating layer 143 away from the base substrate 14 and are electrically connected to the active layer 221 via the first gate insulating layer 141, the second gate insulating layer 142 and through holes in the interlayer insulating layer 143. A first planarization layer 144 is disposed on the side of the source / drain electrodes away from the base substrate 14 to provide a first planarization surface, thereby planarizing the third pixel circuit.

[0131] For example, the active layer 321, gate 322, and source / drain electrodes (i.e., source 323 and drain 324) of the thin film transistor 32 are disposed in the same layer and made of the same material as the active layer 121, gate 122, and source / drain electrodes (i.e., source 123 and drain 124) of the thin film transistor 12. The first capacitor plate 331 and second capacitor plate 332 of the storage capacitor 33 are disposed in the same layer and made of the same material as the first capacitor plate 131 and second capacitor plate 132 of the storage capacitor 13, respectively.

[0132] For example, as shown in FIG. 12, the first planarization layer 144 has a first through-hole 144A, and the first relay electrode 315 is disposed on the side away from the base substrate 14 of the first planarization layer 144 and is electrically connected to the source 323 (or drain 324) of the source-drain electrode through the first through-hole 144A. The second planarization layer 145 and the third planarization layer 146 have a second through-hole 145A, and the sixth electrode 313 of the fourth light-emitting element 31 is electrically connected to the first relay electrode 315 through the second through-hole 145A.

[0133] For example, in another embodiment, the first relay electrode 315 may be further disposed on the side away from the base substrate 14 of the second planarization layer 145. In this case, the first through-hole 144A penetrates through the first planarization layer 144 and the second planarization layer 145, and the second through-hole 145A penetrates through the third planarization layer 146.

[0134] Note that since the first pixel circuit, the second pixel circuit, and the third pixel circuit in the second display region 20 have the same structure as the fourth pixel circuit in the third display region 30, they can be formed using the same patterning process in the manufacturing process. For example, the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, the first planarization layer 144, the second planarization layer 145, the third planarization layer 146, the pixel defining layer 147, and the encapsulation layer 148 are disposed in the same layers in the second display region 20 and the third display region 30, and are more integrated in some embodiments, for example, they are the same insulating layer. Therefore, the same reference numerals are adopted in the drawings.

[0135] For example, as shown in FIGS. 9A, 9B, 11, and 12, the base substrate 14 may be a glass plate, a quartz plate, a metal plate, a resin-based plate, or the like. For example, the material of the base substrate may include an organic material. For example, the organic material may be a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the base substrate 14 may be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure do not limit this.

[0136] FIG. 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2000, and the display device 2000 may include the display substrate 1000 of any one of the above embodiments.

[0137] For example, as shown in FIG. 13, the display device 2000 may further include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding region of the display substrate 1000, and the control chip is attached to the flexible circuit board to be electrically connected to the display region. Or, the control chip is directly bonded to the bonding region to be electrically connected to the display region.

[0138] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip can further include a memory, can further include a power module, etc., and realizes the power supply and signal input / output functions through conductors, signal lines, etc. installed separately. For example, the control chip can further include a hardware circuit and computer-executable code, etc. The hardware circuit can include conventional very large scale integration (VLSI) circuits, or conventional semiconductors such as gate arrays and logic chips, transistors, or other discrete elements, and the hardware circuit can further include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0139] For example, the display device 2000 according to at least one embodiment of the present disclosure may be an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. The display device 2000 can further include other components such as a data driving circuit and a timing controller, and the embodiments of the present disclosure do not limit this.

[0140] For example, as shown in FIGS. 3B, 9A, and 9B, the display device 2000 further includes a sensor 192. The sensor 192 is installed on the second side S2 (for example, the non-display side) of the display substrate 1000. The sensor 192 is configured to receive light (for example, collimated light or collimated light) from the first side S1 (for example, the display side of the display substrate) of the display substrate 1000. The orthographic projection of the sensor 192 on the base substrate 14 at least partially overlaps with the first display region 10.

[0141] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 can be realized in the form of a chip, etc. The sensor 192 is installed on the non-display side S2 (the side opposite to the user) of the display substrate.

[0142] For example, the sensor 192 and the first display area 10 at least locally overlap in the normal direction of the display surface of the display substrate.

[0143] For example, the sensor 192 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 192, and may be, for example, a CMOS image sensor or a CCD image sensor. The sensor 192 may also be an infrared sensor, a distance sensor, etc. The sensor 192 is used to realize the camera of a mobile terminal such as a mobile phone or a notebook computer, and may further include optical elements such as lenses, mirrors, or optical waveguides as needed to modulate the optical path. The embodiments of the present disclosure do not limit the type, function, and installation form of the sensor 192.

[0144] The sensor 192 is installed on the non-display side S2 of the display panel by means of a double-sided tape or the like, and the orthographic projection of the sensor 192 on the base substrate 14 at least locally overlaps with the first display area 10 and is configured to receive light from the first side S1. Thereby, the first display area 10 provides convenience for the installation of the sensor 192 while realizing the display.

[0145] Note that, for the sake of clear and concise description, the embodiments of the present disclosure do not show all the constituent units of the display device. To realize the substrate functions of the display device, those skilled in the art can provide and install other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0146] Regarding the technical effects of the display device according to the above embodiments, reference can be made to the technical effects of the display substrate according to the embodiments of the present disclosure, and the description is omitted here.

[0147] The following points need to be further explained. (1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and normal designs can be referred to for other structures.

[0148] (2) If there is no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0149] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily imagined by those skilled in the art within the technical scope disclosed in the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should follow the protection scope of the claims.

Claims

1. A display substrate having a first side used for display and a second side facing the first side, which is a base substrate including a display area, the display area including a first display area and a second display area at least locally surrounding the first display area, the first display area including a first sub-pixel array, and the first display area enabling light from the first side of the display substrate to be at least locally transmitted to the second side of the display substrate, the first sub-pixel array including a plurality of light-emitting elements including a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged in an array, the second display area including a first pixel circuit array including a plurality of first pixel circuit units, and the plurality of first pixel circuit units including a plurality of first pixel circuits and a plurality of second pixel circuits, the base substrate; A plurality of first connection wirings at least locally extending along a first direction and connecting the plurality of first pixel circuits and the plurality of first light-emitting elements in a one-to-one correspondence, wherein the first pixel circuit is configured to drive the first light-emitting element by the first connection wiring, the plurality of first connection wirings; A plurality of second connection wirings at least locally extending along the first direction and connecting the plurality of second pixel circuits and the plurality of second light-emitting elements in a one-to-one correspondence, wherein the second pixel circuit is configured to drive the second light-emitting element by the second connection wiring, the plurality of second connection wirings, and including; Each of the plurality of light-emitting elements includes a first electrode, and the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are arranged in the same row along the first direction, In the first display area, at least a part of the plurality of first connection wirings is located on the first side of the row in which the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located in a second direction, and at least a part of the plurality of second connection wirings is located on the second side of the row in which the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located in the second direction, The second direction intersects the first direction, and the first side and the second side of the row in which the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located face each other in the second direction, the display substrate.

2. In the first direction, the plurality of first light-emitting elements are located on the side closer to the second display area of the plurality of second light-emitting elements, the display substrate according to claim 1.

3. each of the plurality of first connection wirings includes a first body portion and at least one first bent portion; the first body portion extends along the first direction and is located on a first side of a row in which first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located, and the first body portion is connected to the first electrodes of the plurality of first light-emitting elements in a one-to-one correspondence; 3. The display substrate of claim 1, wherein the at least one first bend is connected to the first pixel circuit and the first body portion, and the at least one first bend extends from the first pixel circuit to a first side of the first pixel circuit, thereby separating the first body portion from the first electrodes of the plurality of first light-emitting elements in the first display region.

4. At least a portion of the at least one first bent portion extends along a third direction toward a first side of the first pixel circuit; The display substrate of claim 3 , wherein the third direction intersects with the first direction and the second direction.

5. At least one first bent portion of the plurality of first connection wirings includes a first sub-bent portion, the first sub-bent portion is located on a first side of the first pixel circuit and extends along the third direction, the first sub-bent portion is connected to the first pixel circuit and the first body portion, The display substrate of claim 4 , wherein one of the first pixel circuits connected to the first sub-bend portion is adjacent to the second pixel circuit.

6. at least one first bent portion of the plurality of first connection wirings extends from a second side of the first pixel circuit to a first side of the first pixel circuit, and includes a second sub-bent portion, a third sub-bent portion, a first sub-connection portion, and a second sub-connection portion; the first sub-connection portion and the second sub-bent portion are located on a second side of the first pixel circuit, the second sub-bent portion extends along the third direction, and the first sub-connection portion extends along the first direction and is connected to the first pixel circuit and the second sub-bent portion; the second sub-connection portion extends along the second direction and is located between two adjacent first pixel circuits, the second sub-connection portion is connected to the second sub-bent portion and the third sub-bent portion; the third sub-bent portion is located on a first side of the first pixel circuit, the third sub-bent portion extends along a third direction and is connected to a first body portion of the first connection wiring, The display substrate according to claim 4 , wherein the second side and the first side of the first pixel circuit face each other in the second direction.

7. At least one first bending portion of the plurality of first connection wirings includes a second sub-bending portion, a third sub-bending portion, a first sub-connection portion, and a second sub-connection portion. The first sub-connection portion and the second sub-bending portion are located on the second side of the first pixel circuit. The second sub-bending portion extends along the third direction. The first sub-connection portion extends along the first direction and is connected to the first pixel circuit and the second sub-bending portion. The second sub-connection portion extends along the second direction and is located between an adjacent first pixel circuit and a second sub-pixel circuit. The second sub-connection portion is connected to the second sub-bending portion and the third sub-bending portion. The third sub-bending portion is located on the first side of the first pixel circuit. The third sub-bending portion extends along the third direction and is connected to the first main body portion of the first connection wiring. The second side and the first side of the first pixel circuit face each other in the second direction. The display substrate according to claim 5.

8. Each of the plurality of second connection wirings includes a second main body portion. The second main body portion extends along the first direction and is located on the second side of the row in which the first electrodes of the plurality of first light-emitting elements and the plurality of second light-emitting elements are located. The second main body portion is connected to the first electrode of the second light-emitting element and the second pixel circuit. In the first display area, the orthographic projection of the main body portion of the second connection wiring on the base substrate overlaps with the orthographic projection of at least one of the plurality of second light-emitting elements and the first electrodes of the plurality of first light-emitting elements on the base substrate. The display substrate according to any one of claims 3 to 7.

9. The first main body portions of the plurality of first connection wirings and the second main body portions of the plurality of second connection wirings are arranged in parallel in the first direction. The display substrate according to claim 8.

10. The plurality of first connection wirings and the plurality of second connection wirings are transparent conductive wirings. The display substrate according to any one of claims 1 to 9.

11. Further includes a first insulating layer, a second insulating layer, a third insulating layer, a first transparent wiring layer, and a second transparent wiring layer. the first insulating layer is located on a side of the plurality of first pixel circuits and the plurality of second pixel circuits that is remote from the base substrate, the second insulating layer is located on a side of the first insulating layer that is remote from the base substrate, the third insulating layer is located on a side of the second insulating layer that is remote from the base substrate, the first transparent wiring layer is located between the first insulating layer and the second insulating layer, the second transparent wiring layer is located on a side of the second insulating layer that is remote from the base substrate, and first electrodes of the plurality of first light-emitting elements are located on a side of the third insulating layer that is remote from the base substrate, 11. The display substrate of claim 10, wherein the first transparent wiring layer includes one of two adjacent ones of the plurality of first connection wirings and one of two adjacent ones of the plurality of second connection wirings, and the second transparent wiring layer includes the other of the two adjacent ones of the first connection wirings and the other of the two adjacent ones of the plurality of second connection wirings.

12. Further comprising a plurality of pixel circuit connection holes located in the second display area, the pixel circuit connection holes including a plurality of first pixel circuit connection holes and a plurality of second pixel circuit connection holes; the first pixel circuit connection hole penetrates the first insulating layer, and the second pixel circuit connection hole penetrates the first insulating layer and the second insulating layer; a first connection wiring and a second connection wiring located in the first transparent wiring layer are connected to the first pixel circuit and the second pixel circuit via the first pixel circuit connection hole, respectively; The display substrate of claim 11 , wherein the first connection wiring and the second connection wiring located in the second transparent wiring layer are connected to the first pixel circuit and the second pixel circuit through the second pixel circuit connection hole, respectively.

13. a plurality of electrode connection holes, each of which is located in the first display area and on a first side of a row in which the first electrodes of the first light-emitting elements and the second light-emitting elements are located, the plurality of electrode connection holes including a plurality of first electrode connection holes and a plurality of second electrode connection holes; the first electrode connection hole penetrates the second insulating layer and the third insulating layer, the second electrode connection hole penetrates the third insulating layer, a first connection wiring and a second connection wiring located in the first transparent wiring layer are connected to first electrodes of the first light emitting element and the second light emitting element through the first electrode connection holes, respectively; The display substrate according to claim 11 or 12, wherein the first connection wiring and the second connection wiring located in the second transparent wiring layer are connected to the first electrodes of the first light-emitting element and the second light-emitting element, respectively, through the second electrode connection holes.

14. Further comprising at least one first virtual wiring located in the first display area, The at least one first virtual wiring is located between the plurality of first light-emitting elements and the first electrodes of the plurality of second light-emitting elements in adjacent rows and extends along the second direction, The at least one first virtual wiring is connected to an end connected to the electrode connection hole of the second connection wiring and extends in a direction away from the first electrode of the second light-emitting element from the electrode connection hole, The display substrate according to claim 13, wherein a positive projection of the at least one first virtual wiring on the base substrate does not overlap with the first connection wiring and the second connection wiring.

15. Further comprising a pixel defining layer located on a side of the first electrodes of the plurality of light-emitting elements away from the base substrate and including a plurality of first pixel openings, and the plurality of first pixel openings form light-emitting regions of the plurality of light-emitting elements by corresponding one-to-one with the plurality of light-emitting elements, Each of the plurality of light-emitting elements further includes a first light-emitting layer and a second electrode located on a side of the pixel defining layer away from the base substrate, and the first light-emitting layer is located within the first pixel opening and between the first electrode and the second electrode, At least some of the first electrodes of the plurality of light-emitting elements include a first electrode main body portion and a first electrode connection portion, The first electrode main body portion is located in the light-emitting region of the light-emitting element, and the first electrode connection portion connects the electrode connection hole and the first electrode main body portion. The display substrate according to claim 13 or 14.

16. The second display area further includes a second sub-pixel array including a plurality of first pixel units, and the plurality of first pixel units and the plurality of first pixel circuit units are alternately arranged, Each of the plurality of first pixel units includes a third light-emitting element and a third pixel circuit, and the third pixel circuit is electrically connected to the third light-emitting element to drive the third light-emitting element, The first sub-pixel array and the second sub-pixel array include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, Each pixel of the first sub-pixel array and the second sub-pixel array includes at least one of the first sub-pixels, at least one of the second sub-pixels, and at least one of the third sub-pixels. The display substrate according to any one of claims 1 to 15.

17. The display area further includes a third display area that at least locally surrounds the second display area. The third display area includes a third sub-pixel array. The third sub-pixel array includes a plurality of second pixel units. Each of the plurality of second pixel units includes a fourth light-emitting element and a fourth pixel circuit. The fourth pixel circuit is electrically connected to the fourth light-emitting element to drive the fourth light-emitting element. The third sub-pixel array includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. One of two adjacent pixels in the third sub-pixel array includes at least one of the first sub-pixels and at least one of the second sub-pixels, and the other of the two adjacent pixels includes at least one of the first sub-pixels and at least one of the third sub-pixels. Each second sub-pixel and each third sub-pixel are shared by at least two adjacent pixels. The display substrate according to any one of claims 1 to 15.

18. The first sub-pixel is a green sub-pixel. The second sub-pixel is a red sub-pixel. The third sub-pixel is a blue sub-pixel. The display substrate according to claim 16 or 17.

19. A display device including the display substrate according to any one of claims 1 to 18.

20. The display device according to claim 19, further including a sensor that is installed on the second side of the display substrate and is configured to receive light from the first side of the display substrate.

21. The display device according to claim 20, wherein a front projection of the sensor on the base substrate overlaps at least locally with the first display area.

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