Data Bus Signal Conditioner and Level Shifter

Abstract

The circuit (206) includes a signal conditioner circuit element (208), a level shifter circuit element (212), and a state detector and controller circuit element (210) coupled between the signal conditioner circuit element (208) and the level shifter circuit element (212). The state detector and controller circuit element (208) includes receiver circuit elements (228-238) and a finite state machine (222) coupled to the receiver circuit elements (228-238). The finite state machine (222) is configured to detect a first data rate from the signal, and to control operation of the signal conditioner circuit element (208) in response to detecting the first data rate and to control operation of the level shifter circuit element (212) during a second data rate.

Description

Technical Field

[0001] This application generally relates to data bus interfaces, and more specifically to data bus signal regulators and level shifters.

Background Art

[0002] Data buses, including those compliant with one or more Universal Serial Bus (USB) industry standard specifications (generally referred to as USB in this specification), are widely used to facilitate communication between devices. With the expansion of USB, a wide variety of USB-compliant devices with various communication and power requirements have emerged. For example, the embedded USB industry standard specification (generally referred to as eUSB2 in this specification) enables low-power communication between devices such as integrated circuits (ICs) or chips that are mounted on a circuit board or included in an assembly within a computer system. However, while eUSB2 enables serial communication between devices at low voltages, as the feature size of devices decreases and the distance between devices on a circuit board or other assembly increases, additional mechanisms are required to support continuous communication between devices.

[0003] For example, some specifications recommend that a particular bus be implemented such that it is shorter than a specified maximum length. Buses longer than the specified maximum length can degrade the data exchanged over the bus. In addition, supply (such as voltage supply and ground) limitations can affect the specified maximum length of a bus. To facilitate increasing the bus length, some specifications identify which type of repeater can be used (e.g., the hybrid repeater specified by eUSB2). However, such repeaters require complex state machines and can degrade the data passing through the repeater. In addition, certain repeaters require higher power.

Summary of the Invention

[0004] In one example, a circuit includes a signal conditioner circuit element, a level shifter circuit element, and a state detector and controller circuit element coupled between the signal conditioner circuit element and the level shifter circuit element. The state detector and controller circuit element includes a receiver circuit element and a finite state machine coupled to the receiver circuit element. The finite state machine is configured to detect a first data rate from a signal, control the operation of the signal conditioner circuit element in response to the detection of the first data rate, and control the operation of the level shifter circuit element during a second data rate.

[0005] In another example, an intermediate circuit is adapted to be coupled between first and second communication devices using first and second conductors and is operable to facilitate communication between the first and second communication devices. The intermediate circuit has first and second outputs and includes a state detector and controller circuit coupled to be coupled to the first and second conductors. The intermediate circuit also includes a signal conditioning circuit coupled to the first output and adapted to be coupled to the first and second conductors, and a level shifter coupled to the second output and adapted to be coupled to the first and second conductors. The state detector and controller circuit is configured to detect a state of the communication, enable the signal conditioning circuit in response to the detection of a first state of the communication, and enable the level shifter during a second state of the communication. For example, the first state of the communication is a high data rate and the second state of the communication is a low data rate or a full data rate.

[0006] In another example, the system includes a first integrated circuit, a second integrated circuit, and an intermediate circuit coupled between the first and second integrated circuits. The intermediate circuit includes a first switch, a signal conditioning circuit element configured to boost an edge of a signal while the first switch is closed, a second switch, a level shifter circuit element operable while the second switch is closed, and a state detector and controller circuit element. The state detector and controller circuit element includes a receiver circuit element and a finite state machine coupled to the receiver circuit element. The finite state machine is configured to detect a first data rate from a signal received at the receiver circuit element, close the first switch in response to the detection of the first data rate, and close the second switch during a second data rate.

[0007] In another example, a method includes receiving a signal and detecting a first data rate from the signal. The method further includes operating a signal conditioning circuit element to boost an edge of the signal in response to detecting the first data rate, and operating a level shifter circuit element to shift a voltage level of the signal from a first voltage level to a second voltage level during a second data rate.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0018] The same reference numerals are used in the drawings to indicate the same or similar (such as structure and / or function) features. The features in the drawings are not necessarily drawn to a certain scale.

[0019] In some of the described examples, an intermediate device is used between two devices and / or buses. The intermediate device, in some examples, uses a simplified state machine that does not utilize a protocol handshake defined by some bus standard (such as eUSB2). For example, the intermediate device includes a receiver circuit element that senses a voltage to which a state machine, such as a digital finite state machine, responds when controlling the operation of a signal conditioning circuit element and a level shifter circuit element. In some examples, signal conditioning includes edge boosting instead of repeating packets. Further, in some examples, the level shifter circuit element enables communication between devices operating at different voltage supply levels and ground levels.

[0020] First, refer to FIG. 1, which is a block diagram showing a system 100 according to the described example. System 100 includes two devices 102 and 104 and an intermediate device 106. In one example, devices 102 - 106 are included in or on the same physical arrangement or assembly 114. For example, the physical arrangement 114 is a computer system such as a laptop, desktop, mobile phone, tablet, wearable device, television, or monitor. In another example, the physical arrangement 114 is a circuit board such as a printed circuit board (PCB). Also, although only two devices 102 and 104 and one intermediate device 106 are shown, additional such devices may be included within system 100.

[0021] Devices 102 and 104 can communicate via data bus 101 (also referred to herein as bus 101) using a communication protocol and are thus also referred to herein as communication devices. For example, bus 101 may include one or more conductors for transferring signaling or signals between devices 102 and 104. Also, a conductor may include one or more electrical traces or other types of signal lines. In some examples, the conductors of bus 101 terminate at an intermediate device 106, such as level shifter circuit element 112, so that devices 102 and 104 do not have a direct electrical connection. In other examples, the conductors of bus 101 flow through intermediate device 106, such as at signal conditioner circuit element 108, so that devices 102 and 104 can maintain a direct electrical connection.

[0022] In another example, devices 102 and 104 include circuit elements (not shown) that enable serial communication via bus 101 using a communication protocol defined by, consistent with, and / or compliant with an embedded USB2 (eUSB2) physical layer supplement to the USB Revision 2.0 specification, Revision 1.1, or an eUSB2 specification before or after that, which is incorporated herein by reference. Devices that can communicate using a protocol defined by, consistent with, and / or compliant with eUSB2 are referred to as eUSB2 devices, and a bus, cable, or other electrical connection that provides such communication between eUSB2 devices is referred to as an eUSB2 bus.

[0023] Examples of devices 102 and 104 include ICs or package systems such as system-on-chip (SoC), data storage or memory devices, eUSB2 repeaters, etc. Also, as eUSB2 devices, devices 102 and 104 may include circuit elements (not shown) for communicating in a native mode where neither device 102 nor 104 is an eUSB2 repeater, or in a repeater mode where one of devices 102 or 104 is an eUSB2 repeater.

[0024] The intermediate device 106 facilitates communication between devices 102 and 104 via bus 101. The intermediate device 106 includes a signal conditioner (or signal conditioning) circuit element 108, a state detector and controller circuit element 110, and a level shifter circuit element 112 (or simply level shifter 112). The components or elements 108-112 of the intermediate device 106 may be included on a single semiconductor substrate (and packaged within a single semiconductor package), may be included on multiple semiconductor substrates (and packaged within a single semiconductor package as a single IC), or may be included as a module separately from devices 102 and 104 within multiple IC packages.

[0025] The state detector and controller circuit element 110 monitors signaling, e.g., one or more signals or sequences of signals, such as those included in one or more eUSB2 packets and / or control commands or messages, on bus 101. The state detector and controller circuit element 110 then detects the state of communication on bus 101 (referred to herein as the bus state or simply the state) from the signaling. Also, in response to the detected state, the state detector and controller circuit element 110 controls, e.g., enables or disables, the operation of the signal conditioner circuit element 108 and / or the level shifter circuit element 112.

[0026] To monitor the signaling on bus 101 and detect the bus state, the state detector and controller circuit element 110 includes a receiver circuit element (not shown) coupled to bus 101 to receive the signaling, and one or more finite state machines (not shown) to detect the bus state from the received signaling. The detected state may include or indicate, for example, the port configuration at startup, the data (e.g., bit) rate or other data communication speed used for communication, the suspension or resumption of communication, entry into or exit from a low power mode or other power management state, the reset of a device on the bus, the connection or disconnection of a device, etc.

[0027] In one example, when detecting a first data rate, e.g., an eUSB2 high speed data rate, the state detector and controller circuit element 110 enables the signal conditioner circuit element 108 and disables the level shifter circuit element 112. Conversely, when detecting a second data rate, e.g., an eUSB2 low speed or full speed data rate, the state detector and controller circuit element 110 disables the signal conditioner circuit element 108 and enables the level shifter circuit element 112. In another example, when detecting a low power mode or state, e.g., an eUSB2 L1 power state (also referred to herein as the L1 state), the state detector and controller circuit element 110 causes the intermediate device 106 to enter a low power mode or state by disabling all or a portion of the signal conditioner circuit element 108. The intermediate device 106 may also disable all or a portion of the level shifter circuit element 112 while in the low power mode or state. Entering the low power mode enables power savings.

[0028] The level shifter circuit element 112 converts signals on the bus 101 from one logic level or voltage domain to another between the devices 102 and 104. In one example, the level shifter circuit element 112 converts signals without using a retimer circuit element at the bit level, e.g., at one bit at a given point in time, and is thus also referred to herein as a “bit level repeater”. This enables communication between the devices 102 and 104, including two eUSB2 devices, via the bus 101 when the devices have different supply and ground levels, using the advantage of being protocol independent, i.e., not related to the communication protocol used between the devices. This is contrary to an eUSB2 hybrid repeater that requires the ability to be implemented as a “packet level repeater” by converting an entire packet and control commands or messages between eUSB2 devices by conforming to the eUSB2 definition for ports, retimers and full clock and data recovery (CDR) circuit elements. Thus, the bit level repeater described herein can be advantageously implemented with less complexity and associated cost than an eUSB2 hybrid repeater.

[0029] A further advantage of the level shifter circuit element 112 is that it can enable communication between devices 102 and 104 as one or more characteristic sizes of components of the device (e.g., transistors) are reduced. For example, eUSB2 currently supports devices that operate at 1.2 and 1.0 volts (V) (e.g., support a 5 nanometer (nm) process node), and between them, the level shifter circuit element 112 can directly convert signals between two eUSB2 devices at the bit level. As the characteristic size is reduced, for example, in the case of 3nm and 2nm process nodes, and further, with associated low voltage domains such as 0.8V, the level shifter circuit element 112 can convert signals between additional voltage domains. This advantageously enables the use of the intermediate device 106 to support bit-level conversion of eUSB2 device to eUSB2 device when eUSB2 expands to accommodate the low voltage domain.

[0030] The signal regulator circuit element 108 includes a signal booster circuit element (not shown) that boosts the power of signaling on the bus 101 without the complexity of acting as a packet repeater here. In one example, the signal regulator circuit element 108 adjusts the signal on the bus 101 during eUSB2 high-speed signaling by detecting the edges of the active signal on the bus 101 and injecting an active current onto the bus 101. Injecting current onto the bus 101 can increase the edge transition rate and correspondingly decrease the transition time of the edge on the bus 101, thus improving the eye pattern of the signal and increasing the length of the bus 101. Therefore, the signal regulator circuit element 108 can advantageously overcome the limitation of the maximum trace length of 10 inches between two eUSB2 devices to meet the eye pattern constraints defined in the eUSB2 standard. The use of a longer bus is advantageous in some applications where a larger circuit board or flexible cable connection is desired.

[0031] Figure 2 shows an eUSB2 system 200 according to the example to be described. System 200 is an exemplary implementation of system 100 in FIG. 1. System 200 includes two eUSB2 devices 202 and 204 and an intermediate device 206. eUSB2 devices 202 and 204 are exemplary implementations of devices 102 and 104, and intermediate device 206 is an exemplary implementation of intermediate device 106.

[0032] In one example, devices 202-206 are included in or on the same physical arrangement or assembly 214. For example, physical arrangement 214 is a computer system such as a laptop, desktop, mobile phone, tablet, wearable device, television, or monitor. In another example, physical arrangement 214 is a circuit board such as a PCB. Also, although only two eUSB2 devices 202 and 204 and one intermediate device 206 are shown, additional such devices may be included within system 200. Also, eUSB2 devices 202 and 204 may each be included on a single semiconductor substrate (and packaged within a single semiconductor package), included on multiple semiconductor substrates (and packaged within a single semiconductor package as a single IC), or included as modules within multiple IC packages.

[0033] In one example, eUSB2 device 202 is a SoC that operates as a host or controller device, and eUSB2 device 204 is a connected device, which can be another SoC, a data storage or memory device, an eUSB2 repeater, etc. Other examples of eUSB2 devices 202 and 204 are also expected to be within the scope of this description. eUSB2 devices 202 and 204 include circuit elements (not shown) that enable serial communication via bus 201 using a communication protocol defined by, consistent with, and / or compliant with eUSB2. Depending on the device type, devices 202 and 204 include circuit elements (not shown) for communicating in native mode and / or repeater mode.

[0034] Bus 201 includes conductors 203, 205, 207, and 209 for transferring signaling between eUSB2 devices 202 and 204. A conductor can include one or more electrical traces, conductors, or other types of signal lines. As shown, eUSB2 device 202 includes an eUSB2 data + pin eDP0 (eDP0 pin) coupled to conductor 203 of data bus 201, and an eUSB2 data - pin eDM0 (eDM0 pin) coupled to conductor 205 of data bus 201. eUSB2 device 204 includes an eUSB2 data + pin eDP1 (eDP1 pin) coupled to conductor 207 of data bus 201, and an eUSB2 data - pin eDM1 (eDM1 pin) coupled to conductor 209 of data bus 201.

[0035] In the illustrated example of FIG. 2, the eDP0, eDM0, eDP1, and eDM1 pins, and bus 201 enable eUSB2 devices 202 and 204 to communicate signaling at a first data rate called "high speed", a second data rate called "full speed", and a third data rate called "low speed". The "high speed" data rate is the highest data rate supported by eUSB2 and is currently defined in the standard as 480 megabits per second (Mb / s). The "full speed" data rate is an intermediate data rate supported by eUSB2 and is currently defined in the standard as 12 Mb / s. The "low speed" data rate is the lowest data rate supported by eUSB2 and is currently defined in the standard as 1.5 Mb / s.

[0036] The intermediate device 206 is coupled to the bus 201 and facilitates communication between devices 202 and 204. In this example, the intermediate device 206 (similar to the intermediate device 106 in FIG. 1) includes a signal conditioner circuit element 208 (similar to the signal conditioner circuit element 108 in FIG. 1), a state detector and controller circuit element 210 (similar to the state detector and controller circuit element 110 in FIG. 1), a level shifter circuit element 212 (similar to the level shifter circuit element 112 in FIG. 1), an L1 mode or state detector circuit element 216 (also referred to herein as the L1 circuit element 216), and an eSE1 mode or state detector circuit element 218 (also referred to herein as the eSE1 circuit element 218). The components or elements 208-212, 216, and 218 of the intermediate device 206 may be included on a single semiconductor substrate (and packaged within a single semiconductor package), may be included on a plurality of semiconductor substrates (and packaged within a single semiconductor package as a single IC), or may be included as a module separately from the eUSB2 devices 202 and 204 within a plurality of IC packages.

[0037] The state detector and controller circuit element 210 monitors signaling, e.g., one or more signals or sequences of signals included in one or more packets and / or control messages on the bus 201. The state detector and controller circuit element 210 then detects the state of communication on the bus 201 (i.e., the bus state or status) from the signaling. In response to the detected state, the state detector and controller circuit element 210 controls, e.g., enables or disables, the operation of the signal conditioner circuit element 208, the level shifter circuit element 212, the L1 circuit element 216, and / or the eSE1 circuit element 218. Also, when enabled, the L1 circuit element 216 and / or the eSE1 circuit element 218 may provide an input to the state detector and controller circuit element 210 to further control the operation of the signal conditioner circuit element 208 and / or the level shifter circuit element 212.

[0038] To monitor the signaling on bus 201 and detect the bus state, the state detector and controller circuit element 210 includes a receiver circuit element coupled to bus 201 to receive the signaling, and a digital finite state machine (FSM) 222 for detecting the bus state from the received signaling. The digital FSM 222 includes an FSM 224 implemented by digital circuit elements and one or more oscillators 226 coupled to the FSM 224. The digital circuit elements of the FSM 224 can include one or more, or combinations thereof, of logic gates, combinational logic, flip-flops, relays, resistors, programmable logic devices, and / or programmable logic controllers. The FSM 224 is implemented as a simplified state machine that passively detects the bus state instead of actively participating in protocol handshakes like a packet repeater. The oscillator 226 provides one or more clock signals to enable sampling of the signal at the receiver output used by the FSM 224 to detect the bus state. The oscillator 226 can be implemented using a crystal oscillator, a microelectromechanical systems (MEMS) device, a bulk acoustic wave device, or other electronic device oscillator.

[0039] The state detector and the receiver circuit elements of the controller circuit element 210 include single-ended or single-input receivers 228, 230, 232, and 234, and differential receivers 236 and 238. For example, receivers 228 to 234 are voltage buffers, such as single-ended complementary metal-oxide-semiconductor (CMOS) buffers, which act as analog comparators that compare a single signal at the input with a function of the supply voltage provided to a comparator to determine the signal at the output. For example, when the signal input to a single-ended receiver exceeds half of the voltage supply, the output signal is at logic level 1, and when it does not, the output signal is at logic level 0. Receivers 236 and 238 are differential receivers that compare the signals at two inputs to generate a signal at the output. For example, when the signal at the eDP0 pin exceeds the signal at the eDM0 pin, the output signal is at logic level 1, and when it does not, the output is at logic level 0. Similarly, when the signal at the eDP1 pin exceeds the signal at the eDM1 pin, the output signal is at logic level 1, and when it does not, the output is at logic level 0. In other examples, differential receivers 236 and 238 are not included in the state detector and the controller circuit element 210.

[0040] As shown, the input of receiver 228 is coupled to conductor 203 to receive signaling from the eDP0 pin of eUSB2 device 202, and the input of receiver 230 is coupled to conductor 205 to receive signaling from the eDM0 pin of eUSB2 device 202. The input of receiver 236 is coupled to conductors 203 and 205 respectively to receive signaling from both the eDP0 and eDM0 pins. Further shown, the input of receiver 232 is coupled to conductor 207 to receive signaling from the eDP1 pin of eUSB2 device 204, and the input of receiver 234 is coupled to conductor 209 to receive signaling from the eDM1 pin of eUSB2 device 204. The input of receiver 238 is coupled to conductors 207 and 209 respectively to receive signaling from both the eDP1 and eDM1 pins. The outputs of receivers 228 to 238 are coupled to FSM224.

[0041] During operation, the FSM 224 samples signaling from receivers 228-238 via its digital circuit elements to determine the bus state. For example, when the eUSB2 device 202 functions as an SoC controller or host, the eUSB2 device 202 may detect the startup or connection of the eUSB2 device 204 on the bus 201. Alternatively, during communication on the bus 201, if the eUSB2 device 204 supports low-speed, full-speed, and high-speed signaling, the data rate may change from one data rate to another, e.g., from low-speed or full-speed to high-speed signaling. In response or accordingly, the eUSB2 device 202 and / or the eUSB2 device 204 transmits signaling on the bus 201 indicating the data rate for communication on the bus 201. In one example, the signaling includes a specific sequence of voltage levels distinguishable by the FSM 224. The signaling may include control signaling, e.g., control commands or messages indicating the L0 state and the data rate of the L0 state.

[0042] In one example, the FSM 224 receives one or more voltage output signal sequences from receivers 228 and 230 that the FSM 224 identifies as low-speed or full-speed signaling on the bus 201. In accordance with eUSB2, to distinguish low-speed from full-speed signaling, all low-speed signaling is the reciprocal of full-speed, e.g., eD+ and eD- are swapped except for control message signaling. Alternatively, the FSM 224 receives one or more voltage output signal sequences from receivers 228 and 230 and / or one or more voltage output signal sequences from the differential receiver 236 that the FSM 224 identifies as high-speed signaling on the bus 201.

[0043] In one example, when detecting the eUSB2 high-speed data rate, the FSM224 transmits one or more signals on conductor 211 that couples the signal conditioner circuit element 208 to the state detector and controller circuit element 210. The FSM224 also transmits one or more signals on conductor 213 that couples the level shifter circuit element 212 to the state detector and controller circuit element 210. One or more signals (e.g., an enable signal) on conductor 211 enable the operation of the signal conditioner circuit element 208. One or more signals (e.g., a disable signal) on conductor 213 disable the operation of the level shifter circuit element 212. Conversely, when detecting the eUSB2 low-speed or full-speed data rate, or by default when the signal conditioner circuit element 208 is not operating, the FSM224 transmits one or more signals on conductors 211 and 213 to disable the operation of the signal conditioner circuit element 208 and to enable the operation of the level shifter circuit element 212. In one example, the enable signal is a logic level 1 or "high" signal or state, and the disable signal is a logic level 0 or "low" signal or state. However, in another example, the opposite may be implemented.

[0044] In addition, when detecting the eUSB2 high-speed data rate, the FSM224 transmits one or more signals on conductor 215 that couples the L1 circuit element 216 to the state detector and controller circuit element 210. One or more signals on conductor 215 enable the operation of the L1 circuit element 216 during the operation of the signal conditioner circuit element 208.

[0045] When the L1 circuit element 216 detects the eUSB2 L1 state, it signals the FSM224 via the conductor 215 that couples the L1 circuit element 216 to the state detector and controller circuit element 210. In response, the FSM224 may transmit one or more signals on the conductors 211 and 215 to disable the operation of the signal conditioner circuit element 208 and the L1 circuit element 216, for example, until the FSM224 detects the resumed state of eUSB2 L1. In response to the L1 resumed state and, in some examples, when detecting the eUSB2 high data rate, the FSM224 may transmit one or more signals on the conductors 211 and 215 to re-enable the operation of the signal conditioner circuit element 208 and the L1 circuit element 216. The L1 state is part of the link power management according to eUSB2. The exemplary implementation and its operation of the L1 circuit element 216 will be described later with reference to FIGS. 6-8.

[0046] The eSE1 circuit element 218 detects the eUSB2 single-ended 1 (eSE1) state or the XeSE1 state. Exemplary eSE1 states include, by way of example, Extended Single-Ended 1 (ESE1), SOWake, SOResume, and SOReset. In a particular example, the ESE1 state notifies of a device disconnect event or a port reset event during the startup of the eUSB2 device 202 and / or 204. The eSE1 circuit element 218 that detects a port reset during startup proceeds to the FSM224 that detects the data rate used on the bus 201 and enables it in this example. The ESE1 state is detected when the signaling on both of the conductors 203 and 205 is at the logical level 1, or when the high state or signaling on both of the conductors 207 and 209 is in the high state for a time period defined by the eUSB2 standard.

[0047] During operation of the FSM 224 to detect a high state from the output signals of receivers 228 and 230 or receivers 232 and 234, and in response thereto, the FSM 224 transmits one or more signals on conductor 217 that couples the eSE1 circuit element 218 to the state detector and controller circuit element 210. One or more signals on conductor 217 reset the operation of the eSE1 circuit element 218. When the eSE1 circuit element 218 detects an ESE1 state, it signals the FSM 224 via conductor 217 that couples the eSE1 circuit element 218 to the state detector and controller circuit element 210. The FSM 224 can then proceed to detect the data rate on bus 201.

[0048] In one example, the eSE1 circuit element 218 includes four single-ended receivers (not shown), such as CMOS buffers, and a counter function (not shown), such as an oscillator coupled to the receivers to generate a clock signal and a digital counter. Two of the receivers are each coupled to conductors 203 and 205 to detect signaling from the eUSB2 device 202. The other two receivers are each coupled to conductors 207 and 209 to detect signaling from the eUSB2 device 204. The eSE1 circuit element 218 may also include switches that couple the receivers to bus 201.

[0049] Upon receiving one or more signals on conductor 217, two of the switches close to couple two of the receivers to bus 201. The closed switches each couple a receiver to conductors 203 and 205 or each couple a receiver to conductors 207 and 209. When the counter indicates that a high state of the signal is maintained at the receiver output for an amount of time required to indicate an ESE1 state, the eSE1 circuit element 218 signals the FSM 224 via conductor 217. After receiving signaling indicating an ESE1 state, the FSM 224 may respond by transmitting one or more signals on conductor 217 to open the switches and reset the counter of the eSE1 circuit element.

[0050] The level shifter circuit element 212 is implemented as a bit-level repeater that converts signals on bus 201 between one logical level or voltage domain to another logical level or voltage domain between eUSB2 devices 202 and 204. In the illustrated example, the voltage domain in which the eUSB2 devices 202 and 204 operate internally, or to which they are adapted, is one of 0.8V, 1.0V, or 1.2V, which determines the high logical level, e.g., 1, in a binary configuration. The low logical level, e.g., 0, is determined by the ground reference for the level shifter circuit element 212.

[0051] The level shifter circuit element 212 includes receivers 240, 242, 244, 246 and conversion circuit elements 248, 250, 252, 254 that enable bidirectional voltage level conversion between eUSB2 devices 202 and 204. In one example, receivers 240 - 246 are single-ended CMOS buffers and conversion circuit elements 248 - 254 include switches.

[0052] As shown, the input of receiver 240 is coupled to conductor 203, and the input of receiver 242 is coupled to conductor 205 to receive signaling at the voltage level supported by eUSB2 device 202. The output of receiver 240 is coupled to the input of conversion circuit element 248, and the output of receiver 242 is coupled to the input of conversion circuit element 250. Also, the output of conversion circuit element 248 is coupled to conductor 207 and the output of conversion circuit element 250 is coupled to conductor 209 to enable conversion of the signaling from receivers 240 and 242 to the voltage and ground reference levels supported by eUSB2 device 204.

[0053] In the reverse direction, the input of receiver 244 is coupled to conductor 207, and the input of receiver 246 is coupled to conductor 209 to receive signaling at the voltage levels supported by eUSB2 device 204. The output of receiver 244 is coupled to the input of conversion circuit element 252, and the output of receiver 246 is coupled to the input of conversion circuit element 254. Also, the output of conversion circuit element 252 is coupled to conductor 203, and the output of conversion circuit element 254 is coupled to conductor 205 to enable conversion of the signaling from receivers 244 and 246 to the voltage and ground reference levels supported by eUSB2 device 202.

[0054] In one implementation, only one direction of level shifter circuit element 212 is active at a given time, for example, in the case of communication from eUSB2 device 202 to eUSB2 device 204, or in the case of communication from eUSB2 device 204 to eUSB2 device 202. For example, the signaling on conductor 213 that enables the operation of level shifter circuit element 212 also sets the direction in which the voltage conversion is to be performed. An exemplary implementation of level shifter circuit element 212 will be described below with reference to FIG. 3.

[0055] Signal conditioner circuit element 208 includes switch SW1, switch SW2, and a high-speed (HS) signal booster circuit element 220 (also referred to herein as signal booster circuit element 220). Switches SW1 and SW2 can include one or more transistors of a suitable type, such as field effect transistors (FETs) and / or bipolar junction transistors (BJTs). The first terminal or end of switch SW1 is coupled to conductor 203, and the second terminal of switch SW1 is coupled to conductor 207 and to signal booster circuit element 220. The first terminal of switch SW2 is coupled to conductor 205, and the second terminal of switch SW2 is coupled to conductor 209.

[0056] In response to one or more signals on conductor 211, switches SW1 and SW2 transition from an open state (open) to a closed state (closed) to couple signal booster circuit element 220 to bus 201. When coupled, signal booster circuit element 220 boosts the power of the signaling on bus 201. An exemplary implementation of signal conditioner circuit element 208 will be described below with reference to FIGS. 4 and 5.

[0057] FIG. 3 shows a level shifter circuit element 312 according to the example being described. Level shifter circuit element 312 is an exemplary partial implementation of level shifter circuit element 112 of FIG. 1 and level shifter circuit element 212 of FIG. 2. In particular, the components illustrated in FIG. 3 enable voltage conversion of low-speed and full-speed signaling from eUSB2 device 202 to eUSB2 device 204. The same or similar circuit elements may be used to enable voltage conversion of low-speed and full-speed signaling from eUSB2 device 204 to eUSB2 device 202.

[0058] Level shifter circuit element 312 includes receivers 240 and 242 coupled to eDP0 and eDM0 pins via conductors 203 and 205 respectively, programmable voltage supplies 300 and 302, conversion circuit element 348 including switches SW3 and SW4, conversion circuit element 350 including switches SW5 and SW6, and switches SW7 and SW8. Switches SW3 and SW4 operate alternately, meaning that when one switch is open, the other switch is closed, and vice versa. Similarly, switches SW5 and SW6 operate alternately. Also, switches SW3 - SW8 can include one or more transistors of a suitable type such as FETs and / or BJTs. Also, programmable voltage supplies 300 and 302 can each be programmed to 0.8V, 1.0V, or 1.2V. However, other voltage levels are also expected to be within the scope of this description.

[0059] Programmable voltage supply 300 is coupled to each input of receivers 240 and 242 and the voltage level V supported by eUSB2 device 202 SUPPLY1is programmed. The programmable voltage supply 302 is coupled to the respective first terminals of switches SW3 and SW5 and has a voltage level V supported by the eUSB2 device 204 SUPPLY2 is programmed. The second terminal of switch SW3 is coupled to the output of receiver 240 and the first terminal of switch SW4. The third terminal of switch SW3 is coupled to the second terminal of switch SW4 and the first terminal of switch SW7. The third terminal of switch SW4 is coupled to the ground reference 304 (also referred to herein as ground 304) of the eUSB2 device 204. Conductor 213 is coupled to the respective second terminals of switches SW7 and SW8, and the third terminal of switch SW7 is coupled to conductor 207

[0060] The second terminal of switch SW5 is coupled to the output of receiver 242 and the first terminal of switch SW6. The third terminal of switch SW5 is coupled to the second terminal of switch SW6 and the first terminal of switch SW8. The third terminal of switch SW6 is coupled to ground 304, and the third terminal of switch SW8 is coupled to conductor 209

[0061] In response to an enable signal, e.g., a logic 1, on conductor 213, switches SW7 and SW8 transition from an open state to a closed state to couple the conversion circuit elements 348 and 350 to conductors 207 and 209, respectively. In one example, when the signaling at the input of receiver 240 exceeds VSUPPLY1 / 2, the output of receiver 240 is at a logic level 1, which represents a logic level 1 for the eUSB2 device 202. The logic level 1 at the output of receiver 240 closes switch SW3 to provide V SUPPLY2 on conductor 207, which represents a logic level 1 for the eUSB2 device 204. The logic level 1 at the output of receiver 240 causes switch SW4 to be in an open state

[0062] Conversely, when the signaling at the input of receiver 240 is V SUPPLY1When it is less than V / 2, the output of the receiver 240 is at a logic level 0, which represents a logic level 0 for the eUSB2 device 202. The logic level 0 at the output of the receiver 240 closes the switch SW4 to provide a ground reference 304 on the conductor 207, which represents a logic level 0 for the eUSB2 device 204. The logic level 0 at the output of the receiver 240 results in the open state of the switch SW3.

[0063] Similarly, when the signaling at the input of the receiver 242 is above V SUPPLY1 / 2, the output of the receiver 242 is at a logic level 1, which represents a logic level 1 for the eUSB2 device 202. The logic level 1 at the output of the receiver 242 closes the switch SW5 to provide V on the conductor 209, which represents a logic level 1 for the eUSB2 device 204. The logic level 1 at the output of the receiver 242 results in the open state of the switch SW6. SUPPLY2 When the signaling at the input of the receiver 242 is above V

[0064] Conversely, when the signaling at the input of the receiver 242 is less than V SUPPLY1 / 2, the output of the receiver 242 is at a logic level 0, which represents a logic level 0 for the eUSB2 device 202. The logic level 0 at the output of the receiver 242 closes the switch SW6 to provide a ground reference 304 on the conductor 209, which represents a logic level 0 for the eUSB2 device 204. The logic level 0 at the output of the receiver 242 results in the open state of the switch SW5. Also, in response to receiving a disable signal, e.g., a logic 0, on the conductor 213, the switches SW7 and SW8 transition from a closed state to an open state to disconnect the conversion circuit elements 348 and 350 from the conductors 207 and 209, respectively.

[0065] FIG. 4 shows a signal regulator circuit element 408 according to the example to be described. The signal regulator circuit element 408 is an exemplary implementation of the signal regulator circuit element 108 of FIG. 1 and the signal regulator circuit element 208 of FIG. 2. The signal regulator circuit element 408 includes switches SW1 and SW2, switches SW9 and SW10, and a signal booster circuit element 220.

[0066] The signal line 401 of the conductor 211 is coupled to the first terminal of each of the switches SW1 and SW2, and the signal line 403 of the conductor 211 is coupled to the first terminal of each of the switches SW9 and SW10. The second terminal of the switch SW1 is coupled to the conductor 203, and the third terminal of the switch SW1 is coupled to the conductor 207 and the second terminal of the switch SW9. The third terminal of the switch SW9 is coupled to the signal booster circuit element 220. The second terminal of the switch SW2 is coupled to the conductor 205, and the third terminal of the switch SW2 is coupled to the conductor 209 and the second terminal of the switch SW10. The third terminal of the switch SW10 is coupled to the signal booster circuit element 220.

[0067] In response to an enable signal, such as a logic 1, on the signal lines 401 and 403 of the conductor 211, the switches SW1, SW2, SW9, and SW10 transition from an open state to a closed state. The closed switches SW1 and SW9 couple the conductors 203 and 207 to the signal booster circuit element 220, and the closed switches SW2 and SW10 couple the conductors 205 and 209 to the signal booster circuit element 220. This enables the operation of the signal booster circuit element 220.

[0068] FIG. 5 shows a schematic diagram of a signal booster circuit element 520 according to the example to be described. The signal booster circuit element 520 is an exemplary implementation of the signal booster circuit element 220 of FIGS. 2 and 4. The signal booster circuit element 520 includes transition detector circuits 500 and 502, current sources 504 and 506, and switches SW11 and SW12. In one example, the transition detection circuit 500 receives differential signals of data + and data - (e.g., from the eDP0 and eDM0 pins, or from the eDP1 and eDM1 pins) and is a differential comparator having first and second inputs coupled to the bus 201 for detecting the rising edge of the differential signal therefrom. Similarly, the transition detection circuit 502 receives differential signals of data + and data - and is a differential comparator having first and second inputs coupled to the bus 201 for detecting the falling edge of the differential signal therefrom.

[0069] The output of the transition detector circuit 500 is coupled to the first terminal of the switch SW11. The second terminal of the switch SW11 is coupled to the output of the current source 504, and the third terminal of the switch SW11 is coupled to the bus 201 to receive signaling from the eDP0 and eDP1 pins during the operation of the signal booster circuit element 220. Similarly, the output of the transition detector circuit 502 is coupled to the first terminal of the switch SW12. The second terminal of the switch SW12 is coupled to the output of the current source 506, and the third terminal of the switch SW12 is coupled to the bus 201 to receive signaling from the eDM0 and eDM1 pins during the operation of the signal booster circuit element 220.

[0070] When detecting the rising edge of the differential signal on the bus 201, the transition detector circuit 500 outputs a signal to close the switch SW11. In response, the current source 504 supplies current to the conductor 203 or 207 (depending on the direction of the high-speed signaling) to boost the rising edge on the conductor. When the rising edge is not detected, the transition detector circuit 500 outputs a signal to open the switch SW11 to disconnect the current source 504 from the bus 201.

[0071] When detecting the falling edge of the differential signal on the bus 201, the transition detector circuit 502 outputs a signal to close the switch SW12. In response, the current source 506 sinks the current from the conductor 205 or 209 (depending on the direction of the high-speed signaling) to boost the falling edge on the conductor. When the falling edge is not detected, the transition detector circuit 502 outputs a signal to open the switch SW12 to disconnect the current source 506 from the bus 201.

[0072] In another example, current sources 504 and 506 are adjustable current sources. For example, the state detector and controller circuit element 210 (or 110) may include a circuit element (not shown) that senses the impedance on bus 201 to determine the boost current provided via current sources 504 and 506. Also, in some examples, the signal booster circuit element 520 is triggered only when a high-speed packet is transmitted on bus 202. Otherwise, the signal booster circuit element is idle.

[0073] The injected current improves the rise and fall times of signals traveling in either direction via bus 201 so as to increase the signal transmission distance. The packet repeater may add jitter and skew, may truncate the start of packet bits, and may add drive bits at the end of the packet. However, the signal booster circuit element 520 may be implemented without one or more of these constraints.

[0074] FIG. 6 shows an L1 circuit element 616 according to the example to be described. The L1 circuit element 616 is an exemplary implementation of the L1 circuit element 216 of FIG. 2. The L1 circuit element 616 includes a clock and data recovery (CDR) circuit 600 and an FSM 602. The CDR circuit 600 derives a clock, for example a 480 megahertz (MHz) clock, from one or more packets on bus 201 and provides it to the FSM 602 for use in detecting the L1 state.

[0075] The CDR circuit 600 includes a receiver 604, current sources 606 and 608, differential amplifiers 610, comparators 612 and 614, a delay circuit 618, switches SW13 to SW15, capacitors C1 and C2, and resistors R1 and R2. In one example, the delay circuit 618 is a delay line, the capacitors C1 and C2 have the same capacitance, the resistors R1 and R2 have the same resistance value, and the receiver 604 is a differential receiver that compares the signals at its two inputs to generate a signal at its output. For example, when the signal at the eDP0 pin exceeds the signal at the eDM0 pin, the output signal is at logic level 1, and when it does not exceed, the output signal is at logic level 0. Similarly, when the signal at the eDP1 pin exceeds the signal at the eDM1 pin, the output signal is at logic level 1, and when it does not exceed, the output signal is at logic level 0. Also, the switches SW13 to SW15 can be FETs, BJTs, or a combination thereof.

[0076] The FSM 602 includes digital logic 622 and a counter 624. The logic 622 is used to detect a packet identifier (PID) used to indicate the L1 state. Additional logic (not shown), such as for performing other functions such as detecting one or more additional PIDs, can be included in the FSM 602. The counter 624 is coupled to the output of the receiver 604 and assists in detecting the PID from one or more packets on the data bus 201. The FSM 602 can include one or more of logic gates, combinational logic, flip-flops, relays, resistors, programmable logic devices, and / or programmable logic controllers, or a combination thereof. The FSM 602 also passively detects information from the communication on the bus 201 but does not actively participate in communication protocol exchanges.

[0077] As shown, the output of the receiver 604 is coupled to the respective first terminals of switches SW13 and SW14, and also to the input of the FSM 602. The second terminal of switch SW13 is coupled to the output of the current source 606, and the third terminal of switch SW13 is coupled to the first terminal of capacitor C1, the non-inverting input of the differential amplifier 610, and the non-inverting input of the comparator 614. The second terminal of capacitor C1 is coupled to the ground reference 620 (also referred to herein as ground 620).

[0078] The resistor R1 and R2 and the differential amplifier 610 are all coupled together to form a voltage multiplier, in this case a voltage doubler. That is, the inverting input of the differential amplifier 610 is coupled to the respective first terminals of the resistor R1 and R2. The second terminal of resistor R1 is coupled to the ground 620, and the second terminal of resistor R2 is coupled to the output of the differential amplifier 610.

[0079] The inverting input of the comparator 612 is also coupled to the output of the differential amplifier 610. The non-inverting input of the comparator 612 is coupled to the non-inverting input of the comparator 614, the respective first terminals of the switch SW15 and the capacitor C2, and the output of the current supply 608 via the switch SW14. The respective second terminals of the capacitor C2 and the switch SW15 are coupled to the ground 620. The output of the comparator 612 is coupled to the input of the delay circuit 618, and the output of the delay circuit 618 is coupled to the third terminal of the switch SW15. Finally, the output of the comparator 614 is coupled to another input of the FSM 602 to assist in detecting the PID from one or more packets on the data bus 201.

[0080] The operation of the CDR circuit 600 will be described with reference to the exemplary signaling diagram 700 illustrated in FIG. 7. The signaling diagram 700 shows differential signals 702 and 704 provided at the input of the receiver 604. In one example, signal 702 is the signal provided on conductor 203 from the eDP0 pin, and signal 704 is the signal provided on conductor 205 from the eDM0 pin. Alternatively, signal 702 is the signal provided on conductor 207 from the eDP1 pin, and signal 704 is the signal provided on conductor 209 from the eDM1 pin. For clarity, the operation of the L1 circuit element 616 will be described with reference to the eUSB2 device 202 that transmits high-speed signaling to the eUSB2 device 204, and the signaling includes an eUSB2 packet. Accordingly, signal 702 is referred to as the eDP0 signal 702, and signal 704 is referred to as the eDM0 signal 704.

[0081] The end of packet (EOP) of the first packet is shown at 706. Following the EOP, SE0 (single-ended zero) is shown at 708. The SE0 state is indicated by both the eDP0 signal 702 and the eDM0 signal 704, and in this example, is a logic level 0 or low state. The SE0 state is just before the start of the next packet, and the start of the SYNC pattern 710 indicates the start of the next packet. The CDR circuit 600 uses the SYNC pattern 710 to generate a 480 MHz clock.

[0082] During the SE0 state, the L1 circuit element 616 is reset. For example, the FSM 224 detects the SE0 state and sends an enable / reset signal through conductor 215 to the L1 circuit element 616. In response to the enable / reset signal, the FSM 602 resets the logic 622 to its starting state, resets the counter 624, which resets the clock of the FSM 602. Also, in the illustrated implementation, current sources 606 and 608 are in an OFF state at the start of the SYNC pattern. In a further example, since the FSM 224 enables / resets the L1 circuit element 616 only when first enabling the signal conditioner circuit element 210, the circuit elements 210 and 616 can operate simultaneously. Subsequent SE0 states are detected by logic (not shown) included in the FSM 602, and this detection leads to the reset of the L1 circuit element 616.

[0083] The start of the first SYNC bit of the SYNC pattern 710 is shown at 712. Thereafter, each time the eDP0 signal 702 transitions to be greater than the eDM0 signal 704 (thereby causing the output of the receiver 604 to transition to logic 1), the counter 624 increments to count the number of SYNC bits. The switches SW13 and SW14 close in response to logic 1 at the output of the receiver 604. However, whether the current sources 606 and 608 are in an ON state to charge their respective capacitors C1 and C2 to which they are coupled depends on the counter value.

[0084] That is, at 716, the current source 606 is turned ON after and / or in response to the counter 624 counting the first SYNC bit. This enables the current source 606 to charge the capacitor C1 when the switch SW13 closes. The current source 606 is turned OFF at 718 after and / or in response to the counter 624 counting the third SYNC bit. By this point, the capacitor C1 has been charged for an amount of time sufficient to generate a voltage V1 across the capacitor C1.

[0085] Voltage V1 is provided as a reference voltage at the inverting input of comparator 614. Voltage V1 is also provided to the non-inverting input of differential amplifier 610, generating a voltage of 2×V1 at the output of differential amplifier 610. Voltage 2×V1 is provided as a reference voltage at the inverting input of comparator 612. The accuracy of reference voltages V1 and 2×V1 is limited by the leakage on capacitor C1.

[0086] At 720, current source 608 is turned ON after counter 624 counts the seventh SYNC bit and / or in response to counter 624 counting the seventh SYNC bit. The current ratio Ix to I (Ix / I) between current sources 608 and 606 is used to adjust the clock frequency to compensate for the delay between turning OFF current source 606 and turning ON current source 608. The turn-ON of current source 608 enables the charging of capacitor C2 when switch SW14 is closed and further enables the operation of comparators 612 and 614 and switch SW15 to generate a 480 MHz clock signal (CLK) at the output of comparator 614. Generally, the timing information from signals 702 and 704 is stored in the form of a voltage VRAMP across capacitor C2.

[0087] More specifically, when capacitor C2 is charging, the ramp voltage VRAMP rises and is provided to the non-inverting inputs of comparators 612 and 614 respectively. While VRAMP < V1, CLK is low and the reset signal (RESET) output from comparator 612 is low. The low RESET keeps switch SW15 open. When VRAMP exceeds V1, CLK goes high. When VRAMP exceeds 2×V1, RESET goes high.

[0088] After the delay is generated by the delay circuit element 618, the high RESET closes the switch SW15. In response, the capacitor C2 starts discharging and pulling down VRAMP. When VRAMP becomes lower than 2×V1, RESET goes low. However, the low RESET is delayed for a time sufficient to lower VRAMP below V1 and pull down CLK. When the low RESET is provided to the switch SW15, SW15 transitions to the open state to allow the capacitor C2 to start recharging for generating the next CLK pulse.

[0089] Although not shown in FIG. 7, the PID of the current packet starts after the SYNC pattern 710 ends. The FSM 602 receives both output signals from the receiver 604 and CLK. CLK is used to sample the output signal from the receiver 604 to enable the logic 622 to detect the PID indicating entry into the low power state. For example, entry into the L1 state is indicated by the EXT PID 1010. The logic 622 ends if it fails to detect the EXT PID. In response, the L1 circuit element 616 is reset and waits for the next packet. However, if the logic 622 detects the EXT PID, the L1 circuit element 616 resets and attempts to detect the SUB PID and ACK PID using additional logic (not shown) of the FSM 602. If the FSM 602 fails to detect the SUB PID or ACK PID, the L1 circuit element 616 is reset and waits for the next packet. When the EXT PID, SUB PID, and ACK PID are detected, the FSM 602 signals the FSM 224 on the conductor 215, for example using logic 1, to indicate a valid entry into the L1 state.

[0090] FIG. 8 shows a signaling diagram 800 showing simulation results from the L1 circuit element 616 that detects the L1 state. The signaling diagram 800 shows an eDP and eDM signal 802 that carries a plurality of packets, a CLK signal 804 generated from the packets communicated by the eDP and eDM signal 802, and a signal 806 on the conductor 215. Decomposed segments 808 of the eDP and eDM signal 802 and the CLK signal 804 include a generated CLK signal 810 used to detect the EXT PID 812 of the first packet, a generated CLK signal 814 used to detect the SUB PID 816 of the second packet, and a generated CLK signal 818 used to detect the ACK PID 820 of the third packet. After the ACK PID is detected, the FSM 602 transmits a logic 1 to the FSM 624 on the conductor 215 (shown at 824) to enter the L1 state. In this example, as shown at 822, the FSM 602 waits for 10 microseconds after the ACK PID signals L1 detection. However, in other examples, this waiting period may be different or there may be no waiting period.

[0091] FIG. 9 is a flowchart of an exemplary method 900 for operating an intermediate device that includes a signal regulator circuit element, a level shifter circuit element, and a state detector and controller circuit element. In one example, method 900 is performed by the intermediate device 106 described with reference to FIG. 1. In another example, method 900 is performed by the intermediate device 206 described with reference to FIG. 2. In yet another example, method 900 implements only some or some of the functionality or operability of the intermediate device according to the example being described, and method 900 shows one exemplary method of operation. For clarity, method 900 will be described with reference to the exemplary intermediate device 206 as described above with reference to FIGS. 2-8.

[0092] According to method 900, the state detector and controller circuit element 210 use one or more of receivers 228 - 238 to receive a signal from bus 201 and operate digital FSM 222 in block 902 to detect the bus state or communication state from the signal. Detecting the bus state includes detecting a first data rate or a second data rate from the signal received at the receiver circuit element in block 904. In this example, FSM 224 determines in block 904 whether a high speed (HS) data rate has been detected. If FSM 224 does not detect a high speed data rate but instead detects a low speed or full speed data rate, FSM 224 enables the operation of level shifter circuit element 212 in block 906. Level shifter circuit element 212 is for shifting the voltage level of a signal from a first voltage level to a second voltage level. In one example, the level shifter circuit element is implemented and operates according to exemplary level shifter circuit element 312. While operating level shifter circuit element 212, method 900 also continues the operation of digital FSM 222 including data rate detection in block 902 to enable detection of other bus states as necessary.

[0093] When the FSM224 detects a high data rate, the FSM224 enables the operation of the signal conditioner circuit element 208 in block 908 and the operation of the L1 circuit element 216 in block 910. In one example, the signal conditioner circuit element is implemented and operates according to the exemplary signal conditioner circuit element 408 and the HS signal booster 520, and the L1 circuit element is implemented and operates according to the exemplary L1 circuit element 616. For example, operating the signal conditioner circuit element 208 is for boosting the edges of the signal. Also, in one example, operating the L1 circuit element 216 is for detecting the L1 state in block 912. For example, operating the L1 circuit element 216 includes generating a clock signal by, for example, a CDR circuit 600 that uses each synchronization (SYNC) pattern within the packets communicated within the signal. Also, detecting the L1 state includes providing a clock signal to a finite state machine, such as the FSM622, and using the clock signal to detect the indications of the EXT PID, SUB PID, and ACK PID in a series of packets by the finite state machine.

[0094] In block 912, if the L1 state is not detected, method 900 continues by operating the signal conditioner circuit element 208 in block 908 and the L1 circuit element 216 in block 910. If the L1 state is detected, the intermediate device 206 operates in a low power state in block 914. The low power state includes the minimum disable of the signal conditioner circuit element 208. The low power state continues until the L1 resume state is detected in block 916. When the L1 resume state is detected, method 900 continues with the operation of the digital FSM222 including the detection of the data rate in block 902 to enable the detection of other bus states as needed.

[0095] While operating the signal conditioner circuit element 208 or the level shifter circuit element 212, the digital FSM 222 also enables the operation of the eSE1 circuit element 218 in block 918. Operating the eSE1 circuit element 218 is for detecting one or more eSE1 states from the signal in block 920. In one example, the eSE1 circuit element 218 can continue to operate until an eSE1 state is detected in block 920. Once detected, the digital FSM 222 can disable one or both of the level shifter circuit element 212 or the signal conditioner circuit element 208 in blocks 922 and 924. Method 900 includes detecting the data rate and can continue with the operation of the digital FSM 222 in block 902 to enable the detection of other bus states as needed.

[0096] FIG. 10 is a flowchart of an exemplary method 1000 for operating an intermediate device that includes a signal conditioner circuit element, a level shifter circuit element, and a state detector and controller circuit element. In one example, method 1000 is performed by the intermediate device 106 described with reference to FIG. 1. In another example, method 1000 is performed by the intermediate device 206 described with reference to FIG. 2. In yet another example, method 1000 implements only some or several of the functionality or operability of the intermediate device according to the example being described, and method 1000 shows one exemplary method of operation. For clarity, method 1000 will be described with reference to the exemplary intermediate device 206 as described above with reference to FIGS. 2-8.

[0097] According to method 1000, the state detector and controller circuit element 210 receive signals from bus 201 using one or more of receivers 228 - 234, and operate digital FSM 222 in block 1000 to detect the bus state or communication state from the signals. In this example, digital FSM 222 does not actively detect low or full speed data rates. Thus, in block 1004, when a high data rate is not detected, FSM 222 enables level shifter circuit element 212.

[0098] However, detecting the bus state includes detecting a high speed (HS) data rate from the signals received at the receiver circuit element in block 1006. If FSM 224 does not detect a high data rate, the operation of level shifter circuit element 212 continues in block 1004. In one example, the level shifter circuit element is implemented and operates according to exemplary level shifter circuit element 312.

[0099] When the FSM224 detects a high data rate, the FSM224 enables the operation of the signal conditioner circuit element 208 in block 1008, the operation of the L1 circuit element 216 in block 1010, and the eSE1 circuit element in block 1018. In one example, the signal conditioner circuit element is implemented and operates according to the exemplary signal conditioner circuit element 408 and the HS signal booster 520, the L1 circuit element is implemented and operates according to the exemplary L1 circuit element 616, and the eSE1 circuit element is implemented and operates according to the exemplary eSE1 circuit element 218. For example, operating the L1 circuit element 216 is for detecting the L1 state in block 1012, and the eSE1 circuit element 218 is for detecting one or more eSE1 states in block 1020. For example, operating the L1 circuit element 216 includes generating a clock signal, for example, by a CDR circuit 600 that uses each synchronization (SYNC) pattern communicated within the signal in a packet. Also, detecting the L1 state includes providing a clock signal to a finite state machine, for example, FSM622, and using the clock signal to detect instructions of EXT PID, SUB PID, and ACK PID in a series of packets by the finite state machine.

[0100] In block 1012, when the L1 state is detected, the intermediate device 206 operates in a low power state. The low power state includes, at a minimum, disabling the signal conditioner circuit element 208 in block 1026. However, in this example, the low power state includes enabling the digital FSM222 to operate the level shifter circuit element 212 in block 1014. The low power state continues until an L1 resume state is detected in block 1016. When the L1 resume state is detected, method 1000 enables the operation of the signal conditioner circuit element 208 in block 1010 and also disables the level shifter circuit element 212. Also, in some examples, when the L1 state is detected, the eSE1 circuit element 218 is also disabled.

[0101] Operating the eSE1 circuit element 218 is for detecting one or more eSE1 states from the signal at block 1020. In one example, the eSE1 circuit element 218 can continue to operate until the start of the eSE1 state is detected at block 1020 and until the end of the high data rate is detected at block 1024. When detected, the digital FSM 222 disables the operation of the signal conditioner circuit element 208 at block 1022 and enables the operation of the level shifter circuit element 212 at block 1004. The method 1000 can continue with the operation of the digital FSM 222 to enable the detection of the high data rate at block 1006. When detecting the eSE1 state and the high end at blocks 1020 and 1024, the digital FSM 222 can also disable the L1 circuit element 216 and the eSE1 circuit element 218.

[0102] In this specification and the claims, the terms "including" and "having" and their variations are as inclusive as the term "comprising" unless otherwise specified. Additionally, the terms "coupled" or "coupled to" mean an indirect or direct electrical or mechanical connection. This term can encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal for controlling device B to perform a certain action, in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B via an intervening component C when the intervening component C does not substantially change the functional relationship between device A and device B, and device B is controlled by device A via the control signal generated by device A.

[0103] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer during manufacture to perform that function and / or can be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration can be via the device's firmware and / or software programming, via construction and / or layout of hardware components and the device's interconnections, or via a combination thereof.

[0104] A circuit or device described herein as including particular components can instead be adapted to be coupled to those components to form the described circuit elements or devices. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) can instead include only semiconductor elements (such as semiconductor dies and / or integrated circuit (IC) packages) within a single physical device and can be adapted, either during or after manufacture, to be coupled to at least some of the passive elements and / or such sources by an end user and / or third party, etc., to form the described structure.

[0105] The circuits described herein are reconfigurable to include components that are replaced to provide functionality that is at least partially similar to the functionality available prior to the replacement of the components. A component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide a certain amount of impedance represented by the illustrated resistor, unless otherwise specified. For example, a resistor or capacitor illustrated and described herein as a single component may instead be, respectively, multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be, respectively, multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0106] Although the above refers to a particular transistor structure, other transistor or device structures may be used instead. For example, with minor additional changes or without additional changes, a p-type MOSFET may be used instead of an n-type MOSFET. Also, other types of transistors (such as bipolar transistors, NPN or PNP) may be utilized instead of the illustrated transistors. Capacitors may be implemented using different device structures (such as metal structures formed through each other to form parallel plate capacitors), or may be formed on layers (metal or doped semiconductor) closer to or farther from the surface of the semiconductor substrate.

[0107] As used herein, the terms "terminal," "node," "interconnection," and "pin" are used interchangeably. Unless otherwise specifically stated, these terms are generally used to mean an interconnection between, or an end of, device elements, circuit elements, integrated circuits, devices, or other electronic equipment or semiconductor components.

[0108] The use of the phrase "grounding" in the foregoing description includes chassis grounding, grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of ground connection that is applicable or suitable to the teachings of this specification. Unless otherwise specified, the terms "about," "approximately," or "substantially" preceding a value mean + / - 10 percent of the indicated value.

[0109] In the claims, modifications are possible in the examples described, and other examples are possible.

Claims

1. A circuit comprising: a signal conditioner circuit element; a level shifter circuit element; a state detector and controller circuit element coupled between the signal conditioner circuit element and the level shifter circuit element, a receiver circuit element; a first finite state machine coupled to the receiver circuit element, which detects a bus state from a signal on a data bus, and enables or disables the signal conditioner circuit element in response to the bus state to disable or enable the level shifter circuit element, wherein the first finite state machine is configured as such; the state detector and controller circuit element including the first finite state machine; and the circuit including the state detector and controller circuit element.

2. The circuit according to claim 1, wherein the bus state indicates a first data rate or a second data rate, and the first finite state machine is further configured to enable the operation of the signal conditioner circuit element in response to the first data rate, and enable the operation of the level shifter circuit element in response to the second data rate. The circuit is further configured as such.

3. The circuit according to claim 2, wherein the first data rate is a high data rate, and the second data rate is a low data rate or a full speed data rate.

4. The circuit according to claim 1, further comprising a low power state detection circuit element, including a differential receiver, a clock and data recovery (CDR) circuit coupled to the differential receiver, and a second finite state machine coupled to the differential receiver and the CDR circuit, which is configured to detect a low power state from the signal using a clock signal generated by the CDR circuit; the circuit further including the low power state detection circuit element including the second finite state machine.

5. The circuit according to claim 4, wherein the CDR circuit is configured to generate the clock signal using a synchronization pattern of a packet communicated in the signal, and the second finite state machine is further configured to detect a link power management LPM-L1 state using a packet identifier of the packet.

6. The circuit according to claim 1, wherein the signal conditioner circuit element is configured to boost an edge of the signal.

7. A system comprising: a first integrated circuit; a second integrated circuit; an intermediate circuit coupled on a data bus between the first integrated circuit and the second integrated circuit, a first switch, a signal conditioning circuit element configured to boost an edge of a signal on the data bus in response to the first switch being closed, a second switch, a level shifter circuit element operable in response to the second switch being closed, a state detector and controller circuit element comprising a receiver circuit element coupled to the data bus, a first finite state machine coupled to the receiver circuit element, detecting a bus state from a signal received at the receiver circuit element, closing or opening the first switch and opening or closing the second switch in response to the bus state, wherein the first finite state machine is configured as such, the state detector and controller circuit element including the intermediate circuit including a system including.

8. The system according to claim 7, wherein the first integrated circuit is a first embedded universal serial bus (eUSB2) device and the second integrated circuit is a second eUSB2 device.

9. The system according to claim 7, wherein the bus state indicates a first data rate or a second data rate, the first data rate is a high data rate, the second data rate is a low data rate or a full speed data rate, and the first finite state machine enables operation of the signal conditioning circuit element in response to the first data rate, and enables operation of the level shifter circuit element in response to the second data rate. wherein the system is further configured as such.

10. The system according to claim 7, a low power state detection circuit element comprising a differential receiver, a clock and data recovery (CDR) circuit coupled to the differential receiver, a second finite state machine coupled to the differential receiver and the CDR circuit, configured to detect a link power management LPM-L1 (L1) state from the signal using a clock signal generated by the CDR circuit, wherein the system further includes the low power state detection circuit element including.

11. The system according to claim 10, wherein the CDR circuit is configured to generate the clock signal using a synchronization pattern of packets communicated within the signal. A system, wherein the second finite state machine is further configured to detect the L1 state using the packet identifier of the packet. **Claim 12** A method comprising: Receiving a signal on a data bus; Detecting a bus state from the signal; In response to the bus state, enabling or disabling a signal conditioner circuit element that boosts an edge of the signal and enabling or disabling a level shifter circuit element that shifts a voltage level of the signal from a first voltage level to a second voltage level. A method as described above. **Claim 13** The method according to claim 12, wherein operating the signal conditioner circuit element and the level shifter circuit element comprises: Enabling the signal conditioner circuit element in response to the bus state indicating a high data rate; Enabling the level shifter circuit element in response to the bus state indicating a low data rate or a full data rate. A method as described above. **Claim 14** The method according to claim 12, further comprising operating a low power mode detection circuit element in response to the bus state to detect a link power management LPM-L1 (L1) state from the signal. **Claim 15** The method according to claim 14, wherein operating the low power mode detection circuit element comprises generating a clock signal using respective synchronization (SYNC) patterns within packets communicated in the signal. **Claim 16** The method according to claim 15, wherein detecting the L1 state comprises: Providing the clock signal to a finite state machine; Using the clock signal to detect an EXT packet identifier (PID), a SUB PID, and an ACK PID in a series of the packets by the finite state machine. A method as described above. **Claim 17** ​ ​ ​ ​ ​ ​ A level shifter coupled to the second output and adapted to be coupled to the data bus, the level shifter, comprising, wherein the state detector and the controller circuit, detect a bus state, enable the signal conditioning circuit in response to detecting a first bus state, enable the level shifter in response to detecting a second bus state, an intermediate circuit configured as such.

19. The intermediate circuit according to claim 18, wherein the first bus state is a high data rate and the second bus state is a low data rate or a full data rate, an intermediate circuit.

20. The intermediate circuit according to claim 18, wherein the signal conditioning circuit is configured to boost an edge of a signal on the data bus, an intermediate circuit.

21. The intermediate circuit according to claim 18, wherein the level shifter is configured to shift a voltage level of a signal on the data bus, an intermediate circuit.

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