Display panel and display device

Abstract

Provided is a display panel and a display device, the display panel including: a first display area; a second display area located at least on one side of the first display area; a plurality of pixel units, the density of which is less than that of the pixel units in the second display area, each pixel unit including a pixel circuit; and a first power supply line configured to provide a first voltage signal to the pixel circuit, the first power supply line including a plurality of first conductive wires, a plurality of second conductive wires, and a plurality of third conductive wires, the first conductive wires extending from the second display area to the first display area, the plurality of second conductive wires located in the first display area and between adjacent first conductive wires, the second conductive wires extending along a first direction, the third conductive wires extending along a second direction, the first direction intersecting the second direction, the third conductive wires extending from the second display area to the first display area, adjacent second conductive wires spaced apart from each other along the first direction, and the second conductive wires connected to the first conductive wires via the third conductive wires.

Description

Technical Field

[0001] (Cross - reference to related applications) For all purposes, this patent application claims the priority of Chinese Patent Application No. 202010498518.8 filed on June 4, 2020, and the entire content disclosed in the above - mentioned Chinese patent application is incorporated herein by reference as part of this application.

[0002] At least one embodiment of the present disclosure relates to a display panel and a display device.

Background Art

[0003] Based on the design of an under - screen camera, the display panel usually includes a high pixel density (Pixels Per Inch, PPI) region and a low PPI region. However, in a general display panel, the light transmittance of the low PPI region is low, which is disadvantageous for improving the display effect in the imaging region of the camera.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] At least one embodiment of the present disclosure includes a first display area, a second display area located at least on one side of the first display area, and a plurality of pixel units located in the first display area and the second display area, wherein the density of the pixel units in the first display area is less than the density of the pixel units in the second display area. The pixel unit includes a pixel circuit, and a first power line configured to provide a first voltage signal to the pixel circuit. The first power line includes a plurality of first conductors, a plurality of second conductors, and a plurality of third conductors. The first conductors extend from the second display area to the first display area. The plurality of second conductors are located in the first display area and are positioned between adjacent first conductors. The second conductors extend along a first direction. The third conductors extend along a second direction. The first direction intersects the second direction. The third conductors extend from the second display area to the first display area. Adjacent second conductors are spaced apart from each other along the first direction. The second conductors are connected to the first conductors via the third conductors, providing a display panel.

[0006] According to the display panel according to some embodiments of the present disclosure, the plurality of second conductors are sequentially arranged along the first direction.

[0007] According to the display panel according to some embodiments of the present disclosure, the adjacent second conductors are not directly connected.

[0008] According to the display panel according to some embodiments of the present disclosure, the length of the portion of the first conductor located in the first display area in the first direction is greater than the length of the second conductor in the first direction.

[0009] According to the display panel according to some embodiments of the present disclosure, the first conductor includes portions located in different layers, and the portions located in different layers are connected via vias penetrating an insulating layer.

[0010] According to the display panel according to some embodiments of the present disclosure, the first power line further includes a fourth conductor extending along the second direction, the second conductor is connected to the first conductor via the fourth conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction.

[0011] According to the display panel according to some embodiments of the present disclosure, it includes a plurality of fourth conductors located between adjacent third conductors, the plurality of fourth conductors are arranged in sequence along the second direction, and adjacent fourth conductors are spaced apart from each other in the second direction.

[0012] According to the display panel according to some embodiments of the present disclosure, a part of the first conductor and the third conductor are located in the same layer, and the fourth conductor and the third conductor are located in the same layer.

[0013] According to the display panel according to some embodiments of the present disclosure, the pixel units located in the first display area constitute a plurality of pixel islands, the pixel islands include at least two pixel units located in two adjacent rows, and the first conductor and the second conductor respectively overlap with the two pixel units located in the two adjacent rows.

[0014] According to the display panel according to some embodiments of the present disclosure, the pixel unit further includes a light-emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected via a conductive part, the second conductor further includes a connection arm, the connection arm is spaced apart from the conductive part of one pixel unit overlapping with the second conductor in the pixel island in the third direction and partially overlaps in the third direction, the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0015] According to the display panel according to some embodiments of the present disclosure, the shape of the connection arm includes a C shape.

[0016] According to the display panel according to some embodiments of the present disclosure, the first conductor has a branch, and the branch is spaced apart from the conductive portion of one pixel unit overlapping the first conductor in the pixel island in the third direction and partially overlaps in the third direction.

[0017] According to the display panel according to some embodiments of the present disclosure, the first direction is perpendicular to the second direction.

[0018] According to the display panel according to some embodiments of the present disclosure, the first power line further includes a fifth conductor, the fifth conductor extends along the first direction, is located in the second display area, is located between adjacent first conductors, and is spaced apart from an adjacent second conductor along the first direction.

[0019] According to the display panel according to some embodiments of the present disclosure, the display panel further includes an initialization signal line configured to provide an initialization signal to the pixel circuit, and the second conductor is surrounded by a part of the initialization signal line.

[0020] According to the display panel according to some embodiments of the present disclosure, the first conductor includes a first part and a second part, the first part of the first conductor is located in the same layer as the second conductor, the second part of the first conductor is not located in the same layer as the second conductor, and the first part of the first conductor is surrounded by a part of the initialization signal line.

[0021] According to the display panel according to some embodiments of the present disclosure, the first part of the first conductor has a first sub-part extending along the first direction and a second sub-part extending along the second direction, and the second sub-part has a branch extending along the first direction.

[0022] According to the display panel according to some embodiments of the present disclosure, the length of the branch in the first direction is less than the length of the first sub-part in the first direction.

[0023] According to the display panel according to some embodiments of the present disclosure, the pixel unit further includes a light-emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected via a conductive portion, the branch is spaced apart from the conductive portion of one pixel unit that overlaps the first conductor in the pixel island in the third direction, and partially overlaps in the third direction, the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0024] According to the display panel according to some embodiments of the present disclosure, the second conductor further includes a connection arm, the connection arm is spaced apart from the conductive portion of one pixel unit that overlaps the second conductor in the pixel island in the third direction, and partially overlaps in the third direction.

[0025] According to the display panel according to some embodiments of the present disclosure, the display panel further includes a base substrate and a data line configured to provide a data signal to the pixel circuit, the data line includes a first data line, the first data line extends from the first display area to the second display area, and the first data line partially overlaps with the orthographic projection of the third conductor on the base substrate.

[0026] According to the display panel according to some embodiments of the present disclosure, the first data line includes a first portion and a second portion, the first portion of the first data line partially overlaps with the third conductor, the second portion of the first data line does not overlap with the third conductor, and the first portion of the first data line and the second portion of the first data line are located in different layers.

[0027] According to the display panel according to some embodiments of the present disclosure, there is a light transmission area between adjacent pixel islands, and the first portion of the first data line is located between adjacent pixel islands.

[0028] According to a display panel according to some embodiments of the present disclosure, two first data lines are provided, and the two first data lines are respectively connected to two adjacent columns of pixel units, and the two first data lines are partially overlapped with the orthographic projection of the same third conductor on the base substrate.

[0029] According to a display panel according to some embodiments of the present disclosure, the display panel further includes a gate line configured to provide a scanning signal to one row of pixel units, and the gate line includes a first gate line extending from the second display area to the first display area, and the light transmission area is surrounded by two adjacent first gate lines and two adjacent first data lines.

[0030] Some embodiments of the present disclosure further provide a display device including any of the above display panels.

[0031] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings described below relate only to some embodiments of the present disclosure and do not limit the present disclosure.

Brief Description of the Drawings

[0032]

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DETAILED DESCRIPTION OF THE INVENTION

[0033] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, hereinafter, with reference to the drawings of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present disclosure.

[0034] Unless otherwise defined, technical or scientific terms used in this disclosure should have a general meaning understandable to those skilled in the art. The terms "first", "second" and similar terms used in this disclosure do not indicate any order, number or importance, but are merely used to distinguish different components. Similarly, similar terms such as "including" or "comprising" refer to the element or member described before the term including the elements or members listed after the term and their equivalents, and do not exclude other elements or members. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections whether directly connected or indirectly connected. Terms such as "above", "below", "left", "right" are only used to indicate relative positional relationships, and if the absolute position of the object to be described changes, the relative positional relationship may also change accordingly.

[0035] In a general display panel, regardless of whether it is a high-PPI region or a low-PPI region, all first power lines use a mesh structure. In order to improve the light transmittance of the low-PPI region and the display effect in the imaging region of the camera, the display panel according to the embodiments of the present disclosure optimizes the signal lines in the low-PPI region to achieve a higher transmittance. For example, the embodiments of the present disclosure optimize the conductors arranged vertically and horizontally in the mesh first power line.

[0036] FIG. 1A to FIG. 1C are schematic diagrams of a display panel according to some embodiments of the present disclosure. As shown in FIGS. 1A to 1C, the display panel includes a first display area R1 and a second display area R2. The first display area R1 is a high pixel density (Pixels Per Inch, PPI) area, and the second display area R2 is a low PPI area. The second display area R2 is a partial light transmission area. As shown in FIGS. 1A to 1C, the second display area R2 is located at least on one side of the first display area R1. The display panels shown in FIGS. 1A and 1B further include a third area R3. For example, a sensor such as a camera may be installed in the first display area R1 (see FIG. 1C), or may be installed in the first display area R1 and the third area R3 (see FIGS. 1A and 1B). The third area R3 shown in FIGS. 1A and 1B may be a hole digging area, that is, a through hole is formed by removing the material at the position corresponding to the third area R3. The sensor can receive ambient light. Taking the sensor as a camera as an example, an under-screen camera is realized. Thus, when the screen is used normally, the first display area corresponding to the sensor can display the screen normally. On the other hand, when shooting is performed by the camera, the first display area can transmit ambient light to assist normal use. For example, the sensor is installed on the non-display side of the display panel. The sensor may be called an under-screen device.

[0037] FIG. 1A further shows a plurality of gate lines 113 and a plurality of data lines 313. The plurality of gate lines 113 includes a first gate line GL1, and the plurality of data lines 313 includes a first data line DL1. The first gate line GL1 extends from a second display area R2 to a first display area R1. The first data line DL1 extends from the first display area R1 to the second display area R2. In an embodiment of the present disclosure, for an element extending from the first display area R1 to the second display area R2, it may be understood that the element is located in the first display area R1 and the second display area R2, and it can also be said that an element extends from the second display area R2 to the first display area R1. For clarity of illustration, FIG. 1A exemplarily shows some of the gate lines 113 and some of the data lines 313, and the numbers of the gate lines 113 and the data lines 313 can be determined as needed. The plurality of gate lines 113 and the plurality of data lines 313 intersect each other and are insulated from each other.

[0038] FIG. 2 is a schematic diagram of a second display area of a display panel according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of a first display area of a display panel according to an embodiment of the present disclosure. As shown in FIGS. 2 and 3, the display panel includes a plurality of pixel units P0, and the plurality of pixel units P0 include a first pixel unit 101, a second pixel unit 102, a third pixel unit 103, and a fourth pixel unit 104. One first pixel unit 101, one second pixel unit 102, one third pixel unit 103, and one fourth pixel unit 104 constitute a pixel group P1. For example, one pixel group P1 includes two pixels. In the pixel group P1, one first pixel unit 101 and one second pixel unit 102 constitute one pixel, and one third pixel unit 103 and one fourth pixel unit 104 constitute one pixel. One pixel group P1 forms two virtual pixels to improve the display effect. For example, one pixel group P1 is one repeating unit and is arranged in an array in the second display area R2. As shown in FIG. 3, in the first display area R1, one pixel group P1 is called one pixel island A1. The first display area R1 includes a plurality of light transmission areas R0, and the light transmission areas R0 are located between adjacent pixel islands A1. The light transmission area R0 can transmit ambient light. For example, the light transmission area R0 may include a base substrate and a transparent insulating layer located on the base substrate, and the light transmission area R0 has no light shielding structure such as a metal wiring, for example. For example, the light transmission area R0 is located within an area surrounded by four adjacent pixel islands A1, but is not limited thereto. For example, as shown in FIG. 3, adjacent pixel islands A1 may be installed at intervals.

[0039] In an embodiment of the present disclosure, it is exemplified that the first pixel unit 101 is a red pixel unit, the second pixel unit 102 is a green pixel unit, the third pixel unit 103 is a blue pixel unit, and the fourth pixel unit 104 is a green pixel unit. However, in other embodiments, the pixel group may use pixel units of other colors. Of course, in other embodiments, the arrangement method of the plurality of pixel units P0 in the display panel is not limited to that shown in FIGS. 2 and 3.

[0040] As shown in FIGS. 2 and 3, a plurality of pixel units P0 are located in the first display area R1 and the second display area R2, and the density of the pixel units in the first display area R1 is less than the density of the pixel units in the second display area R2. Alternatively, the density of the pixels in the first display area R1 is less than the density of the pixels in the second display area R2. The density of the pixel units in the first display area R1 shown in FIG. 3 is 1 / 4 of the density of the pixel units in the second display area R2. That is, the density of the pixels in the first display area R1 shown in FIG. 3 is 1 / 4 of the density of the pixels in the second display area R2. The arrangement of the light transmission area R0 and the pixel units in the first display area R1 is not limited to that shown in FIG. 3 and can be set as required. For example, in other embodiments, the density of the pixel units in the first display area R1 is 1 / 2, 1 / 3, 1 / 6, or 1 / 8, etc., other values different from 1 / 4, of the density of the pixel units in the second display area R2.

[0041] For example, as shown in FIGS. 1A and 3, the display panel further includes a gate line 113 and a data line 313. The gate line 113 and the data line 313 are insulated from each other. Each gate line 113 is connected to one row of pixel units, and each data line 313 is connected to one column of pixel units. For example, the gate line 113 is configured to provide a scanning signal to one row of pixel units. [[ID=\\5]]

[0042] For example, as shown in FIGS. 1A and 3, the data line 313 includes a first data line DL1. The first data line DL1 is at least located in the first display area R1. For example, the first data line DL1 extends from the first display area R1 to the second display area R2.

[0043] For example, as shown in FIGS. 1A and 3, the gate line includes a first gate line GL1, and the first gate line GL1 extends from the second display area R2 to the first display area R1. As shown in FIG. 3, the light transmission area R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.

[0044] FIG. 4 is a schematic diagram of a pixel unit and a signal line for providing signals to the pixel unit in a display panel according to an embodiment of the present disclosure. As shown in FIG. 4, the display panel includes a plurality of pixel units P0, and each pixel unit P0 includes a light-emitting element EMC and a pixel circuit 10 for supplying a driving current to the light-emitting element EMC. The light-emitting element EMC may be an electroluminescent element, for example, an organic electroluminescent element, for example, an organic light-emitting diode (OLED).

[0045] As shown in FIG. 4, the display panel further includes an initialization signal line 210, a light-emitting control signal line 110, a data line 313, a first power supply line 311, and a second power supply line 312. For example, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light-emitting control signal line 110 is configured to provide a light-emitting control signal EM to the pixel unit P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power supply line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, the second power supply line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its magnitude may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be equal to or less than the second voltage signal ELVSS. For example, the pixel circuit 10 is controlled by signals such as a scan signal SCAN, a data signal DATA, an initialization signal Vint, a first voltage signal ELVDD, a second voltage signal ELVSS, and a light-emitting control signal EM to output a driving current to drive the light-emitting element EMC to emit light. As shown in FIG. 4, the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power supply line 312.

[0046] FIG. 5 is a schematic diagram of a display panel. As shown in FIG. 5, regardless of whether it is the first display area R1 or the second display area R2, the first power line 3110 uses a mesh structure, the horizontal portions of the first power line 3110 are directly connected, and the vertical portions of the first power line 3110 are directly connected. However, due to the wiring method of the first power line with this mesh structure, the light transmittance of the first display area R1 is low.

[0047] FIGS. 6A to 6E are schematic diagrams of display panels according to some embodiments of the present disclosure. As shown in FIGS. 6A to 6E, the first power line 311 includes a plurality of first conductors L1, a plurality of second conductors L2, and a plurality of third conductors L3. The first conductors L1 extend from the second display area R2 to the first display area R1. The plurality of second conductors L2 are located in the first display area R1 and are located between adjacent first conductors L1. Each second conductor L2 extends along the first direction D1. The third conductor L3 is located at least in the first display area R1. For example, the third conductor L3 extends from the second display area R2 to the first display area R1, and the third conductor L3 extends along the second direction D2. The first direction D1 intersects the second direction D2, and adjacent second conductors L2 are spaced apart from each other along the first direction D1. The second conductor L2 is connected to the first conductor L1 via the third conductor L3. For example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto. For example, the first conductor L1 extends along the first direction D1. For example, in the embodiments of the present disclosure, the second conductor L2 is located only in the first display area R1. In the embodiments of the present disclosure, an element extending along a certain direction is not necessarily a straight line and may have a curved or broken line portion. For example, the extending direction of an element is the general extending tendency of the element. For example, each part of the element does not necessarily extend along the direction.

[0048] The display panel according to the embodiments of the present disclosure adjusts the structure of the first power line in the first display area, which is equivalent to removing a part of the first power line installed along the second direction in a general display panel, simplifies the first power line in the first display area, and improves the light transmittance of the first display area.

[0049] For example, as shown in FIGS. 6A to 6E, the first conductor L1 and the second conductor L2 are each connected to adjacent two rows of pixel units in one pixel island A1, but are not limited thereto. In other embodiments, the pixel island A1 may include two or more rows of pixel units. For example, as shown in FIGS. 6A to 6E, the pixel island A1 includes at least two pixel units located in adjacent two rows, and the first conductor L1 and the second conductor L2 each overlap with two pixel units located in adjacent two rows. For example, as shown in FIGS. 6A to 6E, the first conductor L1 overlaps with the first pixel unit 101, and the second conductor L2 overlaps with the third pixel unit 103. For example, as shown in FIGS. 6A to 6E, the first conductor L1 further overlaps with the second pixel unit 102, and the second conductor L2 further overlaps with the fourth pixel unit 104.

[0050] For example, as shown in FIGS. 6A to 6E, a plurality of second conductors L2 are arranged in sequence along the first direction D1. For example, as shown in FIGS. 6A to 6E, adjacent second conductors L2 are not directly connected, and by removing a part of the first power line installed along the first direction, a plurality of second conductors L2 that are not directly connected are formed.

[0051] For example, as shown in FIGS. 6A to 6E, in order to improve the light transmittance of the first display area, the length of the portion of the first conductor L1 located in the first display area R1 in the first direction D1 is greater than the length of the second conductor L2 in the first direction D1.

[0052] For example, as shown in FIGS. 6A to 6E, the first power line 311 further includes a fourth conductor L4. The fourth conductor L4 extends along the second direction D2. The second conductor L2 is connected to the first conductor L1 via the fourth conductor L4. The length of the fourth conductor L4 in the second direction D2 is less than or equal to the length of the third conductor L3 in the second direction D2. In the display panels shown in FIGS. 6A, 6B, and 6E, the length of the fourth conductor L4 in the second direction D2 is less than the length of the third conductor L3 in the second direction D2. In the display panel shown in FIG. 6C, the length of the fourth conductor L4 in the second direction D2 is equal to the length of the third conductor L3 in the second direction D2.

[0053] For example, as shown in FIGS. 6A to 6E, in order to further improve the light transmittance of the first display region, a plurality of fourth conductors L4 are provided. The plurality of fourth conductors L4 are arranged in order along the second direction D2, and adjacent fourth conductors L4 are spaced apart from each other in the second direction D2. For example, as shown in FIG. 6A, a plurality of fourth conductors L41 are located between the third conductor L31 and the third conductor L32, and the third conductor L31 and the third conductor L32 are adjacent third conductors L3. Although FIG. 6A shows three fourth conductors L41, the number of fourth conductors L4 located between adjacent third conductors L3 is not limited to that shown, and can be determined as required. The fact that the plurality of fourth conductors L4 are spaced apart from each other in the second direction D2 is equivalent to removing a portion installed along the second direction of some of the first power lines in a general display panel, thereby reducing the wiring, optimizing the wiring space, and improving the light transmittance.

[0054] For example, as shown in FIGS. 6A to 6E, the first power line 311 further includes a fifth conductor L5. The fifth conductor L5 extends along the first direction D1. The fifth conductor L5 is located in the second display region R2. The fifth conductor L5 is located between adjacent first conductors L1, and the fifth conductor L5 and the adjacent second conductor L2 are spaced apart from each other along the first direction D1. Thereby, the wiring can be reduced at the boundary position between the first display region and the second display region, and the light transmittance can be improved.

[0055] In the display panel shown in FIG. 6E, each pixel island includes pixel units arranged in 2 rows and 3 columns. In the embodiments of the present disclosure, the number of pixel units included in each pixel island and the arrangement method of the pixel units are not limited. As long as the number of pixel units included in each pixel island is two or more rows, the arrangement method of the first power line according to the embodiments of the present disclosure can be used.

[0056] As shown in FIGS. 6A and 6B, in the display panel, the first power line 311 further includes a plurality of sixth conductors L6, the sixth conductors L6 are located in the second display area R2, and extend along the second direction D2. In the second display area R2, the plurality of fifth conductors L5 and the plurality of sixth conductors L6 are arranged to intersect. In an embodiment of the present disclosure, both the fifth conductor L5 and the sixth conductor L6 are located only in the second display area R2.

[0057] FIG. 7A is a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 7A, the same gate line 113 connects pixel units located in the second display area on both sides of the first display area R1 and pixel units located in the first display area R1 to form a row of pixel units. In an embodiment of the present disclosure, the form of the first conductor is not limited, as long as it can extend from the second display area R2 to the first display area R1. The first power line in FIG. 7A may be replaced by the first power line in another embodiment of the present disclosure. Moreover, the extending manner of the gate line 113 is not limited to that shown in FIG. 7A, and the arrangement manner of the gate line 113 only needs to be able to connect the pixels in the second display area R2 and the pixels in the first display area R1.

[0058] FIG. 7B is a schematic diagram of a display panel according to an embodiment of the present disclosure. Compared with the display panel shown in FIG. 7A, the display panel shown in FIG. 7B has adjusted the installation positions of some of the gate lines located in the first display area. That is, in the display panel shown in FIG. 7B, one gate line is installed above and below the pixel island respectively. On the other hand, in the display panel shown in FIG. 7A, two gate lines are installed below the pixel island.

[0059] FIGS. 6A-6E, 7A and 7B take as an example that the second conductor is connected to one of two adjacent first conductors and not directly connected to the other. In the display panels shown in FIGS. 6A-6E, 7A and 7B, the fourth conductor contacts one of two adjacent first conductors, for example, through a via penetrating an insulating layer.

[0060] For example, in an embodiment of the present disclosure, the pixel units in one row are the pixel units connected to the same gate line 113, while the pixel units in one column are the pixel units connected to the same data line 313. In the embodiment of the present disclosure, as an example, the first conductor L1, the second conductor L2, and the fifth conductor L5 all extend along the row direction, and the third conductor L3, the fourth conductor L4, and the sixth conductor L6 extend along the column direction, but it is not limited thereto. In other embodiments, the first conductor L1, the second conductor L2, and the fifth conductor L5 may all extend along the column direction, and the third conductor L3, the fourth conductor L4, and the sixth conductor L6 may extend along the row direction. Correspondingly, the second direction D2 and the first direction D1 may also be interchanged with each other.

[0061] FIGS. 6A to 6E take the example that the pixel island includes the pixel units in two rows. However, in other embodiments, the pixel island may include the pixel units in three rows or more rows. In this case, the plurality of second conductors may be understood as the second conductors connected to the pixel units in the same row. When the first conductor L1, the second conductor L2, and the fifth conductor L5 all extend along the column direction, and the third conductor L3, the fourth conductor L4, and the sixth conductor L6 extend along the row direction, the plurality of second conductors may be understood as the second conductors connected to the pixel units in the same column.

[0062] Hereinafter, some embodiments of the present disclosure will be described with reference to FIGS. 8 to 25. FIGS. 8 to 24 will be described by taking the pixel circuit of 7T1C as an example.

[0063] FIG. 8 is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the present disclosure. FIG. 9 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure. FIG. 10 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure. FIG. 11 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure. FIG. 12 is a plan view of a first insulating layer in a display panel according to an embodiment of the present disclosure. FIG. 13 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the present disclosure. FIG. 14 is a plan view of a second insulating layer in a display panel according to an embodiment of the present disclosure. FIG. 15 is a plan view of a pixel electrode layer in a display panel according to an embodiment of the present disclosure. FIG. 16 is a plan view of a pixel definition layer in a display panel according to an embodiment of the present disclosure. FIG. 17 is a schematic diagram of an active layer for forming a thin film transistor in a display panel according to an embodiment of the present disclosure. FIG. 18 is a schematic plan view after forming a second conductive pattern layer and a first insulating layer in a display panel according to an embodiment of the present disclosure. FIG. 19 is a schematic plan view after forming a third conductive pattern layer in a display panel according to an embodiment of the present disclosure. FIG. 20 is a schematic plan view after forming a second insulating layer in a display panel according to an embodiment of the present disclosure. FIG. 21 is a schematic plan view after forming a pixel electrode layer in a display panel according to an embodiment of the present disclosure. FIG. 22 is a schematic plan view after forming pixel definition in a display panel according to an embodiment of the present disclosure. FIG. 23 is a schematic plan view of pixel islands adjacent in a second direction in a first display region of a display panel according to an embodiment of the present disclosure. FIG. 24 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. FIG. 25 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. In the embodiments of the present disclosure, for clarity of illustration, in the plan view, the insulating layer is shown in the form of vias, and the insulating layer itself has been subjected to a transparency treatment.

[0064] For example, as shown in FIG. 8, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The emission control signal line 110 is configured to provide an emission control signal EM to the pixel unit P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power supply line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, the second power supply line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its magnitude may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be equal to or less than the second voltage signal ELVSS. For example, the pixel circuit is controlled by signals such as the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, and the emission control signal EM to output a drive current and drive the light-emitting element 20 to emit light. The light-emitting element 20 is driven by the corresponding pixel circuit 10 to emit red light, green light, blue light, or white light.

[0065] As shown in FIG. 8, the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first emission control transistor T4, a second emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The driving transistor T1 is electrically connected to the light-emitting element 20 and is controlled by signals such as the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS to output a drive current and drive the light-emitting element 20 to emit light.

[0066] For example, the display panel according to an embodiment of the present disclosure further includes a data driving circuit and a scanning driving circuit. The data driving circuit is configured to provide a data signal DATA to the pixel unit P0 based on an instruction of the control circuit, and the scanning driving circuit is configured to provide signals such as a light emission control signal EM, a scanning signal SCAN, and a reset control signal RESET to the pixel unit P0 based on an instruction of the control circuit. For example, the control circuit includes, but is not limited to, an external integrated circuit (IC). For example, the scanning driving circuit has a GOA (Gate driver On Array) structure attached to the display panel, or a driving chip (IC) structure bonded to the display panel. For example, different driving circuits may be used to provide the light emission control signal EM and the scanning signal SCAN respectively. For example, the display panel further includes a power supply (not shown) configured to provide the above voltage signals, which may be a voltage source or a current source as required. The power supply is configured to provide a first voltage signal ELVDD, a second power supply voltage ELVSS, an initialization signal Vint, etc. to the pixel unit P0 via a first power supply line 311, a second power supply line 312, and an initialization signal line 210 respectively.

[0067] As shown in FIG. 8, the second pole C12 of the storage capacitor C1 is electrically connected to the first power supply line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T32 of the threshold compensation transistor T3. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first pole T21 and the second pole T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first pole T11 of the driving transistor T1 respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

[0068] For example, as shown in FIG. 8, the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110.

[0069] For example, as shown in FIG. 8, the first electrode T41 and the second electrode T42 of the first light emission control transistor T4 are electrically connected to the first power line 311 and the first electrode T11 of the drive transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light emission control transistor T5 are electrically connected to the second electrode T12 of the drive transistor T1 and the pixel electrode E1 (which can be the anode of the OLED) of the light emitting element 20, respectively. The common electrode E2 (which can be the common electrode of the OLED, for example, the cathode) of the light emitting element 20 is electrically connected to the second power line 312.

[0070] For example, as shown in FIG. 8, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (the first initialization signal line 211), and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the drive transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first electrode T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (the second initialization signal line 212), and the second electrode T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light emitting element 20.

[0071] FIG. 9 shows a semiconductor pattern SCP, FIG. 10 shows a first conductive pattern layer LY1, and a first gate insulating layer is provided between the first conductive pattern layer LY1 and the semiconductor pattern SCP. By doping the semiconductor pattern SCP using the first conductive pattern layer LY1 as a mask, the regions of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 retain semiconductor characteristics and form the channels of thin film transistors, while the regions of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 are made conductive and form the sources or drains of thin film transistors. 17 shows an active layer ALT formed after the semiconductor pattern SCP is partially made conductive.

[0072] As shown in FIG. 10, the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and a first pole C11 of a storage capacitor C1. FIG. 10 further shows a first portion DL11 (conductor 114) of the first data line DL1. FIG. 10 further shows a gate line GL0, and the gate line GL0 is a part of the gate line extending from the second display area to the first display area. For example, as shown in FIG. 19, in an embodiment of the present disclosure, the first reset control signal line 111 and the second reset control signal line 112 are connected.

[0073] FIG. 11 shows the second conductive pattern layer LY2, and a second gate insulating layer is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes a stop block BK0, a stop block BK1, an initialization signal line 210, and a second pole C12 of the storage capacitor C1. The second pole C12 of the storage capacitor C1 has an opening OPN. The initialization signal line 210 includes a first initialization signal line 211 and a second initialization signal line 212. As shown in FIG. 11, the second conductive pattern layer LY2 includes a first portion L11 and a third portion L13 of the first conductor L1. As shown in FIG. 11, the stop block BK0 extends from the first conductor L1. FIG. 12 shows the pattern of the first insulating layer ISL1. The dotted objects in the figure are vias in the first insulating layer ISL1, and the first insulating layer ISL1 includes at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3. The first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3 can refer to those shown in FIGS. 24 and 25. FIG. 18 is a plan schematic diagram after forming the first insulating layer ISL1.

[0074] FIG. 13 shows the third conductive pattern layer LY3. The third conductive pattern layer LY3 includes a third conductor L3 (a part of the first power supply line 311), a second portion DL12 of the data line (a part of the data line 313), a first connection electrode 31a, a second connection electrode 31b, a third connection electrode 31c, and a fourth connection electrode 31d. As shown in FIG. 13, the third conductive pattern layer LY3 further includes a second portion L12 of the first conductor L1. The first portion L11 and the third portion L13 of the first conductor L1 are connected through the second portion L12.

[0075] As shown in FIGS. 13, 17, 18, and 19, the data line 313 is electrically connected to the first pole T21 of the data write transistor T2 via the via V4, the first power line 311 is electrically connected to the first pole T41 of the first light emission control transistor T4 via the via V3, the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 via the via V6, and the first power line 311 is electrically connected to the conductive block BK1 via the via V5. One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 via the via V11, and the other end of the first connection electrode 31a is connected to the first pole T61 of the first reset transistor T6 via the via V12. Thus, the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211. One end of the second connection electrode 31b is electrically connected to the second pole T62 of the first reset transistor T6 via the via V21, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1) via the via V22. Thereby, the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1). One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 via the via V31, and the other end of the third connection electrode 31c is connected to the first pole T71 of the second reset transistor T7 via the via V32. Thus, the first pole T71 of the second reset transistor T7 is electrically connected to the first initialization signal line 211. The fourth connection electrode 31d is electrically connected to the second pole T52 of the second light emission control transistor T5 via the via V1. The fourth connection electrode 31d is electrically connected to the pixel electrode E1 (see FIG. 8) of the light emitting element 20 formed subsequently.

[0076] FIG. 14 shows the second insulating layer ISL2, and the dot-like object in FIG. 14 is the via V1 in the second insulating layer ISL2. As shown in FIG. 14, the via V1 includes the vias V10, V20, V30, and V40. FIG. 20 is a plan view after forming the second insulating layer.

[0077] FIG. 15 shows the electrode layer ETL. The electrode layer ETL includes a plurality of pixel electrodes E1. The electrode layer ETL includes the pixel electrode E11 of the first pixel unit 101, the pixel electrode E12 of the second pixel unit 102, the pixel electrode E13 of the third pixel unit 103, and the pixel electrode E14 of the fourth pixel unit 104. The pixel electrode E11 of the first pixel unit 101 is connected to the corresponding fourth connection electrode 31d via the via V10, the pixel electrode E12 of the second pixel unit 102 is connected to the corresponding fourth connection electrode 31d via the via V20, the pixel electrode E13 of the third pixel unit 103 is connected to the corresponding fourth connection electrode 31d via the via V30, and the pixel electrode E14 of the fourth pixel unit 104 is connected to the corresponding fourth connection electrode 31d via the via V40. FIG. 21 is a plan view of the display panel after forming the electrode layer.

[0078] As shown in FIGS. 15 and 22, the pixel electrode E14 of the fourth pixel unit 104 includes a supplementary portion E0, and the orthographic projection of the supplementary portion E0 on the base substrate can cover the orthographic projection of the shared electrode (the second pole T22 of the data writing transistor T2 and the second pole T42 of the first light emission control transistor T4) of the data writing transistor T2 and the first light emission control transistor T4 on the base substrate, thereby improving the stability and lifespan of the data writing transistor T2 and the first light emission control transistor T4, and thereby improving the long-term light emission stability and lifespan of the display panel.

[0079] FIG. 16 shows a plan view of the pixel definition layer. As shown in FIG. 16, the pixel definition layer PDL includes a plurality of openings, and the plurality of openings include the opening OPN1, the opening OPN2, the opening OPN3, and the opening OPN4. FIG. 22 shows a schematic diagram of the display panel after forming the pixel definition layer. As shown in FIG. 22, the opening OPN1 exposes a part of the pixel electrode E11, the opening OPN2 exposes a part of the pixel electrode E12, the opening OPN3 exposes a part of the pixel electrode E13, and the opening OPN4 exposes a part of the pixel electrode E14. In subsequent processes, a light-emitting functional layer and a common electrode are formed, and further a light-emitting element EMC is formed.

[0080] Note that all the transistors used in an embodiment of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. Since the source and drain of the transistors used herein may have a symmetric structure, the source and drain may not have a structural distinction. In an embodiment of the present disclosure, in order to distinguish the two poles other than the gate of the transistor, one is directly described as the first pole and the other as the second pole. Therefore, in the embodiments of the present disclosure, the first and second poles of all or some of the transistors can be mutually exchanged as needed. For example, the first pole of the transistor described in the embodiments of the present disclosure may be the source and the second pole may be the drain, or the first pole of the transistor may be the drain and the second pole may be the source.

[0081] Also, according to the characteristics of the transistor, the transistor may be divided into N-type and P-type transistors. The embodiments of the present disclosure will be described by taking the example that all the transistors use P-type transistors. Based on the description and teaching of the present disclosure for this implementation form, those skilled in the art can easily conceive of an implementation form in which at least some of the transistors in the pixel circuit of the embodiments of the present disclosure use N-type transistors, that is, an implementation form using N-type transistors or a combination of N-type transistors and P-type transistors. Therefore, these implementation forms also belong to the protection scope of the present disclosure.

[0082] Figures 8 to 25 will be described by taking the pixel circuit of 7T1C as an example. The embodiments of the present disclosure include this but are not limited thereto. Note that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may include, for example, other numbers of transistor structures such as 7T2C structure, 6T1C structure, 6T2C structure, or 9T2C structure, but the embodiments of the present disclosure do not limit this.

[0083] FIG. 25 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. For example, as shown in FIG. 25, the display panel includes a thin film transistor 50 and a storage capacitor C1. The thin film transistor 50 includes an active layer ATL1 located on a base substrate BS, a first gate insulating layer GI1 located on a side of the active layer ATL1 away from the base substrate BS, and a gate GE located on a side of the first gate insulating layer GI1 away from the base substrate BS. The display panel further includes a second gate insulating layer GI2 located on a side of the gate GE away from the base substrate BS, an interlayer insulating layer ILD located on a side of the second gate insulating layer GI2 away from the base substrate BS, and a connection electrode CNE1 located on a side of the interlayer insulating layer ILD away from the base substrate BS. The active layer ATL1 includes a channel CN11, a first electrode ET1 and a second electrode ET2 located on both sides of the channel CN11, respectively, and the connection electrode CNE1 is connected to the second electrode ET2 through a via penetrating the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD. The storage capacitor C1 includes a first electrode C11 and a second electrode C12. The first electrode C11 and the gate GE are located in the same layer, both are located in the first conductive pattern layer LY1, the second electrode C12 is located between the second gate insulating layer GI2 and the interlayer insulating layer ILD, and is located in the second conductive pattern layer LY2. One of the first electrode ET1 and the second electrode ET2 is a source, and the other is a drain. The connection electrode CNE1 is located in the third conductive pattern layer LY3. The display panel further includes a passivation layer PVX and a planarization layer PLN. For example, the connection electrode CNE1 may be the fourth connection electrode 31d described above, and the thin film transistor 50 may be the second light emission control transistor T5 described above.

[0084] As shown in FIG. 25, the display panel further includes a light-emitting element EMC, the light-emitting element EMC includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2, and the pixel electrode E1 is connected to a connection electrode CNE1 through a via penetrating a passivation layer PVX and a planarization layer PLN. The display panel further includes a package layer CPS, and the package layer CPS includes a first package layer CPS1, a second package layer CPS2, and a third package layer CPS3. For example, the first package layer CPS1 and the third package layer CPS3 are inorganic material layers, and the second package layer CPS2 is an organic material layer. For example, the pixel electrode E1 is an anode and the common electrode E2 is a cathode, but is not limited thereto.

[0085] For example, the light-emitting element EMC includes an organic light-emitting diode. The light-emitting functional layer is located between the common electrode E2 and the pixel electrode E1. The light-emitting functional layer EML includes at least a light-emitting layer, and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0086] As shown in FIG. 25, the display panel further includes a pixel definition layer PDL and a spacer PS. The pixel definition layer PDL has an opening configured to limit the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit, and the spacer PS is configured to support a fine metal mask when forming the light-emitting functional layer EML. FIG. 25 shows that spacers PS are installed on both opposite sides of the light-emitting element, but is not limited thereto.

[0087] For example, the data line is configured to input a data signal to the pixel unit, and the first power signal line is configured to input a first power voltage to the driving transistor. The second power signal line is configured to input a second power voltage to the pixel unit. The first power voltage is a constant voltage, and the second power voltage is a constant voltage. For example, the first power voltage is a positive voltage and the second power voltage is a negative voltage, but is not limited thereto. For example, in some embodiments, the first power voltage is a positive voltage and the second power signal line is grounded.

[0088] As shown in FIG. 25, in the embodiment of the present disclosure, the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

[0089] For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS are all made of insulating materials. For example, the materials of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX include at least one of SiOx and SiNx, but are not limited thereto. For example, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS may be made of an organic insulating material such as resin, but are not limited thereto.

[0090] As shown in FIG. 17, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, and the first channel CN1 and the second channel CN2 are connected via a conductive portion CP. As shown in FIG. 18, the second conductor L2 further includes a connection arm L21. The threshold compensation transistor T3 is a dual-gate transistor. When the threshold compensation transistor T3 is turned off, the conductive portion CP is in a floating state and is easily jumped under the influence of the surrounding inter-line voltage. The voltage jump of the conductive portion CP has an adverse effect on the leakage current of the threshold compensation transistor T3, and further has an adverse effect on the emission luminance of the pixel unit. Therefore, it is necessary to stabilize the voltage of the conductive portion CP, and a stop block may be designed to form a capacitor together with the conductive portion CP. The stop block may have a certain voltage signal to also stabilize the voltage of the conductive portion CP in the floating state. The stop block BK0, the stop block BK, and the connection arm L21 mentioned in the embodiment of the present disclosure all play a role in stabilizing the voltage of the conductive portion CP.

[0091] As shown in FIG. 24, the connection arm L21 partially overlaps with the conductive part CP of the threshold compensation transistor T3 to form the capacitor C0, and a first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connection arm L21 and the conductive part CP. FIG. 24 further shows a second channel CN2. The capacitor C0 may be called a stable capacitor, and the connection arm L21 and the conductive part CP are two electrode plates of the capacitor C0. As shown in FIG. 24, the gate GE2 and the second channel CN2 overlap in a direction perpendicular to the base substrate BS. The gate GE2 is one gate of the threshold compensation transistor T3. As shown in FIG. 24, the second connection electrode 31b is connected to the second pole T32 of the threshold compensation transistor T3.

[0092] As shown in FIG. 19, the second conductor L2 further includes a connection arm L21. The connection arm L21 and the conductive part CP are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3 (see FIG. 24). For example, the shape of the connection arm L21 includes a C shape. Note that the connection arm L21 may be substantially C-shaped. Of course, the connection arm L21 may use other shapes as long as it can exert the function of stabilizing the threshold compensation transistor T3.

[0093] For example, the third direction D3 is perpendicular to the first direction D1 and the second direction D2. The third direction D3 is perpendicular to the base substrate BS. A first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connection arm L21 and the conductive part CP. For example, the first direction D1 and the second direction D2 are parallel to the main surface of the base substrate BS, and the third direction D3 is perpendicular to the main surface of the base substrate BS. Various elements are fabricated on the main surface of the base substrate BS.

[0094] As shown in FIGS. 11, 19, and 24, the first portion L11 includes a first sub-portion La extending along a first direction D1 and a second sub-portion Lb extending along a second direction. The second sub-portion Lb has a branch extending along the first direction D1, and the stop block BK0 is a branch of the second sub-portion Lb. As shown in FIGS. 17, 19, and 24, the branch (stop block BK0) of the second sub-portion Lb is spaced apart from the conductive portion of one pixel unit overlapping the first conductor L1 in the pixel island in a third direction D3 and partially overlaps in the third direction D3. As shown in FIGS. 17, 19, and 24, the branch (stop block BK0) of the second sub-portion Lb is spaced apart from the conductive portion CP of one pixel unit (the upper left pixel unit in FIG. 24) overlapping the first conductor L1 in the pixel island in a third direction D3 and partially overlaps in the third direction D3. For example, the length of the branch (stop block BK0) in the first direction D1 is less than the length of the first sub-portion La in the first direction D1.

[0095] For example, as shown in FIGS. 8, 17, 19, and 24, the pixel circuit 10 includes a first transistor and a second transistor. The first transistor is connected to the second transistor, the second transistor is connected to a light-emitting element, the first transistor includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 are connected via a conductive portion CP, and the second conductor L2 further includes a connection arm L21. The connection arm L21 is spaced apart from the conductive portion CP of one pixel unit (the lower left pixel unit in FIG. 19) overlapping the second conductor L2 in the pixel island in a third direction D3 and partially overlaps in the third direction D3. For example, the first transistor and the second transistor are respectively a threshold compensation transistor T3 in the pixel circuit 10 and a light-emitting control transistor connected to the light-emitting element. For example, the light-emitting control transistor connected to the light-emitting element is the second light-emitting control transistor T5. Of course, in other embodiments of the present disclosure, a stop block or a connection arm forming a capacitor together with the conductive portion CP of the first transistor in the pixel island may use other forms, which are not limited herein.

[0096] For example, as shown in FIG. 19, in an embodiment of the present disclosure, both the stop block BK0 (a branch of the second sub - part Lb) and the connection arm L21 are connected to the third conductor L3 of the pixel units in this column. However, the stop block BK is connected to the third conductor in a column adjacent to the column of pixel units where the shielded conductive part is located. That is, as shown in FIG. 19, the stop block BK0 (a branch of the second sub - part Lb), the connection arm L21, and the stop block BK are all connected to the same third conductor L3.

[0097] For example, as shown in FIG. 11, the initialization signal line 210 includes a plurality of hollow regions HP. The second conductor L2 is located within one hollow region HP and is surrounded by the portion of the initialization signal line that surrounds the hollow region HP of the initialization signal line. The second conductor L2 does not overlap with the portion of the initialization signal line that surrounds the hollow region. That is, the second conductor L2 is completely surrounded by the portion of the initialization signal line that surrounds the hollow region HP. In an embodiment of the present disclosure, the hollow region HP is located at a position corresponding to the thin - film portion removed when the initialization signal line 210 is fabricated.

[0098] For example, as shown in FIGS. 11, 13, and 19, the first conductor L1 includes a first portion L11 and a second portion L12. The first portion L11 of the first conductor L1 is located in the same layer as the second conductor L2, and the second portion L12 of the first conductor L1 is not located in the same layer as the second conductor L2. The second portion L12 of the first conductor L1 at least partially overlaps with the initialization signal line 210. As shown in FIGS. 11, 13, and 19, both the first portion L11 of the first conductor L1 and the second conductor L2 are located in the second conductive pattern layer LY2, and the second portion L12 of the first conductor L1 is located in the third conductive pattern layer LY3.

[0099] For example, as shown in FIGS. 11, 13, and 19, the second conductor L2 is surrounded by a part of the initialization signal line 210, and the first portion L11 of the first conductor L1 is surrounded by a part of the initialization signal line 210. As shown in FIGS. 11, 13, and 19, the second conductor L2 is surrounded by the lower - side portion 210a of the initialization signal line 210, and the first portion L11 of the first conductor L1 is surrounded by the upper - side portion 210b of the initialization signal line 210.

[0100] For example, as shown in FIGS. 3 and 19, the data line 313 includes a first data line DL1. The first data line DL1 extends from a first display region R1 to a second display region R2, and the first data line DL1 partially overlaps with the orthographic projection of a third conductor L3 on the base substrate BS. This installation form is advantageous for reducing the wiring area and improving the light transmittance.

[0101] For example, as shown in FIGS. 13, 18, and 19, the first data line DL1 includes a first portion DL11 and a second portion DL12. The first portion DL11 of the first data line DL1 partially overlaps with the third conductor L3, and the second portion DL12 of the first data line DL1 does not overlap with the third conductor L4. The first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are located in different layers. For example, the first portion DL11 (conductor 214) of the left first data line DL1 in FIG. 19 is located in the second conductive pattern layer, the second portion DL12 of the left first data line DL1 is located in the third conductive pattern layer, the first portion DL11 (conductor 114) of the right first data line DL1 in FIG. 19 is located in the first conductive pattern layer, and the second portion DL12 of the right first data line DL1 is located in the third conductive pattern layer. For example, as shown in FIGS. 3, 19, and 23, the first portion DL11 of the first data line DL1 is located between adjacent pixel islands A1.

[0102] For example, as shown in FIGS. 13 and 19, two first data lines DL1 are provided. The two first data lines DL1 are respectively connected to two adjacent columns of pixel units, and the two first data lines DL1 partially overlap with the orthographic projection of the same third conductor L3 on the base substrate BS. With this installation form, the data lines located between the pixel islands in two adjacent columns of pixel units can be hidden under the third conductor, thereby reducing the wiring area and improving the light transmittance.

[0103] For example, the first conductor L1 includes portions located in different layers, and the portions located in different layers are connected via vias penetrating an insulating layer. As shown in FIG. 19, the first conductor L1 includes a first portion L11, a second portion L12, and a third portion L13. The first portion L11 and the third portion L13 are located in the second conductive pattern layer LY2, and the second portion L12 is located in the third conductive pattern layer LY3. The first portion L11 and the second portion L12 are connected via a via V41 penetrating the insulating layer, and the third portion L13 and the second portion L12 are connected via a via V42 penetrating the insulating layer. As shown in FIGS. 24 and 25, an interlayer dielectric layer ILD is provided between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the via V41 penetrates the interlayer dielectric layer ILD, and the via V42 penetrates the interlayer dielectric layer ILD.

[0104] For example, as shown in FIG. 19, a part (the second portion L12) of the first conductor L1 and the third conductor L3 are located in the same layer, and both are located in the third conductive pattern layer LY3. The fourth conductor L4 and the third conductor L3 are located in the same layer, and both are located in the third conductive pattern layer LY3.

[0105] At least one embodiment of the present disclosure further provides a display device including any one of the above display panels. For example, the display device may be a display device such as an Organic Light-Emitting Diode (OLED) display, and any product or component having a display function such as a television, a digital camera, a mobile phone, a wristwatch, a tablet PC, a notebook computer, a navigator, etc. including these display devices.

[0106] For example, in an embodiment of the present disclosure, the first conductor L1 may include a portion located in the first conductive pattern layer and a portion located in the second conductive pattern layer. The second conductor L2 may be composed only of a portion located in the second conductive pattern layer. The third conductor L3 may be composed only of a portion located in the third conductive pattern layer. The fourth conductor L43 may be composed only of a portion located in the third conductive pattern layer. The fifth conductor L5 may be composed of a portion located in the first conductive pattern layer and a portion located in the second conductive pattern layer, but is not limited thereto and can be set as needed.

[0107] For example, as shown in FIGS. 11 and 19, in an embodiment of the present disclosure, the second electrode C12 of the storage capacitor C1 of the pixel unit P0 is a part of the second conductor L2 or a part of the first conductor L1.

[0108] The following points need to be further explained.

[0109] (1) Unless otherwise defined, in the embodiments and drawings of the present disclosure, the same reference numerals represent the same meanings.

[0110] (2) The drawings of the embodiments of the present disclosure relate only to the structures according to the embodiments of the present disclosure, and other structures may refer to normal designs.

[0111] (3) For clarity, in the drawings for explaining the embodiments of the present disclosure, the thicknesses of layers or regions are enlarged. As can be understood, when an element such as a layer, film, region, or substrate is described as being located "above" or "below" another element, the element may be "directly" located "above" or "below" the other element, or there may be intermediate elements.

[0112] (4) Unless there is a contradiction, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0113] Although specific embodiments of the present disclosure have been described above, the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should conform to the protection scope of the claims.

Claims

1. A display panel, comprising: a base substrate including a first display area and a second display area located at least on one side of the first display area; a plurality of pixel units located in the first display area and the second display area, wherein the density of the pixel units in the first display area is less than the density of the pixel units in the second display area, and the pixel units are a plurality of pixel units including pixel circuits, and the pixel units located in the first display area constitute a plurality of pixel islands, and there is a light transmission area between adjacent pixel islands, and the pixel islands include at least two pixel units; a first power line configured to provide a first voltage signal to the pixel circuit; The first power line includes a first conductor, a second conductor, and a third conductor. The first conductor extends from the second display area to the first display area. The second conductor is located in the first display area and extends along a first direction. The third conductor extends along a second direction. The first direction intersects the second direction. Adjacent second conductors are spaced apart from each other along the first direction. The second conductor is connected to the third conductor. The orthographic projection of the second conductor on the base substrate overlaps with the orthographic projection of at least two pixel units of the pixel islands on the base substrate. The display panel further includes a data line configured to provide a data signal to the pixel circuit. The data line includes a first data line. The first data line extends from the first display area to the second display area. The first data line includes a first portion located between adjacent pixel islands. The display panel further includes a gate line configured to provide a scan signal to a row of pixel units. The gate line includes a first gate line extending from the second display area to the first display area. The light transmission area is surrounded by two adjacent first gate lines and two adjacent first data lines.

2. The display panel according to claim 1, wherein the plurality of second conductors are arranged in sequence along the first direction.

3. The display panel according to claim 1 or 2, wherein the adjacent second conductors are not directly connected.

4. The display panel according to any one of claims 1 to 3, wherein the length of the portion of the first conductor located in the first display area in the first direction is greater than the length of the second conductor in the first direction.

5. The first conductor includes portions located in different layers, and the portions located in the different layers are connected via vias penetrating an insulating layer. The display panel according to any one of claims 1 to 4.

6. The first power line further includes a fourth conductor extending along the second direction, the second conductor is connected to the first conductor via the fourth conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction. The display panel according to any one of claims 1 to 5.

7. Including a plurality of fourth conductors located between adjacent third conductors, the plurality of fourth conductors are arranged in order along the second direction, and adjacent fourth conductors are spaced apart from each other in the second direction. The display panel according to any one of claims 1 to 6.

8. [[ID=⑥]]A part of the first conductor and the third conductor are located in the same layer. The display panel according to claim 6 or 7.

9. The orthographic projection of the first conductor on the base substrate and the orthographic projection of at least two pixel units of the pixel island on the base substrate overlap. The display panel according to any one of claims 1 to 8.

10. The pixel unit further includes a light-emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected via a conductive portion, the second conductor further includes a connection arm, the connection arm is spaced apart from the conductive portion of one pixel unit overlapping the second conductor in the pixel island in the third direction and partially overlaps in the third direction, the third direction is perpendicular to the first direction and perpendicular to the second direction. The display panel according to claim 9.

11. The shape of the connection arm includes a C shape. The display panel according to claim 10.

12. The first conductor has a branch, the branch is spaced apart from the conductive portion of one pixel unit overlapping the first conductor in the pixel island in the third direction and partially overlaps in the third direction. The display panel according to claim 10 or 11.

13. The first direction is perpendicular to the second direction. The display panel according to any one of claims 1 to 12.

14. The first power line further includes a fifth conductor, is located in the second display region, is located between adjacent first conductors, and is spaced apart from an adjacent second conductor along the first direction. The display panel according to any one of claims 1 to 13.

15. The display panel according to claim 9, further comprising an initialization signal line configured to provide an initialization signal to the pixel circuit, wherein the second conductor is surrounded by a part of the initialization signal line.

16. The first conductor includes a first part and a second part. The first part of the first conductor is located in the same layer as the second conductor, the second part of the first conductor is not located in the same layer as the second conductor, and the first part of the first conductor is surrounded by a part of the initialization signal line. The display panel according to claim 15.

17. The first part of the first conductor has a first sub-part extending along the first direction and a second sub-part extending along the second direction, and the second sub-part has a branch extending along the first direction. The display panel according to claim 16.

18. The length of the branch in the first direction is less than the length of the first sub-part in the first direction. The display panel according to claim 17.

19. The pixel unit further includes a light-emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected through a conductive part, the branch is spaced apart from the conductive part of one pixel unit overlapping the first conductor in the pixel island in a third direction and partially overlaps in the third direction, the third direction is perpendicular to the first direction and perpendicular to the second direction. The display panel according to claim 17 or 18.

20. The second conductor further includes a connection arm, the connection arm is spaced apart from the conductive part of one pixel unit overlapping the second conductor in the pixel island in a third direction and partially overlaps in the third direction. The display panel according to claim 19.

21. The first data line further includes a second portion, and the first portion and the second portion of the first data line are located in different layers respectively. The display panel according to any one of claims 1 to 20.

22. The orthographic projection of the second portion of the first data line on the base substrate and the orthographic projection of at least two pixel units of the pixel island on the base substrate overlap. The display panel according to claim 21.

23. Two first data lines are provided, and the two first data lines are respectively connected to two adjacent columns of pixel units. The orthographic projection of the two first data lines on the base substrate and the orthographic projection of the same third conductor partially overlap. The display panel according to any one of claims 1 to 22.

24. A display device including the display panel according to any one of claims 1 to 23.

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